From: Damien Le Moal <damien.lemoal@wdc.com> To: Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv@lists.infradead.org Cc: Atish Patra <atish.patra@wdc.com>, Anup Patel <anup.patel@wdc.com>, Sean Anderson <seanga2@gmail.com>, Paul Walmsley <paul.walmsley@sifive.com>, Rob Herring <robh@kernel.org>, devicetree@vger.kernel.org Subject: [PATCH v14 03/16] dt-bindings: update risc-v cpu properties Date: Tue, 2 Feb 2021 19:36:10 +0900 [thread overview] Message-ID: <20210202103623.200809-4-damien.lemoal@wdc.com> (raw) In-Reply-To: <20210202103623.200809-1-damien.lemoal@wdc.com> The Canaan Kendryte K210 SoC CPU cores are based on a rocket chip version using a draft verion of the RISC-V ISA specifications. To avoid any confusion with CPU cores using stable specifications, add the compatible string "canaan,k210" for this SoC CPU cores. Also add the "riscv,none" value to the mmu-type property to allow a DT to indicate that the CPU being described does not have an MMU or that it has an MMU that is not usable (which is the case for the K210 SoC). Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index eb6843f69f7c..e534f6a7cfa1 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -39,6 +39,7 @@ properties: - sifive,u74 - sifive,u5 - sifive,u7 + - canaan,k210 - const: riscv - const: riscv # Simulator only description: @@ -56,6 +57,7 @@ properties: - riscv,sv32 - riscv,sv39 - riscv,sv48 + - riscv,none riscv,isa: description: -- 2.29.2
WARNING: multiple messages have this Message-ID (diff)
From: Damien Le Moal <damien.lemoal@wdc.com> To: Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv@lists.infradead.org Cc: devicetree@vger.kernel.org, Rob Herring <robh@kernel.org>, Anup Patel <anup.patel@wdc.com>, Sean Anderson <seanga2@gmail.com>, Atish Patra <atish.patra@wdc.com>, Paul Walmsley <paul.walmsley@sifive.com> Subject: [PATCH v14 03/16] dt-bindings: update risc-v cpu properties Date: Tue, 2 Feb 2021 19:36:10 +0900 [thread overview] Message-ID: <20210202103623.200809-4-damien.lemoal@wdc.com> (raw) In-Reply-To: <20210202103623.200809-1-damien.lemoal@wdc.com> The Canaan Kendryte K210 SoC CPU cores are based on a rocket chip version using a draft verion of the RISC-V ISA specifications. To avoid any confusion with CPU cores using stable specifications, add the compatible string "canaan,k210" for this SoC CPU cores. Also add the "riscv,none" value to the mmu-type property to allow a DT to indicate that the CPU being described does not have an MMU or that it has an MMU that is not usable (which is the case for the K210 SoC). Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index eb6843f69f7c..e534f6a7cfa1 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -39,6 +39,7 @@ properties: - sifive,u74 - sifive,u5 - sifive,u7 + - canaan,k210 - const: riscv - const: riscv # Simulator only description: @@ -56,6 +57,7 @@ properties: - riscv,sv32 - riscv,sv39 - riscv,sv48 + - riscv,none riscv,isa: description: -- 2.29.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-02-02 10:37 UTC|newest] Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-02-02 10:36 [PATCH v14 00/16] RISC-V Kendryte K210 support improvements Damien Le Moal 2021-02-02 10:36 ` [PATCH v14 01/16] clk: Add RISC-V Canaan Kendryte K210 clock driver Damien Le Moal 2021-02-02 10:36 ` Damien Le Moal 2021-02-02 10:36 ` [PATCH v14 02/16] dt-bindings: add Canaan boards compatible strings Damien Le Moal 2021-02-02 10:36 ` Damien Le Moal 2021-02-02 17:55 ` Atish Patra 2021-02-02 17:55 ` Atish Patra 2021-02-02 10:36 ` Damien Le Moal [this message] 2021-02-02 10:36 ` [PATCH v14 03/16] dt-bindings: update risc-v cpu properties Damien Le Moal 2021-02-02 17:54 ` Atish Patra 2021-02-02 17:54 ` Atish Patra 2021-02-02 10:36 ` [PATCH v14 04/16] dt-bindings: update sifive plic compatible string Damien Le Moal 2021-02-02 10:36 ` Damien Le Moal 2021-02-02 18:26 ` Atish Patra 2021-02-02 18:26 ` Atish Patra 2021-02-03 12:38 ` Damien Le Moal 2021-02-03 12:38 ` Damien Le Moal 2021-02-02 10:36 ` [PATCH v14 05/16] dt-bindings: update sifive clint " Damien Le Moal 2021-02-02 10:36 ` Damien Le Moal 2021-02-02 17:52 ` Atish Patra 2021-02-02 17:52 ` Atish Patra 2021-02-02 10:36 ` [PATCH v14 06/16] dt-bindings: update sifive uart " Damien Le Moal 2021-02-02 10:36 ` Damien Le Moal 2021-02-02 18:27 ` Atish Patra 2021-02-02 18:27 ` Atish Patra 2021-02-02 10:36 ` [PATCH v14 07/16] dt-bindings: fix sifive gpio properties Damien Le Moal 2021-02-02 10:36 ` Damien Le Moal 2021-02-02 18:45 ` Atish Patra 2021-02-02 18:45 ` Atish Patra 2021-02-02 23:54 ` Sean Anderson 2021-02-02 23:54 ` Sean Anderson 2021-02-02 19:02 ` Rob Herring 2021-02-02 19:02 ` Rob Herring 2021-02-03 0:01 ` Sean Anderson 2021-02-03 0:01 ` Sean Anderson 2021-02-03 20:23 ` Rob Herring 2021-02-03 20:23 ` Rob Herring 2021-02-03 23:13 ` Sean Anderson 2021-02-03 23:13 ` Sean Anderson 2021-02-03 12:52 ` Damien Le Moal 2021-02-03 12:52 ` Damien Le Moal 2021-02-03 20:41 ` Rob Herring 2021-02-03 20:41 ` Rob Herring 2021-02-04 0:47 ` Damien Le Moal 2021-02-04 0:47 ` Damien Le Moal 2021-02-05 0:29 ` Damien Le Moal 2021-02-05 0:29 ` Damien Le Moal 2021-02-05 20:02 ` Rob Herring 2021-02-05 20:02 ` Rob Herring 2021-02-05 22:53 ` Damien Le Moal 2021-02-05 22:53 ` Damien Le Moal 2021-02-05 22:55 ` Sean Anderson 2021-02-05 22:55 ` Sean Anderson 2021-02-05 23:32 ` Damien Le Moal 2021-02-05 23:32 ` Damien Le Moal 2021-02-06 0:31 ` Sean Anderson 2021-02-06 0:31 ` Sean Anderson 2021-02-06 0:52 ` Damien Le Moal 2021-02-06 0:52 ` Damien Le Moal 2021-02-07 17:37 ` Rob Herring 2021-02-07 17:37 ` Rob Herring 2021-02-02 10:36 ` [PATCH v14 08/16] dt-bindings: add resets property to dw-apb-timer Damien Le Moal 2021-02-02 10:36 ` Damien Le Moal 2021-02-02 18:45 ` Atish Patra 2021-02-02 18:45 ` Atish Patra 2021-02-02 10:36 ` [PATCH v14 09/16] riscv: Update Canaan Kendryte K210 device tree Damien Le Moal 2021-02-02 10:36 ` Damien Le Moal 2021-02-02 10:36 ` [PATCH v14 10/16] riscv: Add SiPeed MAIX BiT board " Damien Le Moal 2021-02-02 10:36 ` Damien Le Moal 2021-02-02 10:36 ` [PATCH v14 11/16] riscv: Add SiPeed MAIX DOCK " Damien Le Moal 2021-02-02 10:36 ` Damien Le Moal 2021-02-02 10:36 ` [PATCH v14 12/16] riscv: Add SiPeed MAIX GO " Damien Le Moal 2021-02-02 10:36 ` Damien Le Moal 2021-02-02 10:36 ` [PATCH v14 13/16] riscv: Add SiPeed MAIXDUINO " Damien Le Moal 2021-02-02 10:36 ` Damien Le Moal 2021-02-02 10:36 ` [PATCH v14 14/16] riscv: Add Kendryte KD233 " Damien Le Moal 2021-02-02 10:36 ` Damien Le Moal 2021-02-02 10:36 ` [PATCH v14 15/16] riscv: Update Canaan Kendryte K210 defconfig Damien Le Moal 2021-02-02 18:49 ` Atish Patra 2021-02-02 10:36 ` [PATCH v14 16/16] riscv: Add Canaan Kendryte K210 SD card defconfig Damien Le Moal 2021-02-02 18:48 ` Atish Patra
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