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From: Damien Le Moal <damien.lemoal@wdc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv@lists.infradead.org
Cc: Atish Patra <atish.patra@wdc.com>,
	Anup Patel <anup.patel@wdc.com>,
	Sean Anderson <seanga2@gmail.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Rob Herring <robh@kernel.org>,
	devicetree@vger.kernel.org
Subject: [PATCH v14 04/16] dt-bindings: update sifive plic compatible string
Date: Tue,  2 Feb 2021 19:36:11 +0900	[thread overview]
Message-ID: <20210202103623.200809-5-damien.lemoal@wdc.com> (raw)
In-Reply-To: <20210202103623.200809-1-damien.lemoal@wdc.com>

Add the compatible string "canaan,k210-plic" to the Sifive plic bindings
to indicate the use of the "sifive,plic-1.0.0" IP block in the Canaan
Kendryte K210 SoC. The description is also updated to reflect this
change, that is, that SoCs from other vendors may also use this plic
implementation.

Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
---
 .../sifive,plic-1.0.0.yaml                    | 20 ++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index b9a61c9f7530..3db86d329e1e 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -8,10 +8,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: SiFive Platform-Level Interrupt Controller (PLIC)
 
 description:
-  SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
-  (PLIC) high-level specification in the RISC-V Privileged Architecture
-  specification. The PLIC connects all external interrupts in the system to all
-  hart contexts in the system, via the external interrupt source in each hart.
+  SiFive other RISC-V and other SoCs include an implementation of the
+  Platform-Level Interrupt Controller (PLIC) high-level specification in
+  the RISC-V Privileged Architecture specification. The PLIC connects all
+  external interrupts in the system to all hart contexts in the system, via
+  the external interrupt source in each hart.
 
   A hart context is a privilege mode in a hardware execution thread. For example,
   in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
@@ -41,9 +42,14 @@ maintainers:
 
 properties:
   compatible:
-    items:
-      - const: sifive,fu540-c000-plic
-      - const: sifive,plic-1.0.0
+    oneOf:
+      - items:
+          - const: sifive,fu540-c000-plic
+          - const: sifive,plic-1.0.0
+
+      - items:
+          - const: canaan,k210-plic
+          - const: sifive,plic-1.0.0
 
   reg:
     maxItems: 1
-- 
2.29.2


WARNING: multiple messages have this Message-ID (diff)
From: Damien Le Moal <damien.lemoal@wdc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv@lists.infradead.org
Cc: devicetree@vger.kernel.org, Rob Herring <robh@kernel.org>,
	Anup Patel <anup.patel@wdc.com>,
	Sean Anderson <seanga2@gmail.com>,
	Atish Patra <atish.patra@wdc.com>,
	Paul Walmsley <paul.walmsley@sifive.com>
Subject: [PATCH v14 04/16] dt-bindings: update sifive plic compatible string
Date: Tue,  2 Feb 2021 19:36:11 +0900	[thread overview]
Message-ID: <20210202103623.200809-5-damien.lemoal@wdc.com> (raw)
In-Reply-To: <20210202103623.200809-1-damien.lemoal@wdc.com>

Add the compatible string "canaan,k210-plic" to the Sifive plic bindings
to indicate the use of the "sifive,plic-1.0.0" IP block in the Canaan
Kendryte K210 SoC. The description is also updated to reflect this
change, that is, that SoCs from other vendors may also use this plic
implementation.

Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
---
 .../sifive,plic-1.0.0.yaml                    | 20 ++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index b9a61c9f7530..3db86d329e1e 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -8,10 +8,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: SiFive Platform-Level Interrupt Controller (PLIC)
 
 description:
-  SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
-  (PLIC) high-level specification in the RISC-V Privileged Architecture
-  specification. The PLIC connects all external interrupts in the system to all
-  hart contexts in the system, via the external interrupt source in each hart.
+  SiFive other RISC-V and other SoCs include an implementation of the
+  Platform-Level Interrupt Controller (PLIC) high-level specification in
+  the RISC-V Privileged Architecture specification. The PLIC connects all
+  external interrupts in the system to all hart contexts in the system, via
+  the external interrupt source in each hart.
 
   A hart context is a privilege mode in a hardware execution thread. For example,
   in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
@@ -41,9 +42,14 @@ maintainers:
 
 properties:
   compatible:
-    items:
-      - const: sifive,fu540-c000-plic
-      - const: sifive,plic-1.0.0
+    oneOf:
+      - items:
+          - const: sifive,fu540-c000-plic
+          - const: sifive,plic-1.0.0
+
+      - items:
+          - const: canaan,k210-plic
+          - const: sifive,plic-1.0.0
 
   reg:
     maxItems: 1
-- 
2.29.2


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  parent reply	other threads:[~2021-02-02 10:38 UTC|newest]

Thread overview: 81+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-02 10:36 [PATCH v14 00/16] RISC-V Kendryte K210 support improvements Damien Le Moal
2021-02-02 10:36 ` [PATCH v14 01/16] clk: Add RISC-V Canaan Kendryte K210 clock driver Damien Le Moal
2021-02-02 10:36   ` Damien Le Moal
2021-02-02 10:36 ` [PATCH v14 02/16] dt-bindings: add Canaan boards compatible strings Damien Le Moal
2021-02-02 10:36   ` Damien Le Moal
2021-02-02 17:55   ` Atish Patra
2021-02-02 17:55     ` Atish Patra
2021-02-02 10:36 ` [PATCH v14 03/16] dt-bindings: update risc-v cpu properties Damien Le Moal
2021-02-02 10:36   ` Damien Le Moal
2021-02-02 17:54   ` Atish Patra
2021-02-02 17:54     ` Atish Patra
2021-02-02 10:36 ` Damien Le Moal [this message]
2021-02-02 10:36   ` [PATCH v14 04/16] dt-bindings: update sifive plic compatible string Damien Le Moal
2021-02-02 18:26   ` Atish Patra
2021-02-02 18:26     ` Atish Patra
2021-02-03 12:38     ` Damien Le Moal
2021-02-03 12:38       ` Damien Le Moal
2021-02-02 10:36 ` [PATCH v14 05/16] dt-bindings: update sifive clint " Damien Le Moal
2021-02-02 10:36   ` Damien Le Moal
2021-02-02 17:52   ` Atish Patra
2021-02-02 17:52     ` Atish Patra
2021-02-02 10:36 ` [PATCH v14 06/16] dt-bindings: update sifive uart " Damien Le Moal
2021-02-02 10:36   ` Damien Le Moal
2021-02-02 18:27   ` Atish Patra
2021-02-02 18:27     ` Atish Patra
2021-02-02 10:36 ` [PATCH v14 07/16] dt-bindings: fix sifive gpio properties Damien Le Moal
2021-02-02 10:36   ` Damien Le Moal
2021-02-02 18:45   ` Atish Patra
2021-02-02 18:45     ` Atish Patra
2021-02-02 23:54     ` Sean Anderson
2021-02-02 23:54       ` Sean Anderson
2021-02-02 19:02   ` Rob Herring
2021-02-02 19:02     ` Rob Herring
2021-02-03  0:01     ` Sean Anderson
2021-02-03  0:01       ` Sean Anderson
2021-02-03 20:23       ` Rob Herring
2021-02-03 20:23         ` Rob Herring
2021-02-03 23:13         ` Sean Anderson
2021-02-03 23:13           ` Sean Anderson
2021-02-03 12:52     ` Damien Le Moal
2021-02-03 12:52       ` Damien Le Moal
2021-02-03 20:41       ` Rob Herring
2021-02-03 20:41         ` Rob Herring
2021-02-04  0:47         ` Damien Le Moal
2021-02-04  0:47           ` Damien Le Moal
2021-02-05  0:29           ` Damien Le Moal
2021-02-05  0:29             ` Damien Le Moal
2021-02-05 20:02           ` Rob Herring
2021-02-05 20:02             ` Rob Herring
2021-02-05 22:53             ` Damien Le Moal
2021-02-05 22:53               ` Damien Le Moal
2021-02-05 22:55               ` Sean Anderson
2021-02-05 22:55                 ` Sean Anderson
2021-02-05 23:32                 ` Damien Le Moal
2021-02-05 23:32                   ` Damien Le Moal
2021-02-06  0:31                   ` Sean Anderson
2021-02-06  0:31                     ` Sean Anderson
2021-02-06  0:52                     ` Damien Le Moal
2021-02-06  0:52                       ` Damien Le Moal
2021-02-07 17:37                       ` Rob Herring
2021-02-07 17:37                         ` Rob Herring
2021-02-02 10:36 ` [PATCH v14 08/16] dt-bindings: add resets property to dw-apb-timer Damien Le Moal
2021-02-02 10:36   ` Damien Le Moal
2021-02-02 18:45   ` Atish Patra
2021-02-02 18:45     ` Atish Patra
2021-02-02 10:36 ` [PATCH v14 09/16] riscv: Update Canaan Kendryte K210 device tree Damien Le Moal
2021-02-02 10:36   ` Damien Le Moal
2021-02-02 10:36 ` [PATCH v14 10/16] riscv: Add SiPeed MAIX BiT board " Damien Le Moal
2021-02-02 10:36   ` Damien Le Moal
2021-02-02 10:36 ` [PATCH v14 11/16] riscv: Add SiPeed MAIX DOCK " Damien Le Moal
2021-02-02 10:36   ` Damien Le Moal
2021-02-02 10:36 ` [PATCH v14 12/16] riscv: Add SiPeed MAIX GO " Damien Le Moal
2021-02-02 10:36   ` Damien Le Moal
2021-02-02 10:36 ` [PATCH v14 13/16] riscv: Add SiPeed MAIXDUINO " Damien Le Moal
2021-02-02 10:36   ` Damien Le Moal
2021-02-02 10:36 ` [PATCH v14 14/16] riscv: Add Kendryte KD233 " Damien Le Moal
2021-02-02 10:36   ` Damien Le Moal
2021-02-02 10:36 ` [PATCH v14 15/16] riscv: Update Canaan Kendryte K210 defconfig Damien Le Moal
2021-02-02 18:49   ` Atish Patra
2021-02-02 10:36 ` [PATCH v14 16/16] riscv: Add Canaan Kendryte K210 SD card defconfig Damien Le Moal
2021-02-02 18:48   ` Atish Patra

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