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* [Intel-gfx] [PATCH 1/4] drm/i915/display: Rename for_each_intel_encoder.*_can_psr to for_each_intel_encoder.*_with_psr
@ 2021-02-09 18:14 José Roberto de Souza
  2021-02-09 18:14 ` [Intel-gfx] [PATCH 2/4] drm/i915/display: Only write to register in intel_psr2_program_trans_man_trk_ctl() José Roberto de Souza
                   ` (8 more replies)
  0 siblings, 9 replies; 13+ messages in thread
From: José Roberto de Souza @ 2021-02-09 18:14 UTC (permalink / raw)
  To: intel-gfx

for_each_intel_encoder.*_"can_psr" sounds strange, in my opinion
"with_psr" is better.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.h         |  4 ++--
 drivers/gpu/drm/i915/display/intel_display_debugfs.c |  6 +++---
 drivers/gpu/drm/i915/display/intel_psr.c             | 12 ++++++------
 drivers/gpu/drm/i915/i915_irq.c                      |  4 ++--
 4 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index e3757ecabbf7..c60a58ba60ee 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -418,7 +418,7 @@ enum phy_fia {
 		for_each_if((encoder_mask) &				\
 			    drm_encoder_mask(&intel_encoder->base))
 
-#define for_each_intel_encoder_mask_can_psr(dev, intel_encoder, encoder_mask) \
+#define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \
 	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 		for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \
 			    intel_encoder_can_psr(intel_encoder))
@@ -427,7 +427,7 @@ enum phy_fia {
 	for_each_intel_encoder(dev, intel_encoder)		\
 		for_each_if(intel_encoder_is_dp(intel_encoder))
 
-#define for_each_intel_encoder_can_psr(dev, intel_encoder) \
+#define for_each_intel_encoder_with_psr(dev, intel_encoder) \
 	for_each_intel_encoder((dev), (intel_encoder)) \
 		for_each_if(intel_encoder_can_psr(intel_encoder))
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index d6e4a9237bda..7ce11d851163 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -437,7 +437,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 		return -ENODEV;
 
 	/* Find the first EDP which supports PSR */
-	for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) {
+	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
 		intel_dp = enc_to_intel_dp(encoder);
 		break;
 	}
@@ -459,7 +459,7 @@ i915_edp_psr_debug_set(void *data, u64 val)
 	if (!HAS_PSR(dev_priv))
 		return ret;
 
-	for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) {
+	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
 		drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to %llx\n", val);
@@ -484,7 +484,7 @@ i915_edp_psr_debug_get(void *data, u64 *val)
 	if (!HAS_PSR(dev_priv))
 		return -ENODEV;
 
-	for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) {
+	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
 		// TODO: split to each transcoder's PSR debug state
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index bf214d0e2dec..1d3903612fcb 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1232,8 +1232,8 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
 	    !crtc_state->enable_psr2_sel_fetch)
 		return;
 
-	for_each_intel_encoder_mask_can_psr(&dev_priv->drm, encoder,
-					    crtc_state->uapi.encoder_mask) {
+	for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
+					     crtc_state->uapi.encoder_mask) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
 		if (!intel_dp->psr.enabled)
@@ -1515,8 +1515,8 @@ void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
 	if (!new_crtc_state->has_psr)
 		return;
 
-	for_each_intel_encoder_mask_can_psr(&dev_priv->drm, encoder,
-					    new_crtc_state->uapi.encoder_mask) {
+	for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
+					     new_crtc_state->uapi.encoder_mask) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 		u32 psr_status;
 
@@ -1730,7 +1730,7 @@ void intel_psr_invalidate(struct drm_i915_private *dev_priv,
 	if (origin == ORIGIN_FLIP)
 		return;
 
-	for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) {
+	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
 		unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
@@ -1802,7 +1802,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
 {
 	struct intel_encoder *encoder;
 
-	for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) {
+	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
 		unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 98145a7f28a4..8f6b60661a4d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2096,7 +2096,7 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
 	if (de_iir & DE_EDP_PSR_INT_HSW) {
 		struct intel_encoder *encoder;
 
-		for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) {
+		for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
 			struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
 			u32 psr_iir = intel_uncore_read(&dev_priv->uncore,
@@ -2323,7 +2323,7 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
 		u32 psr_iir;
 		i915_reg_t iir_reg;
 
-		for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) {
+		for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
 			struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
 			if (INTEL_GEN(dev_priv) >= 12)
-- 
2.30.0

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^ permalink raw reply related	[flat|nested] 13+ messages in thread
end of thread, other threads:[~2021-02-22  9:57 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-09 18:14 [Intel-gfx] [PATCH 1/4] drm/i915/display: Rename for_each_intel_encoder.*_can_psr to for_each_intel_encoder.*_with_psr José Roberto de Souza
2021-02-09 18:14 ` [Intel-gfx] [PATCH 2/4] drm/i915/display: Only write to register in intel_psr2_program_trans_man_trk_ctl() José Roberto de Souza
2021-02-11 11:37   ` Mun, Gwan-gyeong
2021-02-09 18:14 ` [Intel-gfx] [PATCH 3/4] drm/i915/display: Remove some redundancy around CAN_PSR() José Roberto de Souza
2021-02-22  9:48   ` Mun, Gwan-gyeong
2021-02-09 18:14 ` [Intel-gfx] [PATCH 4/4] drm/i915/display: Set source_support even if panel do not support PSR José Roberto de Souza
2021-02-22  9:57   ` Mun, Gwan-gyeong
2021-02-09 18:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/display: Rename for_each_intel_encoder.*_can_psr to for_each_intel_encoder.*_with_psr Patchwork
2021-02-09 18:27 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-02-09 18:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-02-09 22:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-02-11 11:34 ` [Intel-gfx] [PATCH 1/4] " Mun, Gwan-gyeong
2021-02-11 11:34 ` Mun, Gwan-gyeong

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