* [PATCH] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
@ 2021-02-19 9:59 ` frank.chang
0 siblings, 0 replies; 6+ messages in thread
From: frank.chang @ 2021-02-19 9:59 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
commit: c445593, but other TB_FLAGS bits for rvv and rvh were
not shift as well so these bits may overlap with each other when
rvv is enabled.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 02758ae0eb4..1b49eb9950b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -379,12 +379,13 @@ typedef CPURISCVState CPUArchState;
typedef RISCVCPU ArchCPU;
#include "exec/cpu-all.h"
-FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
-FIELD(TB_FLAGS, LMUL, 3, 2)
-FIELD(TB_FLAGS, SEW, 5, 3)
-FIELD(TB_FLAGS, VILL, 8, 1)
+/* Skip mem_idx bits */
+FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
+FIELD(TB_FLAGS, LMUL, 4, 2)
+FIELD(TB_FLAGS, SEW, 6, 3)
+FIELD(TB_FLAGS, VILL, 9, 1)
/* Is a Hypervisor instruction load/store allowed? */
-FIELD(TB_FLAGS, HLSX, 9, 1)
+FIELD(TB_FLAGS, HLSX, 10, 1)
bool riscv_cpu_is_32bit(CPURISCVState *env);
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
@ 2021-02-19 9:59 ` frank.chang
0 siblings, 0 replies; 6+ messages in thread
From: frank.chang @ 2021-02-19 9:59 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
commit: c445593, but other TB_FLAGS bits for rvv and rvh were
not shift as well so these bits may overlap with each other when
rvv is enabled.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 02758ae0eb4..1b49eb9950b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -379,12 +379,13 @@ typedef CPURISCVState CPUArchState;
typedef RISCVCPU ArchCPU;
#include "exec/cpu-all.h"
-FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
-FIELD(TB_FLAGS, LMUL, 3, 2)
-FIELD(TB_FLAGS, SEW, 5, 3)
-FIELD(TB_FLAGS, VILL, 8, 1)
+/* Skip mem_idx bits */
+FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
+FIELD(TB_FLAGS, LMUL, 4, 2)
+FIELD(TB_FLAGS, SEW, 6, 3)
+FIELD(TB_FLAGS, VILL, 9, 1)
/* Is a Hypervisor instruction load/store allowed? */
-FIELD(TB_FLAGS, HLSX, 9, 1)
+FIELD(TB_FLAGS, HLSX, 10, 1)
bool riscv_cpu_is_32bit(CPURISCVState *env);
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
2021-02-19 9:59 ` frank.chang
@ 2021-02-19 16:11 ` Richard Henderson
-1 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2021-02-19 16:11 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar, Bastian Koppelmann
On 2/19/21 1:59 AM, frank.chang@sifive.com wrote:
> +/* Skip mem_idx bits */
> +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
Why not just add the mem_idx field to the list?
The separation between the FIELDs and TB_FLAG_*_MASK is unfortunate, and will
be a continuing source of errors.
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
@ 2021-02-19 16:11 ` Richard Henderson
0 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2021-02-19 16:11 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Alistair Francis, Palmer Dabbelt, Sagar Karandikar, Bastian Koppelmann
On 2/19/21 1:59 AM, frank.chang@sifive.com wrote:
> +/* Skip mem_idx bits */
> +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
Why not just add the mem_idx field to the list?
The separation between the FIELDs and TB_FLAG_*_MASK is unfortunate, and will
be a continuing source of errors.
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
2021-02-19 16:11 ` Richard Henderson
@ 2021-02-20 5:14 ` Frank Chang
-1 siblings, 0 replies; 6+ messages in thread
From: Frank Chang @ 2021-02-20 5:14 UTC (permalink / raw)
To: Richard Henderson
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt
[-- Attachment #1: Type: text/plain, Size: 478 bytes --]
On Sat, Feb 20, 2021 at 12:12 AM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 2/19/21 1:59 AM, frank.chang@sifive.com wrote:
> > +/* Skip mem_idx bits */
> > +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
>
> Why not just add the mem_idx field to the list?
>
> The separation between the FIELDs and TB_FLAG_*_MASK is unfortunate, and
> will
> be a continuing source of errors.
>
>
Sure, I will edit it and send out the next version patch.
Thanks,
Frank Chang
>
> r~
>
[-- Attachment #2: Type: text/html, Size: 1045 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
@ 2021-02-20 5:14 ` Frank Chang
0 siblings, 0 replies; 6+ messages in thread
From: Frank Chang @ 2021-02-20 5:14 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
[-- Attachment #1: Type: text/plain, Size: 478 bytes --]
On Sat, Feb 20, 2021 at 12:12 AM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 2/19/21 1:59 AM, frank.chang@sifive.com wrote:
> > +/* Skip mem_idx bits */
> > +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
>
> Why not just add the mem_idx field to the list?
>
> The separation between the FIELDs and TB_FLAG_*_MASK is unfortunate, and
> will
> be a continuing source of errors.
>
>
Sure, I will edit it and send out the next version patch.
Thanks,
Frank Chang
>
> r~
>
[-- Attachment #2: Type: text/html, Size: 1045 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-02-20 5:15 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-19 9:59 [PATCH] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh frank.chang
2021-02-19 9:59 ` frank.chang
2021-02-19 16:11 ` Richard Henderson
2021-02-19 16:11 ` Richard Henderson
2021-02-20 5:14 ` Frank Chang
2021-02-20 5:14 ` Frank Chang
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