[PATCH 0/8]

[PATCH 0/8]

[Patrick Delaunay]

Serie proposed after analysis in [1], to correctly handle Domain Access
Control Register (DACR) and activate the domain checking in MMU against
the permission bits in the translation tables and avoids prefetching issue
on ARMv7, as indicated in [1].

I propose a clean and general solution for ARMv7, when the LPAE is not
activated; after this update, I revert the correction done for OMAP
by the commit de63ac278cba ("ARM: mmu: Set domain permissions to client
access")

Tests on ARMv7 platform is requested before integration,
so I think the target can be v2021.07 (next).

The 2 first patch of the serie solve issues for stm32mp platform
when dcache is activate in pre-reloc or in SPL.

See also correction for LPAE mode in commit 06d43c808d61 ("arm: Set TTB
XN bit in case DCACHE_OFF for LPAE mode")


[1] [PATCH 0/7] arm: cache: cp15: don't map reserved region with no-map
    property
http://u-boot.10912.n7.nabble.com/PATCH-0-7-arm-cache-cp15-don-t-map-reserved-region-with-no-map-property-tt428715.html



Patrick Delaunay (8):
  stm32mp: update MMU config before the relocation
  stm32mp: update the mmu configuration for SPL and prereloc
  arm: remove TTB_SECT_XN_MASK in DCACHE_WRITETHROUGH
  arm: cosmetic: align TTB_SECT define value
  arm: cp15: update DACR value to activate access control
  arm: omap2: remove arm_init_domains
  arm: cp15: remove weak function arm_init_domains
  arm: remove set_dacr/get_dacr functions

 arch/arm/cpu/armv7/cache_v7.c     |  3 ---
 arch/arm/include/asm/cache.h      |  1 -
 arch/arm/include/asm/system.h     | 18 ++------------
 arch/arm/lib/cache-cp15.c         | 13 ++++------
 arch/arm/mach-omap2/omap-cache.c  | 17 -------------
 arch/arm/mach-stm32mp/cpu.c       | 40 +++++++++++++++++++++++--------
 arch/arm/mach-stm32mp/dram_init.c | 13 ++++++----
 7 files changed, 46 insertions(+), 59 deletions(-)

-- 
2.17.1

[PATCH 1/8] stm32mp: update MMU config before the relocation

[Patrick Delaunay]

Mark the top of ram, used for relocated U-Boot as a normal memory
(cacheable and executable) to avoid permission access issue when
U-Boot jumps to this relocated code.

When MMU is activated in pre-reloc stage; only the beginning of
DDR is marked executable.

This patch avoids access issue when DACR is correctly managed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
---

 arch/arm/mach-stm32mp/dram_init.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c
index 32b177bb79..5fc8c6e15d 100644
--- a/arch/arm/mach-stm32mp/dram_init.c
+++ b/arch/arm/mach-stm32mp/dram_init.c
@@ -12,6 +12,7 @@
 #include <lmb.h>
 #include <log.h>
 #include <ram.h>
+#include <asm/system.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -40,6 +41,7 @@ int dram_init(void)
 
 ulong board_get_usable_ram_top(ulong total_size)
 {
+	phys_size_t size;
 	phys_addr_t reg;
 	struct lmb lmb;
 
@@ -47,10 +49,13 @@ ulong board_get_usable_ram_top(ulong total_size)
 	lmb_init(&lmb);
 	lmb_add(&lmb, gd->ram_base, gd->ram_size);
 	boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
-	reg = lmb_alloc(&lmb, CONFIG_SYS_MALLOC_LEN + total_size, SZ_4K);
+	size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE),
+	reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
 
-	if (reg)
-		return ALIGN(reg + CONFIG_SYS_MALLOC_LEN + total_size, SZ_4K);
+	if (!reg)
+		reg = gd->ram_top - size;
 
-	return gd->ram_top;
+	mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION);
+
+	return reg + size;
 }
-- 
2.17.1

[PATCH 2/8] stm32mp: update the mmu configuration for SPL and prereloc

[Patrick Delaunay]

Overidde the weak function dram_bank_mmu_setup() to set the DDR
(preloc case) or the SYSRAM (in SPL case) executable before to enable
the MMU and configure DACR.

This weak function is called in dcache_enable/mmu_setup.

This patchs avoids a permission access issue when the DDR is marked
executable (by calling mmu_set_region_dcache_behaviour with
DCACHE_DEFAULT_OPTION) after MMU setup and domain access permission
activation with DACR in dcache_enable.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
---

 arch/arm/mach-stm32mp/cpu.c | 40 +++++++++++++++++++++++++++----------
 1 file changed, 30 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index 717f80e9ff..030066dc7c 100644
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -210,6 +210,35 @@ u32 get_bootmode(void)
 		    TAMP_BOOT_MODE_SHIFT;
 }
 
+/*
+ * weak function overidde: set the DDR/SYSRAM executable before to enable the
+ * MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc)
+ */
+void dram_bank_mmu_setup(int bank)
+{
+	struct bd_info *bd = gd->bd;
+	int	i;
+	phys_addr_t start;
+	phys_size_t size;
+
+	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+		start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
+		size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
+	} else if (gd->flags & GD_FLG_RELOC) {
+		/* bd->bi_dram is available only after relocation */
+		start = bd->bi_dram[bank].start;
+		size =  bd->bi_dram[bank].size;
+	} else {
+		/* mark cacheable and executable the beggining of the DDR */
+		start = STM32_DDR_BASE;
+		size = CONFIG_DDR_CACHEABLE_SIZE;
+	}
+
+	for (i = start >> MMU_SECTION_SHIFT;
+	     i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
+	     i++)
+		set_section_dcache(i, DCACHE_DEFAULT_OPTION);
+}
 /*
  * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
  * MMU/TLB is updated in enable_caches() for U-Boot after relocation
@@ -225,17 +254,8 @@ static void early_enable_caches(void)
 	gd->arch.tlb_size = PGTABLE_SIZE;
 	gd->arch.tlb_addr = (unsigned long)&early_tlb;
 
+	/* enable MMU (default configuration) */
 	dcache_enable();
-
-	if (IS_ENABLED(CONFIG_SPL_BUILD))
-		mmu_set_region_dcache_behaviour(
-			ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE),
-			ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE),
-			DCACHE_DEFAULT_OPTION);
-	else
-		mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
-						CONFIG_DDR_CACHEABLE_SIZE,
-						DCACHE_DEFAULT_OPTION);
 }
 
 /*
-- 
2.17.1

[PATCH 3/8] arm: remove TTB_SECT_XN_MASK in DCACHE_WRITETHROUGH

[Patrick Delaunay]

The normal memory (other that DCACHE_OFF) should be executable by default,
only the device memory (DCACHE_OFF) used for peripheral access should have
the bit execute never (TTB_SECT_XN_MASK).

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
---

 arch/arm/include/asm/system.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 5fe83699f4..9db64dd69d 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -489,7 +489,7 @@ enum dcache_option {
  */
 enum dcache_option {
 	DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
-	DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
+	DCACHE_WRITETHROUGH = TTB_SECT_DOMAIN(0) | TTB_SECT | TTB_SECT_C_MASK,
 	DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
 	DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
 };
-- 
2.17.1

[PATCH 4/8] arm: cosmetic: align TTB_SECT define value

[Patrick Delaunay]

Align TTB_SECT define value with previous value.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
---

 arch/arm/include/asm/system.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 9db64dd69d..289b820a6d 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -475,7 +475,7 @@ enum dcache_option {
 #define TTB_SECT_XN_MASK	(1 << 4)
 #define TTB_SECT_C_MASK		(1 << 3)
 #define TTB_SECT_B_MASK		(1 << 2)
-#define TTB_SECT			(2 << 0)
+#define TTB_SECT		(2 << 0)
 
 /*
  * Short-descriptor format memory region attributes, without TEX remap
-- 
2.17.1

[PATCH 5/8] arm: cp15: update DACR value to activate access control

[Patrick Delaunay]

Update the initial value of Domain Access Control Register (DACR)
and set by default the access permission to client (DACR_Dn_CLIENT = 1U)
for each of the 16 domains and no more to all-supervisor
(DACR_Dn_MANAGER = 3U).

This patch allows to activate the domain checking in MMU against the
permission bits in the translation tables and avoids prefetching issue
on ARMv7 [1].

Today it was already done for OMAP2 architecture
./arch/arm/mach-omap2/omap-cache.c::arm_init_domains
introduced by commit de63ac278cba ("ARM: mmu: Set domain permissions
to client access") which fixes lot of speculative prefetch aborts seen
on OMAP5 secure devices.

[1] https://developer.arm.com/documentation/ddi0406/b/System-Level-Architecture/Virtual-Memory-System-Architecture--VMSA-/Memory-access-control/The-Execute-Never--XN--attribute-and-instruction-prefetching

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reported-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
---

 arch/arm/lib/cache-cp15.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index abd81d21c7..f78ce33b18 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -202,9 +202,12 @@ static inline void mmu_setup(void)
 	asm volatile("mcr p15, 0, %0, c2, c0, 0"
 		     : : "r" (gd->arch.tlb_addr) : "memory");
 #endif
-	/* Set the access control to all-supervisor */
+	/*
+	 * initial value of Domain Access Control Register (DACR)
+	 * Set the access control to client (1U) for each of the 16 domains
+	 */
 	asm volatile("mcr p15, 0, %0, c3, c0, 0"
-		     : : "r" (~0));
+		     : : "r" (0x55555555));
 
 	arm_init_domains();
 
-- 
2.17.1

[PATCH 6/8] arm: omap2: remove arm_init_domains

[Patrick Delaunay]

Remove the arm_init_domains and the DACR update, as it is now done
in ARMv7 CP15 level.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
---

 arch/arm/mach-omap2/omap-cache.c | 17 -----------------
 1 file changed, 17 deletions(-)

diff --git a/arch/arm/mach-omap2/omap-cache.c b/arch/arm/mach-omap2/omap-cache.c
index 502ea6987a..451d8e4542 100644
--- a/arch/arm/mach-omap2/omap-cache.c
+++ b/arch/arm/mach-omap2/omap-cache.c
@@ -40,9 +40,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ARMV7_DCACHE_POLICY	DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK
 #endif
 
-#define ARMV7_DOMAIN_CLIENT	1
-#define ARMV7_DOMAIN_MASK	(0x3 << 0)
-
 void enable_caches(void)
 {
 
@@ -66,17 +63,3 @@ void dram_bank_mmu_setup(int bank)
 	for (i = start; i < end; i++)
 		set_section_dcache(i, ARMV7_DCACHE_POLICY);
 }
-
-void arm_init_domains(void)
-{
-	u32 reg;
-
-	reg = get_dacr();
-	/*
-	* Set DOMAIN to client access so that all permissions
-	* set in pagetables are validated by the mmu.
-	*/
-	reg &= ~ARMV7_DOMAIN_MASK;
-	reg |= ARMV7_DOMAIN_CLIENT;
-	set_dacr(reg);
-}
-- 
2.17.1

[PATCH 7/8] arm: cp15: remove weak function arm_init_domains

[Patrick Delaunay]

Remove the unused weak function arm_init_domains used to change the
DACR value.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
---

 arch/arm/cpu/armv7/cache_v7.c | 3 ---
 arch/arm/include/asm/cache.h  | 1 -
 arch/arm/lib/cache-cp15.c     | 6 ------
 3 files changed, 10 deletions(-)

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 146cf52608..19ff432352 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -176,9 +176,6 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop)
 {
 }
 
-void arm_init_domains(void)
-{
-}
 #endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index c20e05ec7f..b10edf805b 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -35,7 +35,6 @@ void l2_cache_disable(void);
 void set_section_dcache(int section, enum dcache_option option);
 
 void arm_init_before_mmu(void);
-void arm_init_domains(void);
 void cpu_cache_initialization(void);
 void dram_bank_mmu_setup(int bank);
 
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index f78ce33b18..8a49e5217c 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -21,10 +21,6 @@ __weak void arm_init_before_mmu(void)
 {
 }
 
-__weak void arm_init_domains(void)
-{
-}
-
 static void set_section_phys(int section, phys_addr_t phys,
 			     enum dcache_option option)
 {
@@ -209,8 +205,6 @@ static inline void mmu_setup(void)
 	asm volatile("mcr p15, 0, %0, c3, c0, 0"
 		     : : "r" (0x55555555));
 
-	arm_init_domains();
-
 	/* and enable the mmu */
 	reg = get_cr();	/* get control reg. */
 	set_cr(reg | CR_M);
-- 
2.17.1

[PATCH 8/8] arm: remove set_dacr/get_dacr functions

[Patrick Delaunay]

Remove the unused function set_dacr/get_dacr

Serie-cc: Ard Biesheuvel <ardb@kernel.org>
Serie-cc: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
---

 arch/arm/include/asm/system.h | 14 --------------
 1 file changed, 14 deletions(-)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 289b820a6d..11fceec4d2 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -397,20 +397,6 @@ static inline void set_cr(unsigned int val)
 	isb();
 }
 
-static inline unsigned int get_dacr(void)
-{
-	unsigned int val;
-	asm("mrc p15, 0, %0, c3, c0, 0	@ get DACR" : "=r" (val) : : "cc");
-	return val;
-}
-
-static inline void set_dacr(unsigned int val)
-{
-	asm volatile("mcr p15, 0, %0, c3, c0, 0	@ set DACR"
-	  : : "r" (val) : "cc");
-	isb();
-}
-
 #ifdef CONFIG_ARMV7_LPAE
 /* Long-Descriptor Translation Table Level 1/2 Bits */
 #define TTB_SECT_XN_MASK	(1ULL << 54)
-- 
2.17.1

[PATCH 1/8] stm32mp: update MMU config before the relocation

[Tom Rini]

On Fri, Feb 05, 2021 at 01:53:32PM +0100, Patrick Delaunay wrote:

> Mark the top of ram, used for relocated U-Boot as a normal memory
> (cacheable and executable) to avoid permission access issue when
> U-Boot jumps to this relocated code.
> 
> When MMU is activated in pre-reloc stage; only the beginning of
> DDR is marked executable.
> 
> This patch avoids access issue when DACR is correctly managed.
> 
> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

Applied to u-boot/next, thanks!

-- 
Tom
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[PATCH 2/8] stm32mp: update the mmu configuration for SPL and prereloc

[Tom Rini]

On Fri, Feb 05, 2021 at 01:53:33PM +0100, Patrick Delaunay wrote:

> Overidde the weak function dram_bank_mmu_setup() to set the DDR
> (preloc case) or the SYSRAM (in SPL case) executable before to enable
> the MMU and configure DACR.
> 
> This weak function is called in dcache_enable/mmu_setup.
> 
> This patchs avoids a permission access issue when the DDR is marked
> executable (by calling mmu_set_region_dcache_behaviour with
> DCACHE_DEFAULT_OPTION) after MMU setup and domain access permission
> activation with DACR in dcache_enable.
> 
> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

Applied to u-boot/next, thanks!

-- 
Tom
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[PATCH 3/8] arm: remove TTB_SECT_XN_MASK in DCACHE_WRITETHROUGH

[Tom Rini]

On Fri, Feb 05, 2021 at 01:53:34PM +0100, Patrick Delaunay wrote:

> The normal memory (other that DCACHE_OFF) should be executable by default,
> only the device memory (DCACHE_OFF) used for peripheral access should have
> the bit execute never (TTB_SECT_XN_MASK).
> 
> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

Applied to u-boot/next, thanks!

-- 
Tom
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[PATCH 4/8] arm: cosmetic: align TTB_SECT define value

[Tom Rini]

On Fri, Feb 05, 2021 at 01:53:35PM +0100, Patrick Delaunay wrote:

> Align TTB_SECT define value with previous value.
> 
> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

Applied to u-boot/next, thanks!

-- 
Tom
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[PATCH 5/8] arm: cp15: update DACR value to activate access control

[Tom Rini]

On Fri, Feb 05, 2021 at 01:53:36PM +0100, Patrick Delaunay wrote:

> Update the initial value of Domain Access Control Register (DACR)
> and set by default the access permission to client (DACR_Dn_CLIENT = 1U)
> for each of the 16 domains and no more to all-supervisor
> (DACR_Dn_MANAGER = 3U).
> 
> This patch allows to activate the domain checking in MMU against the
> permission bits in the translation tables and avoids prefetching issue
> on ARMv7 [1].
> 
> Today it was already done for OMAP2 architecture
> ./arch/arm/mach-omap2/omap-cache.c::arm_init_domains
> introduced by commit de63ac278cba ("ARM: mmu: Set domain permissions
> to client access") which fixes lot of speculative prefetch aborts seen
> on OMAP5 secure devices.
> 
> [1] https://developer.arm.com/documentation/ddi0406/b/System-Level-Architecture/Virtual-Memory-System-Architecture--VMSA-/Memory-access-control/The-Execute-Never--XN--attribute-and-instruction-prefetching
> 
> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
> Reported-by: Ard Biesheuvel <ardb@kernel.org>
> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

Applied to u-boot/next, thanks!

-- 
Tom
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[PATCH 6/8] arm: omap2: remove arm_init_domains

[Tom Rini]

On Fri, Feb 05, 2021 at 01:53:37PM +0100, Patrick Delaunay wrote:

> Remove the arm_init_domains and the DACR update, as it is now done
> in ARMv7 CP15 level.
> 
> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

Applied to u-boot/next, thanks!

-- 
Tom
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[PATCH 7/8] arm: cp15: remove weak function arm_init_domains

[Tom Rini]

On Fri, Feb 05, 2021 at 01:53:38PM +0100, Patrick Delaunay wrote:

> Remove the unused weak function arm_init_domains used to change the
> DACR value.
> 
> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

Applied to u-boot/next, thanks!

-- 
Tom
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[PATCH 8/8] arm: remove set_dacr/get_dacr functions

[Tom Rini]

On Fri, Feb 05, 2021 at 01:53:39PM +0100, Patrick Delaunay wrote:

> Remove the unused function set_dacr/get_dacr
> 
> Serie-cc: Ard Biesheuvel <ardb@kernel.org>
> Serie-cc: R Sricharan <r.sricharan@ti.com>
> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

Applied to u-boot/next, thanks!

-- 
Tom
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