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From: Atish Patra <atish.patra@wdc.com>
To: linux-kernel@vger.kernel.org
Cc: "Atish Patra" <atish.patra@wdc.com>,
	"Bin Meng" <bin.meng@windriver.com>,
	"Anup Patel" <anup@brainfault.org>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Anup Patel" <anup.patel@wdc.com>,
	"Björn Töpel" <bjorn@kernel.org>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	Conor.Dooley@microchip.com,
	"Daire McNamara" <daire.mcnamara@microchip.com>,
	Ivan.Griffin@microchip.com, Lewis.Hanly@microchip.com
Subject: [PATCH v4 1/5] RISC-V: Add Microchip PolarFire SoC kconfig option
Date: Wed,  3 Mar 2021 12:02:49 -0800	[thread overview]
Message-ID: <20210303200253.1827553-2-atish.patra@wdc.com> (raw)
In-Reply-To: <20210303200253.1827553-1-atish.patra@wdc.com>

Add Microchip PolarFire kconfig option which selects SoC specific
and common drivers that is required for this SoC.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/Kconfig.socs | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 7efcece8896c..82b298bfd3be 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -1,5 +1,12 @@
 menu "SoC selection"
 
+config SOC_MICROCHIP_POLARFIRE
+	bool "Microchip PolarFire SoCs"
+	select MCHP_CLK_MPFS
+	select SIFIVE_PLIC
+	help
+	  This enables support for Microchip PolarFire SoC platforms.
+
 config SOC_SIFIVE
 	bool "SiFive SoCs"
 	select SERIAL_SIFIVE if TTY
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atish.patra@wdc.com>
To: linux-kernel@vger.kernel.org
Cc: "Atish Patra" <atish.patra@wdc.com>,
	"Bin Meng" <bin.meng@windriver.com>,
	"Anup Patel" <anup@brainfault.org>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Anup Patel" <anup.patel@wdc.com>,
	"Björn Töpel" <bjorn@kernel.org>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	Conor.Dooley@microchip.com,
	"Daire McNamara" <daire.mcnamara@microchip.com>,
	Ivan.Griffin@microchip.com, Lewis.Hanly@microchip.com
Subject: [PATCH v4 1/5] RISC-V: Add Microchip PolarFire SoC kconfig option
Date: Wed,  3 Mar 2021 12:02:49 -0800	[thread overview]
Message-ID: <20210303200253.1827553-2-atish.patra@wdc.com> (raw)
In-Reply-To: <20210303200253.1827553-1-atish.patra@wdc.com>

Add Microchip PolarFire kconfig option which selects SoC specific
and common drivers that is required for this SoC.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/Kconfig.socs | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 7efcece8896c..82b298bfd3be 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -1,5 +1,12 @@
 menu "SoC selection"
 
+config SOC_MICROCHIP_POLARFIRE
+	bool "Microchip PolarFire SoCs"
+	select MCHP_CLK_MPFS
+	select SIFIVE_PLIC
+	help
+	  This enables support for Microchip PolarFire SoC platforms.
+
 config SOC_SIFIVE
 	bool "SiFive SoCs"
 	select SERIAL_SIFIVE if TTY
-- 
2.25.1


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  reply	other threads:[~2021-03-04  0:02 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-03 20:02 [PATCH v4 0/5] Add Microchip PolarFire Soc Support Atish Patra
2021-03-03 20:02 ` Atish Patra
2021-03-03 20:02 ` Atish Patra [this message]
2021-03-03 20:02   ` [PATCH v4 1/5] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra
2021-03-03 20:02 ` [PATCH v4 2/5] dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC Atish Patra
2021-03-03 20:02   ` Atish Patra
2021-03-08 20:11   ` Rob Herring
2021-03-08 20:11     ` Rob Herring
2021-03-03 20:02 ` [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra
2021-03-03 20:02   ` Atish Patra
2021-03-09 10:56   ` Ben Dooks
2021-03-09 10:56     ` Ben Dooks
     [not found]     ` <DM6PR11MB3770E7FA8121AA91D9EDC4FEE5929@DM6PR11MB3770.namprd11.prod.outlook.com>
2021-03-09 19:34       ` Atish Patra
2021-03-09 19:34         ` Atish Patra
2021-03-22  6:04   ` Bin Meng
2021-03-22  6:04     ` Bin Meng
2021-03-27 17:22   ` Alex Ghiti
2021-03-27 17:22     ` Alex Ghiti
2021-03-28 15:22     ` Vitaly Wool
2021-03-28 15:22       ` Vitaly Wool
2021-04-18  3:36       ` Atish Patra
2021-04-18  3:36         ` Atish Patra
2021-04-18  4:24         ` Atish Patra
2021-04-18  4:24           ` Atish Patra
2021-04-18 18:39         ` Vitaly Wool
2021-04-18 18:39           ` Vitaly Wool
2021-03-03 20:02 ` [PATCH v4 4/5] RISC-V: Enable Microchip PolarFire ICICLE SoC Atish Patra
2021-03-03 20:02   ` Atish Patra
2021-03-03 20:02 ` [PATCH v4 5/5] MAINTAINERS: add microchip polarfire soc support Atish Patra
2021-03-03 20:02   ` Atish Patra
2021-03-30  4:17 ` [PATCH v4 0/5] Add Microchip PolarFire Soc Support Palmer Dabbelt
2021-03-30  4:17   ` Palmer Dabbelt
2021-04-18  3:26   ` Atish Patra
2021-04-18  3:26     ` Atish Patra
2021-04-22 22:33     ` Atish Patra
2021-04-22 22:33       ` Atish Patra
2021-04-23  1:37       ` Palmer Dabbelt
2021-04-23  1:37         ` Palmer Dabbelt
2021-04-23  8:44         ` Conor.Dooley
2021-04-23  8:44           ` Conor.Dooley

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