* [Intel-gfx] [PATCH 01/56] drm/i915/display: Convert gen5/gen6 tests to IS_IRONLAKE/IS_SANDYBRIDGE
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-12 16:50 ` Ville Syrjälä
2021-03-11 22:35 ` [Intel-gfx] [PATCH 02/56] drm/i915: Add DISPLAY_VER() Matt Roper
` (57 subsequent siblings)
58 siblings, 1 reply; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx
ILK is the only platform that we consider "gen5" and SNB is the only
platform we consider "gen6." Add an IS_SANDYBRIDGE() macro and then
replace numeric platform tests for these two generations with direct
platform tests with the following Coccinelle semantic patch:
@@ expression dev_priv; @@
- IS_GEN(dev_priv, 5)
+ IS_IRONLAKE(dev_priv)
@@ expression dev_priv; @@
- IS_GEN(dev_priv, 6)
+ IS_SANDYBRIDGE(dev_priv)
@@ expression dev_priv; @@
- IS_GEN_RANGE(dev_priv, 5, 6)
+ IS_SANDYBRIDGE(dev_priv) || IS_IRONLAKE(dev_priv)
This will simplify our upcoming patches which eliminate INTEL_GEN()
usage in the display code.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 4 ++--
drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
drivers/gpu/drm/i915/display/intel_cursor.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++------
drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 6 +++---
drivers/gpu/drm/i915/display/intel_fdi.c | 6 +++---
drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 2 +-
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 4 ++--
drivers/gpu/drm/i915/display/intel_pps.c | 6 +++---
drivers/gpu/drm/i915/display/intel_sprite.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 1 +
13 files changed, 30 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 8a52beaed2da..95933cc13d58 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -161,8 +161,8 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
dspcntr = DISPLAY_PLANE_ENABLE;
- if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
- IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
+ if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) ||
+ IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
switch (fb->format->format) {
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index a9019287f7d5..83678feb8897 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2916,9 +2916,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
dev_priv->display.get_cdclk = hsw_get_cdclk;
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
dev_priv->display.get_cdclk = vlv_get_cdclk;
- else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
+ else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
- else if (IS_GEN(dev_priv, 5))
+ else if (IS_IRONLAKE(dev_priv))
dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
else if (IS_GM45(dev_priv))
dev_priv->display.get_cdclk = gm45_get_cdclk;
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 21fe4d2753e9..3057179dd4eb 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -360,7 +360,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
to_i915(plane_state->uapi.plane->dev);
u32 cntl = 0;
- if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
+ if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
switch (drm_rect_width(&plane_state->uapi.dst)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5bfc06c46e28..f47bbe042a64 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -359,7 +359,7 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
u32 val;
/* ILK FDI PLL is always enabled */
- if (IS_GEN(dev_priv, 5))
+ if (IS_IRONLAKE(dev_priv))
return;
/* On Haswell, DDI ports are responsible for the FDI PLL setup */
@@ -7439,7 +7439,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
* plane, not only sprite plane.
*/
if (plane->id != PLANE_CURSOR &&
- (IS_GEN_RANGE(dev_priv, 5, 6) ||
+ (IS_SANDYBRIDGE(dev_priv) || IS_IRONLAKE(dev_priv) ||
IS_IVYBRIDGE(dev_priv)) &&
(turn_on || (!needs_scaling(old_plane_state) &&
needs_scaling(plane_state))))
@@ -11599,7 +11599,7 @@ static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
return false;
- if (IS_GEN(dev_priv, 5) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
+ if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
return false;
return true;
@@ -12407,12 +12407,12 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
{
- if (IS_GEN(dev_priv, 5)) {
+ if (IS_IRONLAKE(dev_priv)) {
u32 fdi_pll_clk =
intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
- } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
+ } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
dev_priv->fdi_pll_freq = 270000;
} else {
return;
@@ -13057,7 +13057,7 @@ static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
* without several WARNs, but for now let's take the easy
* road.
*/
- return IS_GEN(dev_priv, 6) &&
+ return IS_SANDYBRIDGE(dev_priv) &&
crtc_state->hw.active &&
crtc_state->shared_dpll &&
crtc_state->port_clock == 0;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b6b5776f5a66..31263250e7f9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2049,7 +2049,7 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp,
* 1. Wait for the start of vertical blank on the enabled pipe going to FDI
* 2. Program DP PLL enable
*/
- if (IS_GEN(dev_priv, 5))
+ if (IS_IRONLAKE(dev_priv))
intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
intel_dp->DP |= DP_PLL_ENABLE;
@@ -5399,7 +5399,7 @@ intel_dp_update_420(struct intel_dp *intel_dp)
* ILK doesn't seem capable of DP YCbCr output. The
* displayed image is severly corrupted. SNB+ is fine.
*/
- if (IS_GEN(i915, 5))
+ if (IS_IRONLAKE(i915))
return;
is_branch = drm_dp_is_branch(intel_dp->dpcd);
@@ -6817,7 +6817,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
dig_port->dp.set_signal_levels = vlv_set_signal_levels;
else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels;
- else if (IS_GEN(dev_priv, 6) && port == PORT_A)
+ else if (IS_SANDYBRIDGE(dev_priv) && port == PORT_A)
dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels;
else
dig_port->dp.set_signal_levels = g4x_set_signal_levels;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index eaebf123310a..4ba08aa4680b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -128,7 +128,7 @@ static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
to_i915(dig_port->base.base.dev);
u32 precharge, timeout;
- if (IS_GEN(dev_priv, 6))
+ if (IS_SANDYBRIDGE(dev_priv))
precharge = 3;
else
precharge = 5;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 5fd4fa4805ef..c7beda2e35bc 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -255,16 +255,16 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
if (params->fence_id >= 0) {
dpfc_ctl |= DPFC_CTL_FENCE_EN;
- if (IS_GEN(dev_priv, 5))
+ if (IS_IRONLAKE(dev_priv))
dpfc_ctl |= params->fence_id;
- if (IS_GEN(dev_priv, 6)) {
+ if (IS_SANDYBRIDGE(dev_priv)) {
intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
SNB_CPU_FENCE_ENABLE | params->fence_id);
intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
params->fence_y_offset);
}
} else {
- if (IS_GEN(dev_priv, 6)) {
+ if (IS_SANDYBRIDGE(dev_priv)) {
intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
}
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 60b29110099a..d719cd9c5b73 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -373,7 +373,7 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
temp = intel_de_read(dev_priv, reg);
temp &= ~FDI_LINK_TRAIN_NONE;
temp |= FDI_LINK_TRAIN_PATTERN_2;
- if (IS_GEN(dev_priv, 6)) {
+ if (IS_SANDYBRIDGE(dev_priv)) {
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
/* SNB-B */
temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
@@ -810,9 +810,9 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
void
intel_fdi_init_hook(struct drm_i915_private *dev_priv)
{
- if (IS_GEN(dev_priv, 5)) {
+ if (IS_IRONLAKE(dev_priv)) {
dev_priv->display.fdi_link_train = ilk_fdi_link_train;
- } else if (IS_GEN(dev_priv, 6)) {
+ } else if (IS_SANDYBRIDGE(dev_priv)) {
dev_priv->display.fdi_link_train = gen6_fdi_link_train;
} else if (IS_IVYBRIDGE(dev_priv)) {
/* FIXME: detect B0+ stepping and use auto training */
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index 813a4f7033e1..a3715cd42ed0 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -269,7 +269,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
if (HAS_GMCH(dev_priv))
i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
- else if (IS_GEN_RANGE(dev_priv, 5, 6))
+ else if (IS_SANDYBRIDGE(dev_priv) || IS_IRONLAKE(dev_priv))
ilk_set_fifo_underrun_reporting(dev, pipe, enable);
else if (IS_GEN(dev_priv, 7))
ivb_set_fifo_underrun_reporting(dev, pipe, enable, old);
diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
index a9a5df2fee4d..3c4024409d85 100644
--- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
@@ -415,7 +415,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
- else if (IS_GEN_RANGE(dev_priv, 5, 6))
+ else if (IS_SANDYBRIDGE(dev_priv) || IS_IRONLAKE(dev_priv))
return ilk_pipe_crc_ctl_reg(source, val);
else if (INTEL_GEN(dev_priv) < 9)
return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
@@ -545,7 +545,7 @@ intel_is_valid_crc_source(struct drm_i915_private *dev_priv,
return i9xx_crc_source_valid(dev_priv, source);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return vlv_crc_source_valid(dev_priv, source);
- else if (IS_GEN_RANGE(dev_priv, 5, 6))
+ else if (IS_SANDYBRIDGE(dev_priv) || IS_IRONLAKE(dev_priv))
return ilk_crc_source_valid(dev_priv, source);
else if (INTEL_GEN(dev_priv) < 9)
return ivb_crc_source_valid(dev_priv, source);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index f20ba71f4307..27477cafdc38 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -777,7 +777,7 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
pp = ilk_get_pp_control(intel_dp);
- if (IS_GEN(dev_priv, 5)) {
+ if (IS_IRONLAKE(dev_priv)) {
/* ILK workaround: disable reset around power sequence */
pp &= ~PANEL_POWER_RESET;
intel_de_write(dev_priv, pp_ctrl_reg, pp);
@@ -785,7 +785,7 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
}
pp |= PANEL_POWER_ON;
- if (!IS_GEN(dev_priv, 5))
+ if (!IS_IRONLAKE(dev_priv))
pp |= PANEL_POWER_RESET;
intel_de_write(dev_priv, pp_ctrl_reg, pp);
@@ -794,7 +794,7 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
wait_panel_on(intel_dp);
intel_dp->pps.last_power_on = jiffies;
- if (IS_GEN(dev_priv, 5)) {
+ if (IS_IRONLAKE(dev_priv)) {
pp |= PANEL_POWER_RESET; /* restore panel reset bit */
intel_de_write(dev_priv, pp_ctrl_reg, pp);
intel_de_posting_read(dev_priv, pp_ctrl_reg);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 4cbdb8fd4bb1..fb506409a63b 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1078,7 +1078,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
dvscntr = DVS_ENABLE;
- if (IS_GEN(dev_priv, 6))
+ if (IS_SANDYBRIDGE(dev_priv))
dvscntr |= DVS_TRICKLE_FEED_DISABLE;
switch (fb->format->format) {
@@ -1838,7 +1838,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
plane->min_cdclk = g4x_sprite_min_cdclk;
modifiers = i9xx_plane_format_modifiers;
- if (IS_GEN(dev_priv, 6)) {
+ if (IS_SANDYBRIDGE(dev_priv)) {
formats = snb_plane_formats;
num_formats = ARRAY_SIZE(snb_plane_formats);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1d45d7492d10..4fe90a9782e8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1356,6 +1356,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
#define IS_IRONLAKE_M(dev_priv) \
(IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
+#define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
INTEL_INFO(dev_priv)->gt == 1)
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Intel-gfx] [PATCH 01/56] drm/i915/display: Convert gen5/gen6 tests to IS_IRONLAKE/IS_SANDYBRIDGE
2021-03-11 22:35 ` [Intel-gfx] [PATCH 01/56] drm/i915/display: Convert gen5/gen6 tests to IS_IRONLAKE/IS_SANDYBRIDGE Matt Roper
@ 2021-03-12 16:50 ` Ville Syrjälä
0 siblings, 0 replies; 74+ messages in thread
From: Ville Syrjälä @ 2021-03-12 16:50 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Thu, Mar 11, 2021 at 02:35:37PM -0800, Matt Roper wrote:
> ILK is the only platform that we consider "gen5" and SNB is the only
> platform we consider "gen6." Add an IS_SANDYBRIDGE() macro and then
> replace numeric platform tests for these two generations with direct
> platform tests with the following Coccinelle semantic patch:
>
> @@ expression dev_priv; @@
> - IS_GEN(dev_priv, 5)
> + IS_IRONLAKE(dev_priv)
>
> @@ expression dev_priv; @@
> - IS_GEN(dev_priv, 6)
> + IS_SANDYBRIDGE(dev_priv)
>
> @@ expression dev_priv; @@
> - IS_GEN_RANGE(dev_priv, 5, 6)
> + IS_SANDYBRIDGE(dev_priv) || IS_IRONLAKE(dev_priv)
I'd probably make this IS_ILK||IS_SNB. Looks like we tend to use
the old->new order in most of the cases this touches.
> @@ -7439,7 +7439,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
> * plane, not only sprite plane.
> */
> if (plane->id != PLANE_CURSOR &&
> - (IS_GEN_RANGE(dev_priv, 5, 6) ||
> + (IS_SANDYBRIDGE(dev_priv) || IS_IRONLAKE(dev_priv) ||
> IS_IVYBRIDGE(dev_priv)) &&
> (turn_on || (!needs_scaling(old_plane_state) &&
> needs_scaling(plane_state))))
This is at least one case where the IS_SNB||IS_ILK order
makes things look confusing.
Apart from that I like it.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Intel-gfx] [PATCH 02/56] drm/i915: Add DISPLAY_VER()
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 01/56] drm/i915/display: Convert gen5/gen6 tests to IS_IRONLAKE/IS_SANDYBRIDGE Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 03/56] drm/i915/display: Eliminate most usage of INTEL_GEN() Matt Roper
` (56 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx
Although we've long referred to platforms by a single "GEN" number, the
hardware teams have recommended that we stop doing this since the
various component IP blocks are going to start using independent number
schemes with varying cadence. To support this, hardware platforms a bit
down the road are going to start providing MMIO registers that the
driver can read to obtain the "graphics version," "media version," and
"display version" without needing to do a PCI ID -> platform -> version
translation.
Although our current platforms don't yet expose these registers (and the
next couple we release probably won't have them yet either), the
hardware teams would still like to see us move to this independent
numbering scheme now in preparation. For i915 that means we should try
to eliminate all usage of INTEL_GEN() throughout our code and instead
replace it with separate GRAPHICS_VER(), MEDIA_VER(), and DISPLAY_VER()
constructs in the code. For old platforms, these will all usually give
the same value for each IP block (aside from a few special cases like
GLK which we can no more accurately represent as graphics=9 +
display=10), but future platforms will have more flexibility to bump IP
version numbers independently.
The next hardware platform we'll be upstreaming (very soon!) will have a
display version of 13 and a graphics version of 12, so let's just the
first step of breaking out DISPLAY_VER(), but leaving the rest of
INTEL_GEN() untouched for now. For now we'll automatically
derive the display version from the platform's INTEL_GEN() value except
in cases where an alternative display version is explicitly provided in
the device info structure.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.h | 3 +++
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4fe90a9782e8..5ec0524d3418 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1247,6 +1247,8 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
#define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
#define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
+#define DISPLAY_VER(i915) INTEL_INFO(i915)->display_ver
+
#define REVID_FOREVER 0xff
#define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a9f24f2bda33..3543611cf0fc 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -36,7 +36,7 @@
#include "i915_selftest.h"
#define PLATFORM(x) .platform = (x)
-#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
+#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1), .display_ver = x
#define I845_PIPE_OFFSETS \
.pipe_offsets = { \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index d44f64b57b7a..3c7db9c690f4 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -162,6 +162,9 @@ struct intel_device_info {
u8 gen;
u8 gt; /* GT number, 0 if undefined */
+
+ u8 display_ver;
+
intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
enum intel_platform platform;
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 03/56] drm/i915/display: Eliminate most usage of INTEL_GEN()
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 01/56] drm/i915/display: Convert gen5/gen6 tests to IS_IRONLAKE/IS_SANDYBRIDGE Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 02/56] drm/i915: Add DISPLAY_VER() Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 04/56] drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in intel_pm.c Matt Roper
` (55 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx
Use Coccinelle to convert most of the usage of INTEL_GEN() and IS_GEN()
in the display code to use DISPLAY_VER() comparisons instead. The
following semantic patch was used:
@@ expression dev_priv; @@
- INTEL_GEN(dev_priv)
+ DISPLAY_VER(dev_priv)
@@ expression dev_priv; expression E; @@
- !IS_GEN(dev_priv, E)
+ DISPLAY_VER(dev_priv) != E
@@ expression dev_priv; expression E; @@
- IS_GEN(dev_priv, E)
+ DISPLAY_VER(dev_priv) == E
@@
expression dev_priv;
expression from, until;
@@
- !IS_GEN_RANGE(dev_priv, from, until)
+ DISPLAY_VER(dev_priv) < from || DISPLAY_VER(dev_priv) > until
@@
expression dev_priv;
expression from, until;
statement S;
@@
- if (IS_GEN_RANGE(dev_priv, from, until)) S
+ if (DISPLAY_VER(dev_priv) >= from && DISPLAY_VER(dev_priv) <= until) S
@@
expression dev_priv;
expression from, until;
@@
- IS_GEN_RANGE(dev_priv, from, until)
+ (DISPLAY_VER(dev_priv) >= from && DISPLAY_VER(dev_priv) <= until)
There are still some display-related uses of INTEL_GEN() in intel_pm.c
(watermark code) and i915_irq.c. Those will be updated separately.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 52 ++--
drivers/gpu/drm/i915/display/icl_dsi.c | 14 +-
drivers/gpu/drm/i915/display/intel_atomic.c | 6 +-
drivers/gpu/drm/i915/display/intel_audio.c | 18 +-
drivers/gpu/drm/i915/display/intel_bios.c | 14 +-
drivers/gpu/drm/i915/display/intel_bw.c | 10 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 60 ++---
drivers/gpu/drm/i915/display/intel_color.c | 28 +--
.../gpu/drm/i915/display/intel_combo_phy.c | 8 +-
drivers/gpu/drm/i915/display/intel_crt.c | 12 +-
drivers/gpu/drm/i915/display/intel_crtc.c | 20 +-
drivers/gpu/drm/i915/display/intel_csr.c | 4 +-
drivers/gpu/drm/i915/display/intel_cursor.c | 12 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 108 ++++----
.../drm/i915/display/intel_ddi_buf_trans.c | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 236 +++++++++---------
.../drm/i915/display/intel_display_debugfs.c | 44 ++--
.../drm/i915/display/intel_display_power.c | 52 ++--
drivers/gpu/drm/i915/display/intel_dp.c | 46 ++--
drivers/gpu/drm/i915/display/intel_dp_aux.c | 10 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 20 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 12 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 20 +-
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 4 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 56 ++---
.../drm/i915/display/intel_fifo_underrun.c | 6 +-
drivers/gpu/drm/i915/display/intel_gmbus.c | 4 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 10 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 28 +--
drivers/gpu/drm/i915/display/intel_lvds.c | 12 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 12 +-
drivers/gpu/drm/i915/display/intel_panel.c | 18 +-
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 12 +-
drivers/gpu/drm/i915/display/intel_psr.c | 46 ++--
drivers/gpu/drm/i915/display/intel_sdvo.c | 8 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 12 +-
drivers/gpu/drm/i915/display/intel_tc.c | 8 +-
drivers/gpu/drm/i915/display/intel_tv.c | 8 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 8 +-
drivers/gpu/drm/i915/display/intel_vga.c | 4 +-
drivers/gpu/drm/i915/display/skl_scaler.c | 8 +-
.../drm/i915/display/skl_universal_plane.c | 66 ++---
42 files changed, 571 insertions(+), 569 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 95933cc13d58..ffc79b9fff8d 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -128,7 +128,7 @@ static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
else if (IS_IVYBRIDGE(dev_priv))
return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
i9xx_plane == PLANE_C;
- else if (INTEL_GEN(dev_priv) >= 4)
+ else if (DISPLAY_VER(dev_priv) >= 4)
return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
else
return i9xx_plane == PLANE_A;
@@ -141,9 +141,9 @@ static bool i9xx_plane_has_windowing(struct intel_plane *plane)
if (IS_CHERRYVIEW(dev_priv))
return i9xx_plane == PLANE_B;
- else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
+ else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
return false;
- else if (IS_GEN(dev_priv, 4))
+ else if (DISPLAY_VER(dev_priv) == 4)
return i9xx_plane == PLANE_C;
else
return i9xx_plane == PLANE_B ||
@@ -210,7 +210,7 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
return 0;
}
- if (INTEL_GEN(dev_priv) >= 4 &&
+ if (DISPLAY_VER(dev_priv) >= 4 &&
fb->modifier == I915_FORMAT_MOD_X_TILED)
dspcntr |= DISPPLANE_TILED;
@@ -249,7 +249,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
- if (INTEL_GEN(dev_priv) >= 4)
+ if (DISPLAY_VER(dev_priv) >= 4)
offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
plane_state, 0);
else
@@ -266,7 +266,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
* Linear surfaces seem to work just fine, even on hsw/bdw
* despite them not using the linear offset anymore.
*/
- if (INTEL_GEN(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) {
+ if (DISPLAY_VER(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) {
u32 alignment = intel_surf_alignment(fb, 0);
int cpp = fb->format->cpp[0];
@@ -305,7 +305,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
drm_WARN_ON(&dev_priv->drm, src_x > 8191 || src_y > 4095);
- } else if (INTEL_GEN(dev_priv) >= 4 &&
+ } else if (DISPLAY_VER(dev_priv) >= 4 &&
fb->modifier == I915_FORMAT_MOD_X_TILED) {
drm_WARN_ON(&dev_priv->drm, src_x > 4095 || src_y > 4095);
}
@@ -363,7 +363,7 @@ static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
if (crtc_state->csc_enable)
dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
- if (INTEL_GEN(dev_priv) < 5)
+ if (DISPLAY_VER(dev_priv) < 5)
dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
return dspcntr;
@@ -437,7 +437,7 @@ static void i9xx_update_plane(struct intel_plane *plane,
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
- if (INTEL_GEN(dev_priv) >= 4)
+ if (DISPLAY_VER(dev_priv) >= 4)
dspaddr_offset = plane_state->color_plane[0].offset;
else
dspaddr_offset = linear_offset;
@@ -447,7 +447,7 @@ static void i9xx_update_plane(struct intel_plane *plane,
intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
plane_state->color_plane[0].stride);
- if (INTEL_GEN(dev_priv) < 4) {
+ if (DISPLAY_VER(dev_priv) < 4) {
/*
* PLANE_A doesn't actually have a full window
* generator but let's assume we still need to
@@ -468,7 +468,7 @@ static void i9xx_update_plane(struct intel_plane *plane,
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
(y << 16) | x);
- } else if (INTEL_GEN(dev_priv) >= 4) {
+ } else if (DISPLAY_VER(dev_priv) >= 4) {
intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
linear_offset);
intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
@@ -481,7 +481,7 @@ static void i9xx_update_plane(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
- if (INTEL_GEN(dev_priv) >= 4)
+ if (DISPLAY_VER(dev_priv) >= 4)
intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
else
@@ -514,7 +514,7 @@ static void i9xx_disable_plane(struct intel_plane *plane,
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
- if (INTEL_GEN(dev_priv) >= 4)
+ if (DISPLAY_VER(dev_priv) >= 4)
intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
else
intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
@@ -669,7 +669,7 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
ret = val & DISPLAY_PLANE_ENABLE;
- if (INTEL_GEN(dev_priv) >= 5)
+ if (DISPLAY_VER(dev_priv) >= 5)
*pipe = plane->pipe;
else
*pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
@@ -729,7 +729,7 @@ i9xx_plane_max_stride(struct intel_plane *plane,
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- if (INTEL_GEN(dev_priv) >= 3) {
+ if (DISPLAY_VER(dev_priv) >= 3) {
if (modifier == I915_FORMAT_MOD_X_TILED)
return 8*1024;
else
@@ -779,7 +779,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
* On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
* port is hooked to pipe B. Hence we want plane A feeding pipe B.
*/
- if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4 &&
+ if (HAS_FBC(dev_priv) && DISPLAY_VER(dev_priv) < 4 &&
INTEL_NUM_PIPES(dev_priv) == 2)
plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
else
@@ -797,7 +797,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
formats = vlv_primary_formats;
num_formats = ARRAY_SIZE(vlv_primary_formats);
- } else if (INTEL_GEN(dev_priv) >= 4) {
+ } else if (DISPLAY_VER(dev_priv) >= 4) {
/*
* WaFP16GammaEnabling:ivb
* "Workaround : When using the 64-bit format, the plane
@@ -823,7 +823,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
num_formats = ARRAY_SIZE(i8xx_primary_formats);
}
- if (INTEL_GEN(dev_priv) >= 4)
+ if (DISPLAY_VER(dev_priv) >= 4)
plane_funcs = &i965_plane_funcs;
else
plane_funcs = &i8xx_plane_funcs;
@@ -838,7 +838,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
plane->min_cdclk = i9xx_plane_min_cdclk;
if (HAS_GMCH(dev_priv)) {
- if (INTEL_GEN(dev_priv) >= 4)
+ if (DISPLAY_VER(dev_priv) >= 4)
plane->max_stride = i965_plane_max_stride;
else
plane->max_stride = i9xx_plane_max_stride;
@@ -863,17 +863,17 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
plane->async_flip = g4x_primary_async_flip;
plane->enable_flip_done = bdw_primary_enable_flip_done;
plane->disable_flip_done = bdw_primary_disable_flip_done;
- } else if (INTEL_GEN(dev_priv) >= 7) {
+ } else if (DISPLAY_VER(dev_priv) >= 7) {
plane->async_flip = g4x_primary_async_flip;
plane->enable_flip_done = ivb_primary_enable_flip_done;
plane->disable_flip_done = ivb_primary_disable_flip_done;
- } else if (INTEL_GEN(dev_priv) >= 5) {
+ } else if (DISPLAY_VER(dev_priv) >= 5) {
plane->async_flip = g4x_primary_async_flip;
plane->enable_flip_done = ilk_primary_enable_flip_done;
plane->disable_flip_done = ilk_primary_disable_flip_done;
}
- if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
0, plane_funcs,
formats, num_formats,
@@ -895,14 +895,14 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
supported_rotations =
DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
DRM_MODE_REFLECT_X;
- } else if (INTEL_GEN(dev_priv) >= 4) {
+ } else if (DISPLAY_VER(dev_priv) >= 4) {
supported_rotations =
DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
} else {
supported_rotations = DRM_MODE_ROTATE_0;
}
- if (INTEL_GEN(dev_priv) >= 4)
+ if (DISPLAY_VER(dev_priv) >= 4)
drm_plane_create_rotation_property(&plane->base,
DRM_MODE_ROTATE_0,
supported_rotations);
@@ -985,7 +985,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
- if (INTEL_GEN(dev_priv) >= 4) {
+ if (DISPLAY_VER(dev_priv) >= 4) {
if (val & DISPPLANE_TILED) {
plane_config->tiling = I915_TILING_X;
fb->modifier = I915_FORMAT_MOD_X_TILED;
@@ -1006,7 +1006,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
- } else if (INTEL_GEN(dev_priv) >= 4) {
+ } else if (DISPLAY_VER(dev_priv) >= 4) {
if (plane_config->tiling)
offset = intel_de_read(dev_priv,
DSPTILEOFF(i9xx_plane));
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 7f2abc088a66..37e2d93d064c 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -457,7 +457,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
- if (IS_JSL_EHL(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
+ if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
tmp = intel_de_read(dev_priv,
ICL_PORT_PCS_DW1_AUX(phy));
tmp &= ~LATENCY_OPTIM_MASK;
@@ -592,7 +592,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
* a value '0' inside TA_PARAM_REGISTERS otherwise
* leave all fields at HW default values.
*/
- if (IS_GEN(dev_priv, 11)) {
+ if (DISPLAY_VER(dev_priv) == 11) {
if (afe_clk(encoder, crtc_state) <= 800000) {
for_each_dsi_port(port, intel_dsi->ports) {
tmp = intel_de_read(dev_priv,
@@ -692,7 +692,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
for_each_dsi_phy(phy, intel_dsi->phys) {
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
else
val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
@@ -774,7 +774,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
}
}
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
if (is_vid_mode(intel_dsi))
tmp |= BLANKING_PACKET_ENABLE;
}
@@ -1020,7 +1020,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
}
/* program TRANS_VBLANK register, should be same as vtotal programmed */
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
intel_de_write(dev_priv, VBLANK(dsi_trans),
@@ -1158,7 +1158,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
gen11_dsi_configure_transcoder(encoder, crtc_state);
/* Step 4l: Gate DDI clocks */
- if (IS_GEN(dev_priv, 11))
+ if (DISPLAY_VER(dev_priv) == 11)
gen11_dsi_gate_clocks(encoder);
}
@@ -1534,7 +1534,7 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
- int dsc_max_bpc = INTEL_GEN(dev_priv) >= 12 ? 12 : 10;
+ int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10;
bool use_dsc;
int ret;
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 27f7d7109ca3..8b1ecd86a688 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -332,7 +332,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
plane_state->hw.fb->format->is_yuv &&
plane_state->hw.fb->format->num_planes > 1) {
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- if (IS_GEN(dev_priv, 9) &&
+ if (DISPLAY_VER(dev_priv) == 9 &&
!IS_GEMINILAKE(dev_priv)) {
mode = SKL_PS_SCALER_MODE_NV12;
} else if (icl_is_hdr_plane(dev_priv, plane->id)) {
@@ -351,7 +351,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
if (linked)
mode |= PS_PLANE_Y_SEL(linked->id);
}
- } else if (INTEL_GEN(dev_priv) > 9 || IS_GEMINILAKE(dev_priv)) {
+ } else if (DISPLAY_VER(dev_priv) > 9 || IS_GEMINILAKE(dev_priv)) {
mode = PS_SCALER_MODE_NORMAL;
} else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
/*
@@ -460,7 +460,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
* isn't necessary to change between HQ and dyn mode
* on those platforms.
*/
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
continue;
plane = drm_plane_from_index(&dev_priv->drm, i);
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index f7de55707746..eefe211ed958 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -248,7 +248,7 @@ static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_sta
break;
}
- if (INTEL_GEN(dev_priv) < 12 && adjusted_mode->crtc_clock > 148500)
+ if (DISPLAY_VER(dev_priv) < 12 && adjusted_mode->crtc_clock > 148500)
i = ARRAY_SIZE(hdmi_audio_clock);
if (i == ARRAY_SIZE(hdmi_audio_clock)) {
@@ -586,14 +586,14 @@ static void enable_audio_dsc_wa(struct intel_encoder *encoder,
unsigned int hblank_early_prog, samples_room;
unsigned int val;
- if (INTEL_GEN(i915) < 11)
+ if (DISPLAY_VER(i915) < 11)
return;
val = intel_de_read(i915, AUD_CONFIG_BE);
- if (INTEL_GEN(i915) == 11)
+ if (DISPLAY_VER(i915) == 11)
val |= HBLANK_EARLY_ENABLE_ICL(pipe);
- else if (INTEL_GEN(i915) >= 12)
+ else if (DISPLAY_VER(i915) >= 12)
val |= HBLANK_EARLY_ENABLE_TGL(pipe);
if (crtc_state->dsc.compression_enable &&
@@ -933,7 +933,7 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
- } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
+ } else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
} else if (HAS_PCH_SPLIT(dev_priv)) {
@@ -1010,7 +1010,7 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
if (dev_priv->audio_power_refcount++ == 0) {
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (DISPLAY_VER(dev_priv) >= 9) {
intel_de_write(dev_priv, AUD_FREQ_CNTRL,
dev_priv->audio_freq_cntrl);
drm_dbg_kms(&dev_priv->drm,
@@ -1022,7 +1022,7 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
if (IS_GEMINILAKE(dev_priv))
glk_force_audio_cdclk(dev_priv, true);
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
intel_de_write(dev_priv, AUD_PIN_BUF_CTL,
(intel_de_read(dev_priv, AUD_PIN_BUF_CTL) | AUD_PIN_BUF_ENABLE));
}
@@ -1050,7 +1050,7 @@ static void i915_audio_component_codec_wake_override(struct device *kdev,
unsigned long cookie;
u32 tmp;
- if (INTEL_GEN(dev_priv) < 9)
+ if (DISPLAY_VER(dev_priv) < 9)
return;
cookie = i915_audio_component_get_power(kdev);
@@ -1296,7 +1296,7 @@ static void i915_audio_component_init(struct drm_i915_private *dev_priv)
return;
}
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (DISPLAY_VER(dev_priv) >= 9) {
dev_priv->audio_freq_cntrl = intel_de_read(dev_priv,
AUD_FREQ_CNTRL);
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index f3fa1441ce16..7d438d16973c 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -542,7 +542,7 @@ parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
bool alternate)
{
- switch (INTEL_GEN(dev_priv)) {
+ switch (DISPLAY_VER(dev_priv)) {
case 2:
return alternate ? 66667 : 48000;
case 3:
@@ -608,7 +608,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version)
* Only parse SDVO mappings on gens that could have SDVO. This isn't
* accurate and doesn't have to be, as long as it's not too strict.
*/
- if (!IS_GEN_RANGE(dev_priv, 3, 7)) {
+ if (DISPLAY_VER(dev_priv) < 3 || DISPLAY_VER(dev_priv) > 7) {
drm_dbg_kms(&dev_priv->drm, "Skipping SDVO device mapping\n");
return;
}
@@ -682,7 +682,7 @@ parse_driver_features(struct drm_i915_private *dev_priv,
if (!driver)
return;
- if (INTEL_GEN(dev_priv) >= 5) {
+ if (DISPLAY_VER(dev_priv) >= 5) {
/*
* Note that we consider BDB_DRIVER_FEATURE_INT_SDVO_LVDS
* to mean "eDP". The VBT spec doesn't agree with that
@@ -916,7 +916,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
*/
if (bdb->version >= 205 &&
(IS_GEN9_BC(dev_priv) || IS_GEMINILAKE(dev_priv) ||
- INTEL_GEN(dev_priv) >= 10)) {
+ DISPLAY_VER(dev_priv) >= 10)) {
switch (psr_table->tp1_wakeup_time) {
case 0:
dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
@@ -1825,7 +1825,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv,
is_hdmi = is_dvi && (child->device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0;
is_edp = is_dp && (child->device_type & DEVICE_TYPE_INTERNAL_CONNECTOR);
- if (port == PORT_A && is_dvi && INTEL_GEN(dev_priv) < 12) {
+ if (port == PORT_A && is_dvi && DISPLAY_VER(dev_priv) < 12) {
drm_dbg_kms(&dev_priv->drm,
"VBT claims port A supports DVI%s, ignoring\n",
is_hdmi ? "/HDMI" : "");
@@ -2564,8 +2564,8 @@ bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
dvo_port = child->dvo_port;
if (dvo_port == DVO_PORT_MIPIA ||
- (dvo_port == DVO_PORT_MIPIB && INTEL_GEN(dev_priv) >= 11) ||
- (dvo_port == DVO_PORT_MIPIC && INTEL_GEN(dev_priv) < 11)) {
+ (dvo_port == DVO_PORT_MIPIB && DISPLAY_VER(dev_priv) >= 11) ||
+ (dvo_port == DVO_PORT_MIPIC && DISPLAY_VER(dev_priv) < 11)) {
if (port)
*port = dvo_port - DVO_PORT_MIPIA;
return true;
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index d122b9965532..20dbc3759d27 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -77,7 +77,7 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
qi->num_points = dram_info->num_qgv_points;
- if (IS_GEN(dev_priv, 12))
+ if (DISPLAY_VER(dev_priv) == 12)
switch (dram_info->type) {
case INTEL_DRAM_DDR4:
qi->t_bl = 4;
@@ -89,7 +89,7 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
qi->t_bl = 16;
break;
}
- else if (IS_GEN(dev_priv, 11))
+ else if (DISPLAY_VER(dev_priv) == 11)
qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
if (drm_WARN_ON(&dev_priv->drm,
@@ -271,9 +271,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
icl_get_bw_info(dev_priv, &adls_sa_info);
else if (IS_ROCKETLAKE(dev_priv))
icl_get_bw_info(dev_priv, &rkl_sa_info);
- else if (IS_GEN(dev_priv, 12))
+ else if (DISPLAY_VER(dev_priv) == 12)
icl_get_bw_info(dev_priv, &tgl_sa_info);
- else if (IS_GEN(dev_priv, 11))
+ else if (DISPLAY_VER(dev_priv) == 11)
icl_get_bw_info(dev_priv, &icl_sa_info);
}
@@ -533,7 +533,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
u32 mask = (1 << num_qgv_points) - 1;
/* FIXME earlier gens need some checks too */
- if (INTEL_GEN(dev_priv) < 11)
+ if (DISPLAY_VER(dev_priv) < 11)
return 0;
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 83678feb8897..640b6423f23b 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1375,7 +1375,7 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
{
u32 val, ratio;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
icl_readout_refclk(dev_priv, cdclk_config);
else if (IS_CANNONLAKE(dev_priv))
cnl_readout_refclk(dev_priv, cdclk_config);
@@ -1397,7 +1397,7 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
* CNL+ have the ratio directly in the PLL enable register, gen9lp had
* it in a separate PLL control register.
*/
- if (INTEL_GEN(dev_priv) >= 10)
+ if (DISPLAY_VER(dev_priv) >= 10)
ratio = val & CNL_CDCLK_PLL_RATIO_MASK;
else
ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
@@ -1413,9 +1413,9 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
bxt_de_pll_readout(dev_priv, cdclk_config);
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
cdclk_config->bypass = cdclk_config->ref / 2;
- else if (INTEL_GEN(dev_priv) >= 11)
+ else if (DISPLAY_VER(dev_priv) >= 11)
cdclk_config->bypass = 50000;
else
cdclk_config->bypass = cdclk_config->ref;
@@ -1433,7 +1433,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
break;
case BXT_CDCLK_CD2X_DIV_SEL_1_5:
drm_WARN(&dev_priv->drm,
- IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,
+ IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 10,
"Unsupported divider\n");
div = 3;
break;
@@ -1441,7 +1441,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
div = 4;
break;
case BXT_CDCLK_CD2X_DIV_SEL_4:
- drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10,
+ drm_WARN(&dev_priv->drm,
+ DISPLAY_VER(dev_priv) >= 10,
"Unsupported divider\n");
div = 8;
break;
@@ -1530,12 +1531,12 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
{
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
if (pipe == INVALID_PIPE)
return TGL_CDCLK_CD2X_PIPE_NONE;
else
return TGL_CDCLK_CD2X_PIPE(pipe);
- } else if (INTEL_GEN(dev_priv) >= 11) {
+ } else if (DISPLAY_VER(dev_priv) >= 11) {
if (pipe == INVALID_PIPE)
return ICL_CDCLK_CD2X_PIPE_NONE;
else
@@ -1558,7 +1559,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
int ret;
/* Inform power controller of upcoming frequency change. */
- if (INTEL_GEN(dev_priv) >= 10)
+ if (DISPLAY_VER(dev_priv) >= 10)
ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
SKL_CDCLK_PREPARE_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE,
@@ -1591,7 +1592,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
break;
case 3:
drm_WARN(&dev_priv->drm,
- IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,
+ IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 10,
"Unsupported divider\n");
divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
break;
@@ -1599,13 +1600,14 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
divider = BXT_CDCLK_CD2X_DIV_SEL_2;
break;
case 8:
- drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10,
+ drm_WARN(&dev_priv->drm,
+ DISPLAY_VER(dev_priv) >= 10,
"Unsupported divider\n");
divider = BXT_CDCLK_CD2X_DIV_SEL_4;
break;
}
- if (INTEL_GEN(dev_priv) >= 10) {
+ if (DISPLAY_VER(dev_priv) >= 10) {
if (dev_priv->cdclk.hw.vco != 0 &&
dev_priv->cdclk.hw.vco != vco)
cnl_cdclk_pll_disable(dev_priv);
@@ -1636,7 +1638,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
if (pipe != INVALID_PIPE)
intel_wait_for_vblank(dev_priv, pipe);
- if (INTEL_GEN(dev_priv) >= 10) {
+ if (DISPLAY_VER(dev_priv) >= 10) {
ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
cdclk_config->voltage_level);
} else {
@@ -1661,7 +1663,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
intel_update_cdclk(dev_priv);
- if (INTEL_GEN(dev_priv) >= 10)
+ if (DISPLAY_VER(dev_priv) >= 10)
/*
* Can't read out the voltage level :(
* Let's just assume everything is as expected.
@@ -1795,7 +1797,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
*/
void intel_cdclk_init_hw(struct drm_i915_private *i915)
{
- if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
+ if (IS_GEN9_LP(i915) || DISPLAY_VER(i915) >= 10)
bxt_cdclk_init_hw(i915);
else if (IS_GEN9_BC(i915))
skl_cdclk_init_hw(i915);
@@ -1810,7 +1812,7 @@ void intel_cdclk_init_hw(struct drm_i915_private *i915)
*/
void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
{
- if (INTEL_GEN(i915) >= 10 || IS_GEN9_LP(i915))
+ if (DISPLAY_VER(i915) >= 10 || IS_GEN9_LP(i915))
bxt_cdclk_uninit_hw(i915);
else if (IS_GEN9_BC(i915))
skl_cdclk_uninit_hw(i915);
@@ -1850,7 +1852,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *b)
{
/* Older hw doesn't have the capability */
- if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv))
+ if (DISPLAY_VER(dev_priv) < 10 && !IS_GEN9_LP(dev_priv))
return false;
return a->cdclk != b->cdclk &&
@@ -1998,9 +2000,9 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int pixel_rate = crtc_state->pixel_rate;
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
return DIV_ROUND_UP(pixel_rate, 2);
- else if (IS_GEN(dev_priv, 9) ||
+ else if (DISPLAY_VER(dev_priv) == 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
return pixel_rate;
else if (IS_CHERRYVIEW(dev_priv))
@@ -2051,7 +2053,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
/* Display WA #1145: glk,cnl */
min_cdclk = max(316800, min_cdclk);
- } else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) {
+ } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) {
/* Display WA #1144: skl,bxt */
min_cdclk = max(432000, min_cdclk);
}
@@ -2061,7 +2063,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
* According to BSpec, "The CD clock frequency must be at least twice
* the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
*/
- if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
+ if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9)
min_cdclk = max(2 * 96000, min_cdclk);
/*
@@ -2588,14 +2590,14 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
{
int max_cdclk_freq = dev_priv->max_cdclk_freq;
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
return 2 * max_cdclk_freq;
- else if (IS_GEN(dev_priv, 9) ||
+ else if (DISPLAY_VER(dev_priv) == 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
return max_cdclk_freq;
else if (IS_CHERRYVIEW(dev_priv))
return max_cdclk_freq*95/100;
- else if (INTEL_GEN(dev_priv) < 4)
+ else if (DISPLAY_VER(dev_priv) < 4)
return 2*max_cdclk_freq*90/100;
else
return max_cdclk_freq*90/100;
@@ -2616,7 +2618,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
dev_priv->max_cdclk_freq = 552000;
else
dev_priv->max_cdclk_freq = 556800;
- } else if (INTEL_GEN(dev_priv) >= 11) {
+ } else if (DISPLAY_VER(dev_priv) >= 11) {
if (dev_priv->cdclk.hw.ref == 24000)
dev_priv->max_cdclk_freq = 648000;
else
@@ -2831,7 +2833,7 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
freq = pch_rawclk(dev_priv);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
freq = vlv_hrawclk(dev_priv);
- else if (INTEL_GEN(dev_priv) >= 3)
+ else if (DISPLAY_VER(dev_priv) >= 3)
freq = i9xx_hrawclk(dev_priv);
else
/* no rawclk on other platforms, or no need to know it */
@@ -2852,7 +2854,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
dev_priv->cdclk.table = rkl_cdclk_table;
- } else if (INTEL_GEN(dev_priv) >= 12) {
+ } else if (DISPLAY_VER(dev_priv) >= 12) {
dev_priv->display.set_cdclk = bxt_set_cdclk;
dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
@@ -2864,7 +2866,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
dev_priv->cdclk.table = icl_cdclk_table;
- } else if (INTEL_GEN(dev_priv) >= 11) {
+ } else if (DISPLAY_VER(dev_priv) >= 11) {
dev_priv->display.set_cdclk = bxt_set_cdclk;
dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
@@ -2906,7 +2908,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
}
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEN9_LP(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEN9_LP(dev_priv))
dev_priv->display.get_cdclk = bxt_get_cdclk;
else if (IS_GEN9_BC(dev_priv))
dev_priv->display.get_cdclk = skl_get_cdclk;
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index ff7dcb7088bf..558f21c6803b 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -173,7 +173,7 @@ static void ilk_update_pipe_csc(struct intel_crtc *crtc,
coeff[6] << 16 | coeff[7]);
intel_de_write(dev_priv, PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16);
- if (INTEL_GEN(dev_priv) >= 7) {
+ if (DISPLAY_VER(dev_priv) >= 7) {
intel_de_write(dev_priv, PIPE_CSC_POSTOFF_HI(pipe),
postoff[0]);
intel_de_write(dev_priv, PIPE_CSC_POSTOFF_ME(pipe),
@@ -225,7 +225,7 @@ static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
*/
return crtc_state->limited_color_range &&
(IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
- IS_GEN_RANGE(dev_priv, 9, 10));
+ (DISPLAY_VER(dev_priv) >= 9 && DISPLAY_VER(dev_priv) <= 10));
}
static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
@@ -530,7 +530,7 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state)
intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
crtc_state->gamma_mode);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
icl_load_csc_matrix(crtc_state);
else
ilk_load_csc_matrix(crtc_state);
@@ -737,7 +737,7 @@ static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state)
* ToDo: Extend the ABI to be able to program values
* from 3.0 to 7.0
*/
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0),
1 << 16);
intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1),
@@ -1222,7 +1222,7 @@ static bool need_plane_update(struct intel_plane *plane,
* We have to reconfigure that even if the plane is inactive.
*/
return crtc_state->active_planes & BIT(plane->id) ||
- (INTEL_GEN(dev_priv) < 9 &&
+ (DISPLAY_VER(dev_priv) < 9 &&
plane->id == PLANE_PRIMARY);
}
@@ -1709,7 +1709,7 @@ int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_stat
else
return i9xx_gamma_precision(crtc_state);
} else {
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
return icl_gamma_precision(crtc_state);
else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
return glk_gamma_precision(crtc_state);
@@ -2105,7 +2105,7 @@ void intel_color_init(struct intel_crtc *crtc)
dev_priv->display.color_commit = i9xx_color_commit;
dev_priv->display.load_luts = chv_load_luts;
dev_priv->display.read_luts = chv_read_luts;
- } else if (INTEL_GEN(dev_priv) >= 4) {
+ } else if (DISPLAY_VER(dev_priv) >= 4) {
dev_priv->display.color_check = i9xx_color_check;
dev_priv->display.color_commit = i9xx_color_commit;
dev_priv->display.load_luts = i965_load_luts;
@@ -2117,31 +2117,31 @@ void intel_color_init(struct intel_crtc *crtc)
dev_priv->display.read_luts = i9xx_read_luts;
}
} else {
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
dev_priv->display.color_check = icl_color_check;
- else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ else if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
dev_priv->display.color_check = glk_color_check;
- else if (INTEL_GEN(dev_priv) >= 7)
+ else if (DISPLAY_VER(dev_priv) >= 7)
dev_priv->display.color_check = ivb_color_check;
else
dev_priv->display.color_check = ilk_color_check;
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
dev_priv->display.color_commit = skl_color_commit;
else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
dev_priv->display.color_commit = hsw_color_commit;
else
dev_priv->display.color_commit = ilk_color_commit;
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 11) {
dev_priv->display.load_luts = icl_load_luts;
dev_priv->display.read_luts = icl_read_luts;
} else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
dev_priv->display.load_luts = glk_load_luts;
dev_priv->display.read_luts = glk_read_luts;
- } else if (INTEL_GEN(dev_priv) >= 8) {
+ } else if (DISPLAY_VER(dev_priv) >= 8) {
dev_priv->display.load_luts = bdw_load_luts;
- } else if (INTEL_GEN(dev_priv) >= 7) {
+ } else if (DISPLAY_VER(dev_priv) >= 7) {
dev_priv->display.load_luts = ivb_load_luts;
} else {
dev_priv->display.load_luts = ilk_load_luts;
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index c55813c6194a..5df57d16a401 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -278,7 +278,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
if (!icl_combo_phy_enabled(dev_priv, phy))
return false;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN0(phy),
ICL_PORT_TX_DW8_ODCC_CLK_SEL |
ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK,
@@ -401,7 +401,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);
skip_phy_misc:
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN0(phy));
val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK;
val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL;
@@ -473,7 +473,7 @@ static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
void intel_combo_phy_init(struct drm_i915_private *i915)
{
- if (INTEL_GEN(i915) >= 11)
+ if (DISPLAY_VER(i915) >= 11)
icl_combo_phys_init(i915);
else if (IS_CANNONLAKE(i915))
cnl_combo_phys_init(i915);
@@ -481,7 +481,7 @@ void intel_combo_phy_init(struct drm_i915_private *i915)
void intel_combo_phy_uninit(struct drm_i915_private *i915)
{
- if (INTEL_GEN(i915) >= 11)
+ if (DISPLAY_VER(i915) >= 11)
icl_combo_phys_uninit(i915);
else if (IS_CANNONLAKE(i915))
cnl_combo_phys_uninit(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 7f3d11c5ce3e..06ee0ba3388d 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -165,7 +165,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
u32 adpa;
- if (INTEL_GEN(dev_priv) >= 5)
+ if (DISPLAY_VER(dev_priv) >= 5)
adpa = ADPA_HOTPLUG_BITS;
else
adpa = 0;
@@ -356,7 +356,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
* DAC limit supposedly 355 MHz.
*/
max_clock = 270000;
- else if (IS_GEN_RANGE(dev_priv, 3, 4))
+ else if ((DISPLAY_VER(dev_priv) >= 3 && DISPLAY_VER(dev_priv) <= 4))
max_clock = 400000;
else
max_clock = 350000;
@@ -711,7 +711,7 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
/* Set the border color to purple. */
intel_uncore_write(uncore, bclrpat_reg, 0x500050);
- if (!IS_GEN(dev_priv, 2)) {
+ if (DISPLAY_VER(dev_priv) != 2) {
u32 pipeconf = intel_uncore_read(uncore, pipeconf_reg);
intel_uncore_write(uncore,
pipeconf_reg,
@@ -890,7 +890,7 @@ intel_crt_detect(struct drm_connector *connector,
if (ret > 0) {
if (intel_crt_detect_ddc(connector))
status = connector_status_connected;
- else if (INTEL_GEN(dev_priv) < 4)
+ else if (DISPLAY_VER(dev_priv) < 4)
status = intel_crt_load_detect(crt,
to_intel_crtc(connector->state->crtc)->pipe);
else if (dev_priv->params.load_detect_test)
@@ -949,7 +949,7 @@ void intel_crt_reset(struct drm_encoder *encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->dev);
struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
- if (INTEL_GEN(dev_priv) >= 5) {
+ if (DISPLAY_VER(dev_priv) >= 5) {
u32 adpa;
adpa = intel_de_read(dev_priv, crt->adpa_reg);
@@ -1047,7 +1047,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
else
crt->base.pipe_mask = ~0;
- if (IS_GEN(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
connector->interlace_allowed = 0;
else
connector->interlace_allowed = 1;
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 3248f49999bb..e4a8cb41501f 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -70,9 +70,9 @@ u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
(crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
return 0;
- if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
return 0xffffffff; /* full 32 bit counter */
- else if (INTEL_GEN(dev_priv) >= 3)
+ else if (DISPLAY_VER(dev_priv) >= 3)
return 0xffffff; /* only 24 bits of frame count */
else
return 0; /* Gen2 doesn't have a hardware frame counter */
@@ -265,7 +265,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
crtc->pipe = pipe;
crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
primary = skl_universal_plane_create(dev_priv, pipe,
PLANE_PRIMARY);
else
@@ -279,7 +279,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
for_each_sprite(dev_priv, pipe, sprite) {
struct intel_plane *plane;
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
plane = skl_universal_plane_create(dev_priv, pipe,
PLANE_SPRITE0 + sprite);
else
@@ -302,16 +302,16 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
if (IS_CHERRYVIEW(dev_priv) ||
IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
funcs = &g4x_crtc_funcs;
- else if (IS_GEN(dev_priv, 4))
+ else if (DISPLAY_VER(dev_priv) == 4)
funcs = &i965_crtc_funcs;
else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
funcs = &i915gm_crtc_funcs;
- else if (IS_GEN(dev_priv, 3))
+ else if (DISPLAY_VER(dev_priv) == 3)
funcs = &i915_crtc_funcs;
else
funcs = &i8xx_crtc_funcs;
} else {
- if (INTEL_GEN(dev_priv) >= 8)
+ if (DISPLAY_VER(dev_priv) >= 8)
funcs = &bdw_crtc_funcs;
else
funcs = &ilk_crtc_funcs;
@@ -327,7 +327,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
dev_priv->pipe_to_crtc_mapping[pipe] = crtc;
- if (INTEL_GEN(dev_priv) < 9) {
+ if (DISPLAY_VER(dev_priv) < 9) {
enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
@@ -335,7 +335,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
}
- if (INTEL_GEN(dev_priv) >= 10)
+ if (DISPLAY_VER(dev_priv) >= 10)
drm_crtc_create_scaling_filter_property(&crtc->base,
BIT(DRM_SCALING_FILTER_DEFAULT) |
BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
@@ -546,7 +546,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
* Incase of mipi dsi command mode, we need to set frame update
* request for every commit.
*/
- if (INTEL_GEN(dev_priv) >= 11 &&
+ if (DISPLAY_VER(dev_priv) >= 11 &&
intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
icl_dsi_frame_update(new_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index 42005c1b5f0e..82360593b0a6 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -705,11 +705,11 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
csr->fw_path = RKL_CSR_PATH;
csr->required_version = RKL_CSR_VERSION_REQUIRED;
csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
- } else if (INTEL_GEN(dev_priv) >= 12) {
+ } else if (DISPLAY_VER(dev_priv) >= 12) {
csr->fw_path = TGL_CSR_PATH;
csr->required_version = TGL_CSR_VERSION_REQUIRED;
csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
- } else if (IS_GEN(dev_priv, 11)) {
+ } else if (DISPLAY_VER(dev_priv) == 11) {
csr->fw_path = ICL_CSR_PATH;
csr->required_version = ICL_CSR_VERSION_REQUIRED;
csr->max_fw_size = ICL_CSR_MAX_FW_SIZE;
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 3057179dd4eb..0132ed3cb09d 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -338,7 +338,7 @@ static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 cntl = 0;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
return cntl;
if (crtc_state->gamma_enable)
@@ -347,7 +347,7 @@ static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
if (crtc_state->csc_enable)
cntl |= MCURSOR_PIPE_CSC_ENABLE;
- if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
+ if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
return cntl;
@@ -527,7 +527,7 @@ static void i9xx_update_cursor(struct intel_plane *plane,
* the CURCNTR write arms the update.
*/
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
skl_write_cursor_wm(plane, crtc_state);
if (!intel_crtc_needs_modeset(crtc_state))
@@ -583,7 +583,7 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
ret = val & MCURSOR_MODE;
- if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
*pipe = plane->pipe;
else
*pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
@@ -783,7 +783,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
if (ret)
goto fail;
- if (INTEL_GEN(dev_priv) >= 4)
+ if (DISPLAY_VER(dev_priv) >= 4)
drm_plane_create_rotation_property(&cursor->base,
DRM_MODE_ROTATE_0,
DRM_MODE_ROTATE_0 |
@@ -792,7 +792,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
drm_plane_enable_fb_damage_clips(&cursor->base);
drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ba83682e1d3e..3e641b36bbd3 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -174,7 +174,7 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
enum port port)
{
/* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
- if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
usleep_range(518, 1000);
return;
}
@@ -390,7 +390,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
temp = TRANS_DDI_FUNC_ENABLE;
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
temp |= TGL_TRANS_DDI_SELECT_PORT(port);
else
temp |= TRANS_DDI_SELECT_PORT(port);
@@ -458,7 +458,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
temp |= TRANS_DDI_MODE_SELECT_DP_MST;
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
enum transcoder master;
master = crtc_state->mst_master_transcoder;
@@ -471,7 +471,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
}
- if (IS_GEN_RANGE(dev_priv, 8, 10) &&
+ if ((DISPLAY_VER(dev_priv) >= 8 && DISPLAY_VER(dev_priv) <= 10) &&
crtc_state->master_transcoder != INVALID_TRANSCODER) {
u8 master_select =
bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
@@ -490,7 +490,7 @@ void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 11) {
enum transcoder master_transcoder = crtc_state->master_transcoder;
u32 ctl2 = 0;
@@ -536,7 +536,7 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 ctl;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
intel_de_write(dev_priv,
TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
@@ -546,11 +546,11 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
ctl &= ~TRANS_DDI_FUNC_ENABLE;
- if (IS_GEN_RANGE(dev_priv, 8, 10))
- ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
- TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
+ if (DISPLAY_VER(dev_priv) >= 8 && DISPLAY_VER(dev_priv) <= 10)
+ ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
- if (INTEL_GEN(dev_priv) >= 12) {
+
+ if (DISPLAY_VER(dev_priv) >= 12) {
if (!intel_dp_mst_is_master_trans(crtc_state)) {
ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
TRANS_DDI_MODE_SELECT_MASK);
@@ -714,7 +714,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
if (!trans_wakeref)
continue;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
port_mask = TGL_TRANS_DDI_PORT_MASK;
ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
} else {
@@ -854,7 +854,7 @@ void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
if (cpu_transcoder != TRANSCODER_EDP) {
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
intel_de_write(dev_priv,
TRANS_CLK_SEL(cpu_transcoder),
TGL_TRANS_CLK_SEL_PORT(port));
@@ -871,7 +871,7 @@ void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
if (cpu_transcoder != TRANSCODER_EDP) {
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
intel_de_write(dev_priv,
TRANS_CLK_SEL(cpu_transcoder),
TGL_TRANS_CLK_SEL_DISABLED);
@@ -971,12 +971,12 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
enum phy phy = intel_port_to_phy(dev_priv, port);
int n_entries;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
if (intel_phy_is_combo(dev_priv, phy))
tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
else
tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
- } else if (INTEL_GEN(dev_priv) == 11) {
+ } else if (DISPLAY_VER(dev_priv) == 11) {
if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
@@ -1147,7 +1147,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
int n_entries, ln;
u32 val;
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
ddi_translations = jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
@@ -2210,7 +2210,7 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
dig_port->tc_mode == TC_PORT_TBT_ALT)
return;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
HIP_INDEX_VAL(tc_port, 0x0));
ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
@@ -2276,7 +2276,7 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
MISSING_CASE(pin_assignment);
}
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
HIP_INDEX_VAL(tc_port, 0x0));
intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0);
@@ -2303,7 +2303,7 @@ i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));
else
return DP_TP_CTL(encoder->port);
@@ -2314,7 +2314,7 @@ i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));
else
return DP_TP_STATUS(encoder->port);
@@ -2621,7 +2621,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
int level = intel_ddi_dp_level(intel_dp);
- if (INTEL_GEN(dev_priv) < 11)
+ if (DISPLAY_VER(dev_priv) < 11)
drm_WARN_ON(&dev_priv->drm,
is_mst && (port == PORT_A || port == PORT_E));
else
@@ -2644,7 +2644,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
icl_program_mg_dp_mode(dig_port, crtc_state);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
icl_ddi_vswing_sequence(encoder, crtc_state, level);
else if (IS_CANNONLAKE(dev_priv))
cnl_ddi_vswing_sequence(encoder, crtc_state, level);
@@ -2663,7 +2663,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
true);
intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
intel_dp_start_link_train(intel_dp, crtc_state);
- if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
+ if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
!is_trans_port_sync_mode(crtc_state))
intel_dp_stop_link_train(intel_dp, crtc_state);
@@ -2683,7 +2683,7 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
else
hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
@@ -2818,7 +2818,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
*/
intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
if (is_mst) {
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
u32 val;
@@ -2843,7 +2843,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
* Configure Transcoder Clock select to direct no clock to the
* transcoder"
*/
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
intel_ddi_disable_pipe_clock(old_crtc_state);
intel_pps_vdd_on(intel_dp);
@@ -2904,7 +2904,7 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
intel_dsc_disable(old_crtc_state);
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
skl_scaler_disable(old_crtc_state);
else
ilk_pfit_disable(old_crtc_state);
@@ -3035,7 +3035,7 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state,
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
enum port port = encoder->port;
- if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
+ if (port == PORT_A && DISPLAY_VER(dev_priv) < 9)
intel_dp_stop_link_train(intel_dp, crtc_state);
intel_edp_backlight_on(crtc_state, conn_state);
@@ -3064,7 +3064,7 @@ gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
[PORT_E] = TRANSCODER_A,
};
- drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9);
+ drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9);
if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
port = PORT_A;
@@ -3090,9 +3090,9 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
"[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
connector->base.id, connector->name);
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
tgl_ddi_vswing_sequence(encoder, crtc_state, level);
- else if (INTEL_GEN(dev_priv) == 11)
+ else if (DISPLAY_VER(dev_priv) == 11)
icl_ddi_vswing_sequence(encoder, crtc_state, level);
else if (IS_CANNONLAKE(dev_priv))
cnl_ddi_vswing_sequence(encoder, crtc_state, level);
@@ -3424,7 +3424,7 @@ static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
* In this case there is requirement to wait for a minimum number of
* idle patterns to be sent.
*/
- if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
+ if (port == PORT_A && DISPLAY_VER(dev_priv) < 12)
return;
if (intel_de_wait_for_set(dev_priv,
@@ -3450,11 +3450,11 @@ static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
struct intel_crtc_state *crtc_state)
{
- if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000)
+ if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)
crtc_state->min_voltage_level = 2;
else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
crtc_state->min_voltage_level = 3;
- else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
+ else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
crtc_state->min_voltage_level = 1;
else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
crtc_state->min_voltage_level = 2;
@@ -3465,7 +3465,7 @@ static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *de
{
u32 master_select;
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 11) {
u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
@@ -3589,7 +3589,7 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
intel_dp_get_m_n(intel_crtc, pipe_config);
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 11) {
i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
pipe_config->fec_enable =
@@ -3613,7 +3613,7 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
pipe_config->lane_count =
((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
pipe_config->mst_master_transcoder =
REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
@@ -3700,7 +3700,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
HDMI_INFOFRAME_TYPE_DRM,
&pipe_config->infoframes.drm);
- if (INTEL_GEN(dev_priv) >= 8)
+ if (DISPLAY_VER(dev_priv) >= 8)
bdw_get_trans_port_sync_config(pipe_config);
intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
@@ -3934,7 +3934,7 @@ intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
* We don't enable port sync on BDW due to missing w/as and
* due to not having adjusted the modeset sequence appropriately.
*/
- if (INTEL_GEN(dev_priv) < 9)
+ if (DISPLAY_VER(dev_priv) < 9)
return 0;
if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
@@ -4029,9 +4029,9 @@ intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
dig_port->dp.set_link_train = intel_ddi_set_link_train;
dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
dig_port->dp.set_signal_levels = tgl_set_signal_levels;
- else if (INTEL_GEN(dev_priv) >= 11)
+ else if (DISPLAY_VER(dev_priv) >= 11)
dig_port->dp.set_signal_levels = icl_set_signal_levels;
else if (IS_CANNONLAKE(dev_priv))
dig_port->dp.set_signal_levels = cnl_set_signal_levels;
@@ -4300,7 +4300,7 @@ intel_ddi_max_lanes(struct intel_digital_port *dig_port)
enum port port = dig_port->base.port;
int max_lanes = 4;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
return max_lanes;
if (port == PORT_A || port == PORT_E) {
@@ -4402,9 +4402,9 @@ static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port por
static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port)
{
- if (INTEL_GEN(i915) >= 12)
+ if (DISPLAY_VER(i915) >= 12)
return port >= PORT_TC1;
- else if (INTEL_GEN(i915) >= 11)
+ else if (DISPLAY_VER(i915) >= 11)
return port >= PORT_C;
else
return false;
@@ -4461,7 +4461,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder = &dig_port->base;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
@@ -4471,7 +4471,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
port >= PORT_TC1 ? port_tc_name(port) : port_name(port),
tc_port != TC_PORT_NONE ? "TC" : "",
tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
- } else if (INTEL_GEN(dev_priv) >= 11) {
+ } else if (DISPLAY_VER(dev_priv) >= 11) {
enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
@@ -4540,7 +4540,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
encoder->get_config = icl_ddi_combo_get_config;
}
- } else if (INTEL_GEN(dev_priv) >= 11) {
+ } else if (DISPLAY_VER(dev_priv) >= 11) {
if (intel_ddi_is_tc(dev_priv, port)) {
encoder->enable_clock = icl_ddi_tc_enable_clock;
encoder->disable_clock = icl_ddi_tc_disable_clock;
@@ -4576,20 +4576,20 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
else if (IS_ROCKETLAKE(dev_priv))
encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
- else if (INTEL_GEN(dev_priv) >= 12)
+ else if (DISPLAY_VER(dev_priv) >= 12)
encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
else if (IS_JSL_EHL(dev_priv))
encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
- else if (IS_GEN(dev_priv, 11))
+ else if (DISPLAY_VER(dev_priv) == 11)
encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
- else if (IS_GEN(dev_priv, 10))
+ else if (DISPLAY_VER(dev_priv) == 10)
encoder->hpd_pin = cnl_hpd_pin(dev_priv, port);
- else if (IS_GEN(dev_priv, 9))
+ else if (DISPLAY_VER(dev_priv) == 9)
encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
else
encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
dig_port->saved_port_bits =
intel_de_read(dev_priv, DDI_BUF_CTL(port))
& DDI_BUF_PORT_REVERSAL;
@@ -4638,12 +4638,12 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
goto err;
}
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 11) {
if (intel_phy_is_tc(dev_priv, phy))
dig_port->connected = intel_tc_port_connected;
else
dig_port->connected = lpt_digital_port_connected;
- } else if (INTEL_GEN(dev_priv) >= 8) {
+ } else if (DISPLAY_VER(dev_priv) >= 8) {
if (port == PORT_A || IS_GEN9_LP(dev_priv))
dig_port->connected = bdw_digital_port_connected;
else
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index f65c2b35461c..50746e2725e8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1355,13 +1355,13 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder,
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
int n_entries;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
if (intel_phy_is_combo(dev_priv, phy))
tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
else
tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries);
*default_entry = n_entries - 1;
- } else if (INTEL_GEN(dev_priv) == 11) {
+ } else if (DISPLAY_VER(dev_priv) == 11) {
if (intel_phy_is_combo(dev_priv, phy))
icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
else
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f47bbe042a64..933b9d791691 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -227,7 +227,7 @@ static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
u32 line1, line2;
u32 line_mask;
- if (IS_GEN(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
line_mask = DSL_LINEMASK_GEN2;
else
line_mask = DSL_LINEMASK_GEN3;
@@ -267,7 +267,7 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- if (INTEL_GEN(dev_priv) >= 4) {
+ if (DISPLAY_VER(dev_priv) >= 4) {
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
i915_reg_t reg = PIPECONF(cpu_transcoder);
@@ -855,7 +855,7 @@ void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
{
- return IS_GEN(dev_priv, 2) ? 2048 : 4096;
+ return DISPLAY_VER(dev_priv) == 2 ? 2048 : 4096;
}
static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
@@ -891,7 +891,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
case DRM_FORMAT_MOD_LINEAR:
return intel_tile_size(dev_priv);
case I915_FORMAT_MOD_X_TILED:
- if (IS_GEN(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
return 128;
else
return 512;
@@ -906,7 +906,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
return 64;
fallthrough;
case I915_FORMAT_MOD_Y_TILED:
- if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
+ if (DISPLAY_VER(dev_priv) == 2 || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
else
return 512;
@@ -1024,12 +1024,12 @@ static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_pr
static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
{
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
return 256 * 1024;
else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return 128 * 1024;
- else if (INTEL_GEN(dev_priv) >= 4)
+ else if (DISPLAY_VER(dev_priv) >= 4)
return 4 * 1024;
else
return 0;
@@ -1037,7 +1037,7 @@ static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_pr
static bool has_async_flips(struct drm_i915_private *i915)
{
- return INTEL_GEN(i915) >= 5;
+ return DISPLAY_VER(i915) >= 5;
}
unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
@@ -1046,7 +1046,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
struct drm_i915_private *dev_priv = to_i915(fb->dev);
/* AUX_DIST needs only 4K alignment */
- if ((INTEL_GEN(dev_priv) < 12 && is_aux_plane(fb, color_plane)) ||
+ if ((DISPLAY_VER(dev_priv) < 12 && is_aux_plane(fb, color_plane)) ||
is_ccs_plane(fb, color_plane))
return 4096;
@@ -1067,7 +1067,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED:
- if (INTEL_GEN(dev_priv) >= 12 &&
+ if (DISPLAY_VER(dev_priv) >= 12 &&
is_semiplanar_uv_plane(fb, color_plane))
return intel_tile_row_size(fb, color_plane);
fallthrough;
@@ -1084,7 +1084,7 @@ static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- return INTEL_GEN(dev_priv) < 4 ||
+ return DISPLAY_VER(dev_priv) < 4 ||
(plane->has_fbc &&
plane_state->view.type == I915_GGTT_VIEW_NORMAL);
}
@@ -1167,7 +1167,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
* mode that matches the user configuration.
*/
ret = i915_vma_pin_fence(vma);
- if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
+ if (ret != 0 && DISPLAY_VER(dev_priv) < 4) {
i915_vma_unpin(vma);
vma = ERR_PTR(ret);
goto err;
@@ -1417,7 +1417,7 @@ static int intel_fb_offset_to_xy(int *x, int *y,
unsigned int height;
u32 alignment;
- if (INTEL_GEN(dev_priv) >= 12 &&
+ if (DISPLAY_VER(dev_priv) >= 12 &&
is_semiplanar_uv_plane(fb, color_plane))
alignment = intel_tile_row_size(fb, color_plane);
else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
@@ -1637,9 +1637,9 @@ u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
* The new CCS hash mode makes remapping impossible
*/
if (!is_ccs_modifier(modifier)) {
- if (INTEL_GEN(dev_priv) >= 7)
+ if (DISPLAY_VER(dev_priv) >= 7)
return 256*1024;
- else if (INTEL_GEN(dev_priv) >= 4)
+ else if (DISPLAY_VER(dev_priv) >= 4)
return 128*1024;
}
@@ -1679,13 +1679,13 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
* require the entire fb to accommodate that to avoid
* potential runtime errors at plane configuration time.
*/
- if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
+ if (DISPLAY_VER(dev_priv) == 9 && color_plane == 0 && fb->width > 3840)
tile_width *= 4;
/*
* The main surface pitch must be padded to a multiple of four
* tile widths.
*/
- else if (INTEL_GEN(dev_priv) >= 12)
+ else if (DISPLAY_VER(dev_priv) >= 12)
tile_width *= 4;
}
return tile_width;
@@ -1708,7 +1708,7 @@ bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
* Would also need to deal with the fence POT alignment
* and gen2 2KiB GTT tile size.
*/
- if (INTEL_GEN(dev_priv) < 4)
+ if (DISPLAY_VER(dev_priv) < 4)
return false;
/*
@@ -2394,7 +2394,7 @@ static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
* Gen2 reports pipe underruns whenever all planes are disabled.
* So disable underrun reporting before all the planes get disabled.
*/
- if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
+ if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
intel_disable_plane(plane, crtc_state);
@@ -3257,7 +3257,7 @@ static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
return false;
/* WA Display #0827: Gen9:all */
- if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
return true;
return false;
@@ -3268,7 +3268,7 @@ static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
/* Wa_2006604312:icl,ehl */
- if (crtc_state->scaler_state.scaler_users > 0 && IS_GEN(dev_priv, 11))
+ if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
return true;
return false;
@@ -3468,7 +3468,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
* chance of catching underruns with the intermediate watermarks
* vs. the old plane configuration.
*/
- if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
+ if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
/*
@@ -3866,7 +3866,7 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
val = MBUS_DBOX_A_CREDIT(2);
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
val |= MBUS_DBOX_BW_CREDIT(2);
val |= MBUS_DBOX_B_CREDIT(12);
} else {
@@ -3964,7 +3964,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
}
intel_set_pipe_src_size(new_crtc_state);
- if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
bdw_set_pipemisc(new_crtc_state);
if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {
@@ -3992,7 +3992,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
if (psl_clkgate_wa)
glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
skl_pfit_enable(new_crtc_state);
else
ilk_pfit_enable(new_crtc_state);
@@ -4004,18 +4004,18 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
intel_color_load_luts(new_crtc_state);
intel_color_commit(new_crtc_state);
/* update DSPCNTR to configure gamma/csc for pipe bottom color */
- if (INTEL_GEN(dev_priv) < 9)
+ if (DISPLAY_VER(dev_priv) < 9)
intel_disable_primary_plane(new_crtc_state);
hsw_set_linetime_wm(new_crtc_state);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
icl_set_pipe_chicken(crtc);
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
icl_pipe_mbus_enable(crtc);
if (new_crtc_state->bigjoiner_slave)
@@ -4156,7 +4156,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
return phy <= PHY_D;
else if (IS_JSL_EHL(dev_priv))
return phy <= PHY_C;
- else if (INTEL_GEN(dev_priv) >= 11)
+ else if (DISPLAY_VER(dev_priv) >= 11)
return phy <= PHY_B;
else
return false;
@@ -4189,7 +4189,7 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
return TC_PORT_NONE;
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
return TC_PORT_1 + port - PORT_TC1;
else
return TC_PORT_1 + port - PORT_C;
@@ -4441,7 +4441,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
crtc->active = true;
- if (!IS_GEN(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
intel_encoders_pre_enable(state, crtc);
@@ -4466,7 +4466,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
intel_encoders_enable(state, crtc);
/* prevents spurious underruns */
- if (IS_GEN(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
intel_wait_for_vblank(dev_priv, pipe);
}
@@ -4497,7 +4497,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
* On gen2 planes are double buffered but the pipe isn't, so we must
* wait for planes to fully turn off before disabling the pipe.
*/
- if (IS_GEN(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
intel_wait_for_vblank(dev_priv, pipe);
intel_encoders_disable(state, crtc);
@@ -4521,7 +4521,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
intel_encoders_post_pll_disable(state, crtc);
- if (!IS_GEN(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
if (!dev_priv->display.initial_watermarks)
@@ -4760,7 +4760,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
/* GDG double wide on either pipe, otherwise pipe A only */
- return INTEL_GEN(dev_priv) < 4 &&
+ return DISPLAY_VER(dev_priv) < 4 &&
(crtc->pipe == PIPE_A || IS_I915G(dev_priv));
}
@@ -4928,7 +4928,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
- if (INTEL_GEN(dev_priv) < 4) {
+ if (DISPLAY_VER(dev_priv) < 4) {
clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
/*
@@ -4974,7 +4974,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
/* Cantiga+ cannot handle modes with a hsync front porch of 0.
* WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
*/
- if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
+ if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) &&
pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
return -EINVAL;
@@ -5085,7 +5085,7 @@ static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
* Strictly speaking some registers are available before
* gen7, but we only support DRRS on gen7+
*/
- return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
+ return DISPLAY_VER(dev_priv) == 7 || IS_CHERRYVIEW(dev_priv);
}
static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
@@ -5097,7 +5097,7 @@ static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta
enum pipe pipe = crtc->pipe;
enum transcoder transcoder = crtc_state->cpu_transcoder;
- if (INTEL_GEN(dev_priv) >= 5) {
+ if (DISPLAY_VER(dev_priv) >= 5) {
intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
TU_SIZE(m_n->tu) | m_n->gmch_m);
intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
@@ -5185,7 +5185,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
vsyncshift += adjusted_mode->crtc_htotal;
}
- if (INTEL_GEN(dev_priv) > 3)
+ if (DISPLAY_VER(dev_priv) > 3)
intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
vsyncshift);
@@ -5232,10 +5232,10 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (IS_GEN(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
return false;
- if (INTEL_GEN(dev_priv) >= 9 ||
+ if (DISPLAY_VER(dev_priv) >= 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
else
@@ -5339,7 +5339,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
}
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
- if (INTEL_GEN(dev_priv) < 4 ||
+ if (DISPLAY_VER(dev_priv) < 4 ||
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
else
@@ -5365,7 +5365,7 @@ static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
if (IS_I830(dev_priv))
return false;
- return INTEL_GEN(dev_priv) >= 4 ||
+ return DISPLAY_VER(dev_priv) >= 4 ||
IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
}
@@ -5383,7 +5383,7 @@ static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
return;
/* Check whether the pfit is attached to our pipe. */
- if (INTEL_GEN(dev_priv) < 4) {
+ if (DISPLAY_VER(dev_priv) < 4) {
if (crtc->pipe != PIPE_B)
return;
} else {
@@ -5551,7 +5551,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
i9xx_get_pipe_color_config(pipe_config);
intel_color_get_config(pipe_config);
- if (INTEL_GEN(dev_priv) < 4)
+ if (DISPLAY_VER(dev_priv) < 4)
pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
intel_get_transcoder_timings(crtc, pipe_config);
@@ -5559,7 +5559,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
i9xx_get_pfit_config(pipe_config);
- if (INTEL_GEN(dev_priv) >= 4) {
+ if (DISPLAY_VER(dev_priv) >= 4) {
/* No way to read it out on pipes B and C */
if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
tmp = dev_priv->chv_dpll_md[crtc->pipe];
@@ -6239,12 +6239,12 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
val |= PIPEMISC_YUV420_ENABLE |
PIPEMISC_YUV420_MODE_FULL_BLEND;
- if (INTEL_GEN(dev_priv) >= 11 &&
+ if (DISPLAY_VER(dev_priv) >= 11 &&
(crtc_state->active_planes & ~(icl_hdr_plane_mask() |
BIT(PLANE_CURSOR))) == 0)
val |= PIPEMISC_HDR_MODE_PRECISION;
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
@@ -6307,7 +6307,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- if (INTEL_GEN(dev_priv) >= 5) {
+ if (DISPLAY_VER(dev_priv) >= 5) {
m_n->link_m = intel_de_read(dev_priv,
PIPE_LINK_M1(transcoder));
m_n->link_n = intel_de_read(dev_priv,
@@ -6427,7 +6427,7 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
* ivb/hsw (since we don't use the higher upscaling modes which
* differentiates them) so just WARN about this case for now.
*/
- drm_WARN_ON(&dev_priv->drm, IS_GEN(dev_priv, 7) &&
+ drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 &&
(ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
}
@@ -6562,7 +6562,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
enum transcoder panel_transcoder;
u32 tmp;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
panel_transcoder_mask |=
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
@@ -6701,7 +6701,7 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (!(tmp & TRANS_DDI_FUNC_ENABLE))
return;
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
else
port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
@@ -6712,7 +6712,7 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
* DDI E. So just check whether this pipe is wired to DDI E and whether
* the PCH transcoder is on.
*/
- if (INTEL_GEN(dev_priv) < 9 &&
+ if (DISPLAY_VER(dev_priv) < 9 &&
(port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
pipe_config->has_pch_encoder = true;
@@ -6759,7 +6759,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
/* we cannot read out most state, so don't bother.. */
pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
} else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
- INTEL_GEN(dev_priv) >= 11) {
+ DISPLAY_VER(dev_priv) >= 11) {
hsw_get_ddi_port_state(crtc, pipe_config);
intel_get_transcoder_timings(crtc, pipe_config);
}
@@ -6788,7 +6788,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
pipe_config->csc_mode = intel_de_read(dev_priv,
PIPE_CSC_MODE(crtc->pipe));
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (DISPLAY_VER(dev_priv) >= 9) {
tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
@@ -6810,7 +6810,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
skl_get_pfit_config(pipe_config);
else
ilk_get_pfit_config(pipe_config);
@@ -7110,7 +7110,7 @@ static int i9xx_pll_refclk(struct drm_device *dev,
return dev_priv->vbt.lvds_ssc_freq;
else if (HAS_PCH_SPLIT(dev_priv))
return 120000;
- else if (!IS_GEN(dev_priv, 2))
+ else if (DISPLAY_VER(dev_priv) != 2)
return 96000;
else
return 48000;
@@ -7143,7 +7143,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
}
- if (!IS_GEN(dev_priv, 2)) {
+ if (DISPLAY_VER(dev_priv) != 2) {
if (IS_PINEVIEW(dev_priv))
clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
@@ -7340,7 +7340,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
bool turn_off, turn_on, visible, was_visible;
int ret;
- if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
+ if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
ret = skl_update_scaler_plane(crtc_state, plane_state);
if (ret)
return ret;
@@ -7381,21 +7381,21 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
turn_off, turn_on, mode_changed);
if (turn_on) {
- if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
+ if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
crtc_state->update_wm_pre = true;
/* must disable cxsr around plane enable/disable */
if (plane->id != PLANE_CURSOR)
crtc_state->disable_cxsr = true;
} else if (turn_off) {
- if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
+ if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
crtc_state->update_wm_post = true;
/* must disable cxsr around plane enable/disable */
if (plane->id != PLANE_CURSOR)
crtc_state->disable_cxsr = true;
} else if (intel_wm_need_update(old_plane_state, plane_state)) {
- if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) {
/* FIXME bollocks */
crtc_state->update_wm_pre = true;
crtc_state->update_wm_post = true;
@@ -7512,7 +7512,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
struct intel_plane_state *plane_state;
int i;
- if (INTEL_GEN(dev_priv) < 11)
+ if (DISPLAY_VER(dev_priv) < 11)
return 0;
/*
@@ -7674,7 +7674,7 @@ static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_cdclk_state *cdclk_state;
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
crtc_state->linetime = skl_linetime_wm(crtc_state);
else
crtc_state->linetime = hsw_linetime_wm(crtc_state);
@@ -7701,7 +7701,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
bool mode_changed = intel_crtc_needs_modeset(crtc_state);
int ret;
- if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
+ if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) &&
mode_changed && !crtc_state->hw.active)
crtc_state->update_wm_post = true;
@@ -7755,7 +7755,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
}
}
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (DISPLAY_VER(dev_priv) >= 9) {
if (mode_changed || crtc_state->update_pipe) {
ret = skl_update_scaler_crtc(crtc_state);
if (ret)
@@ -7773,7 +7773,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
return ret;
}
- if (INTEL_GEN(dev_priv) >= 9 ||
+ if (DISPLAY_VER(dev_priv) >= 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
ret = hsw_compute_linetime_wm(state, crtc);
if (ret)
@@ -7878,7 +7878,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
IS_CHERRYVIEW(dev_priv)))
bpp = 10*3;
- else if (INTEL_GEN(dev_priv) >= 5)
+ else if (DISPLAY_VER(dev_priv) >= 5)
bpp = 12*3;
else
bpp = 8*3;
@@ -8147,7 +8147,7 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
pipe_config->linetime, pipe_config->ips_linetime);
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
drm_dbg_kms(&dev_priv->drm,
"num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
crtc->num_scalers,
@@ -8723,7 +8723,7 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
return dev_priv->params.fastboot;
/* Enable fastboot by default on Skylake and newer */
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
return true;
/* Enable fastboot by default on VLV and CHV */
@@ -8935,7 +8935,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(lane_count);
PIPE_CONF_CHECK_X(lane_lat_optim_mask);
- if (INTEL_GEN(dev_priv) < 8) {
+ if (DISPLAY_VER(dev_priv) < 8) {
PIPE_CONF_CHECK_M_N(dp_m_n);
if (current_config->has_drrs)
@@ -8994,7 +8994,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(output_format);
PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
- if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
+ if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
PIPE_CONF_CHECK_BOOL(limited_color_range);
@@ -9009,7 +9009,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_X(gmch_pfit.control);
/* pfit ratios are autocomputed by the hw on gen4+ */
- if (INTEL_GEN(dev_priv) < 4)
+ if (DISPLAY_VER(dev_priv) < 4)
PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
@@ -9093,7 +9093,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_X(dsi_pll.ctrl);
PIPE_CONF_CHECK_X(dsi_pll.div);
- if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
+ if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
PIPE_CONF_CHECK_I(pipe_bpp);
PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
@@ -9179,7 +9179,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
struct intel_plane *plane;
u8 hw_enabled_slices;
- if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
+ if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active)
return;
hw = kzalloc(sizeof(*hw), GFP_KERNEL);
@@ -9192,7 +9192,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
- if (INTEL_GEN(dev_priv) >= 11 &&
+ if (DISPLAY_VER(dev_priv) >= 11 &&
hw_enabled_slices != dev_priv->dbuf.enabled_slices)
drm_err(&dev_priv->drm,
"mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
@@ -9572,7 +9572,7 @@ intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
* However if queried just before the start of vblank we'll get an
* answer that's slightly in the future.
*/
- if (IS_GEN(dev_priv, 2)) {
+ if (DISPLAY_VER(dev_priv) == 2) {
int vtotal;
vtotal = adjusted_mode.crtc_vtotal;
@@ -9779,7 +9779,7 @@ static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
/* See {hsw,vlv,ivb}_plane_ratio() */
return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
- IS_IVYBRIDGE(dev_priv) || (INTEL_GEN(dev_priv) >= 11);
+ IS_IVYBRIDGE(dev_priv) || (DISPLAY_VER(dev_priv) >= 11);
}
static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
@@ -10455,7 +10455,7 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
+ if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
if (crtc_state->has_pch_encoder) {
@@ -10483,7 +10483,7 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
intel_set_pipe_src_size(new_crtc_state);
/* on skylake this is done by detaching scalers */
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (DISPLAY_VER(dev_priv) >= 9) {
skl_detach_scalers(new_crtc_state);
if (new_crtc_state->pch_pfit.enabled)
@@ -10503,11 +10503,11 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
* HSW/BDW only really need this here for fastboot, after
* that the value should not change without a full modeset.
*/
- if (INTEL_GEN(dev_priv) >= 9 ||
+ if (DISPLAY_VER(dev_priv) >= 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
hsw_set_linetime_wm(new_crtc_state);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
icl_set_pipe_chicken(crtc);
}
@@ -10530,10 +10530,10 @@ static void commit_pipe_config(struct intel_atomic_state *state,
new_crtc_state->update_pipe)
intel_color_commit(new_crtc_state);
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
skl_detach_scalers(new_crtc_state);
- if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
bdw_set_pipemisc(new_crtc_state);
if (new_crtc_state->update_pipe)
@@ -10599,7 +10599,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
commit_pipe_config(state, crtc);
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
skl_update_planes_on_crtc(state, crtc);
else
i9xx_update_planes_on_crtc(state, crtc);
@@ -11073,7 +11073,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
* chance of catching underruns with the intermediate watermarks
* vs. the new plane configuration.
*/
- if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
+ if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
if (dev_priv->display.optimize_watermarks)
@@ -11209,7 +11209,7 @@ static int intel_atomic_commit(struct drm_device *dev,
* FIXME doing watermarks and fb cleanup from a vblank worker
* (assuming we had any) would solve these problems.
*/
- if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
+ if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {
struct intel_crtc_state *new_crtc_state;
struct intel_crtc *crtc;
int i;
@@ -11306,7 +11306,7 @@ static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
if (!dma_fence_is_i915(fence))
return;
- if (INTEL_GEN(to_i915(crtc->dev)) < 6)
+ if (DISPLAY_VER(to_i915(crtc->dev)) < 6)
return;
if (drm_crtc_vblank_get(crtc))
@@ -11607,7 +11607,7 @@ static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
{
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
return false;
if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
@@ -11648,7 +11648,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_TC1);
intel_ddi_init(dev_priv, PORT_TC2);
- } else if (INTEL_GEN(dev_priv) >= 12) {
+ } else if (DISPLAY_VER(dev_priv) >= 12) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_TC1);
@@ -11664,7 +11664,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
intel_ddi_init(dev_priv, PORT_C);
intel_ddi_init(dev_priv, PORT_D);
icl_dsi_init(dev_priv);
- } else if (IS_GEN(dev_priv, 11)) {
+ } else if (DISPLAY_VER(dev_priv) == 11) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
@@ -11821,7 +11821,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
} else if (IS_PINEVIEW(dev_priv)) {
intel_lvds_init(dev_priv);
intel_crt_init(dev_priv);
- } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
+ } else if ((DISPLAY_VER(dev_priv) >= 3 && DISPLAY_VER(dev_priv) <= 4)) {
bool found = false;
if (IS_MOBILE(dev_priv))
@@ -11865,7 +11865,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (SUPPORTS_TV(dev_priv))
intel_tv_init(dev_priv);
- } else if (IS_GEN(dev_priv, 2)) {
+ } else if (DISPLAY_VER(dev_priv) == 2) {
if (IS_I85X(dev_priv))
intel_lvds_init(dev_priv);
@@ -11985,7 +11985,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
* gen2/3 display engine uses the fence if present,
* so the tiling mode must match the fb modifier exactly.
*/
- if (INTEL_GEN(dev_priv) < 4 &&
+ if (DISPLAY_VER(dev_priv) < 4 &&
tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
drm_dbg_kms(&dev_priv->drm,
"tiling_mode must match fb modifier exactly on gen2/3\n");
@@ -12130,18 +12130,18 @@ intel_mode_valid(struct drm_device *dev,
return MODE_BAD;
/* Transcoder timing limits */
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 11) {
hdisplay_max = 16384;
vdisplay_max = 8192;
htotal_max = 16384;
vtotal_max = 8192;
- } else if (INTEL_GEN(dev_priv) >= 9 ||
+ } else if (DISPLAY_VER(dev_priv) >= 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
vdisplay_max = 4096;
htotal_max = 8192;
vtotal_max = 8192;
- } else if (INTEL_GEN(dev_priv) >= 3) {
+ } else if (DISPLAY_VER(dev_priv) >= 3) {
hdisplay_max = 4096;
vdisplay_max = 4096;
htotal_max = 8192;
@@ -12165,7 +12165,7 @@ intel_mode_valid(struct drm_device *dev,
mode->vtotal > vtotal_max)
return MODE_V_ILLEGAL;
- if (INTEL_GEN(dev_priv) >= 5) {
+ if (DISPLAY_VER(dev_priv) >= 5) {
if (mode->hdisplay < 64 ||
mode->htotal - mode->hdisplay < 32)
return MODE_H_ILLEGAL;
@@ -12194,7 +12194,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
* intel_mode_valid() should be
* sufficient on older platforms.
*/
- if (INTEL_GEN(dev_priv) < 9)
+ if (DISPLAY_VER(dev_priv) < 9)
return MODE_OK;
/*
@@ -12202,7 +12202,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
* plane so let's not advertize modes that are
* too big for that.
*/
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 11) {
plane_width_max = 5120 << bigjoiner;
plane_height_max = 4320;
} else {
@@ -12242,7 +12242,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
intel_dpll_init_clock_hook(dev_priv);
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (DISPLAY_VER(dev_priv) >= 9) {
dev_priv->display.get_pipe_config = hsw_get_pipe_config;
dev_priv->display.crtc_enable = hsw_crtc_enable;
dev_priv->display.crtc_disable = hsw_crtc_disable;
@@ -12267,7 +12267,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
intel_fdi_init_hook(dev_priv);
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (DISPLAY_VER(dev_priv) >= 9) {
dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
dev_priv->display.get_initial_plane_config = skl_get_initial_plane_config;
} else {
@@ -12523,13 +12523,13 @@ static void intel_mode_config_init(struct drm_i915_private *i915)
* Maximum framebuffer dimensions, chosen to match
* the maximum render engine surface size on gen4+.
*/
- if (INTEL_GEN(i915) >= 7) {
+ if (DISPLAY_VER(i915) >= 7) {
mode_config->max_width = 16384;
mode_config->max_height = 16384;
- } else if (INTEL_GEN(i915) >= 4) {
+ } else if (DISPLAY_VER(i915) >= 4) {
mode_config->max_width = 8192;
mode_config->max_height = 8192;
- } else if (IS_GEN(i915, 3)) {
+ } else if (DISPLAY_VER(i915) == 3) {
mode_config->max_width = 4096;
mode_config->max_height = 4096;
} else {
@@ -12872,7 +12872,7 @@ intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
{
struct intel_crtc *crtc;
- if (INTEL_GEN(dev_priv) >= 4)
+ if (DISPLAY_VER(dev_priv) >= 4)
return;
for_each_intel_crtc(&dev_priv->drm, crtc) {
@@ -12931,7 +12931,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (INTEL_GEN(dev_priv) >= 9 ||
+ if (DISPLAY_VER(dev_priv) >= 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
u32 val;
@@ -13003,7 +13003,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
* Disable any background color set by the BIOS, but enable the
* gamma and CSC to match how we program our planes.
*/
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe),
SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE);
}
@@ -13328,7 +13328,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
*/
if (plane_state->uapi.visible && plane->min_cdclk) {
if (crtc_state->double_wide ||
- INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
crtc_state->min_cdclk[plane->id] =
DIV_ROUND_UP(crtc_state->pixel_rate, 2);
else
@@ -13419,7 +13419,7 @@ static void intel_early_display_was(struct drm_i915_private *dev_priv)
* Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
* Also known as Wa_14010480278.
*/
- if (IS_GEN_RANGE(dev_priv, 10, 12) || IS_GEMINILAKE(dev_priv))
+ if ((DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12) || IS_GEMINILAKE(dev_priv))
intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
@@ -13574,7 +13574,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
vlv_wm_get_hw_state(dev_priv);
vlv_wm_sanitize(dev_priv);
- } else if (INTEL_GEN(dev_priv) >= 9) {
+ } else if (DISPLAY_VER(dev_priv) >= 9) {
skl_wm_get_hw_state(dev_priv);
} else if (HAS_PCH_SPLIT(dev_priv)) {
ilk_wm_get_hw_state(dev_priv);
@@ -13843,16 +13843,16 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv)
error->plane[i].control = intel_de_read(dev_priv, DSPCNTR(i));
error->plane[i].stride = intel_de_read(dev_priv, DSPSTRIDE(i));
- if (INTEL_GEN(dev_priv) <= 3) {
+ if (DISPLAY_VER(dev_priv) <= 3) {
error->plane[i].size = intel_de_read(dev_priv,
DSPSIZE(i));
error->plane[i].pos = intel_de_read(dev_priv,
DSPPOS(i));
}
- if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
+ if (DISPLAY_VER(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
error->plane[i].addr = intel_de_read(dev_priv,
DSPADDR(i));
- if (INTEL_GEN(dev_priv) >= 4) {
+ if (DISPLAY_VER(dev_priv) >= 4) {
error->plane[i].surface = intel_de_read(dev_priv,
DSPSURF(i));
error->plane[i].tile_offset = intel_de_read(dev_priv,
@@ -13926,13 +13926,13 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
err_printf(m, "Plane [%d]:\n", i);
err_printf(m, " CNTR: %08x\n", error->plane[i].control);
err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
- if (INTEL_GEN(dev_priv) <= 3) {
+ if (DISPLAY_VER(dev_priv) <= 3) {
err_printf(m, " SIZE: %08x\n", error->plane[i].size);
err_printf(m, " POS: %08x\n", error->plane[i].pos);
}
- if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
+ if (DISPLAY_VER(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
- if (INTEL_GEN(dev_priv) >= 4) {
+ if (DISPLAY_VER(dev_priv) >= 4) {
err_printf(m, " SURF: %08x\n", error->plane[i].surface);
err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 20194ccfec05..1666aa23092b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -58,11 +58,11 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
if (intel_fbc_is_active(dev_priv)) {
u32 mask;
- if (INTEL_GEN(dev_priv) >= 8)
+ if (DISPLAY_VER(dev_priv) >= 8)
mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
- else if (INTEL_GEN(dev_priv) >= 7)
+ else if (DISPLAY_VER(dev_priv) >= 7)
mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
- else if (INTEL_GEN(dev_priv) >= 5)
+ else if (DISPLAY_VER(dev_priv) >= 5)
mask = intel_de_read(dev_priv, ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
else if (IS_G4X(dev_priv))
mask = intel_de_read(dev_priv, DPFC_STATUS) & DPFC_COMP_SEG_MASK;
@@ -83,7 +83,7 @@ static int i915_fbc_false_color_get(void *data, u64 *val)
{
struct drm_i915_private *dev_priv = data;
- if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
+ if (DISPLAY_VER(dev_priv) < 7 || !HAS_FBC(dev_priv))
return -ENODEV;
*val = dev_priv->fbc.false_color;
@@ -96,7 +96,7 @@ static int i915_fbc_false_color_set(void *data, u64 val)
struct drm_i915_private *dev_priv = data;
u32 reg;
- if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
+ if (DISPLAY_VER(dev_priv) < 7 || !HAS_FBC(dev_priv))
return -ENODEV;
mutex_lock(&dev_priv->fbc.lock);
@@ -128,7 +128,7 @@ static int i915_ips_status(struct seq_file *m, void *unused)
seq_printf(m, "Enabled by kernel parameter: %s\n",
yesno(dev_priv->params.enable_ips));
- if (INTEL_GEN(dev_priv) >= 8) {
+ if (DISPLAY_VER(dev_priv) >= 8) {
seq_puts(m, "Currently: unknown\n");
} else {
if (intel_de_read(dev_priv, IPS_CTL) & IPS_ENABLE)
@@ -150,7 +150,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
/* no global SR status; inspect per-plane WM */;
else if (HAS_PCH_SPLIT(dev_priv))
sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM1_LP_SR_EN;
@@ -550,7 +550,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
CSR_VERSION_MINOR(csr->version));
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
if (IS_DGFX(dev_priv)) {
dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
} else {
@@ -1190,7 +1190,7 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
struct skl_ddb_entry *entry;
struct intel_crtc *crtc;
- if (INTEL_GEN(dev_priv) < 9)
+ if (DISPLAY_VER(dev_priv) < 9)
return -ENODEV;
drm_modeset_lock_all(dev);
@@ -1339,7 +1339,7 @@ static int i915_lpsp_status(struct seq_file *m, void *unused)
{
struct drm_i915_private *i915 = node_to_i915(m->private);
- switch (INTEL_GEN(i915)) {
+ switch (DISPLAY_VER(i915)) {
case 12:
case 11:
LPSP_STATUS(!intel_lpsp_power_well_enabled(i915, ICL_DISP_PW_3));
@@ -1616,7 +1616,7 @@ static void wm_latency_show(struct seq_file *m, const u16 wm[8])
* - WM1+ latency values in 0.5us units
* - latencies are in us on gen9/vlv/chv
*/
- if (INTEL_GEN(dev_priv) >= 9 ||
+ if (DISPLAY_VER(dev_priv) >= 9 ||
IS_VALLEYVIEW(dev_priv) ||
IS_CHERRYVIEW(dev_priv) ||
IS_G4X(dev_priv))
@@ -1636,7 +1636,7 @@ static int pri_wm_latency_show(struct seq_file *m, void *data)
struct drm_i915_private *dev_priv = m->private;
const u16 *latencies;
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
latencies = dev_priv->wm.skl_latency;
else
latencies = dev_priv->wm.pri_latency;
@@ -1651,7 +1651,7 @@ static int spr_wm_latency_show(struct seq_file *m, void *data)
struct drm_i915_private *dev_priv = m->private;
const u16 *latencies;
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
latencies = dev_priv->wm.skl_latency;
else
latencies = dev_priv->wm.spr_latency;
@@ -1666,7 +1666,7 @@ static int cur_wm_latency_show(struct seq_file *m, void *data)
struct drm_i915_private *dev_priv = m->private;
const u16 *latencies;
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
latencies = dev_priv->wm.skl_latency;
else
latencies = dev_priv->wm.cur_latency;
@@ -1680,7 +1680,7 @@ static int pri_wm_latency_open(struct inode *inode, struct file *file)
{
struct drm_i915_private *dev_priv = inode->i_private;
- if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
+ if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
return -ENODEV;
return single_open(file, pri_wm_latency_show, dev_priv);
@@ -1759,7 +1759,7 @@ static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
struct drm_i915_private *dev_priv = m->private;
u16 *latencies;
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
latencies = dev_priv->wm.skl_latency;
else
latencies = dev_priv->wm.pri_latency;
@@ -1774,7 +1774,7 @@ static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
struct drm_i915_private *dev_priv = m->private;
u16 *latencies;
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
latencies = dev_priv->wm.skl_latency;
else
latencies = dev_priv->wm.spr_latency;
@@ -1789,7 +1789,7 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
struct drm_i915_private *dev_priv = m->private;
u16 *latencies;
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
latencies = dev_priv->wm.skl_latency;
else
latencies = dev_priv->wm.cur_latency;
@@ -1986,7 +1986,7 @@ static int i915_drrs_ctl_set(void *data, u64 val)
struct drm_device *dev = &dev_priv->drm;
struct intel_crtc *crtc;
- if (INTEL_GEN(dev_priv) < 7)
+ if (DISPLAY_VER(dev_priv) < 7)
return -ENODEV;
for_each_intel_crtc(dev, crtc) {
@@ -2244,7 +2244,7 @@ static int i915_lpsp_capability_show(struct seq_file *m, void *data)
if (connector->status != connector_status_connected)
return -ENODEV;
- switch (INTEL_GEN(i915)) {
+ switch (DISPLAY_VER(i915)) {
case 12:
/*
* Actually TGL can drive LPSP on port till DDI_C
@@ -2416,7 +2416,7 @@ int intel_connector_debugfs_add(struct drm_connector *connector)
connector, &i915_hdcp_sink_capability_fops);
}
- if (INTEL_GEN(dev_priv) >= 10 &&
+ if (DISPLAY_VER(dev_priv) >= 10 &&
((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort &&
!to_intel_connector(connector)->mst_port) ||
connector->connector_type == DRM_MODE_CONNECTOR_eDP))
@@ -2424,7 +2424,7 @@ int intel_connector_debugfs_add(struct drm_connector *connector)
connector, &i915_dsc_fec_support_fops);
/* Legacy panels doesn't lpsp on any platform */
- if ((INTEL_GEN(dev_priv) >= 9 || IS_HASWELL(dev_priv) ||
+ if ((DISPLAY_VER(dev_priv) >= 9 || IS_HASWELL(dev_priv) ||
IS_BROADWELL(dev_priv)) &&
(connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7e0eaa872350..e7546dc5caac 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -408,7 +408,7 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
if (power_well->desc->hsw.has_fuses) {
enum skl_power_gate pg;
- pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
+ pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
SKL_PW_CTL_IDX_TO_PG(pw_idx);
/*
* For PW1 we have to wait both for the PW0/PG0 fuse state
@@ -441,7 +441,7 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
if (power_well->desc->hsw.has_fuses) {
enum skl_power_gate pg;
- pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
+ pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
SKL_PW_CTL_IDX_TO_PG(pw_idx);
gen9_wait_for_power_well_fuses(dev_priv, pg);
}
@@ -484,7 +484,7 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
intel_de_write(dev_priv, regs->driver,
val | HSW_PWR_WELL_CTL_REQ(pw_idx));
- if (INTEL_GEN(dev_priv) < 12) {
+ if (DISPLAY_VER(dev_priv) < 12) {
val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy));
intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy),
val | ICL_LANE_ENABLE_AUX);
@@ -550,7 +550,7 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
if (drm_WARN_ON(&dev_priv->drm, !dig_port))
return;
- if (INTEL_GEN(dev_priv) == 11 && dig_port->tc_legacy_port)
+ if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port)
return;
drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
@@ -619,14 +619,14 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
* exit sequence.
*/
timeout_expected = is_tbt;
- if (INTEL_GEN(dev_priv) == 11 && dig_port->tc_legacy_port) {
+ if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port) {
icl_tc_cold_exit(dev_priv);
timeout_expected = true;
}
hsw_wait_for_power_well_enable(dev_priv, power_well, timeout_expected);
- if (INTEL_GEN(dev_priv) >= 12 && !is_tbt) {
+ if (DISPLAY_VER(dev_priv) >= 12 && !is_tbt) {
enum tc_port tc_port;
tc_port = TGL_AUX_PW_TO_TC_PORT(power_well->desc->hsw.idx);
@@ -709,7 +709,7 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
* BIOS's own request bits, which are forced-on for these power wells
* when exiting DC5/6.
*/
- if (IS_GEN(dev_priv, 9) && !IS_GEN9_LP(dev_priv) &&
+ if (DISPLAY_VER(dev_priv) == 9 && !IS_GEN9_LP(dev_priv) &&
(id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
val |= intel_de_read(dev_priv, regs->bios);
@@ -804,10 +804,10 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
mask = DC_STATE_EN_UPTO_DC5;
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
| DC_STATE_EN_DC9;
- else if (IS_GEN(dev_priv, 11))
+ else if (DISPLAY_VER(dev_priv) == 11)
mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
else if (IS_GEN9_LP(dev_priv))
mask |= DC_STATE_EN_DC9;
@@ -1035,7 +1035,7 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
enum i915_power_well_id high_pg;
/* Power wells at this level and above must be disabled for DC5 entry */
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
high_pg = ICL_DISP_PW_3;
else
high_pg = SKL_DISP_PW_2;
@@ -1192,7 +1192,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
if (IS_GEN9_LP(dev_priv))
bxt_verify_ddi_phy_power_wells(dev_priv);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
/*
* DMC retains HW context only for port A, the other combo
* PHY's HW context for port B is lost after DC transitions,
@@ -4535,9 +4535,9 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
if (IS_DG1(dev_priv))
max_dc = 3;
- else if (INTEL_GEN(dev_priv) >= 12)
+ else if (DISPLAY_VER(dev_priv) >= 12)
max_dc = 4;
- else if (INTEL_GEN(dev_priv) >= 10 || IS_GEN9_BC(dev_priv))
+ else if (DISPLAY_VER(dev_priv) >= 10 || IS_GEN9_BC(dev_priv))
max_dc = 2;
else if (IS_GEN9_LP(dev_priv))
max_dc = 1;
@@ -4549,7 +4549,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
* not depending on the DMC firmware. It's needed by system
* suspend/resume, so allow it unconditionally.
*/
- mask = IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 11 ?
+ mask = IS_GEN9_LP(dev_priv) || DISPLAY_VER(dev_priv) >= 11 ?
DC_STATE_EN_DC9 : 0;
if (!dev_priv->params.disable_power_well)
@@ -4678,9 +4678,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
} else if (IS_ROCKETLAKE(dev_priv)) {
err = set_power_wells(power_domains, rkl_power_wells);
- } else if (IS_GEN(dev_priv, 12)) {
+ } else if (DISPLAY_VER(dev_priv) == 12) {
err = set_power_wells(power_domains, tgl_power_wells);
- } else if (IS_GEN(dev_priv, 11)) {
+ } else if (DISPLAY_VER(dev_priv) == 11) {
err = set_power_wells(power_domains, icl_power_wells);
} else if (IS_CNL_WITH_PORT_F(dev_priv)) {
err = set_power_wells(power_domains, cnl_power_wells);
@@ -4837,7 +4837,7 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
* expect us to program the abox_ctl0 register as well, even though
* we don't have to program other instance-0 registers like BW_BUDDY.
*/
- if (IS_GEN(dev_priv, 12))
+ if (DISPLAY_VER(dev_priv) == 12)
abox_regs |= BIT(0);
for_each_set_bit(i, &abox_regs, sizeof(abox_regs))
@@ -5396,7 +5396,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
/* 4. Enable CDCLK. */
intel_cdclk_init_hw(dev_priv);
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
gen12_dbuf_slices_config(dev_priv);
/* 5. Enable DBUF. */
@@ -5406,14 +5406,14 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
icl_mbus_init(dev_priv);
/* 7. Program arbiter BW_BUDDY registers */
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
tgl_bw_buddy_init(dev_priv);
if (resume && dev_priv->csr.dmc_payload)
intel_csr_load_program(dev_priv);
/* Wa_14011508470 */
- if (IS_GEN(dev_priv, 12)) {
+ if (DISPLAY_VER(dev_priv) == 12) {
val = DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM |
DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR;
intel_uncore_rmw(&dev_priv->uncore, GEN11_CHICKEN_DCPR_2, 0, val);
@@ -5619,7 +5619,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
power_domains->initializing = true;
- if (INTEL_GEN(i915) >= 11) {
+ if (DISPLAY_VER(i915) >= 11) {
icl_display_core_init(i915, resume);
} else if (IS_CANNONLAKE(i915)) {
cnl_display_core_init(i915, resume);
@@ -5780,7 +5780,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
intel_display_power_flush_work(i915);
intel_power_domains_verify_state(i915);
- if (INTEL_GEN(i915) >= 11)
+ if (DISPLAY_VER(i915) >= 11)
icl_display_core_uninit(i915);
else if (IS_CANNONLAKE(i915))
cnl_display_core_uninit(i915);
@@ -5908,7 +5908,7 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
void intel_display_power_suspend_late(struct drm_i915_private *i915)
{
- if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
+ if (DISPLAY_VER(i915) >= 11 || IS_GEN9_LP(i915)) {
bxt_enable_dc9(i915);
/* Tweaked Wa_14010685332:icp,jsp,mcc */
if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC)
@@ -5921,7 +5921,7 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915)
void intel_display_power_resume_early(struct drm_i915_private *i915)
{
- if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
+ if (DISPLAY_VER(i915) >= 11 || IS_GEN9_LP(i915)) {
gen9_sanitize_dc_state(i915);
bxt_disable_dc9(i915);
/* Tweaked Wa_14010685332:icp,jsp,mcc */
@@ -5935,7 +5935,7 @@ void intel_display_power_resume_early(struct drm_i915_private *i915)
void intel_display_power_suspend(struct drm_i915_private *i915)
{
- if (INTEL_GEN(i915) >= 11) {
+ if (DISPLAY_VER(i915) >= 11) {
icl_display_core_uninit(i915);
bxt_enable_dc9(i915);
} else if (IS_GEN9_LP(i915)) {
@@ -5948,7 +5948,7 @@ void intel_display_power_suspend(struct drm_i915_private *i915)
void intel_display_power_resume(struct drm_i915_private *i915)
{
- if (INTEL_GEN(i915) >= 11) {
+ if (DISPLAY_VER(i915) >= 11) {
bxt_disable_dc9(i915);
icl_display_core_init(i915, true);
if (i915->csr.dmc_payload) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 31263250e7f9..04bf536f6a12 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -261,8 +261,8 @@ bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
struct intel_encoder *encoder = &intel_dig_port->base;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- return INTEL_GEN(dev_priv) >= 12 ||
- (INTEL_GEN(dev_priv) == 11 &&
+ return DISPLAY_VER(dev_priv) >= 12 ||
+ (DISPLAY_VER(dev_priv) == 11 &&
encoder->port != PORT_A);
}
@@ -339,10 +339,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
drm_WARN_ON(&dev_priv->drm,
intel_dp->source_rates || intel_dp->num_source_rates);
- if (INTEL_GEN(dev_priv) >= 10) {
+ if (DISPLAY_VER(dev_priv) >= 10) {
source_rates = cnl_rates;
size = ARRAY_SIZE(cnl_rates);
- if (IS_GEN(dev_priv, 10))
+ if (DISPLAY_VER(dev_priv) == 10)
max_rate = cnl_max_source_rate(intel_dp);
else if (IS_JSL_EHL(dev_priv))
max_rate = ehl_max_source_rate(intel_dp);
@@ -530,7 +530,7 @@ u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
static int
small_joiner_ram_size_bits(struct drm_i915_private *i915)
{
- if (INTEL_GEN(i915) >= 11)
+ if (DISPLAY_VER(i915) >= 11)
return 7680 * 8;
else
return 6144 * 8;
@@ -823,7 +823,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
* Output bpp is stored in 6.4 format so right shift by 4 to get the
* integer value since we support only integer values of bpp.
*/
- if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
+ if ((DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
if (intel_dp_is_edp(intel_dp)) {
dsc_max_output_bpp =
@@ -993,10 +993,10 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
/* On TGL, FEC is supported on all Pipes */
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
return true;
- if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
+ if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
return true;
return false;
@@ -1315,7 +1315,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return -EINVAL;
/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
else
dsc_max_bpc = min_t(u8, 10,
@@ -1554,7 +1554,7 @@ static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
{
if (IS_G4X(dev_priv))
return false;
- if (INTEL_GEN(dev_priv) < 12 && port == PORT_A)
+ if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
return false;
return true;
@@ -3681,7 +3681,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
intel_dp_set_common_rates(intel_dp);
/* Read the eDP DSC DPCD registers */
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
intel_dp_get_dsc_sink_cap(intel_dp);
/*
@@ -4862,7 +4862,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
to_intel_crtc_state(crtc->base.state);
/* retrain on the MST master transcoder */
- if (INTEL_GEN(dev_priv) >= 12 &&
+ if (DISPLAY_VER(dev_priv) >= 12 &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
!intel_dp_mst_is_master_trans(crtc_state))
continue;
@@ -4966,7 +4966,7 @@ static int intel_dp_do_phy_test(struct intel_encoder *encoder,
to_intel_crtc_state(crtc->base.state);
/* test on the MST master transcoder */
- if (INTEL_GEN(dev_priv) >= 12 &&
+ if (DISPLAY_VER(dev_priv) >= 12 &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
!intel_dp_mst_is_master_trans(crtc_state))
continue;
@@ -5417,7 +5417,7 @@ intel_dp_update_420(struct intel_dp *intel_dp)
DP_DS_HDMI_BT709_RGB_YCBCR_CONV |
DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
- if (INTEL_GEN(i915) >= 11) {
+ if (DISPLAY_VER(i915) >= 11) {
/* Let PCON convert from RGB->YCbCr if possible */
if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
intel_dp->dfp.rgb_to_ycbcr = true;
@@ -5535,7 +5535,7 @@ intel_dp_detect(struct drm_connector *connector,
}
/* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
intel_dp_get_dsc_sink_cap(intel_dp);
intel_dp_configure_mst(intel_dp);
@@ -5922,7 +5922,7 @@ static int intel_dp_connector_atomic_check(struct drm_connector *conn,
* We don't enable port sync on BDW due to missing w/as and
* due to not having adjusted the modeset sequence appropriately.
*/
- if (INTEL_GEN(dev_priv) < 9)
+ if (DISPLAY_VER(dev_priv) < 9)
return 0;
if (!intel_connector_needs_modeset(state, conn))
@@ -6010,10 +6010,10 @@ bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
* eDP not supported on g4x. so bail out early just
* for a bit extra safety in case the VBT is bonkers.
*/
- if (INTEL_GEN(dev_priv) < 5)
+ if (DISPLAY_VER(dev_priv) < 5)
return false;
- if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
+ if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
return true;
return intel_bios_is_port_edp(dev_priv, port);
@@ -6034,7 +6034,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
intel_attach_broadcast_rgb_property(connector);
if (HAS_GMCH(dev_priv))
drm_connector_attach_max_bpc_property(connector, 6, 10);
- else if (INTEL_GEN(dev_priv) >= 5)
+ else if (DISPLAY_VER(dev_priv) >= 5)
drm_connector_attach_max_bpc_property(connector, 6, 12);
/* Register HDMI colorspace for case of lspcon */
@@ -6045,7 +6045,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
intel_attach_dp_colorspace_property(connector);
}
- if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
+ if (IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 11)
drm_object_attach_property(&connector->base,
connector->dev->mode_config.hdr_output_metadata_property,
0);
@@ -6126,7 +6126,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
return;
}
- if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
switch (index) {
case DRRS_HIGH_RR:
intel_dp_set_m_n(crtc_state, M1_N1);
@@ -6139,7 +6139,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
drm_err(&dev_priv->drm,
"Unsupported refreshrate type\n");
}
- } else if (INTEL_GEN(dev_priv) > 6) {
+ } else if (DISPLAY_VER(dev_priv) > 6) {
i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
u32 val;
@@ -6467,7 +6467,7 @@ intel_dp_drrs_init(struct intel_connector *connector,
INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
mutex_init(&dev_priv->drrs.mutex);
- if (INTEL_GEN(dev_priv) <= 6) {
+ if (DISPLAY_VER(dev_priv) <= 6) {
drm_dbg_kms(&dev_priv->drm,
"DRRS supported for Gen7 and above\n");
return NULL;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 4ba08aa4680b..b7eee37d040a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -647,10 +647,10 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
struct intel_encoder *encoder = &dig_port->base;
enum aux_ch aux_ch = dig_port->aux_ch;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
- } else if (INTEL_GEN(dev_priv) >= 9) {
+ } else if (DISPLAY_VER(dev_priv) >= 9) {
intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
intel_dp->aux_ch_data_reg = skl_aux_data_reg;
} else if (HAS_PCH_SPLIT(dev_priv)) {
@@ -661,7 +661,7 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
}
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
@@ -670,7 +670,7 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
else
intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
else
intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
@@ -678,7 +678,7 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
drm_dp_aux_init(&intel_dp->aux);
/* Failure to allocate our preferred name is not critical */
- if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
+ if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
aux_ch - AUX_CH_USBC1 + '1',
encoder->base.name);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 906860ad8eb8..2daa3f67791e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -177,7 +177,7 @@ intel_dp_mst_transcoder_mask(struct intel_atomic_state *state,
u8 transcoders = 0;
int i;
- if (INTEL_GEN(dev_priv) < 12)
+ if (DISPLAY_VER(dev_priv) < 12)
return 0;
for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
@@ -228,7 +228,7 @@ intel_dp_mst_atomic_master_trans_check(struct intel_connector *connector,
struct drm_connector_list_iter connector_list_iter;
struct intel_connector *connector_iter;
- if (INTEL_GEN(dev_priv) < 12)
+ if (DISPLAY_VER(dev_priv) < 12)
return 0;
if (!intel_connector_needs_modeset(state, &connector->base))
@@ -390,7 +390,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
intel_dp->active_mst_links--;
last_mst_stream = intel_dp->active_mst_links == 0;
drm_WARN_ON(&dev_priv->drm,
- INTEL_GEN(dev_priv) >= 12 && last_mst_stream &&
+ DISPLAY_VER(dev_priv) >= 12 && last_mst_stream &&
!intel_dp_mst_is_master_trans(old_crtc_state));
intel_crtc_vblank_off(old_crtc_state);
@@ -414,7 +414,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
intel_ddi_disable_transcoder_func(old_crtc_state);
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
skl_scaler_disable(old_crtc_state);
else
ilk_pfit_disable(old_crtc_state);
@@ -440,7 +440,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
* From older GENs spec: "Configure Transcoder Clock Select to direct
* no clock to the transcoder"
*/
- if (INTEL_GEN(dev_priv) < 12 || !last_mst_stream)
+ if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream)
intel_ddi_disable_pipe_clock(old_crtc_state);
@@ -488,7 +488,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
intel_mst->connector = connector;
first_mst_stream = intel_dp->active_mst_links == 0;
drm_WARN_ON(&dev_priv->drm,
- INTEL_GEN(dev_priv) >= 12 && first_mst_stream &&
+ DISPLAY_VER(dev_priv) >= 12 && first_mst_stream &&
!intel_dp_mst_is_master_trans(pipe_config));
drm_dbg_kms(&dev_priv->drm, "active links %d\n",
@@ -521,7 +521,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
* first MST stream, so it's done on the DDI for the first stream and
* here for the following ones.
*/
- if (INTEL_GEN(dev_priv) < 12 || !first_mst_stream)
+ if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
intel_ddi_enable_pipe_clock(encoder, pipe_config);
intel_ddi_set_dp_msa(pipe_config, conn_state);
@@ -831,7 +831,7 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
- if (INTEL_GEN(dev_priv) <= 12) {
+ if (DISPLAY_VER(dev_priv) <= 12) {
ret = intel_dp_init_hdcp(dig_port, intel_connector);
if (ret)
drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP MST init failed, skipping.\n",
@@ -945,10 +945,10 @@ intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id)
if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp))
return 0;
- if (INTEL_GEN(i915) < 12 && port == PORT_A)
+ if (DISPLAY_VER(i915) < 12 && port == PORT_A)
return 0;
- if (INTEL_GEN(i915) < 11 && port == PORT_E)
+ if (DISPLAY_VER(i915) < 11 && port == PORT_E)
return 0;
intel_dp->mst_mgr.cbs = &mst_cbs;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 166e9a3a8c09..e010acf2a4f6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -847,7 +847,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
break;
}
- if (INTEL_GEN(dev_priv) >= 4)
+ if (DISPLAY_VER(dev_priv) >= 4)
dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
if (crtc_state->sdvo_tv_clock)
@@ -861,7 +861,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
dpll |= DPLL_VCO_ENABLE;
crtc_state->dpll_hw_state.dpll = dpll;
- if (INTEL_GEN(dev_priv) >= 4) {
+ if (DISPLAY_VER(dev_priv) >= 4) {
u32 dpll_md = (crtc_state->pixel_multiplier - 1)
<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
crtc_state->dpll_hw_state.dpll_md = dpll_md;
@@ -926,7 +926,7 @@ static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
to_intel_atomic_state(crtc_state->uapi.state);
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
- INTEL_GEN(dev_priv) >= 11) {
+ DISPLAY_VER(dev_priv) >= 11) {
struct intel_encoder *encoder =
intel_get_crtc_new_encoder(state, crtc_state);
@@ -1346,7 +1346,7 @@ static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
void
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
{
- if (INTEL_GEN(dev_priv) >= 9 || HAS_DDI(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
else if (HAS_PCH_SPLIT(dev_priv))
dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock;
@@ -1358,7 +1358,7 @@ intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
else if (IS_PINEVIEW(dev_priv))
dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
- else if (!IS_GEN(dev_priv, 2))
+ else if (DISPLAY_VER(dev_priv) != 2)
dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
else
dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
@@ -1398,7 +1398,7 @@ void i9xx_enable_pll(struct intel_crtc *crtc,
intel_de_posting_read(dev_priv, reg);
udelay(150);
- if (INTEL_GEN(dev_priv) >= 4) {
+ if (DISPLAY_VER(dev_priv) >= 4) {
intel_de_write(dev_priv, DPLL_MD(crtc->pipe),
crtc_state->dpll_hw_state.dpll_md);
} else {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 22ee8e13b518..2e08fbbab942 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -247,7 +247,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
unsigned int pipe_mask = BIT(crtc->pipe);
/* PCH only available on ILK+ */
- if (INTEL_GEN(dev_priv) < 5)
+ if (DISPLAY_VER(dev_priv) < 5)
return;
if (pll == NULL)
@@ -3017,7 +3017,7 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
switch (dev_priv->dpll.ref_clks.nssc) {
default:
MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
@@ -3112,7 +3112,7 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
DPLL_CFGCR1_KDIV(pll_params->kdiv) |
DPLL_CFGCR1_PDIV(pll_params->pdiv);
- if (INTEL_GEN(i915) >= 12)
+ if (DISPLAY_VER(i915) >= 12)
pll_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
else
pll_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
@@ -3222,7 +3222,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
u64 tmp;
bool use_ssc = false;
bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
- bool is_dkl = INTEL_GEN(dev_priv) >= 12;
+ bool is_dkl = DISPLAY_VER(dev_priv) >= 12;
memset(pll_state, 0, sizeof(*pll_state));
@@ -3422,7 +3422,7 @@ static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv,
ref_clock = dev_priv->dpll.ref_clks.nssc;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT;
m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK;
@@ -3884,7 +3884,7 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
RKL_DPLL_CFGCR0(id));
hw_state->cfgcr1 = intel_de_read(dev_priv,
RKL_DPLL_CFGCR1(id));
- } else if (INTEL_GEN(dev_priv) >= 12) {
+ } else if (DISPLAY_VER(dev_priv) >= 12) {
hw_state->cfgcr0 = intel_de_read(dev_priv,
TGL_DPLL_CFGCR0(id));
hw_state->cfgcr1 = intel_de_read(dev_priv,
@@ -3941,7 +3941,7 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
} else if (IS_ROCKETLAKE(dev_priv)) {
cfgcr0_reg = RKL_DPLL_CFGCR0(id);
cfgcr1_reg = RKL_DPLL_CFGCR1(id);
- } else if (INTEL_GEN(dev_priv) >= 12) {
+ } else if (DISPLAY_VER(dev_priv) >= 12) {
cfgcr0_reg = TGL_DPLL_CFGCR0(id);
cfgcr1_reg = TGL_DPLL_CFGCR1(id);
} else {
@@ -4172,7 +4172,7 @@ static void mg_pll_enable(struct drm_i915_private *dev_priv,
icl_pll_power_enable(dev_priv, pll, enable_reg);
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
dkl_pll_write(dev_priv, pll);
else
icl_mg_pll_write(dev_priv, pll);
@@ -4433,11 +4433,11 @@ void intel_shared_dpll_init(struct drm_device *dev)
dpll_mgr = &dg1_pll_mgr;
else if (IS_ROCKETLAKE(dev_priv))
dpll_mgr = &rkl_pll_mgr;
- else if (INTEL_GEN(dev_priv) >= 12)
+ else if (DISPLAY_VER(dev_priv) >= 12)
dpll_mgr = &tgl_pll_mgr;
else if (IS_JSL_EHL(dev_priv))
dpll_mgr = &ehl_pll_mgr;
- else if (INTEL_GEN(dev_priv) >= 11)
+ else if (DISPLAY_VER(dev_priv) >= 11)
dpll_mgr = &icl_pll_mgr;
else if (IS_CANNONLAKE(dev_priv))
dpll_mgr = &cnl_pll_mgr;
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index e349caef1926..c2a2cd1f84dc 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -203,7 +203,7 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
break;
}
- if (INTEL_GEN(dev_priv) < 11)
+ if (DISPLAY_VER(dev_priv) < 11)
vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
out:
@@ -380,7 +380,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
/* pull up/down */
value = *data++ & 1;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
else if (IS_VALLEYVIEW(dev_priv))
vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index c7beda2e35bc..f888e1c6ff7a 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -67,9 +67,9 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
int lines;
intel_fbc_get_plane_source_size(cache, NULL, &lines);
- if (IS_GEN(dev_priv, 7))
+ if (DISPLAY_VER(dev_priv) == 7)
lines = min(lines, 2048);
- else if (INTEL_GEN(dev_priv) >= 8)
+ else if (DISPLAY_VER(dev_priv) >= 8)
lines = min(lines, 2560);
/* Hardware needs the full buffer stride, not just the active area. */
@@ -109,7 +109,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
cfb_pitch = params->fb.stride;
/* FBC_CTL wants 32B or 64B units */
- if (IS_GEN(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
cfb_pitch = (cfb_pitch / 32) - 1;
else
cfb_pitch = (cfb_pitch / 64) - 1;
@@ -118,7 +118,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
intel_de_write(dev_priv, FBC_TAG(i), 0);
- if (IS_GEN(dev_priv, 4)) {
+ if (DISPLAY_VER(dev_priv) == 4) {
u32 fbc_ctl2;
/* Set it up... */
@@ -222,9 +222,9 @@ static void snb_fbc_recompress(struct drm_i915_private *dev_priv)
static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
{
- if (INTEL_GEN(dev_priv) >= 6)
+ if (DISPLAY_VER(dev_priv) >= 6)
snb_fbc_recompress(dev_priv);
- else if (INTEL_GEN(dev_priv) >= 4)
+ else if (DISPLAY_VER(dev_priv) >= 4)
i965_fbc_recompress(dev_priv);
else
i8xx_fbc_recompress(dev_priv);
@@ -354,7 +354,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
{
- if (INTEL_GEN(dev_priv) >= 5)
+ if (DISPLAY_VER(dev_priv) >= 5)
return ilk_fbc_is_active(dev_priv);
else if (IS_GM45(dev_priv))
return g4x_fbc_is_active(dev_priv);
@@ -371,9 +371,9 @@ static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
fbc->active = true;
fbc->activated = true;
- if (INTEL_GEN(dev_priv) >= 7)
+ if (DISPLAY_VER(dev_priv) >= 7)
gen7_fbc_activate(dev_priv);
- else if (INTEL_GEN(dev_priv) >= 5)
+ else if (DISPLAY_VER(dev_priv) >= 5)
ilk_fbc_activate(dev_priv);
else if (IS_GM45(dev_priv))
g4x_fbc_activate(dev_priv);
@@ -389,7 +389,7 @@ static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
fbc->active = false;
- if (INTEL_GEN(dev_priv) >= 5)
+ if (DISPLAY_VER(dev_priv) >= 5)
ilk_fbc_deactivate(dev_priv);
else if (IS_GM45(dev_priv))
g4x_fbc_deactivate(dev_priv);
@@ -426,7 +426,7 @@ static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
static u64 intel_fbc_cfb_base_max(struct drm_i915_private *i915)
{
- if (INTEL_GEN(i915) >= 5 || IS_G4X(i915))
+ if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915))
return BIT_ULL(28);
else
return BIT_ULL(32);
@@ -473,7 +473,7 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv,
ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
4096, 0, end);
- if (ret && INTEL_GEN(dev_priv) <= 4) {
+ if (ret && DISPLAY_VER(dev_priv) <= 4) {
return 0;
} else if (ret) {
compression_threshold <<= 1;
@@ -504,7 +504,7 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
fbc->threshold = ret;
- if (INTEL_GEN(dev_priv) >= 5)
+ if (DISPLAY_VER(dev_priv) >= 5)
intel_de_write(dev_priv, ILK_DPFC_CB_BASE,
fbc->compressed_fb.start);
else if (IS_GM45(dev_priv)) {
@@ -590,14 +590,14 @@ static bool stride_is_valid(struct drm_i915_private *dev_priv,
if (stride < 512)
return false;
- if (IS_GEN(dev_priv, 2) || IS_GEN(dev_priv, 3))
+ if (DISPLAY_VER(dev_priv) == 2 || DISPLAY_VER(dev_priv) == 3)
return stride == 4096 || stride == 8192;
- if (IS_GEN(dev_priv, 4) && !IS_G4X(dev_priv) && stride < 2048)
+ if (DISPLAY_VER(dev_priv) == 4 && !IS_G4X(dev_priv) && stride < 2048)
return false;
/* Display WA #1105: skl,bxt,kbl,cfl,glk */
- if (IS_GEN(dev_priv, 9) &&
+ if (DISPLAY_VER(dev_priv) == 9 &&
modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
return false;
@@ -617,7 +617,7 @@ static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
case DRM_FORMAT_XRGB1555:
case DRM_FORMAT_RGB565:
/* 16bpp not supported on gen2 */
- if (IS_GEN(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
return false;
/* WaFbcOnly1to1Ratio:ctg */
if (IS_G4X(dev_priv))
@@ -631,10 +631,10 @@ static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
static bool rotation_is_valid(struct drm_i915_private *dev_priv,
u32 pixel_format, unsigned int rotation)
{
- if (INTEL_GEN(dev_priv) >= 9 && pixel_format == DRM_FORMAT_RGB565 &&
+ if (DISPLAY_VER(dev_priv) >= 9 && pixel_format == DRM_FORMAT_RGB565 &&
drm_rotation_90_or_270(rotation))
return false;
- else if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
+ else if (DISPLAY_VER(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
rotation != DRM_MODE_ROTATE_0)
return false;
@@ -653,13 +653,13 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
struct intel_fbc *fbc = &dev_priv->fbc;
unsigned int effective_w, effective_h, max_w, max_h;
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
max_w = 5120;
max_h = 4096;
- } else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
+ } else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
max_w = 4096;
max_h = 4096;
- } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
+ } else if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) {
max_w = 4096;
max_h = 2048;
} else {
@@ -680,7 +680,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
{
switch (modifier) {
case DRM_FORMAT_MOD_LINEAR:
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
return true;
return false;
case I915_FORMAT_MOD_X_TILED:
@@ -844,7 +844,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
* For now this will effectively disable FBC with 90/270 degree
* rotation.
*/
- if (INTEL_GEN(dev_priv) < 9 && cache->fence_id < 0) {
+ if (DISPLAY_VER(dev_priv) < 9 && cache->fence_id < 0) {
fbc->no_fbc_reason = "framebuffer not tiled or fenced";
return false;
}
@@ -903,14 +903,14 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
* having a Y offset that isn't divisible by 4 causes FIFO underrun
* and screen flicker.
*/
- if (INTEL_GEN(dev_priv) >= 9 &&
+ if (DISPLAY_VER(dev_priv) >= 9 &&
(fbc->state_cache.plane.adjusted_y & 3)) {
fbc->no_fbc_reason = "plane Y offset is misaligned";
return false;
}
/* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
- if (INTEL_GEN(dev_priv) >= 11 &&
+ if (DISPLAY_VER(dev_priv) >= 11 &&
(cache->plane.src_h + cache->plane.adjusted_y) % 4) {
fbc->no_fbc_reason = "plane height + offset is non-modulo of 4";
return false;
@@ -1036,7 +1036,7 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state,
* if at least one frame has already passed.
*/
if (fbc->activated &&
- (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
+ (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
need_vblank_wait = true;
fbc->activated = false;
}
@@ -1445,7 +1445,7 @@ static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
if (!HAS_FBC(dev_priv))
return 0;
- if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
+ if (IS_BROADWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 9)
return 1;
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index a3715cd42ed0..5b1136838b9c 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -271,9 +271,9 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
else if (IS_SANDYBRIDGE(dev_priv) || IS_IRONLAKE(dev_priv))
ilk_set_fifo_underrun_reporting(dev, pipe, enable);
- else if (IS_GEN(dev_priv, 7))
+ else if (DISPLAY_VER(dev_priv) == 7)
ivb_set_fifo_underrun_reporting(dev, pipe, enable, old);
- else if (INTEL_GEN(dev_priv) >= 8)
+ else if (DISPLAY_VER(dev_priv) >= 8)
bdw_set_fifo_underrun_reporting(dev, pipe, enable);
return old;
@@ -432,7 +432,7 @@ void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
if (HAS_GMCH(dev_priv))
i9xx_check_fifo_underruns(crtc);
- else if (IS_GEN(dev_priv, 7))
+ else if (DISPLAY_VER(dev_priv) == 7)
ivb_check_fifo_underruns(crtc);
}
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 0c952e1d720e..c8a4f1f5d650 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -392,8 +392,8 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
static unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
{
- return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
- GMBUS_BYTE_COUNT_MAX;
+ return DISPLAY_VER(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
+ GMBUS_BYTE_COUNT_MAX;
}
static int
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index ae1371c36a32..d418fe796263 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -318,7 +318,7 @@ static
u32 intel_hdcp_get_repeater_ctl(struct drm_i915_private *dev_priv,
enum transcoder cpu_transcoder, enum port port)
{
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
switch (cpu_transcoder) {
case TRANSCODER_A:
return HDCP_TRANSA_REP_PRESENT |
@@ -1089,7 +1089,7 @@ static void intel_hdcp_prop_work(struct work_struct *work)
bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
{
return INTEL_INFO(dev_priv)->display.has_hdcp &&
- (INTEL_GEN(dev_priv) >= 12 || port < PORT_E);
+ (DISPLAY_VER(dev_priv) >= 12 || port < PORT_E);
}
static int
@@ -2137,7 +2137,7 @@ static int initialize_hdcp_port_data(struct intel_connector *connector,
struct intel_hdcp *hdcp = &connector->hdcp;
enum port port = dig_port->base.port;
- if (INTEL_GEN(dev_priv) < 12)
+ if (DISPLAY_VER(dev_priv) < 12)
data->fw_ddi = intel_get_mei_fw_ddi_index(port);
else
/*
@@ -2176,7 +2176,7 @@ static bool is_hdcp2_supported(struct drm_i915_private *dev_priv)
if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP))
return false;
- return (INTEL_GEN(dev_priv) >= 10 ||
+ return (DISPLAY_VER(dev_priv) >= 10 ||
IS_GEMINILAKE(dev_priv) ||
IS_KABYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv) ||
@@ -2288,7 +2288,7 @@ int intel_hdcp_enable(struct intel_connector *connector,
hdcp->stream_transcoder = INVALID_TRANSCODER;
}
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
dig_port->hdcp_port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
/*
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 7f384f259fc8..b122c46a5657 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -200,7 +200,7 @@ static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
case DP_SDP_PPS:
return VIDEO_DIP_PPS_DATA_SIZE;
case HDMI_PACKET_TYPE_GAMUT_METADATA:
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
return VIDEO_DIP_GMP_DATA_SIZE;
else
return VIDEO_DIP_DATA_SIZE;
@@ -583,7 +583,7 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
mask |= VIDEO_DIP_ENABLE_DRM_GLK;
return val & mask;
@@ -839,7 +839,7 @@ intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
int ret;
- if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
+ if (!(DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
return true;
if (!crtc_state->has_infoframe)
@@ -2157,11 +2157,11 @@ static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
int max_tmds_clock, vbt_max_tmds_clock;
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
max_tmds_clock = 594000;
- else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
+ else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
max_tmds_clock = 300000;
- else if (INTEL_GEN(dev_priv) >= 5)
+ else if (DISPLAY_VER(dev_priv) >= 5)
max_tmds_clock = 225000;
else
max_tmds_clock = 165000;
@@ -2284,7 +2284,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
true, has_hdmi_sink);
/* if we can't do 8,12bpc we may still be able to do 10bpc */
- if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
+ if (status != MODE_OK && DISPLAY_VER(dev_priv) >= 11)
status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 10),
true, has_hdmi_sink);
}
@@ -2347,7 +2347,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
if (HAS_GMCH(dev_priv))
return false;
- if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
+ if (bpc == 10 && DISPLAY_VER(dev_priv) < 11)
return false;
/*
@@ -2359,7 +2359,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
/* Display Wa_1405510057:icl,ehl */
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
- bpc == 10 && IS_GEN(dev_priv, 11) &&
+ bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
(adjusted_mode->crtc_hblank_end -
adjusted_mode->crtc_hblank_start) % 8 == 2)
return false;
@@ -2546,7 +2546,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
pipe_config->lane_count = 4;
- if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
+ if (scdc->scrambling.supported && (DISPLAY_VER(dev_priv) >= 10 ||
IS_GEMINILAKE(dev_priv))) {
if (scdc->scrambling.low_rates)
pipe_config->hdmi_scrambling = true;
@@ -2705,7 +2705,7 @@ intel_hdmi_detect(struct drm_connector *connector, bool force)
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
- if (INTEL_GEN(dev_priv) >= 11 &&
+ if (DISPLAY_VER(dev_priv) >= 11 &&
!intel_digital_port_connected(encoder))
goto out;
@@ -2965,7 +2965,7 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *c
intel_attach_hdmi_colorspace_property(connector);
drm_connector_attach_content_type_property(connector);
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
drm_object_attach_property(&connector->base,
connector->dev->mode_config.hdr_output_metadata_property, 0);
@@ -3298,7 +3298,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
"Adding HDMI connector on [ENCODER:%d:%s]\n",
intel_encoder->base.base.id, intel_encoder->base.name);
- if (INTEL_GEN(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
+ if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
return;
if (drm_WARN(dev, dig_port->max_lanes < 4,
@@ -3320,7 +3320,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
connector->doublescan_allowed = 0;
connector->stereo_allowed = 1;
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
connector->ycbcr_420_allowed = true;
intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index c6c7c0b9989b..dd12d15f47c7 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -136,12 +136,12 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
pipe_config->hw.adjusted_mode.flags |= flags;
- if (INTEL_GEN(dev_priv) < 5)
+ if (DISPLAY_VER(dev_priv) < 5)
pipe_config->gmch_pfit.lvds_border_bits =
tmp & LVDS_BORDER_ENABLE;
/* gen2/3 store dither state in pfit control, needs to match */
- if (INTEL_GEN(dev_priv) < 4) {
+ if (DISPLAY_VER(dev_priv) < 4) {
tmp = intel_de_read(dev_priv, PFIT_CONTROL);
pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
@@ -179,7 +179,7 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
/* Convert from 100ms to 100us units */
pps->t4 = val * 1000;
- if (INTEL_GEN(dev_priv) <= 4 &&
+ if (DISPLAY_VER(dev_priv) <= 4 &&
pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
drm_dbg_kms(&dev_priv->drm,
"Panel power timings uninitialized, "
@@ -280,7 +280,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
* special lvds dither control bit on pch-split platforms, dithering is
* only controlled through the PIPECONF reg.
*/
- if (IS_GEN(dev_priv, 4)) {
+ if (DISPLAY_VER(dev_priv) == 4) {
/*
* Bspec wording suggests that LVDS port dithering only exists
* for 18bpp panels.
@@ -415,7 +415,7 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
int ret;
/* Should never happen!! */
- if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
+ if (DISPLAY_VER(dev_priv) < 4 && intel_crtc->pipe == 0) {
drm_err(&dev_priv->drm, "Can't support LVDS on pipe A\n");
return -EINVAL;
}
@@ -915,7 +915,7 @@ void intel_lvds_init(struct drm_i915_private *dev_priv)
intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
intel_encoder->port = PORT_NONE;
intel_encoder->cloneable = 0;
- if (INTEL_GEN(dev_priv) < 4)
+ if (DISPLAY_VER(dev_priv) < 4)
intel_encoder->pipe_mask = BIT(PIPE_B);
else
intel_encoder->pipe_mask = ~0;
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index ef8f44f5e751..ad657a77ad4e 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -550,7 +550,7 @@ static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 widt
{
u32 sw;
- if (IS_GEN(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
sw = ALIGN((offset & 31) + width, 32);
else
sw = ALIGN((offset & 63) + width, 64);
@@ -794,7 +794,7 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay,
oconfig |= OCONF_CC_OUT_8BIT;
if (crtc_state->gamma_enable)
oconfig |= OCONF_GAMMA2_ENABLE;
- if (IS_GEN(dev_priv, 4))
+ if (DISPLAY_VER(dev_priv) == 4)
oconfig |= OCONF_CSC_MODE_BT709;
oconfig |= pipe == 0 ?
OCONF_PIPE_A : OCONF_PIPE_B;
@@ -913,7 +913,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
/* XXX: This is not the same logic as in the xorg driver, but more in
* line with the intel documentation for the i965
*/
- if (INTEL_GEN(dev_priv) >= 4) {
+ if (DISPLAY_VER(dev_priv) >= 4) {
/* on i965 use the PGM reg to read out the autoscaler values */
ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
} else {
@@ -1028,7 +1028,7 @@ static int check_overlay_src(struct drm_i915_private *dev_priv,
if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
return -EINVAL;
- if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512)
+ if (DISPLAY_VER(dev_priv) == 4 && rec->stride_Y < 512)
return -EINVAL;
tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
@@ -1255,7 +1255,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
attrs->contrast = overlay->contrast;
attrs->saturation = overlay->saturation;
- if (!IS_GEN(dev_priv, 2)) {
+ if (DISPLAY_VER(dev_priv) != 2) {
attrs->gamma0 = intel_de_read(dev_priv, OGAMC0);
attrs->gamma1 = intel_de_read(dev_priv, OGAMC1);
attrs->gamma2 = intel_de_read(dev_priv, OGAMC2);
@@ -1279,7 +1279,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
update_reg_attrs(overlay, overlay->regs);
if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
- if (IS_GEN(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
goto out_unlock;
if (overlay->active) {
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 4653b5ef382f..5c216a84c6df 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -405,7 +405,7 @@ int intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
break;
case DRM_MODE_SCALE_ASPECT:
/* Scale but preserve the aspect ratio */
- if (INTEL_GEN(dev_priv) >= 4)
+ if (DISPLAY_VER(dev_priv) >= 4)
i965_scale_aspect(crtc_state, &pfit_control);
else
i9xx_scale_aspect(crtc_state, &pfit_control,
@@ -419,7 +419,7 @@ int intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
if (crtc_state->pipe_src_h != adjusted_mode->crtc_vdisplay ||
crtc_state->pipe_src_w != adjusted_mode->crtc_hdisplay) {
pfit_control |= PFIT_ENABLE;
- if (INTEL_GEN(dev_priv) >= 4)
+ if (DISPLAY_VER(dev_priv) >= 4)
pfit_control |= PFIT_SCALING_AUTO;
else
pfit_control |= (VERT_AUTO_SCALE |
@@ -435,7 +435,7 @@ int intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
/* 965+ wants fuzzy fitting */
/* FIXME: handle multiple panels by failing gracefully */
- if (INTEL_GEN(dev_priv) >= 4)
+ if (DISPLAY_VER(dev_priv) >= 4)
pfit_control |= PFIT_PIPE(crtc->pipe) | PFIT_FILTER_FUZZY;
out:
@@ -445,7 +445,7 @@ int intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
}
/* Make sure pre-965 set dither correctly for 18bpp panels. */
- if (INTEL_GEN(dev_priv) < 4 && crtc_state->pipe_bpp == 18)
+ if (DISPLAY_VER(dev_priv) < 4 && crtc_state->pipe_bpp == 18)
pfit_control |= PANEL_8TO6_DITHER_ENABLE;
crtc_state->gmch_pfit.control = pfit_control;
@@ -590,7 +590,7 @@ static u32 i9xx_get_backlight(struct intel_connector *connector, enum pipe unuse
u32 val;
val = intel_de_read(dev_priv, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
- if (INTEL_GEN(dev_priv) < 4)
+ if (DISPLAY_VER(dev_priv) < 4)
val >>= 1;
if (panel->backlight.combination_mode) {
@@ -667,7 +667,7 @@ static void i9xx_set_backlight(const struct drm_connector_state *conn_state, u32
pci_write_config_byte(to_pci_dev(dev_priv->drm.dev), LBPC, lbpc);
}
- if (IS_GEN(dev_priv, 4)) {
+ if (DISPLAY_VER(dev_priv) == 4) {
mask = BACKLIGHT_DUTY_CYCLE_MASK;
} else {
level <<= 1;
@@ -1040,7 +1040,7 @@ static void i9xx_enable_backlight(const struct intel_crtc_state *crtc_state,
* 855gm only, but checking for gen2 is safe, as 855gm is the only gen2
* that has backlight.
*/
- if (IS_GEN(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
intel_de_write(dev_priv, BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE);
}
@@ -1728,7 +1728,7 @@ static int i9xx_setup_backlight(struct intel_connector *connector, enum pipe unu
ctl = intel_de_read(dev_priv, BLC_PWM_CTL);
- if (IS_GEN(dev_priv, 2) || IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
+ if (DISPLAY_VER(dev_priv) == 2 || IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE;
if (IS_PINEVIEW(dev_priv))
@@ -2178,7 +2178,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
} else {
panel->backlight.pwm_funcs = &vlv_pwm_funcs;
}
- } else if (IS_GEN(dev_priv, 4)) {
+ } else if (DISPLAY_VER(dev_priv) == 4) {
panel->backlight.pwm_funcs = &i965_pwm_funcs;
} else {
panel->backlight.pwm_funcs = &i9xx_pwm_funcs;
diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
index 3c4024409d85..c4142991d0d4 100644
--- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
@@ -409,15 +409,15 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
enum pipe pipe,
enum intel_pipe_crc_source *source, u32 *val)
{
- if (IS_GEN(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
return i8xx_pipe_crc_ctl_reg(source, val);
- else if (INTEL_GEN(dev_priv) < 5)
+ else if (DISPLAY_VER(dev_priv) < 5)
return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
else if (IS_SANDYBRIDGE(dev_priv) || IS_IRONLAKE(dev_priv))
return ilk_pipe_crc_ctl_reg(source, val);
- else if (INTEL_GEN(dev_priv) < 9)
+ else if (DISPLAY_VER(dev_priv) < 9)
return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
else
return skl_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
@@ -539,15 +539,15 @@ static int
intel_is_valid_crc_source(struct drm_i915_private *dev_priv,
const enum intel_pipe_crc_source source)
{
- if (IS_GEN(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
return i8xx_crc_source_valid(dev_priv, source);
- else if (INTEL_GEN(dev_priv) < 5)
+ else if (DISPLAY_VER(dev_priv) < 5)
return i9xx_crc_source_valid(dev_priv, source);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return vlv_crc_source_valid(dev_priv, source);
else if (IS_SANDYBRIDGE(dev_priv) || IS_IRONLAKE(dev_priv))
return ilk_crc_source_valid(dev_priv, source);
- else if (INTEL_GEN(dev_priv) < 9)
+ else if (DISPLAY_VER(dev_priv) < 9)
return ivb_crc_source_valid(dev_priv, source);
else
return skl_crc_source_valid(dev_priv, source);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index cd434285e3b7..f6d1bc3269b2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -118,7 +118,7 @@ static void psr_irq_control(struct intel_dp *intel_dp)
* using the same bit definition: handle it as TRANSCODER_EDP to force
* 0 shift in bit definition
*/
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
trans_shift = 0;
imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
} else {
@@ -184,7 +184,7 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
enum transcoder trans_shift;
i915_reg_t imr_reg;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
trans_shift = 0;
imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
} else {
@@ -205,7 +205,7 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
"[transcoder %s] PSR exit completed\n",
transcoder_name(cpu_transcoder));
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (DISPLAY_VER(dev_priv) >= 9) {
u32 val = intel_de_read(dev_priv,
PSR_EVENT(cpu_transcoder));
bool psr2_enabled = intel_dp->psr.psr2_enabled;
@@ -321,7 +321,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
intel_dp->psr.sink_sync_latency =
intel_dp_get_sink_sync_latency(intel_dp);
- if (INTEL_GEN(dev_priv) >= 9 &&
+ if (DISPLAY_VER(dev_priv) >= 9 &&
(intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
bool y_req = intel_dp->psr_dpcd[1] &
DP_PSR2_SU_Y_COORDINATE_REQUIRED;
@@ -402,7 +402,7 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
if (intel_dp->psr.link_standby)
dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
- if (INTEL_GEN(dev_priv) >= 8)
+ if (DISPLAY_VER(dev_priv) >= 8)
dpcd_val |= DP_PSR_CRC_VERIFICATION;
}
@@ -416,7 +416,7 @@ static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 val = 0;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
val |= EDP_PSR_TP4_TIME_0US;
if (dev_priv->params.psr_safest_params) {
@@ -487,7 +487,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
val |= intel_psr1_get_tp_time(intel_dp);
- if (INTEL_GEN(dev_priv) >= 8)
+ if (DISPLAY_VER(dev_priv) >= 8)
val |= EDP_PSR_CRC_ENABLE;
val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) &
@@ -524,13 +524,13 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
val |= EDP_Y_COORDINATE_ENABLE;
val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1);
val |= intel_psr2_get_tp_time(intel_dp);
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
/*
* TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default
* values from BSpec. In order to setting an optimal power
@@ -541,7 +541,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7);
val |= TGL_EDP_PSR2_FAST_WAKE(7);
- } else if (INTEL_GEN(dev_priv) >= 9) {
+ } else if (DISPLAY_VER(dev_priv) >= 9) {
val |= EDP_PSR2_IO_BUFFER_WAKE(7);
val |= EDP_PSR2_FAST_WAKE(7);
}
@@ -574,9 +574,9 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
static bool
transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)
{
- if (INTEL_GEN(dev_priv) < 9)
+ if (DISPLAY_VER(dev_priv) < 9)
return false;
- else if (INTEL_GEN(dev_priv) >= 12)
+ else if (DISPLAY_VER(dev_priv) >= 12)
return trans == TRANSCODER_A;
else
return trans == TRANSCODER_EDP;
@@ -761,15 +761,15 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
return false;
}
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
psr_max_h = 5120;
psr_max_v = 3200;
max_bpp = 30;
- } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ } else if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
psr_max_h = 4096;
psr_max_v = 2304;
max_bpp = 24;
- } else if (IS_GEN(dev_priv, 9)) {
+ } else if (DISPLAY_VER(dev_priv) == 9) {
psr_max_h = 3640;
psr_max_v = 2304;
max_bpp = 24;
@@ -909,7 +909,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
hsw_psr_setup_aux(intel_dp);
- if (intel_dp->psr.psr2_enabled && (IS_GEN(dev_priv, 9) &&
+ if (intel_dp->psr.psr2_enabled && (DISPLAY_VER(dev_priv) == 9 &&
!IS_GEMINILAKE(dev_priv))) {
i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
u32 chicken = intel_de_read(dev_priv, reg);
@@ -930,7 +930,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
EDP_PSR_DEBUG_MASK_LPSP |
EDP_PSR_DEBUG_MASK_MAX_SLEEP;
- if (INTEL_GEN(dev_priv) < 11)
+ if (DISPLAY_VER(dev_priv) < 11)
mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder),
@@ -987,7 +987,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
* first time that PSR HW tries to activate so lets keep PSR disabled
* to avoid any rendering problems.
*/
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
val = intel_de_read(dev_priv,
TRANS_PSR_IIR(intel_dp->psr.transcoder));
val &= EDP_PSR_ERROR(0);
@@ -1169,7 +1169,7 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
* and a better fix is found.
*/
intel_psr_exit(intel_dp);
- else if (INTEL_GEN(dev_priv) >= 9)
+ else if (DISPLAY_VER(dev_priv) >= 9)
/*
* Display WA #0884: skl+
* This documented WA for bxt can be safely applied
@@ -1451,7 +1451,7 @@ void intel_psr_update(struct intel_dp *intel_dp,
/* Force a PSR exit when enabling CRC to avoid CRC timeouts */
if (crtc_state->crc_enabled && psr->enabled)
psr_force_hw_tracking_exit(intel_dp);
- else if (INTEL_GEN(dev_priv) < 9 && psr->enabled) {
+ else if (DISPLAY_VER(dev_priv) < 9 && psr->enabled) {
/*
* Activate PSR again after a force exit when enabling
* CRC in older gens
@@ -1855,7 +1855,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
* So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11.
* But GEN12 supports a instance of PSR registers per transcoder.
*/
- if (INTEL_GEN(dev_priv) < 12 && dig_port->base.port != PORT_A) {
+ if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) {
drm_dbg_kms(&dev_priv->drm,
"PSR condition failed: Port not supported\n");
return;
@@ -1872,14 +1872,14 @@ void intel_psr_init(struct intel_dp *intel_dp)
dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE;
if (dev_priv->params.enable_psr == -1)
- if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
+ if (DISPLAY_VER(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
dev_priv->params.enable_psr = 0;
/* Set link_standby x link_off defaults */
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
/* HSW and BDW require workarounds that we don't implement. */
intel_dp->psr.link_standby = false;
- else if (INTEL_GEN(dev_priv) < 12)
+ else if (DISPLAY_VER(dev_priv) < 12)
/* For new platforms up to TGL let's respect VBT back again */
intel_dp->psr.link_standby = dev_priv->vbt.psr.full_link;
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 3fac60899d8e..f770d6bcd2c9 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -1540,11 +1540,11 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state,
return;
/* Set the SDVO control regs. */
- if (INTEL_GEN(dev_priv) >= 4) {
+ if (DISPLAY_VER(dev_priv) >= 4) {
/* The real mode polarity is set by the SDVO commands, using
* struct intel_sdvo_dtd. */
sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
- if (INTEL_GEN(dev_priv) < 5)
+ if (DISPLAY_VER(dev_priv) < 5)
sdvox |= SDVO_BORDER_ENABLE;
} else {
sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
@@ -1560,7 +1560,7 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state,
else
sdvox |= SDVO_PIPE_SEL(crtc->pipe);
- if (INTEL_GEN(dev_priv) >= 4) {
+ if (DISPLAY_VER(dev_priv) >= 4) {
/* done in crtc_mode_set as the dpll_md reg must be written early */
} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
@@ -1571,7 +1571,7 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state,
}
if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
- INTEL_GEN(dev_priv) < 5)
+ DISPLAY_VER(dev_priv) < 5)
sdvox |= SDVO_STALL_SELECT;
intel_sdvo_write_sdvox(intel_sdvo, sdvox);
}
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index fb506409a63b..d55a13312885 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1392,7 +1392,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
int ret;
if (g4x_fb_scalable(plane_state->hw.fb)) {
- if (INTEL_GEN(dev_priv) < 7) {
+ if (DISPLAY_VER(dev_priv) < 7) {
min_scale = 1;
max_scale = 16 << 16;
} else if (IS_IVYBRIDGE(dev_priv)) {
@@ -1421,7 +1421,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- if (INTEL_GEN(dev_priv) >= 7)
+ if (DISPLAY_VER(dev_priv) >= 7)
plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
else
plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state);
@@ -1482,7 +1482,7 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv)
{
- return INTEL_GEN(dev_priv) >= 9;
+ return DISPLAY_VER(dev_priv) >= 9;
}
static void intel_plane_set_ckey(struct intel_plane_state *plane_state,
@@ -1506,7 +1506,7 @@ static void intel_plane_set_ckey(struct intel_plane_state *plane_state,
* On SKL+ we want dst key enabled on
* the primary and not on the sprite.
*/
- if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY &&
+ if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_PRIMARY &&
set->flags & I915_SET_COLORKEY_DESTINATION)
key->flags = 0;
}
@@ -1545,7 +1545,7 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
* Also multiple planes can't do destination keying on the same
* pipe simultaneously.
*/
- if (INTEL_GEN(dev_priv) >= 9 &&
+ if (DISPLAY_VER(dev_priv) >= 9 &&
to_intel_plane(plane)->id >= PLANE_SPRITE1 &&
set->flags & I915_SET_COLORKEY_DESTINATION)
return -EINVAL;
@@ -1810,7 +1810,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
modifiers = i9xx_plane_format_modifiers;
plane_funcs = &vlv_sprite_funcs;
- } else if (INTEL_GEN(dev_priv) >= 7) {
+ } else if (DISPLAY_VER(dev_priv) >= 7) {
plane->update_plane = ivb_update_plane;
plane->disable_plane = ivb_disable_plane;
plane->get_hw_state = ivb_plane_get_hw_state;
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 2cefc13535a0..88085486ee59 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -28,7 +28,7 @@ tc_cold_get_power_domain(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- if (INTEL_GEN(i915) == 11)
+ if (DISPLAY_VER(i915) == 11)
return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
else
return POWER_DOMAIN_TC_COLD_OFF;
@@ -40,7 +40,7 @@ tc_cold_block(struct intel_digital_port *dig_port)
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
enum intel_display_power_domain domain;
- if (INTEL_GEN(i915) == 11 && !dig_port->tc_legacy_port)
+ if (DISPLAY_VER(i915) == 11 && !dig_port->tc_legacy_port)
return 0;
domain = tc_cold_get_power_domain(dig_port);
@@ -71,7 +71,7 @@ assert_tc_cold_blocked(struct intel_digital_port *dig_port)
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
bool enabled;
- if (INTEL_GEN(i915) == 11 && !dig_port->tc_legacy_port)
+ if (DISPLAY_VER(i915) == 11 && !dig_port->tc_legacy_port)
return;
enabled = intel_display_power_is_enabled(i915,
@@ -455,7 +455,7 @@ static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port,
enum tc_port_mode old_tc_mode = dig_port->tc_mode;
intel_display_power_flush_work(i915);
- if (INTEL_GEN(i915) != 11 || !dig_port->tc_legacy_port) {
+ if (DISPLAY_VER(i915) != 11 || !dig_port->tc_legacy_port) {
enum intel_display_power_domain aux_domain;
bool aux_powered;
diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
index 7a7b99b015a5..2c5c77693474 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.c
+++ b/drivers/gpu/drm/i915/display/intel_tv.c
@@ -1165,7 +1165,7 @@ intel_tv_get_config(struct intel_encoder *encoder,
static bool intel_tv_source_too_wide(struct drm_i915_private *dev_priv,
int hdisplay)
{
- return IS_GEN(dev_priv, 3) && hdisplay > 1024;
+ return DISPLAY_VER(dev_priv) == 3 && hdisplay > 1024;
}
static bool intel_tv_vert_scaling(const struct drm_display_mode *tv_mode,
@@ -1519,7 +1519,7 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
set_color_conversion(dev_priv, color_conversion);
- if (INTEL_GEN(dev_priv) >= 4)
+ if (DISPLAY_VER(dev_priv) >= 4)
intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00404000);
else
intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00606000);
@@ -1789,7 +1789,7 @@ intel_tv_get_modes(struct drm_connector *connector)
continue;
/* no vertical scaling with wide sources on gen3 */
- if (IS_GEN(dev_priv, 3) && input->w > 1024 &&
+ if (DISPLAY_VER(dev_priv) == 3 && input->w > 1024 &&
input->h > intel_tv_mode_vdisplay(tv_mode))
continue;
@@ -1978,7 +1978,7 @@ intel_tv_init(struct drm_i915_private *dev_priv)
/* Create TV properties then attach current values */
for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
/* 1080p50/1080p60 not supported on gen3 */
- if (IS_GEN(dev_priv, 3) &&
+ if (DISPLAY_VER(dev_priv) == 3 &&
tv_modes[i].oversample == 1)
break;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index f58cc5700784..1ccef159a9a0 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -343,10 +343,10 @@ bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
return false;
/* On TGL, DSC is supported on all Pipes */
- if (INTEL_GEN(i915) >= 12)
+ if (DISPLAY_VER(i915) >= 12)
return true;
- if (INTEL_GEN(i915) >= 10 &&
+ if (DISPLAY_VER(i915) >= 10 &&
(pipe != PIPE_A ||
(cpu_transcoder == TRANSCODER_EDP ||
cpu_transcoder == TRANSCODER_DSI_0 ||
@@ -362,7 +362,7 @@ static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state)
const struct drm_i915_private *i915 = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (INTEL_GEN(i915) >= 12)
+ if (DISPLAY_VER(i915) >= 12)
return true;
if (cpu_transcoder == TRANSCODER_EDP ||
@@ -479,7 +479,7 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
* the pipe in use. Hence another reference on the pipe power domain
* will suffice. (Except no VDSC/joining on ICL pipe A.)
*/
- if (INTEL_GEN(i915) >= 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
+ if (DISPLAY_VER(i915) >= 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
else if (is_pipe_dsc(crtc_state))
return POWER_DOMAIN_PIPE(pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c
index 5f8e4f53649d..f002b82ba9c0 100644
--- a/drivers/gpu/drm/i915/display/intel_vga.c
+++ b/drivers/gpu/drm/i915/display/intel_vga.c
@@ -16,7 +16,7 @@ static i915_reg_t intel_vga_cntrl_reg(struct drm_i915_private *i915)
{
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
return VLV_VGACNTRL;
- else if (INTEL_GEN(i915) >= 5)
+ else if (DISPLAY_VER(i915) >= 5)
return CPU_VGACNTRL;
else
return VGACNTRL;
@@ -96,7 +96,7 @@ void intel_vga_reset_io_mem(struct drm_i915_private *i915)
static int
intel_vga_set_state(struct drm_i915_private *i915, bool enable_decode)
{
- unsigned int reg = INTEL_GEN(i915) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
+ unsigned int reg = DISPLAY_VER(i915) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
u16 gmch_ctrl;
if (pci_read_config_word(i915->bridge_dev, reg, &gmch_ctrl)) {
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index b37a87bb190f..17a98cb627df 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -115,7 +115,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
* Once NV12 is enabled, handle it here while allocating scaler
* for NV12.
*/
- if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
+ if (DISPLAY_VER(dev_priv) >= 9 && crtc_state->hw.enable &&
need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
drm_dbg_kms(&dev_priv->drm,
"Pipe/Plane scaling not supported with IF-ID mode\n");
@@ -157,10 +157,10 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
/* range checks */
if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
- (INTEL_GEN(dev_priv) >= 11 &&
+ (DISPLAY_VER(dev_priv) >= 11 &&
(src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
- (INTEL_GEN(dev_priv) < 11 &&
+ (DISPLAY_VER(dev_priv) < 11 &&
(src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
drm_dbg_kms(&dev_priv->drm,
@@ -280,7 +280,7 @@ int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
case DRM_FORMAT_ABGR16161616F:
case DRM_FORMAT_XRGB16161616F:
case DRM_FORMAT_ARGB16161616F:
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
break;
fallthrough;
default:
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 1f335cb09149..91e5d8a5d4a9 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -275,13 +275,13 @@ static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
enum plane_id plane_id)
{
- return INTEL_GEN(dev_priv) >= 11 &&
+ return DISPLAY_VER(dev_priv) >= 11 &&
icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id);
}
bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id)
{
- return INTEL_GEN(dev_priv) >= 11 &&
+ return DISPLAY_VER(dev_priv) >= 11 &&
icl_hdr_plane_mask() & BIT(plane_id);
}
@@ -294,7 +294,7 @@ skl_plane_ratio(const struct intel_crtc_state *crtc_state,
const struct drm_framebuffer *fb = plane_state->hw.fb;
if (fb->format->cpp[0] == 8) {
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
*num = 10;
*den = 8;
} else {
@@ -317,7 +317,7 @@ static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
skl_plane_ratio(crtc_state, plane_state, &num, &den);
/* two pixels per clock on glk+ */
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
den *= 2;
return DIV_ROUND_UP(pixel_rate * num, den);
@@ -810,7 +810,7 @@ static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
u32 plane_ctl = 0;
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
return plane_ctl;
if (crtc_state->gamma_enable)
@@ -834,7 +834,7 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
plane_ctl = PLANE_CTL_ENABLE;
- if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
plane_ctl |= skl_plane_ctl_alpha(plane_state);
plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
@@ -849,7 +849,7 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
- if (INTEL_GEN(dev_priv) >= 10)
+ if (DISPLAY_VER(dev_priv) >= 10)
plane_ctl |= cnl_plane_ctl_flip(rotation &
DRM_MODE_REFLECT_MASK);
@@ -866,7 +866,7 @@ static u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
u32 plane_color_ctl = 0;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
return plane_color_ctl;
if (crtc_state->gamma_enable)
@@ -941,7 +941,7 @@ skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
if (is_ccs_modifier(fb->modifier))
return main_to_ccs_plane(fb, main_plane);
- else if (INTEL_GEN(i915) < 11 &&
+ else if (DISPLAY_VER(i915) < 11 &&
intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
return 1;
else
@@ -976,7 +976,7 @@ skl_program_plane(struct intel_plane *plane,
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
plane_color_ctl = plane_state->color_ctl |
glk_plane_color_ctl_crtc(crtc_state);
@@ -999,7 +999,7 @@ skl_program_plane(struct intel_plane *plane,
if (aux_plane) {
aux_dist = plane_state->color_plane[aux_plane].offset - surf_addr;
- if (INTEL_GEN(dev_priv) < 12)
+ if (DISPLAY_VER(dev_priv) < 12)
aux_dist |= skl_plane_stride(plane_state, aux_plane);
}
@@ -1017,7 +1017,7 @@ skl_program_plane(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
plane_state->cus_ctl);
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
plane_color_ctl);
@@ -1038,7 +1038,7 @@ skl_program_plane(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
(y << 16) | x);
- if (INTEL_GEN(dev_priv) < 11)
+ if (DISPLAY_VER(dev_priv) < 11)
intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
(plane_state->color_plane[1].y << 16) | plane_state->color_plane[1].x);
@@ -1154,7 +1154,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
*/
switch (fb->format->format) {
case DRM_FORMAT_RGB565:
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
break;
fallthrough;
case DRM_FORMAT_C8:
@@ -1262,7 +1262,7 @@ static int skl_plane_max_scale(struct drm_i915_private *dev_priv,
* the best case.
* FIXME need to properly check this later.
*/
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
!intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
return 0x30000 - 1;
else
@@ -1631,7 +1631,7 @@ static bool skl_fb_scalable(const struct drm_framebuffer *fb)
case DRM_FORMAT_ARGB16161616F:
case DRM_FORMAT_XBGR16161616F:
case DRM_FORMAT_ABGR16161616F:
- return INTEL_GEN(to_i915(fb->dev)) >= 11;
+ return DISPLAY_VER(to_i915(fb->dev)) >= 11;
default:
return true;
}
@@ -1687,7 +1687,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
plane_state);
@@ -1719,7 +1719,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
return false;
- if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
+ if (DISPLAY_VER(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
return false;
if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
@@ -1776,7 +1776,7 @@ static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
if (plane_id == PLANE_CURSOR)
return false;
- if (INTEL_GEN(dev_priv) >= 10)
+ if (DISPLAY_VER(dev_priv) >= 10)
return true;
if (IS_GEMINILAKE(dev_priv))
@@ -2009,11 +2009,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
}
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 11) {
plane->min_width = icl_plane_min_width;
plane->max_width = icl_plane_max_width;
plane->max_height = icl_plane_max_height;
- } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ } else if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
plane->max_width = glk_plane_max_width;
plane->max_height = skl_plane_max_height;
} else {
@@ -2029,16 +2029,16 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->min_cdclk = skl_plane_min_cdclk;
if (plane_id == PLANE_PRIMARY) {
- plane->need_async_flip_disable_wa = IS_GEN_RANGE(dev_priv, 9, 10);
+ plane->need_async_flip_disable_wa = (DISPLAY_VER(dev_priv) >= 9 && DISPLAY_VER(dev_priv) <= 10);
plane->async_flip = skl_plane_async_flip;
plane->enable_flip_done = skl_plane_enable_flip_done;
plane->disable_flip_done = skl_plane_disable_flip_done;
}
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
formats = icl_get_plane_formats(dev_priv, pipe,
plane_id, &num_formats);
- else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ else if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
formats = glk_get_plane_formats(dev_priv, pipe,
plane_id, &num_formats);
else
@@ -2046,7 +2046,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane_id, &num_formats);
plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
modifiers = gen12_get_plane_modifiers(dev_priv, plane_id);
plane_funcs = &gen12_plane_funcs;
} else {
@@ -2075,7 +2075,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
- if (INTEL_GEN(dev_priv) >= 10)
+ if (DISPLAY_VER(dev_priv) >= 10)
supported_rotations |= DRM_MODE_REFLECT_X;
drm_plane_create_rotation_property(&plane->base,
@@ -2084,7 +2084,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709);
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020);
drm_plane_create_color_properties(&plane->base,
@@ -2102,10 +2102,10 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
drm_plane_create_zpos_immutable_property(&plane->base, plane_id);
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
drm_plane_enable_fb_damage_clips(&plane->base);
- if (INTEL_GEN(dev_priv) >= 10)
+ if (DISPLAY_VER(dev_priv) >= 10)
drm_plane_create_scaling_filter_property(&plane->base,
BIT(DRM_SCALING_FILTER_DEFAULT) |
BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
@@ -2159,12 +2159,12 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
else
pixel_format = val & PLANE_CTL_FORMAT_MASK;
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
alpha = intel_de_read(dev_priv,
PLANE_COLOR_CTL(pipe, plane_id));
alpha &= PLANE_COLOR_ALPHA_MASK;
@@ -2188,7 +2188,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
case PLANE_CTL_TILED_Y:
plane_config->tiling = I915_TILING_Y;
if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
- fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
+ fb->modifier = DISPLAY_VER(dev_priv) >= 12 ?
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
I915_FORMAT_MOD_Y_TILED_CCS;
else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
@@ -2226,7 +2226,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
break;
}
- if (INTEL_GEN(dev_priv) >= 10 &&
+ if (DISPLAY_VER(dev_priv) >= 10 &&
val & PLANE_CTL_FLIP_HORIZONTAL)
plane_config->rotation |= DRM_MODE_REFLECT_X;
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 04/56] drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in intel_pm.c
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (2 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 03/56] drm/i915/display: Eliminate most usage of INTEL_GEN() Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-12 20:42 ` Srivatsa, Anusha
2021-03-11 22:35 ` [Intel-gfx] [PATCH 05/56] drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in i915_irq.c Matt Roper
` (54 subsequent siblings)
58 siblings, 1 reply; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx
Although most of the code in this file is display-related (watermarks),
there's some functions that are not (e.g., clock gating). Thus we need
to do the conversions to DISPLAY_VER() manually here rather than using
Coccinelle.
In the near-future we'll probably want to think about moving watermark
logic out of intel_pm.c and into watermark-specific files under the
display/ directory.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 132 ++++++++++++++++----------------
1 file changed, 66 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 854ffecd98d9..2616b1845719 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2339,7 +2339,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
if (IS_I945GM(dev_priv))
wm_info = &i945_wm_info;
- else if (!IS_GEN(dev_priv, 2))
+ else if (DISPLAY_VER(dev_priv) != 2)
wm_info = &i915_wm_info;
else
wm_info = &i830_a_wm_info;
@@ -2353,7 +2353,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
crtc->base.primary->state->fb;
int cpp;
- if (IS_GEN(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
cpp = 4;
else
cpp = fb->format->cpp[0];
@@ -2368,7 +2368,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
planea_wm = wm_info->max_wm;
}
- if (IS_GEN(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
wm_info = &i830_bc_wm_info;
fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
@@ -2380,7 +2380,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
crtc->base.primary->state->fb;
int cpp;
- if (IS_GEN(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
cpp = 4;
else
cpp = fb->format->cpp[0];
@@ -2652,9 +2652,9 @@ static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
static unsigned int
ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
{
- if (INTEL_GEN(dev_priv) >= 8)
+ if (DISPLAY_VER(dev_priv) >= 8)
return 3072;
- else if (INTEL_GEN(dev_priv) >= 7)
+ else if (DISPLAY_VER(dev_priv) >= 7)
return 768;
else
return 512;
@@ -2664,10 +2664,10 @@ static unsigned int
ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
int level, bool is_sprite)
{
- if (INTEL_GEN(dev_priv) >= 8)
+ if (DISPLAY_VER(dev_priv) >= 8)
/* BDW primary/sprite plane watermarks */
return level == 0 ? 255 : 2047;
- else if (INTEL_GEN(dev_priv) >= 7)
+ else if (DISPLAY_VER(dev_priv) >= 7)
/* IVB/HSW primary/sprite plane watermarks */
return level == 0 ? 127 : 1023;
else if (!is_sprite)
@@ -2681,7 +2681,7 @@ ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
static unsigned int
ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
{
- if (INTEL_GEN(dev_priv) >= 7)
+ if (DISPLAY_VER(dev_priv) >= 7)
return level == 0 ? 63 : 255;
else
return level == 0 ? 31 : 63;
@@ -2689,7 +2689,7 @@ ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
{
- if (INTEL_GEN(dev_priv) >= 8)
+ if (DISPLAY_VER(dev_priv) >= 8)
return 31;
else
return 15;
@@ -2717,7 +2717,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
* FIFO size is only half of the self
* refresh FIFO size on ILK/SNB.
*/
- if (INTEL_GEN(dev_priv) <= 6)
+ if (DISPLAY_VER(dev_priv) <= 6)
fifo_size /= 2;
}
@@ -2852,7 +2852,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
{
struct intel_uncore *uncore = &dev_priv->uncore;
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (DISPLAY_VER(dev_priv) >= 9) {
u32 val;
int ret, i;
int level, max_level = ilk_wm_max_level(dev_priv);
@@ -2944,14 +2944,14 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
wm[2] = (sskpd >> 12) & 0xFF;
wm[3] = (sskpd >> 20) & 0x1FF;
wm[4] = (sskpd >> 32) & 0x1FF;
- } else if (INTEL_GEN(dev_priv) >= 6) {
+ } else if (DISPLAY_VER(dev_priv) >= 6) {
u32 sskpd = intel_uncore_read(uncore, MCH_SSKPD);
wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
- } else if (INTEL_GEN(dev_priv) >= 5) {
+ } else if (DISPLAY_VER(dev_priv) >= 5) {
u32 mltr = intel_uncore_read(uncore, MLTR_ILK);
/* ILK primary LP0 latency is 700 ns */
@@ -2967,7 +2967,7 @@ static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
u16 wm[5])
{
/* ILK sprite LP0 latency is 1300 ns */
- if (IS_GEN(dev_priv, 5))
+ if (DISPLAY_VER(dev_priv) == 5)
wm[0] = 13;
}
@@ -2975,18 +2975,18 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
u16 wm[5])
{
/* ILK cursor LP0 latency is 1300 ns */
- if (IS_GEN(dev_priv, 5))
+ if (DISPLAY_VER(dev_priv) == 5)
wm[0] = 13;
}
int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
{
/* how many WM levels are we expecting */
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
return 7;
else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
return 4;
- else if (INTEL_GEN(dev_priv) >= 6)
+ else if (DISPLAY_VER(dev_priv) >= 6)
return 3;
else
return 2;
@@ -3012,7 +3012,7 @@ static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
* - latencies are in us on gen9.
* - before then, WM1+ latency values are in 0.5us units
*/
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
latency *= 10;
else if (level > 0)
latency *= 5;
@@ -3105,7 +3105,7 @@ static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
- if (IS_GEN(dev_priv, 6)) {
+ if (DISPLAY_VER(dev_priv) == 6) {
snb_wm_latency_quirk(dev_priv);
snb_wm_lp3_irq_quirk(dev_priv);
}
@@ -3176,7 +3176,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
usable_level = max_level;
/* ILK/SNB: LP2+ watermarks only w/o sprites */
- if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
+ if (DISPLAY_VER(dev_priv) <= 6 && pipe_wm->sprites_enabled)
usable_level = 1;
/* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
@@ -3318,12 +3318,12 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv,
int last_enabled_level = max_level;
/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
- if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
+ if ((DISPLAY_VER(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
config->num_pipes_active > 1)
last_enabled_level = 0;
/* ILK: FBC WM must be disabled always */
- merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
+ merged->fbc_wm_enabled = DISPLAY_VER(dev_priv) >= 6;
/* merge each WM1+ level */
for (level = 1; level <= max_level; level++) {
@@ -3354,7 +3354,7 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv,
* What we should check here is whether FBC can be
* enabled sometime later.
*/
- if (IS_GEN(dev_priv, 5) && !merged->fbc_wm_enabled &&
+ if (DISPLAY_VER(dev_priv) == 5 && !merged->fbc_wm_enabled &&
intel_fbc_is_active(dev_priv)) {
for (level = 2; level <= max_level; level++) {
struct intel_wm_level *wm = &merged->wm[level];
@@ -3411,7 +3411,7 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
if (r->enable)
results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
- if (INTEL_GEN(dev_priv) >= 8)
+ if (DISPLAY_VER(dev_priv) >= 8)
results->wm_lp[wm_lp - 1] |=
r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
else
@@ -3422,7 +3422,7 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
* Always set WM1S_LP_EN when spr_val != 0, even if the
* level is disabled. Doing otherwise could cause underruns.
*/
- if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
+ if (DISPLAY_VER(dev_priv) <= 6 && r->spr_val) {
drm_WARN_ON(&dev_priv->drm, wm_lp != 1);
results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
} else
@@ -3612,7 +3612,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
previous->wm_lp_spr[0] != results->wm_lp_spr[0])
intel_uncore_write(&dev_priv->uncore, WM1S_LP_ILK, results->wm_lp_spr[0]);
- if (INTEL_GEN(dev_priv) >= 7) {
+ if (DISPLAY_VER(dev_priv) >= 7) {
if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
intel_uncore_write(&dev_priv->uncore, WM2S_LP_IVB, results->wm_lp_spr[1]);
if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
@@ -3660,14 +3660,14 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
static bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
- return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
+ return (IS_GEN9_BC(dev_priv) || DISPLAY_VER(dev_priv) >= 10) &&
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
}
static void
skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
{
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
u32 val = 0;
int ret;
@@ -3680,17 +3680,17 @@ skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
}
drm_dbg(&dev_priv->drm, "Couldn't read SAGV block time!\n");
- } else if (IS_GEN(dev_priv, 11)) {
+ } else if (DISPLAY_VER(dev_priv) == 11) {
dev_priv->sagv_block_time_us = 10;
return;
- } else if (IS_GEN(dev_priv, 10)) {
+ } else if (DISPLAY_VER(dev_priv) == 10) {
dev_priv->sagv_block_time_us = 20;
return;
- } else if (IS_GEN(dev_priv, 9)) {
+ } else if (DISPLAY_VER(dev_priv) == 9) {
dev_priv->sagv_block_time_us = 30;
return;
} else {
- MISSING_CASE(INTEL_GEN(dev_priv));
+ MISSING_CASE(DISPLAY_VER(dev_priv));
}
/* Default to an unusable block time */
@@ -3797,7 +3797,7 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
if (!new_bw_state)
return;
- if (INTEL_GEN(dev_priv) < 11 && !intel_can_enable_sagv(dev_priv, new_bw_state)) {
+ if (DISPLAY_VER(dev_priv) < 11 && !intel_can_enable_sagv(dev_priv, new_bw_state)) {
intel_disable_sagv(dev_priv);
return;
}
@@ -3848,7 +3848,7 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
if (!new_bw_state)
return;
- if (INTEL_GEN(dev_priv) < 11 && intel_can_enable_sagv(dev_priv, new_bw_state)) {
+ if (DISPLAY_VER(dev_priv) < 11 && intel_can_enable_sagv(dev_priv, new_bw_state)) {
intel_enable_sagv(dev_priv);
return;
}
@@ -3936,7 +3936,7 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
return tgl_crtc_can_enable_sagv(crtc_state);
else
return skl_crtc_can_enable_sagv(crtc_state);
@@ -3945,7 +3945,7 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
const struct intel_bw_state *bw_state)
{
- if (INTEL_GEN(dev_priv) < 11 &&
+ if (DISPLAY_VER(dev_priv) < 11 &&
bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
return false;
@@ -3998,7 +3998,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
* latter from the plane commit hooks (especially in the legacy
* cursor case)
*/
- pipe_wm->use_sagv_wm = INTEL_GEN(dev_priv) >= 12 &&
+ pipe_wm->use_sagv_wm = DISPLAY_VER(dev_priv) >= 12 &&
intel_can_enable_sagv(dev_priv, new_bw_state);
}
@@ -4022,7 +4022,7 @@ static int intel_dbuf_size(struct drm_i915_private *dev_priv)
drm_WARN_ON(&dev_priv->drm, ddb_size == 0);
- if (INTEL_GEN(dev_priv) < 11)
+ if (DISPLAY_VER(dev_priv) < 11)
return ddb_size - 4; /* 4 blocks for bypass path allocation */
return ddb_size;
@@ -4277,7 +4277,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
val & PLANE_CTL_ORDER_RGBX,
val & PLANE_CTL_ALPHA_MASK);
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 11) {
val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
} else {
@@ -4601,9 +4601,9 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- if (IS_GEN(dev_priv, 12))
+ if (DISPLAY_VER(dev_priv) == 12)
return tgl_compute_dbuf_slices(pipe, active_pipes);
- else if (IS_GEN(dev_priv, 11))
+ else if (DISPLAY_VER(dev_priv) == 11)
return icl_compute_dbuf_slices(pipe, active_pipes);
/*
* For anything else just return one slice yet.
@@ -4796,7 +4796,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
if (!crtc_state->hw.active)
return 0;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
total_data_rate =
icl_get_total_relative_data_rate(state, crtc);
else
@@ -4910,7 +4910,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
/* Gen11+ uses a separate plane for UV watermarks */
drm_WARN_ON(&dev_priv->drm,
- INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
+ DISPLAY_VER(dev_priv) >= 11 && uv_total[plane_id]);
/* Leave disabled planes at (0,0) */
if (total[plane_id]) {
@@ -4957,7 +4957,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
* Wa_1408961008:icl, ehl
* Underruns with WM1+ disabled
*/
- if (IS_GEN(dev_priv, 11) &&
+ if (DISPLAY_VER(dev_priv) == 11 &&
level == 1 && wm->wm[0].plane_en) {
wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
@@ -5006,7 +5006,7 @@ skl_wm_method1(const struct drm_i915_private *dev_priv, u32 pixel_rate,
wm_intermediate_val = latency * pixel_rate * cpp;
ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
ret = add_fixed16_u32(ret, 1);
return ret;
@@ -5086,7 +5086,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
wp->cpp = format->cpp[color_plane];
wp->plane_pixel_rate = plane_pixel_rate;
- if (INTEL_GEN(dev_priv) >= 11 &&
+ if (DISPLAY_VER(dev_priv) >= 11 &&
modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1)
wp->dbuf_block_size = 256;
else
@@ -5120,7 +5120,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
wp->y_min_scanlines,
wp->dbuf_block_size);
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
interm_pbpl++;
wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
@@ -5130,7 +5130,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
wp->dbuf_block_size);
if (!wp->x_tiled ||
- INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
interm_pbpl++;
wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
@@ -5169,7 +5169,7 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
{
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
return true;
/* The number of lines are ignored for the level 0 watermark. */
@@ -5222,7 +5222,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
(wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
selected_result = method2;
} else if (latency >= wp->linetime_us) {
- if (IS_GEN(dev_priv, 9) &&
+ if (DISPLAY_VER(dev_priv) == 9 &&
!IS_GEMINILAKE(dev_priv))
selected_result = min_fixed16(method1, method2);
else
@@ -5263,7 +5263,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
}
}
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 11) {
if (wp->y_tiled) {
int extra_lines;
@@ -5302,7 +5302,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
result->min_ddb_alloc = max(min_ddb_alloc, res_blocks) + 1;
result->plane_en = true;
- if (INTEL_GEN(dev_priv) < 12)
+ if (DISPLAY_VER(dev_priv) < 12)
result->can_sagv = latency >= dev_priv->sagv_block_time_us;
}
@@ -5359,7 +5359,7 @@ static void skl_compute_transition_wm(struct drm_i915_private *dev_priv,
if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
return;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
trans_min = 4;
else
trans_min = 14;
@@ -5422,7 +5422,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
skl_compute_transition_wm(dev_priv, &wm->trans_wm,
&wm->wm[0], &wm_params);
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
skl_compute_transition_wm(dev_priv, &wm->sagv.trans_wm,
@@ -5544,7 +5544,7 @@ static int skl_build_pipe_wm(struct intel_atomic_state *state,
if (plane->pipe != crtc->pipe)
continue;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
ret = icl_build_plane_wm(crtc_state, plane_state);
else
ret = skl_build_plane_wm(crtc_state, plane_state);
@@ -5605,7 +5605,7 @@ void skl_write_plane_wm(struct intel_plane *plane,
skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
skl_plane_trans_wm(pipe_wm, plane_id));
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 11) {
skl_ddb_entry_write(dev_priv,
PLANE_BUF_CFG(pipe, plane_id), ddb_y);
return;
@@ -6135,7 +6135,7 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
ilk_wm_merge(dev_priv, &config, &max, &lp_wm_1_2);
/* 5/6 split only in single pipe config on IVB+ */
- if (INTEL_GEN(dev_priv) >= 7 &&
+ if (DISPLAY_VER(dev_priv) >= 7 &&
config.num_pipes_active == 1 && config.sprites_enabled) {
ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_5_6, &max);
ilk_wm_merge(dev_priv, &config, &max, &lp_wm_5_6);
@@ -6221,7 +6221,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
skl_wm_level_from_reg_val(val, &wm->trans_wm);
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
wm->sagv.wm0 = wm->wm[0];
wm->sagv.trans_wm = wm->trans_wm;
}
@@ -6748,7 +6748,7 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
hw->wm_lp[2] = intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK);
hw->wm_lp_spr[0] = intel_uncore_read(&dev_priv->uncore, WM1S_LP_ILK);
- if (INTEL_GEN(dev_priv) >= 7) {
+ if (DISPLAY_VER(dev_priv) >= 7) {
hw->wm_lp_spr[1] = intel_uncore_read(&dev_priv->uncore, WM2S_LP_IVB);
hw->wm_lp_spr[2] = intel_uncore_read(&dev_priv->uncore, WM3S_LP_IVB);
}
@@ -7649,15 +7649,15 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
skl_setup_sagv_block_time(dev_priv);
/* For FIFO watermark updates */
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (DISPLAY_VER(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
dev_priv->display.compute_global_watermarks = skl_compute_wm;
} else if (HAS_PCH_SPLIT(dev_priv)) {
ilk_setup_wm_latency(dev_priv);
- if ((IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[1] &&
+ if ((DISPLAY_VER(dev_priv) == 5 && dev_priv->wm.pri_latency[1] &&
dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
- (!IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[0] &&
+ (DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&
dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
dev_priv->display.compute_intermediate_wm =
@@ -7700,12 +7700,12 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->display.update_wm = NULL;
} else
dev_priv->display.update_wm = pnv_update_wm;
- } else if (IS_GEN(dev_priv, 4)) {
+ } else if (DISPLAY_VER(dev_priv) == 4) {
dev_priv->display.update_wm = i965_update_wm;
- } else if (IS_GEN(dev_priv, 3)) {
+ } else if (DISPLAY_VER(dev_priv) == 3) {
dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
- } else if (IS_GEN(dev_priv, 2)) {
+ } else if (DISPLAY_VER(dev_priv) == 2) {
if (INTEL_NUM_PIPES(dev_priv) == 1) {
dev_priv->display.update_wm = i845_update_wm;
dev_priv->display.get_fifo_size = i845_get_fifo_size;
--
2.25.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Intel-gfx] [PATCH 04/56] drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in intel_pm.c
2021-03-11 22:35 ` [Intel-gfx] [PATCH 04/56] drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in intel_pm.c Matt Roper
@ 2021-03-12 20:42 ` Srivatsa, Anusha
2021-03-12 20:46 ` Matt Roper
0 siblings, 1 reply; 74+ messages in thread
From: Srivatsa, Anusha @ 2021-03-12 20:42 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt
> Roper
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 04/56] drm/i915: Convert INTEL_GEN() to
> DISPLAY_VER() as appropriate in intel_pm.c
>
> Although most of the code in this file is display-related (watermarks), there's
> some functions that are not (e.g., clock gating). Thus we need to do the
> conversions to DISPLAY_VER() manually here rather than using Coccinelle.
>
> In the near-future we'll probably want to think about moving watermark
> logic out of intel_pm.c and into watermark-specific files under the display/
> directory.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Any reason Patch 4 and Patch 5 are not one single patch? It looks like both replace INTEL_GEN() with DISPLAY_VER() where necessary...
Anusha
> ---
> drivers/gpu/drm/i915/intel_pm.c | 132 ++++++++++++++++----------------
> 1 file changed, 66 insertions(+), 66 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c index 854ffecd98d9..2616b1845719
> 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2339,7 +2339,7 @@ static void i9xx_update_wm(struct intel_crtc
> *unused_crtc)
>
> if (IS_I945GM(dev_priv))
> wm_info = &i945_wm_info;
> - else if (!IS_GEN(dev_priv, 2))
> + else if (DISPLAY_VER(dev_priv) != 2)
> wm_info = &i915_wm_info;
> else
> wm_info = &i830_a_wm_info;
> @@ -2353,7 +2353,7 @@ static void i9xx_update_wm(struct intel_crtc
> *unused_crtc)
> crtc->base.primary->state->fb;
> int cpp;
>
> - if (IS_GEN(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
> cpp = 4;
> else
> cpp = fb->format->cpp[0];
> @@ -2368,7 +2368,7 @@ static void i9xx_update_wm(struct intel_crtc
> *unused_crtc)
> planea_wm = wm_info->max_wm;
> }
>
> - if (IS_GEN(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
> wm_info = &i830_bc_wm_info;
>
> fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B); @@ -
> 2380,7 +2380,7 @@ static void i9xx_update_wm(struct intel_crtc
> *unused_crtc)
> crtc->base.primary->state->fb;
> int cpp;
>
> - if (IS_GEN(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
> cpp = 4;
> else
> cpp = fb->format->cpp[0];
> @@ -2652,9 +2652,9 @@ static u32 ilk_compute_fbc_wm(const struct
> intel_crtc_state *crtc_state, static unsigned int ilk_display_fifo_size(const
> struct drm_i915_private *dev_priv) {
> - if (INTEL_GEN(dev_priv) >= 8)
> + if (DISPLAY_VER(dev_priv) >= 8)
> return 3072;
> - else if (INTEL_GEN(dev_priv) >= 7)
> + else if (DISPLAY_VER(dev_priv) >= 7)
> return 768;
> else
> return 512;
> @@ -2664,10 +2664,10 @@ static unsigned int
> ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
> int level, bool is_sprite)
> {
> - if (INTEL_GEN(dev_priv) >= 8)
> + if (DISPLAY_VER(dev_priv) >= 8)
> /* BDW primary/sprite plane watermarks */
> return level == 0 ? 255 : 2047;
> - else if (INTEL_GEN(dev_priv) >= 7)
> + else if (DISPLAY_VER(dev_priv) >= 7)
> /* IVB/HSW primary/sprite plane watermarks */
> return level == 0 ? 127 : 1023;
> else if (!is_sprite)
> @@ -2681,7 +2681,7 @@ ilk_plane_wm_reg_max(const struct
> drm_i915_private *dev_priv, static unsigned int
> ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level) {
> - if (INTEL_GEN(dev_priv) >= 7)
> + if (DISPLAY_VER(dev_priv) >= 7)
> return level == 0 ? 63 : 255;
> else
> return level == 0 ? 31 : 63;
> @@ -2689,7 +2689,7 @@ ilk_cursor_wm_reg_max(const struct
> drm_i915_private *dev_priv, int level)
>
> static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private
> *dev_priv) {
> - if (INTEL_GEN(dev_priv) >= 8)
> + if (DISPLAY_VER(dev_priv) >= 8)
> return 31;
> else
> return 15;
> @@ -2717,7 +2717,7 @@ static unsigned int ilk_plane_wm_max(const struct
> drm_i915_private *dev_priv,
> * FIFO size is only half of the self
> * refresh FIFO size on ILK/SNB.
> */
> - if (INTEL_GEN(dev_priv) <= 6)
> + if (DISPLAY_VER(dev_priv) <= 6)
> fifo_size /= 2;
> }
>
> @@ -2852,7 +2852,7 @@ static void intel_read_wm_latency(struct
> drm_i915_private *dev_priv, {
> struct intel_uncore *uncore = &dev_priv->uncore;
>
> - if (INTEL_GEN(dev_priv) >= 9) {
> + if (DISPLAY_VER(dev_priv) >= 9) {
> u32 val;
> int ret, i;
> int level, max_level = ilk_wm_max_level(dev_priv); @@ -
> 2944,14 +2944,14 @@ static void intel_read_wm_latency(struct
> drm_i915_private *dev_priv,
> wm[2] = (sskpd >> 12) & 0xFF;
> wm[3] = (sskpd >> 20) & 0x1FF;
> wm[4] = (sskpd >> 32) & 0x1FF;
> - } else if (INTEL_GEN(dev_priv) >= 6) {
> + } else if (DISPLAY_VER(dev_priv) >= 6) {
> u32 sskpd = intel_uncore_read(uncore, MCH_SSKPD);
>
> wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
> wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
> wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
> wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
> - } else if (INTEL_GEN(dev_priv) >= 5) {
> + } else if (DISPLAY_VER(dev_priv) >= 5) {
> u32 mltr = intel_uncore_read(uncore, MLTR_ILK);
>
> /* ILK primary LP0 latency is 700 ns */ @@ -2967,7 +2967,7
> @@ static void intel_fixup_spr_wm_latency(struct drm_i915_private
> *dev_priv,
> u16 wm[5])
> {
> /* ILK sprite LP0 latency is 1300 ns */
> - if (IS_GEN(dev_priv, 5))
> + if (DISPLAY_VER(dev_priv) == 5)
> wm[0] = 13;
> }
>
> @@ -2975,18 +2975,18 @@ static void intel_fixup_cur_wm_latency(struct
> drm_i915_private *dev_priv,
> u16 wm[5])
> {
> /* ILK cursor LP0 latency is 1300 ns */
> - if (IS_GEN(dev_priv, 5))
> + if (DISPLAY_VER(dev_priv) == 5)
> wm[0] = 13;
> }
>
> int ilk_wm_max_level(const struct drm_i915_private *dev_priv) {
> /* how many WM levels are we expecting */
> - if (INTEL_GEN(dev_priv) >= 9)
> + if (DISPLAY_VER(dev_priv) >= 9)
> return 7;
> else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> return 4;
> - else if (INTEL_GEN(dev_priv) >= 6)
> + else if (DISPLAY_VER(dev_priv) >= 6)
> return 3;
> else
> return 2;
> @@ -3012,7 +3012,7 @@ static void intel_print_wm_latency(struct
> drm_i915_private *dev_priv,
> * - latencies are in us on gen9.
> * - before then, WM1+ latency values are in 0.5us units
> */
> - if (INTEL_GEN(dev_priv) >= 9)
> + if (DISPLAY_VER(dev_priv) >= 9)
> latency *= 10;
> else if (level > 0)
> latency *= 5;
> @@ -3105,7 +3105,7 @@ static void ilk_setup_wm_latency(struct
> drm_i915_private *dev_priv)
> intel_print_wm_latency(dev_priv, "Sprite", dev_priv-
> >wm.spr_latency);
> intel_print_wm_latency(dev_priv, "Cursor", dev_priv-
> >wm.cur_latency);
>
> - if (IS_GEN(dev_priv, 6)) {
> + if (DISPLAY_VER(dev_priv) == 6) {
> snb_wm_latency_quirk(dev_priv);
> snb_wm_lp3_irq_quirk(dev_priv);
> }
> @@ -3176,7 +3176,7 @@ static int ilk_compute_pipe_wm(struct
> intel_crtc_state *crtc_state)
> usable_level = max_level;
>
> /* ILK/SNB: LP2+ watermarks only w/o sprites */
> - if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
> + if (DISPLAY_VER(dev_priv) <= 6 && pipe_wm->sprites_enabled)
> usable_level = 1;
>
> /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ @@ -3318,12
> +3318,12 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv,
> int last_enabled_level = max_level;
>
> /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
> - if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
> + if ((DISPLAY_VER(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
> config->num_pipes_active > 1)
> last_enabled_level = 0;
>
> /* ILK: FBC WM must be disabled always */
> - merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
> + merged->fbc_wm_enabled = DISPLAY_VER(dev_priv) >= 6;
>
> /* merge each WM1+ level */
> for (level = 1; level <= max_level; level++) { @@ -3354,7 +3354,7 @@
> static void ilk_wm_merge(struct drm_i915_private *dev_priv,
> * What we should check here is whether FBC can be
> * enabled sometime later.
> */
> - if (IS_GEN(dev_priv, 5) && !merged->fbc_wm_enabled &&
> + if (DISPLAY_VER(dev_priv) == 5 && !merged->fbc_wm_enabled &&
> intel_fbc_is_active(dev_priv)) {
> for (level = 2; level <= max_level; level++) {
> struct intel_wm_level *wm = &merged->wm[level];
> @@ -3411,7 +3411,7 @@ static void ilk_compute_wm_results(struct
> drm_i915_private *dev_priv,
> if (r->enable)
> results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
>
> - if (INTEL_GEN(dev_priv) >= 8)
> + if (DISPLAY_VER(dev_priv) >= 8)
> results->wm_lp[wm_lp - 1] |=
> r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
> else
> @@ -3422,7 +3422,7 @@ static void ilk_compute_wm_results(struct
> drm_i915_private *dev_priv,
> * Always set WM1S_LP_EN when spr_val != 0, even if the
> * level is disabled. Doing otherwise could cause underruns.
> */
> - if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
> + if (DISPLAY_VER(dev_priv) <= 6 && r->spr_val) {
> drm_WARN_ON(&dev_priv->drm, wm_lp != 1);
> results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r-
> >spr_val;
> } else
> @@ -3612,7 +3612,7 @@ static void ilk_write_wm_values(struct
> drm_i915_private *dev_priv,
> previous->wm_lp_spr[0] != results->wm_lp_spr[0])
> intel_uncore_write(&dev_priv->uncore, WM1S_LP_ILK,
> results->wm_lp_spr[0]);
>
> - if (INTEL_GEN(dev_priv) >= 7) {
> + if (DISPLAY_VER(dev_priv) >= 7) {
> if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] !=
> results->wm_lp_spr[1])
> intel_uncore_write(&dev_priv->uncore,
> WM2S_LP_IVB, results->wm_lp_spr[1]);
> if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] !=
> results->wm_lp_spr[2]) @@ -3660,14 +3660,14 @@ static bool
> skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv) static bool
> intel_has_sagv(struct drm_i915_private *dev_priv) {
> - return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
> + return (IS_GEN9_BC(dev_priv) || DISPLAY_VER(dev_priv) >= 10) &&
> dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED; }
>
> static void
> skl_setup_sagv_block_time(struct drm_i915_private *dev_priv) {
> - if (INTEL_GEN(dev_priv) >= 12) {
> + if (DISPLAY_VER(dev_priv) >= 12) {
> u32 val = 0;
> int ret;
>
> @@ -3680,17 +3680,17 @@ skl_setup_sagv_block_time(struct
> drm_i915_private *dev_priv)
> }
>
> drm_dbg(&dev_priv->drm, "Couldn't read SAGV block
> time!\n");
> - } else if (IS_GEN(dev_priv, 11)) {
> + } else if (DISPLAY_VER(dev_priv) == 11) {
> dev_priv->sagv_block_time_us = 10;
> return;
> - } else if (IS_GEN(dev_priv, 10)) {
> + } else if (DISPLAY_VER(dev_priv) == 10) {
> dev_priv->sagv_block_time_us = 20;
> return;
> - } else if (IS_GEN(dev_priv, 9)) {
> + } else if (DISPLAY_VER(dev_priv) == 9) {
> dev_priv->sagv_block_time_us = 30;
> return;
> } else {
> - MISSING_CASE(INTEL_GEN(dev_priv));
> + MISSING_CASE(DISPLAY_VER(dev_priv));
> }
>
> /* Default to an unusable block time */ @@ -3797,7 +3797,7 @@
> void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> if (!new_bw_state)
> return;
>
> - if (INTEL_GEN(dev_priv) < 11 && !intel_can_enable_sagv(dev_priv,
> new_bw_state)) {
> + if (DISPLAY_VER(dev_priv) < 11 && !intel_can_enable_sagv(dev_priv,
> +new_bw_state)) {
> intel_disable_sagv(dev_priv);
> return;
> }
> @@ -3848,7 +3848,7 @@ void intel_sagv_post_plane_update(struct
> intel_atomic_state *state)
> if (!new_bw_state)
> return;
>
> - if (INTEL_GEN(dev_priv) < 11 && intel_can_enable_sagv(dev_priv,
> new_bw_state)) {
> + if (DISPLAY_VER(dev_priv) < 11 && intel_can_enable_sagv(dev_priv,
> +new_bw_state)) {
> intel_enable_sagv(dev_priv);
> return;
> }
> @@ -3936,7 +3936,7 @@ static bool intel_crtc_can_enable_sagv(const struct
> intel_crtc_state *crtc_state
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - if (INTEL_GEN(dev_priv) >= 12)
> + if (DISPLAY_VER(dev_priv) >= 12)
> return tgl_crtc_can_enable_sagv(crtc_state);
> else
> return skl_crtc_can_enable_sagv(crtc_state);
> @@ -3945,7 +3945,7 @@ static bool intel_crtc_can_enable_sagv(const struct
> intel_crtc_state *crtc_state bool intel_can_enable_sagv(struct
> drm_i915_private *dev_priv,
> const struct intel_bw_state *bw_state) {
> - if (INTEL_GEN(dev_priv) < 11 &&
> + if (DISPLAY_VER(dev_priv) < 11 &&
> bw_state->active_pipes && !is_power_of_2(bw_state-
> >active_pipes))
> return false;
>
> @@ -3998,7 +3998,7 @@ static int intel_compute_sagv_mask(struct
> intel_atomic_state *state)
> * latter from the plane commit hooks (especially in the
> legacy
> * cursor case)
> */
> - pipe_wm->use_sagv_wm = INTEL_GEN(dev_priv) >= 12 &&
> + pipe_wm->use_sagv_wm = DISPLAY_VER(dev_priv) >= 12 &&
> intel_can_enable_sagv(dev_priv,
> new_bw_state);
> }
>
> @@ -4022,7 +4022,7 @@ static int intel_dbuf_size(struct drm_i915_private
> *dev_priv)
>
> drm_WARN_ON(&dev_priv->drm, ddb_size == 0);
>
> - if (INTEL_GEN(dev_priv) < 11)
> + if (DISPLAY_VER(dev_priv) < 11)
> return ddb_size - 4; /* 4 blocks for bypass path allocation */
>
> return ddb_size;
> @@ -4277,7 +4277,7 @@ skl_ddb_get_hw_plane_state(struct
> drm_i915_private *dev_priv,
> val & PLANE_CTL_ORDER_RGBX,
> val & PLANE_CTL_ALPHA_MASK);
>
> - if (INTEL_GEN(dev_priv) >= 11) {
> + if (DISPLAY_VER(dev_priv) >= 11) {
> val = intel_uncore_read(&dev_priv->uncore,
> PLANE_BUF_CFG(pipe, plane_id));
> skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
> } else {
> @@ -4601,9 +4601,9 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc
> *crtc, u8 active_pipes)
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> - if (IS_GEN(dev_priv, 12))
> + if (DISPLAY_VER(dev_priv) == 12)
> return tgl_compute_dbuf_slices(pipe, active_pipes);
> - else if (IS_GEN(dev_priv, 11))
> + else if (DISPLAY_VER(dev_priv) == 11)
> return icl_compute_dbuf_slices(pipe, active_pipes);
> /*
> * For anything else just return one slice yet.
> @@ -4796,7 +4796,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state
> *state,
> if (!crtc_state->hw.active)
> return 0;
>
> - if (INTEL_GEN(dev_priv) >= 11)
> + if (DISPLAY_VER(dev_priv) >= 11)
> total_data_rate =
> icl_get_total_relative_data_rate(state, crtc);
> else
> @@ -4910,7 +4910,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state
> *state,
>
> /* Gen11+ uses a separate plane for UV watermarks */
> drm_WARN_ON(&dev_priv->drm,
> - INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
> + DISPLAY_VER(dev_priv) >= 11 &&
> uv_total[plane_id]);
>
> /* Leave disabled planes at (0,0) */
> if (total[plane_id]) {
> @@ -4957,7 +4957,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state
> *state,
> * Wa_1408961008:icl, ehl
> * Underruns with WM1+ disabled
> */
> - if (IS_GEN(dev_priv, 11) &&
> + if (DISPLAY_VER(dev_priv) == 11 &&
> level == 1 && wm->wm[0].plane_en) {
> wm->wm[level].plane_res_b = wm-
> >wm[0].plane_res_b;
> wm->wm[level].plane_res_l = wm-
> >wm[0].plane_res_l; @@ -5006,7 +5006,7 @@ skl_wm_method1(const
> struct drm_i915_private *dev_priv, u32 pixel_rate,
> wm_intermediate_val = latency * pixel_rate * cpp;
> ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
>
> - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> ret = add_fixed16_u32(ret, 1);
>
> return ret;
> @@ -5086,7 +5086,7 @@ skl_compute_wm_params(const struct
> intel_crtc_state *crtc_state,
> wp->cpp = format->cpp[color_plane];
> wp->plane_pixel_rate = plane_pixel_rate;
>
> - if (INTEL_GEN(dev_priv) >= 11 &&
> + if (DISPLAY_VER(dev_priv) >= 11 &&
> modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1)
> wp->dbuf_block_size = 256;
> else
> @@ -5120,7 +5120,7 @@ skl_compute_wm_params(const struct
> intel_crtc_state *crtc_state,
> wp->y_min_scanlines,
> wp->dbuf_block_size);
>
> - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 10 ||
> IS_GEMINILAKE(dev_priv))
> interm_pbpl++;
>
> wp->plane_blocks_per_line = div_fixed16(interm_pbpl, @@ -
> 5130,7 +5130,7 @@ skl_compute_wm_params(const struct intel_crtc_state
> *crtc_state,
> wp->dbuf_block_size);
>
> if (!wp->x_tiled ||
> - INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> interm_pbpl++;
>
> wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
> @@ -5169,7 +5169,7 @@ skl_compute_plane_wm_params(const struct
> intel_crtc_state *crtc_state,
>
> static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level) {
> - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> return true;
>
> /* The number of lines are ignored for the level 0 watermark. */ @@
> -5222,7 +5222,7 @@ static void skl_compute_plane_wm(const struct
> intel_crtc_state *crtc_state,
> (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
> selected_result = method2;
> } else if (latency >= wp->linetime_us) {
> - if (IS_GEN(dev_priv, 9) &&
> + if (DISPLAY_VER(dev_priv) == 9 &&
> !IS_GEMINILAKE(dev_priv))
> selected_result = min_fixed16(method1,
> method2);
> else
> @@ -5263,7 +5263,7 @@ static void skl_compute_plane_wm(const struct
> intel_crtc_state *crtc_state,
> }
> }
>
> - if (INTEL_GEN(dev_priv) >= 11) {
> + if (DISPLAY_VER(dev_priv) >= 11) {
> if (wp->y_tiled) {
> int extra_lines;
>
> @@ -5302,7 +5302,7 @@ static void skl_compute_plane_wm(const struct
> intel_crtc_state *crtc_state,
> result->min_ddb_alloc = max(min_ddb_alloc, res_blocks) + 1;
> result->plane_en = true;
>
> - if (INTEL_GEN(dev_priv) < 12)
> + if (DISPLAY_VER(dev_priv) < 12)
> result->can_sagv = latency >= dev_priv->sagv_block_time_us;
> }
>
> @@ -5359,7 +5359,7 @@ static void skl_compute_transition_wm(struct
> drm_i915_private *dev_priv,
> if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
> return;
>
> - if (INTEL_GEN(dev_priv) >= 11)
> + if (DISPLAY_VER(dev_priv) >= 11)
> trans_min = 4;
> else
> trans_min = 14;
> @@ -5422,7 +5422,7 @@ static int skl_build_plane_wm_single(struct
> intel_crtc_state *crtc_state,
> skl_compute_transition_wm(dev_priv, &wm->trans_wm,
> &wm->wm[0], &wm_params);
>
> - if (INTEL_GEN(dev_priv) >= 12) {
> + if (DISPLAY_VER(dev_priv) >= 12) {
> tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
>
> skl_compute_transition_wm(dev_priv, &wm-
> >sagv.trans_wm, @@ -5544,7 +5544,7 @@ static int
> skl_build_pipe_wm(struct intel_atomic_state *state,
> if (plane->pipe != crtc->pipe)
> continue;
>
> - if (INTEL_GEN(dev_priv) >= 11)
> + if (DISPLAY_VER(dev_priv) >= 11)
> ret = icl_build_plane_wm(crtc_state, plane_state);
> else
> ret = skl_build_plane_wm(crtc_state, plane_state);
> @@ -5605,7 +5605,7 @@ void skl_write_plane_wm(struct intel_plane
> *plane,
> skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
> skl_plane_trans_wm(pipe_wm, plane_id));
>
> - if (INTEL_GEN(dev_priv) >= 11) {
> + if (DISPLAY_VER(dev_priv) >= 11) {
> skl_ddb_entry_write(dev_priv,
> PLANE_BUF_CFG(pipe, plane_id), ddb_y);
> return;
> @@ -6135,7 +6135,7 @@ static void ilk_program_watermarks(struct
> drm_i915_private *dev_priv)
> ilk_wm_merge(dev_priv, &config, &max, &lp_wm_1_2);
>
> /* 5/6 split only in single pipe config on IVB+ */
> - if (INTEL_GEN(dev_priv) >= 7 &&
> + if (DISPLAY_VER(dev_priv) >= 7 &&
> config.num_pipes_active == 1 && config.sprites_enabled) {
> ilk_compute_wm_maximums(dev_priv, 1, &config,
> INTEL_DDB_PART_5_6, &max);
> ilk_wm_merge(dev_priv, &config, &max, &lp_wm_5_6); @@
> -6221,7 +6221,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
>
> skl_wm_level_from_reg_val(val, &wm->trans_wm);
>
> - if (INTEL_GEN(dev_priv) >= 12) {
> + if (DISPLAY_VER(dev_priv) >= 12) {
> wm->sagv.wm0 = wm->wm[0];
> wm->sagv.trans_wm = wm->trans_wm;
> }
> @@ -6748,7 +6748,7 @@ void ilk_wm_get_hw_state(struct
> drm_i915_private *dev_priv)
> hw->wm_lp[2] = intel_uncore_read(&dev_priv->uncore,
> WM3_LP_ILK);
>
> hw->wm_lp_spr[0] = intel_uncore_read(&dev_priv->uncore,
> WM1S_LP_ILK);
> - if (INTEL_GEN(dev_priv) >= 7) {
> + if (DISPLAY_VER(dev_priv) >= 7) {
> hw->wm_lp_spr[1] = intel_uncore_read(&dev_priv->uncore,
> WM2S_LP_IVB);
> hw->wm_lp_spr[2] = intel_uncore_read(&dev_priv->uncore,
> WM3S_LP_IVB);
> }
> @@ -7649,15 +7649,15 @@ void intel_init_pm(struct drm_i915_private
> *dev_priv)
> skl_setup_sagv_block_time(dev_priv);
>
> /* For FIFO watermark updates */
> - if (INTEL_GEN(dev_priv) >= 9) {
> + if (DISPLAY_VER(dev_priv) >= 9) {
> skl_setup_wm_latency(dev_priv);
> dev_priv->display.compute_global_watermarks =
> skl_compute_wm;
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> ilk_setup_wm_latency(dev_priv);
>
> - if ((IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[1] &&
> + if ((DISPLAY_VER(dev_priv) == 5 && dev_priv-
> >wm.pri_latency[1] &&
> dev_priv->wm.spr_latency[1] && dev_priv-
> >wm.cur_latency[1]) ||
> - (!IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[0] &&
> + (DISPLAY_VER(dev_priv) != 5 && dev_priv-
> >wm.pri_latency[0] &&
> dev_priv->wm.spr_latency[0] && dev_priv-
> >wm.cur_latency[0])) {
> dev_priv->display.compute_pipe_wm =
> ilk_compute_pipe_wm;
> dev_priv->display.compute_intermediate_wm = @@
> -7700,12 +7700,12 @@ void intel_init_pm(struct drm_i915_private
> *dev_priv)
> dev_priv->display.update_wm = NULL;
> } else
> dev_priv->display.update_wm = pnv_update_wm;
> - } else if (IS_GEN(dev_priv, 4)) {
> + } else if (DISPLAY_VER(dev_priv) == 4) {
> dev_priv->display.update_wm = i965_update_wm;
> - } else if (IS_GEN(dev_priv, 3)) {
> + } else if (DISPLAY_VER(dev_priv) == 3) {
> dev_priv->display.update_wm = i9xx_update_wm;
> dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
> - } else if (IS_GEN(dev_priv, 2)) {
> + } else if (DISPLAY_VER(dev_priv) == 2) {
> if (INTEL_NUM_PIPES(dev_priv) == 1) {
> dev_priv->display.update_wm = i845_update_wm;
> dev_priv->display.get_fifo_size = i845_get_fifo_size;
> --
> 2.25.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [Intel-gfx] [PATCH 04/56] drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in intel_pm.c
2021-03-12 20:42 ` Srivatsa, Anusha
@ 2021-03-12 20:46 ` Matt Roper
2021-03-17 18:02 ` Jani Nikula
0 siblings, 1 reply; 74+ messages in thread
From: Matt Roper @ 2021-03-12 20:46 UTC (permalink / raw)
To: Srivatsa, Anusha; +Cc: intel-gfx
On Fri, Mar 12, 2021 at 12:42:27PM -0800, Srivatsa, Anusha wrote:
>
>
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt
> > Roper
> > Sent: Thursday, March 11, 2021 2:36 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH 04/56] drm/i915: Convert INTEL_GEN() to
> > DISPLAY_VER() as appropriate in intel_pm.c
> >
> > Although most of the code in this file is display-related (watermarks), there's
> > some functions that are not (e.g., clock gating). Thus we need to do the
> > conversions to DISPLAY_VER() manually here rather than using Coccinelle.
> >
> > In the near-future we'll probably want to think about moving watermark
> > logic out of intel_pm.c and into watermark-specific files under the display/
> > directory.
> >
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>
> Any reason Patch 4 and Patch 5 are not one single patch? It looks like
> both replace INTEL_GEN() with DISPLAY_VER() where necessary...
They're manually changing different sections of the driver (parts which
can't be done in an automated manner), so I wanted to make it easier to
review the two parts separately.
Matt
>
> Anusha
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 132 ++++++++++++++++----------------
> > 1 file changed, 66 insertions(+), 66 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c index 854ffecd98d9..2616b1845719
> > 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -2339,7 +2339,7 @@ static void i9xx_update_wm(struct intel_crtc
> > *unused_crtc)
> >
> > if (IS_I945GM(dev_priv))
> > wm_info = &i945_wm_info;
> > - else if (!IS_GEN(dev_priv, 2))
> > + else if (DISPLAY_VER(dev_priv) != 2)
> > wm_info = &i915_wm_info;
> > else
> > wm_info = &i830_a_wm_info;
> > @@ -2353,7 +2353,7 @@ static void i9xx_update_wm(struct intel_crtc
> > *unused_crtc)
> > crtc->base.primary->state->fb;
> > int cpp;
> >
> > - if (IS_GEN(dev_priv, 2))
> > + if (DISPLAY_VER(dev_priv) == 2)
> > cpp = 4;
> > else
> > cpp = fb->format->cpp[0];
> > @@ -2368,7 +2368,7 @@ static void i9xx_update_wm(struct intel_crtc
> > *unused_crtc)
> > planea_wm = wm_info->max_wm;
> > }
> >
> > - if (IS_GEN(dev_priv, 2))
> > + if (DISPLAY_VER(dev_priv) == 2)
> > wm_info = &i830_bc_wm_info;
> >
> > fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B); @@ -
> > 2380,7 +2380,7 @@ static void i9xx_update_wm(struct intel_crtc
> > *unused_crtc)
> > crtc->base.primary->state->fb;
> > int cpp;
> >
> > - if (IS_GEN(dev_priv, 2))
> > + if (DISPLAY_VER(dev_priv) == 2)
> > cpp = 4;
> > else
> > cpp = fb->format->cpp[0];
> > @@ -2652,9 +2652,9 @@ static u32 ilk_compute_fbc_wm(const struct
> > intel_crtc_state *crtc_state, static unsigned int ilk_display_fifo_size(const
> > struct drm_i915_private *dev_priv) {
> > - if (INTEL_GEN(dev_priv) >= 8)
> > + if (DISPLAY_VER(dev_priv) >= 8)
> > return 3072;
> > - else if (INTEL_GEN(dev_priv) >= 7)
> > + else if (DISPLAY_VER(dev_priv) >= 7)
> > return 768;
> > else
> > return 512;
> > @@ -2664,10 +2664,10 @@ static unsigned int
> > ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
> > int level, bool is_sprite)
> > {
> > - if (INTEL_GEN(dev_priv) >= 8)
> > + if (DISPLAY_VER(dev_priv) >= 8)
> > /* BDW primary/sprite plane watermarks */
> > return level == 0 ? 255 : 2047;
> > - else if (INTEL_GEN(dev_priv) >= 7)
> > + else if (DISPLAY_VER(dev_priv) >= 7)
> > /* IVB/HSW primary/sprite plane watermarks */
> > return level == 0 ? 127 : 1023;
> > else if (!is_sprite)
> > @@ -2681,7 +2681,7 @@ ilk_plane_wm_reg_max(const struct
> > drm_i915_private *dev_priv, static unsigned int
> > ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level) {
> > - if (INTEL_GEN(dev_priv) >= 7)
> > + if (DISPLAY_VER(dev_priv) >= 7)
> > return level == 0 ? 63 : 255;
> > else
> > return level == 0 ? 31 : 63;
> > @@ -2689,7 +2689,7 @@ ilk_cursor_wm_reg_max(const struct
> > drm_i915_private *dev_priv, int level)
> >
> > static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private
> > *dev_priv) {
> > - if (INTEL_GEN(dev_priv) >= 8)
> > + if (DISPLAY_VER(dev_priv) >= 8)
> > return 31;
> > else
> > return 15;
> > @@ -2717,7 +2717,7 @@ static unsigned int ilk_plane_wm_max(const struct
> > drm_i915_private *dev_priv,
> > * FIFO size is only half of the self
> > * refresh FIFO size on ILK/SNB.
> > */
> > - if (INTEL_GEN(dev_priv) <= 6)
> > + if (DISPLAY_VER(dev_priv) <= 6)
> > fifo_size /= 2;
> > }
> >
> > @@ -2852,7 +2852,7 @@ static void intel_read_wm_latency(struct
> > drm_i915_private *dev_priv, {
> > struct intel_uncore *uncore = &dev_priv->uncore;
> >
> > - if (INTEL_GEN(dev_priv) >= 9) {
> > + if (DISPLAY_VER(dev_priv) >= 9) {
> > u32 val;
> > int ret, i;
> > int level, max_level = ilk_wm_max_level(dev_priv); @@ -
> > 2944,14 +2944,14 @@ static void intel_read_wm_latency(struct
> > drm_i915_private *dev_priv,
> > wm[2] = (sskpd >> 12) & 0xFF;
> > wm[3] = (sskpd >> 20) & 0x1FF;
> > wm[4] = (sskpd >> 32) & 0x1FF;
> > - } else if (INTEL_GEN(dev_priv) >= 6) {
> > + } else if (DISPLAY_VER(dev_priv) >= 6) {
> > u32 sskpd = intel_uncore_read(uncore, MCH_SSKPD);
> >
> > wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
> > wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
> > wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
> > wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
> > - } else if (INTEL_GEN(dev_priv) >= 5) {
> > + } else if (DISPLAY_VER(dev_priv) >= 5) {
> > u32 mltr = intel_uncore_read(uncore, MLTR_ILK);
> >
> > /* ILK primary LP0 latency is 700 ns */ @@ -2967,7 +2967,7
> > @@ static void intel_fixup_spr_wm_latency(struct drm_i915_private
> > *dev_priv,
> > u16 wm[5])
> > {
> > /* ILK sprite LP0 latency is 1300 ns */
> > - if (IS_GEN(dev_priv, 5))
> > + if (DISPLAY_VER(dev_priv) == 5)
> > wm[0] = 13;
> > }
> >
> > @@ -2975,18 +2975,18 @@ static void intel_fixup_cur_wm_latency(struct
> > drm_i915_private *dev_priv,
> > u16 wm[5])
> > {
> > /* ILK cursor LP0 latency is 1300 ns */
> > - if (IS_GEN(dev_priv, 5))
> > + if (DISPLAY_VER(dev_priv) == 5)
> > wm[0] = 13;
> > }
> >
> > int ilk_wm_max_level(const struct drm_i915_private *dev_priv) {
> > /* how many WM levels are we expecting */
> > - if (INTEL_GEN(dev_priv) >= 9)
> > + if (DISPLAY_VER(dev_priv) >= 9)
> > return 7;
> > else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > return 4;
> > - else if (INTEL_GEN(dev_priv) >= 6)
> > + else if (DISPLAY_VER(dev_priv) >= 6)
> > return 3;
> > else
> > return 2;
> > @@ -3012,7 +3012,7 @@ static void intel_print_wm_latency(struct
> > drm_i915_private *dev_priv,
> > * - latencies are in us on gen9.
> > * - before then, WM1+ latency values are in 0.5us units
> > */
> > - if (INTEL_GEN(dev_priv) >= 9)
> > + if (DISPLAY_VER(dev_priv) >= 9)
> > latency *= 10;
> > else if (level > 0)
> > latency *= 5;
> > @@ -3105,7 +3105,7 @@ static void ilk_setup_wm_latency(struct
> > drm_i915_private *dev_priv)
> > intel_print_wm_latency(dev_priv, "Sprite", dev_priv-
> > >wm.spr_latency);
> > intel_print_wm_latency(dev_priv, "Cursor", dev_priv-
> > >wm.cur_latency);
> >
> > - if (IS_GEN(dev_priv, 6)) {
> > + if (DISPLAY_VER(dev_priv) == 6) {
> > snb_wm_latency_quirk(dev_priv);
> > snb_wm_lp3_irq_quirk(dev_priv);
> > }
> > @@ -3176,7 +3176,7 @@ static int ilk_compute_pipe_wm(struct
> > intel_crtc_state *crtc_state)
> > usable_level = max_level;
> >
> > /* ILK/SNB: LP2+ watermarks only w/o sprites */
> > - if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
> > + if (DISPLAY_VER(dev_priv) <= 6 && pipe_wm->sprites_enabled)
> > usable_level = 1;
> >
> > /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ @@ -3318,12
> > +3318,12 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv,
> > int last_enabled_level = max_level;
> >
> > /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
> > - if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
> > + if ((DISPLAY_VER(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
> > config->num_pipes_active > 1)
> > last_enabled_level = 0;
> >
> > /* ILK: FBC WM must be disabled always */
> > - merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
> > + merged->fbc_wm_enabled = DISPLAY_VER(dev_priv) >= 6;
> >
> > /* merge each WM1+ level */
> > for (level = 1; level <= max_level; level++) { @@ -3354,7 +3354,7 @@
> > static void ilk_wm_merge(struct drm_i915_private *dev_priv,
> > * What we should check here is whether FBC can be
> > * enabled sometime later.
> > */
> > - if (IS_GEN(dev_priv, 5) && !merged->fbc_wm_enabled &&
> > + if (DISPLAY_VER(dev_priv) == 5 && !merged->fbc_wm_enabled &&
> > intel_fbc_is_active(dev_priv)) {
> > for (level = 2; level <= max_level; level++) {
> > struct intel_wm_level *wm = &merged->wm[level];
> > @@ -3411,7 +3411,7 @@ static void ilk_compute_wm_results(struct
> > drm_i915_private *dev_priv,
> > if (r->enable)
> > results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
> >
> > - if (INTEL_GEN(dev_priv) >= 8)
> > + if (DISPLAY_VER(dev_priv) >= 8)
> > results->wm_lp[wm_lp - 1] |=
> > r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
> > else
> > @@ -3422,7 +3422,7 @@ static void ilk_compute_wm_results(struct
> > drm_i915_private *dev_priv,
> > * Always set WM1S_LP_EN when spr_val != 0, even if the
> > * level is disabled. Doing otherwise could cause underruns.
> > */
> > - if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
> > + if (DISPLAY_VER(dev_priv) <= 6 && r->spr_val) {
> > drm_WARN_ON(&dev_priv->drm, wm_lp != 1);
> > results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r-
> > >spr_val;
> > } else
> > @@ -3612,7 +3612,7 @@ static void ilk_write_wm_values(struct
> > drm_i915_private *dev_priv,
> > previous->wm_lp_spr[0] != results->wm_lp_spr[0])
> > intel_uncore_write(&dev_priv->uncore, WM1S_LP_ILK,
> > results->wm_lp_spr[0]);
> >
> > - if (INTEL_GEN(dev_priv) >= 7) {
> > + if (DISPLAY_VER(dev_priv) >= 7) {
> > if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] !=
> > results->wm_lp_spr[1])
> > intel_uncore_write(&dev_priv->uncore,
> > WM2S_LP_IVB, results->wm_lp_spr[1]);
> > if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] !=
> > results->wm_lp_spr[2]) @@ -3660,14 +3660,14 @@ static bool
> > skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv) static bool
> > intel_has_sagv(struct drm_i915_private *dev_priv) {
> > - return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
> > + return (IS_GEN9_BC(dev_priv) || DISPLAY_VER(dev_priv) >= 10) &&
> > dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED; }
> >
> > static void
> > skl_setup_sagv_block_time(struct drm_i915_private *dev_priv) {
> > - if (INTEL_GEN(dev_priv) >= 12) {
> > + if (DISPLAY_VER(dev_priv) >= 12) {
> > u32 val = 0;
> > int ret;
> >
> > @@ -3680,17 +3680,17 @@ skl_setup_sagv_block_time(struct
> > drm_i915_private *dev_priv)
> > }
> >
> > drm_dbg(&dev_priv->drm, "Couldn't read SAGV block
> > time!\n");
> > - } else if (IS_GEN(dev_priv, 11)) {
> > + } else if (DISPLAY_VER(dev_priv) == 11) {
> > dev_priv->sagv_block_time_us = 10;
> > return;
> > - } else if (IS_GEN(dev_priv, 10)) {
> > + } else if (DISPLAY_VER(dev_priv) == 10) {
> > dev_priv->sagv_block_time_us = 20;
> > return;
> > - } else if (IS_GEN(dev_priv, 9)) {
> > + } else if (DISPLAY_VER(dev_priv) == 9) {
> > dev_priv->sagv_block_time_us = 30;
> > return;
> > } else {
> > - MISSING_CASE(INTEL_GEN(dev_priv));
> > + MISSING_CASE(DISPLAY_VER(dev_priv));
> > }
> >
> > /* Default to an unusable block time */ @@ -3797,7 +3797,7 @@
> > void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> > if (!new_bw_state)
> > return;
> >
> > - if (INTEL_GEN(dev_priv) < 11 && !intel_can_enable_sagv(dev_priv,
> > new_bw_state)) {
> > + if (DISPLAY_VER(dev_priv) < 11 && !intel_can_enable_sagv(dev_priv,
> > +new_bw_state)) {
> > intel_disable_sagv(dev_priv);
> > return;
> > }
> > @@ -3848,7 +3848,7 @@ void intel_sagv_post_plane_update(struct
> > intel_atomic_state *state)
> > if (!new_bw_state)
> > return;
> >
> > - if (INTEL_GEN(dev_priv) < 11 && intel_can_enable_sagv(dev_priv,
> > new_bw_state)) {
> > + if (DISPLAY_VER(dev_priv) < 11 && intel_can_enable_sagv(dev_priv,
> > +new_bw_state)) {
> > intel_enable_sagv(dev_priv);
> > return;
> > }
> > @@ -3936,7 +3936,7 @@ static bool intel_crtc_can_enable_sagv(const struct
> > intel_crtc_state *crtc_state
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >
> > - if (INTEL_GEN(dev_priv) >= 12)
> > + if (DISPLAY_VER(dev_priv) >= 12)
> > return tgl_crtc_can_enable_sagv(crtc_state);
> > else
> > return skl_crtc_can_enable_sagv(crtc_state);
> > @@ -3945,7 +3945,7 @@ static bool intel_crtc_can_enable_sagv(const struct
> > intel_crtc_state *crtc_state bool intel_can_enable_sagv(struct
> > drm_i915_private *dev_priv,
> > const struct intel_bw_state *bw_state) {
> > - if (INTEL_GEN(dev_priv) < 11 &&
> > + if (DISPLAY_VER(dev_priv) < 11 &&
> > bw_state->active_pipes && !is_power_of_2(bw_state-
> > >active_pipes))
> > return false;
> >
> > @@ -3998,7 +3998,7 @@ static int intel_compute_sagv_mask(struct
> > intel_atomic_state *state)
> > * latter from the plane commit hooks (especially in the
> > legacy
> > * cursor case)
> > */
> > - pipe_wm->use_sagv_wm = INTEL_GEN(dev_priv) >= 12 &&
> > + pipe_wm->use_sagv_wm = DISPLAY_VER(dev_priv) >= 12 &&
> > intel_can_enable_sagv(dev_priv,
> > new_bw_state);
> > }
> >
> > @@ -4022,7 +4022,7 @@ static int intel_dbuf_size(struct drm_i915_private
> > *dev_priv)
> >
> > drm_WARN_ON(&dev_priv->drm, ddb_size == 0);
> >
> > - if (INTEL_GEN(dev_priv) < 11)
> > + if (DISPLAY_VER(dev_priv) < 11)
> > return ddb_size - 4; /* 4 blocks for bypass path allocation */
> >
> > return ddb_size;
> > @@ -4277,7 +4277,7 @@ skl_ddb_get_hw_plane_state(struct
> > drm_i915_private *dev_priv,
> > val & PLANE_CTL_ORDER_RGBX,
> > val & PLANE_CTL_ALPHA_MASK);
> >
> > - if (INTEL_GEN(dev_priv) >= 11) {
> > + if (DISPLAY_VER(dev_priv) >= 11) {
> > val = intel_uncore_read(&dev_priv->uncore,
> > PLANE_BUF_CFG(pipe, plane_id));
> > skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
> > } else {
> > @@ -4601,9 +4601,9 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc
> > *crtc, u8 active_pipes)
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > enum pipe pipe = crtc->pipe;
> >
> > - if (IS_GEN(dev_priv, 12))
> > + if (DISPLAY_VER(dev_priv) == 12)
> > return tgl_compute_dbuf_slices(pipe, active_pipes);
> > - else if (IS_GEN(dev_priv, 11))
> > + else if (DISPLAY_VER(dev_priv) == 11)
> > return icl_compute_dbuf_slices(pipe, active_pipes);
> > /*
> > * For anything else just return one slice yet.
> > @@ -4796,7 +4796,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state
> > *state,
> > if (!crtc_state->hw.active)
> > return 0;
> >
> > - if (INTEL_GEN(dev_priv) >= 11)
> > + if (DISPLAY_VER(dev_priv) >= 11)
> > total_data_rate =
> > icl_get_total_relative_data_rate(state, crtc);
> > else
> > @@ -4910,7 +4910,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state
> > *state,
> >
> > /* Gen11+ uses a separate plane for UV watermarks */
> > drm_WARN_ON(&dev_priv->drm,
> > - INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
> > + DISPLAY_VER(dev_priv) >= 11 &&
> > uv_total[plane_id]);
> >
> > /* Leave disabled planes at (0,0) */
> > if (total[plane_id]) {
> > @@ -4957,7 +4957,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state
> > *state,
> > * Wa_1408961008:icl, ehl
> > * Underruns with WM1+ disabled
> > */
> > - if (IS_GEN(dev_priv, 11) &&
> > + if (DISPLAY_VER(dev_priv) == 11 &&
> > level == 1 && wm->wm[0].plane_en) {
> > wm->wm[level].plane_res_b = wm-
> > >wm[0].plane_res_b;
> > wm->wm[level].plane_res_l = wm-
> > >wm[0].plane_res_l; @@ -5006,7 +5006,7 @@ skl_wm_method1(const
> > struct drm_i915_private *dev_priv, u32 pixel_rate,
> > wm_intermediate_val = latency * pixel_rate * cpp;
> > ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
> >
> > - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > + if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > ret = add_fixed16_u32(ret, 1);
> >
> > return ret;
> > @@ -5086,7 +5086,7 @@ skl_compute_wm_params(const struct
> > intel_crtc_state *crtc_state,
> > wp->cpp = format->cpp[color_plane];
> > wp->plane_pixel_rate = plane_pixel_rate;
> >
> > - if (INTEL_GEN(dev_priv) >= 11 &&
> > + if (DISPLAY_VER(dev_priv) >= 11 &&
> > modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1)
> > wp->dbuf_block_size = 256;
> > else
> > @@ -5120,7 +5120,7 @@ skl_compute_wm_params(const struct
> > intel_crtc_state *crtc_state,
> > wp->y_min_scanlines,
> > wp->dbuf_block_size);
> >
> > - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > + if (DISPLAY_VER(dev_priv) >= 10 ||
> > IS_GEMINILAKE(dev_priv))
> > interm_pbpl++;
> >
> > wp->plane_blocks_per_line = div_fixed16(interm_pbpl, @@ -
> > 5130,7 +5130,7 @@ skl_compute_wm_params(const struct intel_crtc_state
> > *crtc_state,
> > wp->dbuf_block_size);
> >
> > if (!wp->x_tiled ||
> > - INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > + DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > interm_pbpl++;
> >
> > wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
> > @@ -5169,7 +5169,7 @@ skl_compute_plane_wm_params(const struct
> > intel_crtc_state *crtc_state,
> >
> > static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level) {
> > - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > + if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > return true;
> >
> > /* The number of lines are ignored for the level 0 watermark. */ @@
> > -5222,7 +5222,7 @@ static void skl_compute_plane_wm(const struct
> > intel_crtc_state *crtc_state,
> > (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
> > selected_result = method2;
> > } else if (latency >= wp->linetime_us) {
> > - if (IS_GEN(dev_priv, 9) &&
> > + if (DISPLAY_VER(dev_priv) == 9 &&
> > !IS_GEMINILAKE(dev_priv))
> > selected_result = min_fixed16(method1,
> > method2);
> > else
> > @@ -5263,7 +5263,7 @@ static void skl_compute_plane_wm(const struct
> > intel_crtc_state *crtc_state,
> > }
> > }
> >
> > - if (INTEL_GEN(dev_priv) >= 11) {
> > + if (DISPLAY_VER(dev_priv) >= 11) {
> > if (wp->y_tiled) {
> > int extra_lines;
> >
> > @@ -5302,7 +5302,7 @@ static void skl_compute_plane_wm(const struct
> > intel_crtc_state *crtc_state,
> > result->min_ddb_alloc = max(min_ddb_alloc, res_blocks) + 1;
> > result->plane_en = true;
> >
> > - if (INTEL_GEN(dev_priv) < 12)
> > + if (DISPLAY_VER(dev_priv) < 12)
> > result->can_sagv = latency >= dev_priv->sagv_block_time_us;
> > }
> >
> > @@ -5359,7 +5359,7 @@ static void skl_compute_transition_wm(struct
> > drm_i915_private *dev_priv,
> > if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
> > return;
> >
> > - if (INTEL_GEN(dev_priv) >= 11)
> > + if (DISPLAY_VER(dev_priv) >= 11)
> > trans_min = 4;
> > else
> > trans_min = 14;
> > @@ -5422,7 +5422,7 @@ static int skl_build_plane_wm_single(struct
> > intel_crtc_state *crtc_state,
> > skl_compute_transition_wm(dev_priv, &wm->trans_wm,
> > &wm->wm[0], &wm_params);
> >
> > - if (INTEL_GEN(dev_priv) >= 12) {
> > + if (DISPLAY_VER(dev_priv) >= 12) {
> > tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
> >
> > skl_compute_transition_wm(dev_priv, &wm-
> > >sagv.trans_wm, @@ -5544,7 +5544,7 @@ static int
> > skl_build_pipe_wm(struct intel_atomic_state *state,
> > if (plane->pipe != crtc->pipe)
> > continue;
> >
> > - if (INTEL_GEN(dev_priv) >= 11)
> > + if (DISPLAY_VER(dev_priv) >= 11)
> > ret = icl_build_plane_wm(crtc_state, plane_state);
> > else
> > ret = skl_build_plane_wm(crtc_state, plane_state);
> > @@ -5605,7 +5605,7 @@ void skl_write_plane_wm(struct intel_plane
> > *plane,
> > skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
> > skl_plane_trans_wm(pipe_wm, plane_id));
> >
> > - if (INTEL_GEN(dev_priv) >= 11) {
> > + if (DISPLAY_VER(dev_priv) >= 11) {
> > skl_ddb_entry_write(dev_priv,
> > PLANE_BUF_CFG(pipe, plane_id), ddb_y);
> > return;
> > @@ -6135,7 +6135,7 @@ static void ilk_program_watermarks(struct
> > drm_i915_private *dev_priv)
> > ilk_wm_merge(dev_priv, &config, &max, &lp_wm_1_2);
> >
> > /* 5/6 split only in single pipe config on IVB+ */
> > - if (INTEL_GEN(dev_priv) >= 7 &&
> > + if (DISPLAY_VER(dev_priv) >= 7 &&
> > config.num_pipes_active == 1 && config.sprites_enabled) {
> > ilk_compute_wm_maximums(dev_priv, 1, &config,
> > INTEL_DDB_PART_5_6, &max);
> > ilk_wm_merge(dev_priv, &config, &max, &lp_wm_5_6); @@
> > -6221,7 +6221,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> >
> > skl_wm_level_from_reg_val(val, &wm->trans_wm);
> >
> > - if (INTEL_GEN(dev_priv) >= 12) {
> > + if (DISPLAY_VER(dev_priv) >= 12) {
> > wm->sagv.wm0 = wm->wm[0];
> > wm->sagv.trans_wm = wm->trans_wm;
> > }
> > @@ -6748,7 +6748,7 @@ void ilk_wm_get_hw_state(struct
> > drm_i915_private *dev_priv)
> > hw->wm_lp[2] = intel_uncore_read(&dev_priv->uncore,
> > WM3_LP_ILK);
> >
> > hw->wm_lp_spr[0] = intel_uncore_read(&dev_priv->uncore,
> > WM1S_LP_ILK);
> > - if (INTEL_GEN(dev_priv) >= 7) {
> > + if (DISPLAY_VER(dev_priv) >= 7) {
> > hw->wm_lp_spr[1] = intel_uncore_read(&dev_priv->uncore,
> > WM2S_LP_IVB);
> > hw->wm_lp_spr[2] = intel_uncore_read(&dev_priv->uncore,
> > WM3S_LP_IVB);
> > }
> > @@ -7649,15 +7649,15 @@ void intel_init_pm(struct drm_i915_private
> > *dev_priv)
> > skl_setup_sagv_block_time(dev_priv);
> >
> > /* For FIFO watermark updates */
> > - if (INTEL_GEN(dev_priv) >= 9) {
> > + if (DISPLAY_VER(dev_priv) >= 9) {
> > skl_setup_wm_latency(dev_priv);
> > dev_priv->display.compute_global_watermarks =
> > skl_compute_wm;
> > } else if (HAS_PCH_SPLIT(dev_priv)) {
> > ilk_setup_wm_latency(dev_priv);
> >
> > - if ((IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[1] &&
> > + if ((DISPLAY_VER(dev_priv) == 5 && dev_priv-
> > >wm.pri_latency[1] &&
> > dev_priv->wm.spr_latency[1] && dev_priv-
> > >wm.cur_latency[1]) ||
> > - (!IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[0] &&
> > + (DISPLAY_VER(dev_priv) != 5 && dev_priv-
> > >wm.pri_latency[0] &&
> > dev_priv->wm.spr_latency[0] && dev_priv-
> > >wm.cur_latency[0])) {
> > dev_priv->display.compute_pipe_wm =
> > ilk_compute_pipe_wm;
> > dev_priv->display.compute_intermediate_wm = @@
> > -7700,12 +7700,12 @@ void intel_init_pm(struct drm_i915_private
> > *dev_priv)
> > dev_priv->display.update_wm = NULL;
> > } else
> > dev_priv->display.update_wm = pnv_update_wm;
> > - } else if (IS_GEN(dev_priv, 4)) {
> > + } else if (DISPLAY_VER(dev_priv) == 4) {
> > dev_priv->display.update_wm = i965_update_wm;
> > - } else if (IS_GEN(dev_priv, 3)) {
> > + } else if (DISPLAY_VER(dev_priv) == 3) {
> > dev_priv->display.update_wm = i9xx_update_wm;
> > dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
> > - } else if (IS_GEN(dev_priv, 2)) {
> > + } else if (DISPLAY_VER(dev_priv) == 2) {
> > if (INTEL_NUM_PIPES(dev_priv) == 1) {
> > dev_priv->display.update_wm = i845_update_wm;
> > dev_priv->display.get_fifo_size = i845_get_fifo_size;
> > --
> > 2.25.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [Intel-gfx] [PATCH 04/56] drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in intel_pm.c
2021-03-12 20:46 ` Matt Roper
@ 2021-03-17 18:02 ` Jani Nikula
0 siblings, 0 replies; 74+ messages in thread
From: Jani Nikula @ 2021-03-17 18:02 UTC (permalink / raw)
To: Matt Roper, Srivatsa, Anusha; +Cc: intel-gfx
On Fri, 12 Mar 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Fri, Mar 12, 2021 at 12:42:27PM -0800, Srivatsa, Anusha wrote:
>>
>>
>> > -----Original Message-----
>> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt
>> > Roper
>> > Sent: Thursday, March 11, 2021 2:36 PM
>> > To: intel-gfx@lists.freedesktop.org
>> > Subject: [Intel-gfx] [PATCH 04/56] drm/i915: Convert INTEL_GEN() to
>> > DISPLAY_VER() as appropriate in intel_pm.c
>> >
>> > Although most of the code in this file is display-related (watermarks), there's
>> > some functions that are not (e.g., clock gating). Thus we need to do the
>> > conversions to DISPLAY_VER() manually here rather than using Coccinelle.
>> >
>> > In the near-future we'll probably want to think about moving watermark
>> > logic out of intel_pm.c and into watermark-specific files under the display/
>> > directory.
>> >
>> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>
>> Any reason Patch 4 and Patch 5 are not one single patch? It looks like
>> both replace INTEL_GEN() with DISPLAY_VER() where necessary...
>
> They're manually changing different sections of the driver (parts which
> can't be done in an automated manner), so I wanted to make it easier to
> review the two parts separately.
Also definitely smaller pieces rather than the big ones!
BR,
Jani.
>
>
> Matt
>
>>
>> Anusha
>> > ---
>> > drivers/gpu/drm/i915/intel_pm.c | 132 ++++++++++++++++----------------
>> > 1 file changed, 66 insertions(+), 66 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
>> > b/drivers/gpu/drm/i915/intel_pm.c index 854ffecd98d9..2616b1845719
>> > 100644
>> > --- a/drivers/gpu/drm/i915/intel_pm.c
>> > +++ b/drivers/gpu/drm/i915/intel_pm.c
>> > @@ -2339,7 +2339,7 @@ static void i9xx_update_wm(struct intel_crtc
>> > *unused_crtc)
>> >
>> > if (IS_I945GM(dev_priv))
>> > wm_info = &i945_wm_info;
>> > - else if (!IS_GEN(dev_priv, 2))
>> > + else if (DISPLAY_VER(dev_priv) != 2)
>> > wm_info = &i915_wm_info;
>> > else
>> > wm_info = &i830_a_wm_info;
>> > @@ -2353,7 +2353,7 @@ static void i9xx_update_wm(struct intel_crtc
>> > *unused_crtc)
>> > crtc->base.primary->state->fb;
>> > int cpp;
>> >
>> > - if (IS_GEN(dev_priv, 2))
>> > + if (DISPLAY_VER(dev_priv) == 2)
>> > cpp = 4;
>> > else
>> > cpp = fb->format->cpp[0];
>> > @@ -2368,7 +2368,7 @@ static void i9xx_update_wm(struct intel_crtc
>> > *unused_crtc)
>> > planea_wm = wm_info->max_wm;
>> > }
>> >
>> > - if (IS_GEN(dev_priv, 2))
>> > + if (DISPLAY_VER(dev_priv) == 2)
>> > wm_info = &i830_bc_wm_info;
>> >
>> > fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B); @@ -
>> > 2380,7 +2380,7 @@ static void i9xx_update_wm(struct intel_crtc
>> > *unused_crtc)
>> > crtc->base.primary->state->fb;
>> > int cpp;
>> >
>> > - if (IS_GEN(dev_priv, 2))
>> > + if (DISPLAY_VER(dev_priv) == 2)
>> > cpp = 4;
>> > else
>> > cpp = fb->format->cpp[0];
>> > @@ -2652,9 +2652,9 @@ static u32 ilk_compute_fbc_wm(const struct
>> > intel_crtc_state *crtc_state, static unsigned int ilk_display_fifo_size(const
>> > struct drm_i915_private *dev_priv) {
>> > - if (INTEL_GEN(dev_priv) >= 8)
>> > + if (DISPLAY_VER(dev_priv) >= 8)
>> > return 3072;
>> > - else if (INTEL_GEN(dev_priv) >= 7)
>> > + else if (DISPLAY_VER(dev_priv) >= 7)
>> > return 768;
>> > else
>> > return 512;
>> > @@ -2664,10 +2664,10 @@ static unsigned int
>> > ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
>> > int level, bool is_sprite)
>> > {
>> > - if (INTEL_GEN(dev_priv) >= 8)
>> > + if (DISPLAY_VER(dev_priv) >= 8)
>> > /* BDW primary/sprite plane watermarks */
>> > return level == 0 ? 255 : 2047;
>> > - else if (INTEL_GEN(dev_priv) >= 7)
>> > + else if (DISPLAY_VER(dev_priv) >= 7)
>> > /* IVB/HSW primary/sprite plane watermarks */
>> > return level == 0 ? 127 : 1023;
>> > else if (!is_sprite)
>> > @@ -2681,7 +2681,7 @@ ilk_plane_wm_reg_max(const struct
>> > drm_i915_private *dev_priv, static unsigned int
>> > ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level) {
>> > - if (INTEL_GEN(dev_priv) >= 7)
>> > + if (DISPLAY_VER(dev_priv) >= 7)
>> > return level == 0 ? 63 : 255;
>> > else
>> > return level == 0 ? 31 : 63;
>> > @@ -2689,7 +2689,7 @@ ilk_cursor_wm_reg_max(const struct
>> > drm_i915_private *dev_priv, int level)
>> >
>> > static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private
>> > *dev_priv) {
>> > - if (INTEL_GEN(dev_priv) >= 8)
>> > + if (DISPLAY_VER(dev_priv) >= 8)
>> > return 31;
>> > else
>> > return 15;
>> > @@ -2717,7 +2717,7 @@ static unsigned int ilk_plane_wm_max(const struct
>> > drm_i915_private *dev_priv,
>> > * FIFO size is only half of the self
>> > * refresh FIFO size on ILK/SNB.
>> > */
>> > - if (INTEL_GEN(dev_priv) <= 6)
>> > + if (DISPLAY_VER(dev_priv) <= 6)
>> > fifo_size /= 2;
>> > }
>> >
>> > @@ -2852,7 +2852,7 @@ static void intel_read_wm_latency(struct
>> > drm_i915_private *dev_priv, {
>> > struct intel_uncore *uncore = &dev_priv->uncore;
>> >
>> > - if (INTEL_GEN(dev_priv) >= 9) {
>> > + if (DISPLAY_VER(dev_priv) >= 9) {
>> > u32 val;
>> > int ret, i;
>> > int level, max_level = ilk_wm_max_level(dev_priv); @@ -
>> > 2944,14 +2944,14 @@ static void intel_read_wm_latency(struct
>> > drm_i915_private *dev_priv,
>> > wm[2] = (sskpd >> 12) & 0xFF;
>> > wm[3] = (sskpd >> 20) & 0x1FF;
>> > wm[4] = (sskpd >> 32) & 0x1FF;
>> > - } else if (INTEL_GEN(dev_priv) >= 6) {
>> > + } else if (DISPLAY_VER(dev_priv) >= 6) {
>> > u32 sskpd = intel_uncore_read(uncore, MCH_SSKPD);
>> >
>> > wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
>> > wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
>> > wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
>> > wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
>> > - } else if (INTEL_GEN(dev_priv) >= 5) {
>> > + } else if (DISPLAY_VER(dev_priv) >= 5) {
>> > u32 mltr = intel_uncore_read(uncore, MLTR_ILK);
>> >
>> > /* ILK primary LP0 latency is 700 ns */ @@ -2967,7 +2967,7
>> > @@ static void intel_fixup_spr_wm_latency(struct drm_i915_private
>> > *dev_priv,
>> > u16 wm[5])
>> > {
>> > /* ILK sprite LP0 latency is 1300 ns */
>> > - if (IS_GEN(dev_priv, 5))
>> > + if (DISPLAY_VER(dev_priv) == 5)
>> > wm[0] = 13;
>> > }
>> >
>> > @@ -2975,18 +2975,18 @@ static void intel_fixup_cur_wm_latency(struct
>> > drm_i915_private *dev_priv,
>> > u16 wm[5])
>> > {
>> > /* ILK cursor LP0 latency is 1300 ns */
>> > - if (IS_GEN(dev_priv, 5))
>> > + if (DISPLAY_VER(dev_priv) == 5)
>> > wm[0] = 13;
>> > }
>> >
>> > int ilk_wm_max_level(const struct drm_i915_private *dev_priv) {
>> > /* how many WM levels are we expecting */
>> > - if (INTEL_GEN(dev_priv) >= 9)
>> > + if (DISPLAY_VER(dev_priv) >= 9)
>> > return 7;
>> > else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>> > return 4;
>> > - else if (INTEL_GEN(dev_priv) >= 6)
>> > + else if (DISPLAY_VER(dev_priv) >= 6)
>> > return 3;
>> > else
>> > return 2;
>> > @@ -3012,7 +3012,7 @@ static void intel_print_wm_latency(struct
>> > drm_i915_private *dev_priv,
>> > * - latencies are in us on gen9.
>> > * - before then, WM1+ latency values are in 0.5us units
>> > */
>> > - if (INTEL_GEN(dev_priv) >= 9)
>> > + if (DISPLAY_VER(dev_priv) >= 9)
>> > latency *= 10;
>> > else if (level > 0)
>> > latency *= 5;
>> > @@ -3105,7 +3105,7 @@ static void ilk_setup_wm_latency(struct
>> > drm_i915_private *dev_priv)
>> > intel_print_wm_latency(dev_priv, "Sprite", dev_priv-
>> > >wm.spr_latency);
>> > intel_print_wm_latency(dev_priv, "Cursor", dev_priv-
>> > >wm.cur_latency);
>> >
>> > - if (IS_GEN(dev_priv, 6)) {
>> > + if (DISPLAY_VER(dev_priv) == 6) {
>> > snb_wm_latency_quirk(dev_priv);
>> > snb_wm_lp3_irq_quirk(dev_priv);
>> > }
>> > @@ -3176,7 +3176,7 @@ static int ilk_compute_pipe_wm(struct
>> > intel_crtc_state *crtc_state)
>> > usable_level = max_level;
>> >
>> > /* ILK/SNB: LP2+ watermarks only w/o sprites */
>> > - if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
>> > + if (DISPLAY_VER(dev_priv) <= 6 && pipe_wm->sprites_enabled)
>> > usable_level = 1;
>> >
>> > /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ @@ -3318,12
>> > +3318,12 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv,
>> > int last_enabled_level = max_level;
>> >
>> > /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
>> > - if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
>> > + if ((DISPLAY_VER(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
>> > config->num_pipes_active > 1)
>> > last_enabled_level = 0;
>> >
>> > /* ILK: FBC WM must be disabled always */
>> > - merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
>> > + merged->fbc_wm_enabled = DISPLAY_VER(dev_priv) >= 6;
>> >
>> > /* merge each WM1+ level */
>> > for (level = 1; level <= max_level; level++) { @@ -3354,7 +3354,7 @@
>> > static void ilk_wm_merge(struct drm_i915_private *dev_priv,
>> > * What we should check here is whether FBC can be
>> > * enabled sometime later.
>> > */
>> > - if (IS_GEN(dev_priv, 5) && !merged->fbc_wm_enabled &&
>> > + if (DISPLAY_VER(dev_priv) == 5 && !merged->fbc_wm_enabled &&
>> > intel_fbc_is_active(dev_priv)) {
>> > for (level = 2; level <= max_level; level++) {
>> > struct intel_wm_level *wm = &merged->wm[level];
>> > @@ -3411,7 +3411,7 @@ static void ilk_compute_wm_results(struct
>> > drm_i915_private *dev_priv,
>> > if (r->enable)
>> > results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
>> >
>> > - if (INTEL_GEN(dev_priv) >= 8)
>> > + if (DISPLAY_VER(dev_priv) >= 8)
>> > results->wm_lp[wm_lp - 1] |=
>> > r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
>> > else
>> > @@ -3422,7 +3422,7 @@ static void ilk_compute_wm_results(struct
>> > drm_i915_private *dev_priv,
>> > * Always set WM1S_LP_EN when spr_val != 0, even if the
>> > * level is disabled. Doing otherwise could cause underruns.
>> > */
>> > - if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
>> > + if (DISPLAY_VER(dev_priv) <= 6 && r->spr_val) {
>> > drm_WARN_ON(&dev_priv->drm, wm_lp != 1);
>> > results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r-
>> > >spr_val;
>> > } else
>> > @@ -3612,7 +3612,7 @@ static void ilk_write_wm_values(struct
>> > drm_i915_private *dev_priv,
>> > previous->wm_lp_spr[0] != results->wm_lp_spr[0])
>> > intel_uncore_write(&dev_priv->uncore, WM1S_LP_ILK,
>> > results->wm_lp_spr[0]);
>> >
>> > - if (INTEL_GEN(dev_priv) >= 7) {
>> > + if (DISPLAY_VER(dev_priv) >= 7) {
>> > if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] !=
>> > results->wm_lp_spr[1])
>> > intel_uncore_write(&dev_priv->uncore,
>> > WM2S_LP_IVB, results->wm_lp_spr[1]);
>> > if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] !=
>> > results->wm_lp_spr[2]) @@ -3660,14 +3660,14 @@ static bool
>> > skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv) static bool
>> > intel_has_sagv(struct drm_i915_private *dev_priv) {
>> > - return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
>> > + return (IS_GEN9_BC(dev_priv) || DISPLAY_VER(dev_priv) >= 10) &&
>> > dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED; }
>> >
>> > static void
>> > skl_setup_sagv_block_time(struct drm_i915_private *dev_priv) {
>> > - if (INTEL_GEN(dev_priv) >= 12) {
>> > + if (DISPLAY_VER(dev_priv) >= 12) {
>> > u32 val = 0;
>> > int ret;
>> >
>> > @@ -3680,17 +3680,17 @@ skl_setup_sagv_block_time(struct
>> > drm_i915_private *dev_priv)
>> > }
>> >
>> > drm_dbg(&dev_priv->drm, "Couldn't read SAGV block
>> > time!\n");
>> > - } else if (IS_GEN(dev_priv, 11)) {
>> > + } else if (DISPLAY_VER(dev_priv) == 11) {
>> > dev_priv->sagv_block_time_us = 10;
>> > return;
>> > - } else if (IS_GEN(dev_priv, 10)) {
>> > + } else if (DISPLAY_VER(dev_priv) == 10) {
>> > dev_priv->sagv_block_time_us = 20;
>> > return;
>> > - } else if (IS_GEN(dev_priv, 9)) {
>> > + } else if (DISPLAY_VER(dev_priv) == 9) {
>> > dev_priv->sagv_block_time_us = 30;
>> > return;
>> > } else {
>> > - MISSING_CASE(INTEL_GEN(dev_priv));
>> > + MISSING_CASE(DISPLAY_VER(dev_priv));
>> > }
>> >
>> > /* Default to an unusable block time */ @@ -3797,7 +3797,7 @@
>> > void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
>> > if (!new_bw_state)
>> > return;
>> >
>> > - if (INTEL_GEN(dev_priv) < 11 && !intel_can_enable_sagv(dev_priv,
>> > new_bw_state)) {
>> > + if (DISPLAY_VER(dev_priv) < 11 && !intel_can_enable_sagv(dev_priv,
>> > +new_bw_state)) {
>> > intel_disable_sagv(dev_priv);
>> > return;
>> > }
>> > @@ -3848,7 +3848,7 @@ void intel_sagv_post_plane_update(struct
>> > intel_atomic_state *state)
>> > if (!new_bw_state)
>> > return;
>> >
>> > - if (INTEL_GEN(dev_priv) < 11 && intel_can_enable_sagv(dev_priv,
>> > new_bw_state)) {
>> > + if (DISPLAY_VER(dev_priv) < 11 && intel_can_enable_sagv(dev_priv,
>> > +new_bw_state)) {
>> > intel_enable_sagv(dev_priv);
>> > return;
>> > }
>> > @@ -3936,7 +3936,7 @@ static bool intel_crtc_can_enable_sagv(const struct
>> > intel_crtc_state *crtc_state
>> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> >
>> > - if (INTEL_GEN(dev_priv) >= 12)
>> > + if (DISPLAY_VER(dev_priv) >= 12)
>> > return tgl_crtc_can_enable_sagv(crtc_state);
>> > else
>> > return skl_crtc_can_enable_sagv(crtc_state);
>> > @@ -3945,7 +3945,7 @@ static bool intel_crtc_can_enable_sagv(const struct
>> > intel_crtc_state *crtc_state bool intel_can_enable_sagv(struct
>> > drm_i915_private *dev_priv,
>> > const struct intel_bw_state *bw_state) {
>> > - if (INTEL_GEN(dev_priv) < 11 &&
>> > + if (DISPLAY_VER(dev_priv) < 11 &&
>> > bw_state->active_pipes && !is_power_of_2(bw_state-
>> > >active_pipes))
>> > return false;
>> >
>> > @@ -3998,7 +3998,7 @@ static int intel_compute_sagv_mask(struct
>> > intel_atomic_state *state)
>> > * latter from the plane commit hooks (especially in the
>> > legacy
>> > * cursor case)
>> > */
>> > - pipe_wm->use_sagv_wm = INTEL_GEN(dev_priv) >= 12 &&
>> > + pipe_wm->use_sagv_wm = DISPLAY_VER(dev_priv) >= 12 &&
>> > intel_can_enable_sagv(dev_priv,
>> > new_bw_state);
>> > }
>> >
>> > @@ -4022,7 +4022,7 @@ static int intel_dbuf_size(struct drm_i915_private
>> > *dev_priv)
>> >
>> > drm_WARN_ON(&dev_priv->drm, ddb_size == 0);
>> >
>> > - if (INTEL_GEN(dev_priv) < 11)
>> > + if (DISPLAY_VER(dev_priv) < 11)
>> > return ddb_size - 4; /* 4 blocks for bypass path allocation */
>> >
>> > return ddb_size;
>> > @@ -4277,7 +4277,7 @@ skl_ddb_get_hw_plane_state(struct
>> > drm_i915_private *dev_priv,
>> > val & PLANE_CTL_ORDER_RGBX,
>> > val & PLANE_CTL_ALPHA_MASK);
>> >
>> > - if (INTEL_GEN(dev_priv) >= 11) {
>> > + if (DISPLAY_VER(dev_priv) >= 11) {
>> > val = intel_uncore_read(&dev_priv->uncore,
>> > PLANE_BUF_CFG(pipe, plane_id));
>> > skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
>> > } else {
>> > @@ -4601,9 +4601,9 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc
>> > *crtc, u8 active_pipes)
>> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > enum pipe pipe = crtc->pipe;
>> >
>> > - if (IS_GEN(dev_priv, 12))
>> > + if (DISPLAY_VER(dev_priv) == 12)
>> > return tgl_compute_dbuf_slices(pipe, active_pipes);
>> > - else if (IS_GEN(dev_priv, 11))
>> > + else if (DISPLAY_VER(dev_priv) == 11)
>> > return icl_compute_dbuf_slices(pipe, active_pipes);
>> > /*
>> > * For anything else just return one slice yet.
>> > @@ -4796,7 +4796,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state
>> > *state,
>> > if (!crtc_state->hw.active)
>> > return 0;
>> >
>> > - if (INTEL_GEN(dev_priv) >= 11)
>> > + if (DISPLAY_VER(dev_priv) >= 11)
>> > total_data_rate =
>> > icl_get_total_relative_data_rate(state, crtc);
>> > else
>> > @@ -4910,7 +4910,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state
>> > *state,
>> >
>> > /* Gen11+ uses a separate plane for UV watermarks */
>> > drm_WARN_ON(&dev_priv->drm,
>> > - INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
>> > + DISPLAY_VER(dev_priv) >= 11 &&
>> > uv_total[plane_id]);
>> >
>> > /* Leave disabled planes at (0,0) */
>> > if (total[plane_id]) {
>> > @@ -4957,7 +4957,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state
>> > *state,
>> > * Wa_1408961008:icl, ehl
>> > * Underruns with WM1+ disabled
>> > */
>> > - if (IS_GEN(dev_priv, 11) &&
>> > + if (DISPLAY_VER(dev_priv) == 11 &&
>> > level == 1 && wm->wm[0].plane_en) {
>> > wm->wm[level].plane_res_b = wm-
>> > >wm[0].plane_res_b;
>> > wm->wm[level].plane_res_l = wm-
>> > >wm[0].plane_res_l; @@ -5006,7 +5006,7 @@ skl_wm_method1(const
>> > struct drm_i915_private *dev_priv, u32 pixel_rate,
>> > wm_intermediate_val = latency * pixel_rate * cpp;
>> > ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
>> >
>> > - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>> > + if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>> > ret = add_fixed16_u32(ret, 1);
>> >
>> > return ret;
>> > @@ -5086,7 +5086,7 @@ skl_compute_wm_params(const struct
>> > intel_crtc_state *crtc_state,
>> > wp->cpp = format->cpp[color_plane];
>> > wp->plane_pixel_rate = plane_pixel_rate;
>> >
>> > - if (INTEL_GEN(dev_priv) >= 11 &&
>> > + if (DISPLAY_VER(dev_priv) >= 11 &&
>> > modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1)
>> > wp->dbuf_block_size = 256;
>> > else
>> > @@ -5120,7 +5120,7 @@ skl_compute_wm_params(const struct
>> > intel_crtc_state *crtc_state,
>> > wp->y_min_scanlines,
>> > wp->dbuf_block_size);
>> >
>> > - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>> > + if (DISPLAY_VER(dev_priv) >= 10 ||
>> > IS_GEMINILAKE(dev_priv))
>> > interm_pbpl++;
>> >
>> > wp->plane_blocks_per_line = div_fixed16(interm_pbpl, @@ -
>> > 5130,7 +5130,7 @@ skl_compute_wm_params(const struct intel_crtc_state
>> > *crtc_state,
>> > wp->dbuf_block_size);
>> >
>> > if (!wp->x_tiled ||
>> > - INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>> > + DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>> > interm_pbpl++;
>> >
>> > wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
>> > @@ -5169,7 +5169,7 @@ skl_compute_plane_wm_params(const struct
>> > intel_crtc_state *crtc_state,
>> >
>> > static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level) {
>> > - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>> > + if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>> > return true;
>> >
>> > /* The number of lines are ignored for the level 0 watermark. */ @@
>> > -5222,7 +5222,7 @@ static void skl_compute_plane_wm(const struct
>> > intel_crtc_state *crtc_state,
>> > (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
>> > selected_result = method2;
>> > } else if (latency >= wp->linetime_us) {
>> > - if (IS_GEN(dev_priv, 9) &&
>> > + if (DISPLAY_VER(dev_priv) == 9 &&
>> > !IS_GEMINILAKE(dev_priv))
>> > selected_result = min_fixed16(method1,
>> > method2);
>> > else
>> > @@ -5263,7 +5263,7 @@ static void skl_compute_plane_wm(const struct
>> > intel_crtc_state *crtc_state,
>> > }
>> > }
>> >
>> > - if (INTEL_GEN(dev_priv) >= 11) {
>> > + if (DISPLAY_VER(dev_priv) >= 11) {
>> > if (wp->y_tiled) {
>> > int extra_lines;
>> >
>> > @@ -5302,7 +5302,7 @@ static void skl_compute_plane_wm(const struct
>> > intel_crtc_state *crtc_state,
>> > result->min_ddb_alloc = max(min_ddb_alloc, res_blocks) + 1;
>> > result->plane_en = true;
>> >
>> > - if (INTEL_GEN(dev_priv) < 12)
>> > + if (DISPLAY_VER(dev_priv) < 12)
>> > result->can_sagv = latency >= dev_priv->sagv_block_time_us;
>> > }
>> >
>> > @@ -5359,7 +5359,7 @@ static void skl_compute_transition_wm(struct
>> > drm_i915_private *dev_priv,
>> > if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
>> > return;
>> >
>> > - if (INTEL_GEN(dev_priv) >= 11)
>> > + if (DISPLAY_VER(dev_priv) >= 11)
>> > trans_min = 4;
>> > else
>> > trans_min = 14;
>> > @@ -5422,7 +5422,7 @@ static int skl_build_plane_wm_single(struct
>> > intel_crtc_state *crtc_state,
>> > skl_compute_transition_wm(dev_priv, &wm->trans_wm,
>> > &wm->wm[0], &wm_params);
>> >
>> > - if (INTEL_GEN(dev_priv) >= 12) {
>> > + if (DISPLAY_VER(dev_priv) >= 12) {
>> > tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
>> >
>> > skl_compute_transition_wm(dev_priv, &wm-
>> > >sagv.trans_wm, @@ -5544,7 +5544,7 @@ static int
>> > skl_build_pipe_wm(struct intel_atomic_state *state,
>> > if (plane->pipe != crtc->pipe)
>> > continue;
>> >
>> > - if (INTEL_GEN(dev_priv) >= 11)
>> > + if (DISPLAY_VER(dev_priv) >= 11)
>> > ret = icl_build_plane_wm(crtc_state, plane_state);
>> > else
>> > ret = skl_build_plane_wm(crtc_state, plane_state);
>> > @@ -5605,7 +5605,7 @@ void skl_write_plane_wm(struct intel_plane
>> > *plane,
>> > skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
>> > skl_plane_trans_wm(pipe_wm, plane_id));
>> >
>> > - if (INTEL_GEN(dev_priv) >= 11) {
>> > + if (DISPLAY_VER(dev_priv) >= 11) {
>> > skl_ddb_entry_write(dev_priv,
>> > PLANE_BUF_CFG(pipe, plane_id), ddb_y);
>> > return;
>> > @@ -6135,7 +6135,7 @@ static void ilk_program_watermarks(struct
>> > drm_i915_private *dev_priv)
>> > ilk_wm_merge(dev_priv, &config, &max, &lp_wm_1_2);
>> >
>> > /* 5/6 split only in single pipe config on IVB+ */
>> > - if (INTEL_GEN(dev_priv) >= 7 &&
>> > + if (DISPLAY_VER(dev_priv) >= 7 &&
>> > config.num_pipes_active == 1 && config.sprites_enabled) {
>> > ilk_compute_wm_maximums(dev_priv, 1, &config,
>> > INTEL_DDB_PART_5_6, &max);
>> > ilk_wm_merge(dev_priv, &config, &max, &lp_wm_5_6); @@
>> > -6221,7 +6221,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
>> >
>> > skl_wm_level_from_reg_val(val, &wm->trans_wm);
>> >
>> > - if (INTEL_GEN(dev_priv) >= 12) {
>> > + if (DISPLAY_VER(dev_priv) >= 12) {
>> > wm->sagv.wm0 = wm->wm[0];
>> > wm->sagv.trans_wm = wm->trans_wm;
>> > }
>> > @@ -6748,7 +6748,7 @@ void ilk_wm_get_hw_state(struct
>> > drm_i915_private *dev_priv)
>> > hw->wm_lp[2] = intel_uncore_read(&dev_priv->uncore,
>> > WM3_LP_ILK);
>> >
>> > hw->wm_lp_spr[0] = intel_uncore_read(&dev_priv->uncore,
>> > WM1S_LP_ILK);
>> > - if (INTEL_GEN(dev_priv) >= 7) {
>> > + if (DISPLAY_VER(dev_priv) >= 7) {
>> > hw->wm_lp_spr[1] = intel_uncore_read(&dev_priv->uncore,
>> > WM2S_LP_IVB);
>> > hw->wm_lp_spr[2] = intel_uncore_read(&dev_priv->uncore,
>> > WM3S_LP_IVB);
>> > }
>> > @@ -7649,15 +7649,15 @@ void intel_init_pm(struct drm_i915_private
>> > *dev_priv)
>> > skl_setup_sagv_block_time(dev_priv);
>> >
>> > /* For FIFO watermark updates */
>> > - if (INTEL_GEN(dev_priv) >= 9) {
>> > + if (DISPLAY_VER(dev_priv) >= 9) {
>> > skl_setup_wm_latency(dev_priv);
>> > dev_priv->display.compute_global_watermarks =
>> > skl_compute_wm;
>> > } else if (HAS_PCH_SPLIT(dev_priv)) {
>> > ilk_setup_wm_latency(dev_priv);
>> >
>> > - if ((IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[1] &&
>> > + if ((DISPLAY_VER(dev_priv) == 5 && dev_priv-
>> > >wm.pri_latency[1] &&
>> > dev_priv->wm.spr_latency[1] && dev_priv-
>> > >wm.cur_latency[1]) ||
>> > - (!IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[0] &&
>> > + (DISPLAY_VER(dev_priv) != 5 && dev_priv-
>> > >wm.pri_latency[0] &&
>> > dev_priv->wm.spr_latency[0] && dev_priv-
>> > >wm.cur_latency[0])) {
>> > dev_priv->display.compute_pipe_wm =
>> > ilk_compute_pipe_wm;
>> > dev_priv->display.compute_intermediate_wm = @@
>> > -7700,12 +7700,12 @@ void intel_init_pm(struct drm_i915_private
>> > *dev_priv)
>> > dev_priv->display.update_wm = NULL;
>> > } else
>> > dev_priv->display.update_wm = pnv_update_wm;
>> > - } else if (IS_GEN(dev_priv, 4)) {
>> > + } else if (DISPLAY_VER(dev_priv) == 4) {
>> > dev_priv->display.update_wm = i965_update_wm;
>> > - } else if (IS_GEN(dev_priv, 3)) {
>> > + } else if (DISPLAY_VER(dev_priv) == 3) {
>> > dev_priv->display.update_wm = i9xx_update_wm;
>> > dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
>> > - } else if (IS_GEN(dev_priv, 2)) {
>> > + } else if (DISPLAY_VER(dev_priv) == 2) {
>> > if (INTEL_NUM_PIPES(dev_priv) == 1) {
>> > dev_priv->display.update_wm = i845_update_wm;
>> > dev_priv->display.get_fifo_size = i845_get_fifo_size;
>> > --
>> > 2.25.4
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Intel-gfx] [PATCH 05/56] drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in i915_irq.c
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (3 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 04/56] drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in intel_pm.c Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 06/56] drm/i915/display: Simplify GLK display version tests Matt Roper
` (53 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx
Convert the display-specific usage of INTEL_GEN, while leaving the
non-display usage as-is for now.
In the near-future we'll probably want to think about moving display
interrupt handling to its own file under the display/ directory.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 66 ++++++++++++++++-----------------
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 44aed4cbf894..23be88d59055 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -192,13 +192,13 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
return;
}
- if (INTEL_GEN(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11)
hpd->hpd = hpd_gen11;
else if (IS_GEN9_LP(dev_priv))
hpd->hpd = hpd_bxt;
- else if (INTEL_GEN(dev_priv) >= 8)
+ else if (DISPLAY_VER(dev_priv) >= 8)
hpd->hpd = hpd_bdw;
- else if (INTEL_GEN(dev_priv) >= 7)
+ else if (DISPLAY_VER(dev_priv) >= 7)
hpd->hpd = hpd_ivb;
else
hpd->hpd = hpd_ilk;
@@ -477,7 +477,7 @@ u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
lockdep_assert_held(&dev_priv->irq_lock);
- if (INTEL_GEN(dev_priv) < 5)
+ if (DISPLAY_VER(dev_priv) < 5)
goto out;
/*
@@ -579,7 +579,7 @@ static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
spin_lock_irq(&dev_priv->irq_lock);
i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
- if (INTEL_GEN(dev_priv) >= 4)
+ if (DISPLAY_VER(dev_priv) >= 4)
i915_enable_pipestat(dev_priv, PIPE_A,
PIPE_LEGACY_BLC_EVENT_STATUS);
@@ -806,7 +806,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
vtotal /= 2;
- if (IS_GEN(dev_priv, 2))
+ if (DISPLAY_VER(dev_priv) == 2)
position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
else
position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
@@ -856,8 +856,8 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
int position;
int vbl_start, vbl_end, hsync_start, htotal, vtotal;
unsigned long irqflags;
- bool use_scanline_counter = INTEL_GEN(dev_priv) >= 5 ||
- IS_G4X(dev_priv) || IS_GEN(dev_priv, 2) ||
+ bool use_scanline_counter = DISPLAY_VER(dev_priv) >= 5 ||
+ IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) == 2 ||
crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
@@ -1304,7 +1304,7 @@ static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
* don't trust that one either.
*/
if (pipe_crc->skipped <= 0 ||
- (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
+ (DISPLAY_VER(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
pipe_crc->skipped++;
spin_unlock(&pipe_crc->lock);
return;
@@ -1366,12 +1366,12 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
{
u32 res1, res2;
- if (INTEL_GEN(dev_priv) >= 3)
+ if (DISPLAY_VER(dev_priv) >= 3)
res1 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES1_I915(pipe));
else
res1 = 0;
- if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
res2 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES2_G4X(pipe));
else
res2 = 0;
@@ -2077,7 +2077,7 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir);
}
- if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT)
+ if (DISPLAY_VER(dev_priv) == 5 && de_iir & DE_PCU_EVENT)
gen5_rps_irq_handler(&dev_priv->gt.rps);
}
@@ -2184,7 +2184,7 @@ static irqreturn_t ilk_irq_handler(int irq, void *arg)
de_iir = raw_reg_read(regs, DEIIR);
if (de_iir) {
raw_reg_write(regs, DEIIR, de_iir);
- if (INTEL_GEN(i915) >= 7)
+ if (DISPLAY_VER(i915) >= 7)
ivb_display_irq_handler(i915, de_iir);
else
ilk_display_irq_handler(i915, de_iir);
@@ -2269,7 +2269,7 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
{
u32 mask;
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
return TGL_DE_PORT_AUX_DDIA |
TGL_DE_PORT_AUX_DDIB |
TGL_DE_PORT_AUX_DDIC |
@@ -2282,15 +2282,15 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
mask = GEN8_AUX_CHANNEL_A;
- if (INTEL_GEN(dev_priv) >= 9)
+ if (DISPLAY_VER(dev_priv) >= 9)
mask |= GEN9_AUX_CHANNEL_B |
GEN9_AUX_CHANNEL_C |
GEN9_AUX_CHANNEL_D;
- if (IS_CNL_WITH_PORT_F(dev_priv) || IS_GEN(dev_priv, 11))
+ if (IS_CNL_WITH_PORT_F(dev_priv) || DISPLAY_VER(dev_priv) == 11)
mask |= CNL_AUX_CHANNEL_F;
- if (IS_GEN(dev_priv, 11))
+ if (DISPLAY_VER(dev_priv) == 11)
mask |= ICL_AUX_CHANNEL_E;
return mask;
@@ -2300,9 +2300,9 @@ static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
{
if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
- else if (INTEL_GEN(dev_priv) >= 11)
+ else if (DISPLAY_VER(dev_priv) >= 11)
return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
- else if (INTEL_GEN(dev_priv) >= 9)
+ else if (DISPLAY_VER(dev_priv) >= 9)
return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
else
return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
@@ -2326,7 +2326,7 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- if (INTEL_GEN(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
iir_reg = TRANS_PSR_IIR(intel_dp->psr.transcoder);
else
iir_reg = EDP_PSR_IIR;
@@ -2340,7 +2340,7 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
intel_psr_irq_handler(intel_dp, psr_iir);
/* prior GEN12 only have one EDP PSR */
- if (INTEL_GEN(dev_priv) < 12)
+ if (DISPLAY_VER(dev_priv) < 12)
break;
}
}
@@ -2408,7 +2408,7 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915)
{
- if (INTEL_GEN(i915) >= 9)
+ if (DISPLAY_VER(i915) >= 9)
return GEN9_PIPE_PLANE1_FLIP_DONE;
else
return GEN8_PIPE_PRIMARY_FLIP_DONE;
@@ -2433,7 +2433,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
}
}
- if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
+ if (DISPLAY_VER(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR);
if (iir) {
intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir);
@@ -2479,7 +2479,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
found = true;
}
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 11) {
u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
if (te_trigger) {
@@ -2809,7 +2809,7 @@ int ilk_enable_vblank(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
enum pipe pipe = to_intel_crtc(crtc)->pipe;
unsigned long irqflags;
- u32 bit = INTEL_GEN(dev_priv) >= 7 ?
+ u32 bit = DISPLAY_VER(dev_priv) >= 7 ?
DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -2920,7 +2920,7 @@ void ilk_disable_vblank(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
enum pipe pipe = to_intel_crtc(crtc)->pipe;
unsigned long irqflags;
- u32 bit = INTEL_GEN(dev_priv) >= 7 ?
+ u32 bit = DISPLAY_VER(dev_priv) >= 7 ?
DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -3094,7 +3094,7 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
enum transcoder trans;
for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
@@ -3523,7 +3523,7 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
- if (INTEL_GEN(dev_priv) >= 8)
+ if (DISPLAY_VER(dev_priv) >= 8)
bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
else
ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
@@ -3714,13 +3714,13 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
enum pipe pipe;
- if (INTEL_GEN(dev_priv) <= 10)
+ if (DISPLAY_VER(dev_priv) <= 10)
de_misc_masked |= GEN8_DE_MISC_GSE;
if (IS_GEN9_LP(dev_priv))
de_port_masked |= BXT_DE_PORT_GMBUS;
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 11) {
enum port port;
if (intel_bios_is_dsi_present(dev_priv, &port))
@@ -3737,7 +3737,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
else if (IS_BROADWELL(dev_priv))
de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
enum transcoder trans;
for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
@@ -3766,7 +3766,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 11) {
u32 de_hpd_masked = 0;
u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
GEN11_DE_TBT_HOTPLUG_MASK;
@@ -4317,7 +4317,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
} else {
if (HAS_PCH_DG1(dev_priv))
dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
- else if (INTEL_GEN(dev_priv) >= 11)
+ else if (DISPLAY_VER(dev_priv) >= 11)
dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
else if (IS_GEN9_LP(dev_priv))
dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 06/56] drm/i915/display: Simplify GLK display version tests
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (4 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 05/56] drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in i915_irq.c Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-12 18:52 ` Ville Syrjälä
2021-03-11 22:35 ` [Intel-gfx] [PATCH 07/56] drm/i915/xelpd: add XE_LPD display characteristics Matt Roper
` (52 subsequent siblings)
58 siblings, 1 reply; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx
GLK has always been a bit of a special case since it reports INTEL_GEN()
as 9, but has version 10 display IP. Now we can properly represent the
display version as 10 and simplify the display generation tests
throughout the display code.
Aside from manually adding the version to the glk_info structure, the
rest of this patch is generated with a Coccinelle semantic patch:
@@ expression dev_priv; @@
- DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)
+ DISPLAY_VER(dev_priv) >= 10
@@ expression dev_priv, E; @@
- E || DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)
+ E || DISPLAY_VER(dev_priv) >= 10
@@ expression dev_priv; @@
- IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 10
+ DISPLAY_VER(dev_priv) >= 10
@@ expression dev_priv; @@
- IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) == 10
+ DISPLAY_VER(dev_priv) == 10
@@ expression dev_priv; @@
- DISPLAY_VER(dev_priv) > 9 || IS_GEMINILAKE(dev_priv)
+ DISPLAY_VER(dev_priv) > 9
@@ expression dev_priv; @@
- IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)
+ DISPLAY_VER(dev_priv) == 10
@@ expression dev_priv; @@
- IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)
+ DISPLAY_VER(dev_priv) == 10
@@ expression dev_priv; @@
- DISPLAY_VER(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)
+ DISPLAY_VER(dev_priv) < 10
@@ expression dev_priv; @@
- (DISPLAY_VER(dev_priv) == 9) && !IS_GEMINILAKE(dev_priv)
+ DISPLAY_VER(dev_priv) == 9
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 7 ++---
drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 10 +++----
drivers/gpu/drm/i915/display/intel_color.c | 8 +++---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 7 ++---
drivers/gpu/drm/i915/display/intel_dp.c | 4 +--
drivers/gpu/drm/i915/display/intel_fbc.c | 4 +--
drivers/gpu/drm/i915/display/intel_hdcp.c | 1 -
drivers/gpu/drm/i915/display/intel_hdmi.c | 13 ++++-----
drivers/gpu/drm/i915/display/intel_psr.c | 7 ++---
.../drm/i915/display/skl_universal_plane.c | 28 +++++++++----------
drivers/gpu/drm/i915/i915_pci.c | 1 +
13 files changed, 45 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 8b1ecd86a688..d0b5414127df 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -332,8 +332,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
plane_state->hw.fb->format->is_yuv &&
plane_state->hw.fb->format->num_planes > 1) {
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- if (DISPLAY_VER(dev_priv) == 9 &&
- !IS_GEMINILAKE(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) == 9) {
mode = SKL_PS_SCALER_MODE_NV12;
} else if (icl_is_hdr_plane(dev_priv, plane->id)) {
/*
@@ -351,7 +350,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
if (linked)
mode |= PS_PLANE_Y_SEL(linked->id);
}
- } else if (DISPLAY_VER(dev_priv) > 9 || IS_GEMINILAKE(dev_priv)) {
+ } else if (DISPLAY_VER(dev_priv) > 9) {
mode = PS_SCALER_MODE_NORMAL;
} else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
/*
@@ -460,7 +459,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
* isn't necessary to change between HQ and dyn mode
* on those platforms.
*/
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10)
continue;
plane = drm_plane_from_index(&dev_priv->drm, i);
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index eefe211ed958..2d21a7796598 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -1022,7 +1022,7 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
if (IS_GEMINILAKE(dev_priv))
glk_force_audio_cdclk(dev_priv, true);
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10)
intel_de_write(dev_priv, AUD_PIN_BUF_CTL,
(intel_de_read(dev_priv, AUD_PIN_BUF_CTL) | AUD_PIN_BUF_ENABLE));
}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 640b6423f23b..1c7cdd17f89a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1433,7 +1433,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
break;
case BXT_CDCLK_CD2X_DIV_SEL_1_5:
drm_WARN(&dev_priv->drm,
- IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 10,
+ DISPLAY_VER(dev_priv) >= 10,
"Unsupported divider\n");
div = 3;
break;
@@ -1592,7 +1592,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
break;
case 3:
drm_WARN(&dev_priv->drm,
- IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 10,
+ DISPLAY_VER(dev_priv) >= 10,
"Unsupported divider\n");
divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
break;
@@ -2000,7 +2000,7 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int pixel_rate = crtc_state->pixel_rate;
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10)
return DIV_ROUND_UP(pixel_rate, 2);
else if (DISPLAY_VER(dev_priv) == 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
@@ -2050,7 +2050,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
crtc_state->has_audio &&
crtc_state->port_clock >= 540000 &&
crtc_state->lane_count == 4) {
- if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) == 10) {
/* Display WA #1145: glk,cnl */
min_cdclk = max(316800, min_cdclk);
} else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) {
@@ -2590,7 +2590,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
{
int max_cdclk_freq = dev_priv->max_cdclk_freq;
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10)
return 2 * max_cdclk_freq;
else if (DISPLAY_VER(dev_priv) == 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 558f21c6803b..c7cf7360309c 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -737,7 +737,7 @@ static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state)
* ToDo: Extend the ABI to be able to program values
* from 3.0 to 7.0
*/
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 10) {
intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0),
1 << 16);
intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1),
@@ -1711,7 +1711,7 @@ int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_stat
} else {
if (DISPLAY_VER(dev_priv) >= 11)
return icl_gamma_precision(crtc_state);
- else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ else if (DISPLAY_VER(dev_priv) == 10)
return glk_gamma_precision(crtc_state);
else if (IS_IRONLAKE(dev_priv))
return ilk_gamma_precision(crtc_state);
@@ -2119,7 +2119,7 @@ void intel_color_init(struct intel_crtc *crtc)
} else {
if (DISPLAY_VER(dev_priv) >= 11)
dev_priv->display.color_check = icl_color_check;
- else if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ else if (DISPLAY_VER(dev_priv) >= 10)
dev_priv->display.color_check = glk_color_check;
else if (DISPLAY_VER(dev_priv) >= 7)
dev_priv->display.color_check = ivb_color_check;
@@ -2136,7 +2136,7 @@ void intel_color_init(struct intel_crtc *crtc)
if (DISPLAY_VER(dev_priv) >= 11) {
dev_priv->display.load_luts = icl_load_luts;
dev_priv->display.read_luts = icl_read_luts;
- } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
+ } else if (DISPLAY_VER(dev_priv) == 10) {
dev_priv->display.load_luts = glk_load_luts;
dev_priv->display.read_luts = glk_read_luts;
} else if (DISPLAY_VER(dev_priv) >= 8) {
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3e641b36bbd3..9e677220f276 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -174,7 +174,7 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
enum port port)
{
/* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
- if (DISPLAY_VER(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) < 10) {
usleep_range(518, 1000);
return;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 933b9d791691..10cedd4d6828 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3257,7 +3257,7 @@ static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
return false;
/* WA Display #0827: Gen9:all */
- if (DISPLAY_VER(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) == 9)
return true;
return false;
@@ -3987,7 +3987,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
crtc->active = true;
/* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
- psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
+ psl_clkgate_wa = (DISPLAY_VER(dev_priv) == 10) &&
new_crtc_state->pch_pfit.enabled;
if (psl_clkgate_wa)
glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
@@ -13327,8 +13327,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
* use plane->min_cdclk() :(
*/
if (plane_state->uapi.visible && plane->min_cdclk) {
- if (crtc_state->double_wide ||
- DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10)
crtc_state->min_cdclk[plane->id] =
DIV_ROUND_UP(crtc_state->pixel_rate, 2);
else
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 04bf536f6a12..95c1f25e1bf3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -823,7 +823,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
* Output bpp is stored in 6.4 format so right shift by 4 to get the
* integer value since we support only integer values of bpp.
*/
- if ((DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
+ if ((DISPLAY_VER(dev_priv) >= 10) &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
if (intel_dp_is_edp(intel_dp)) {
dsc_max_output_bpp =
@@ -3681,7 +3681,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
intel_dp_set_common_rates(intel_dp);
/* Read the eDP DSC DPCD registers */
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10)
intel_dp_get_dsc_sink_cap(intel_dp);
/*
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index f888e1c6ff7a..2abb03cf0e71 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -653,7 +653,7 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
struct intel_fbc *fbc = &dev_priv->fbc;
unsigned int effective_w, effective_h, max_w, max_h;
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 10) {
max_w = 5120;
max_h = 4096;
} else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
@@ -1036,7 +1036,7 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state,
* if at least one frame has already passed.
*/
if (fbc->activated &&
- (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
+ (DISPLAY_VER(dev_priv) >= 10))
need_vblank_wait = true;
fbc->activated = false;
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index d418fe796263..f13704562049 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2177,7 +2177,6 @@ static bool is_hdcp2_supported(struct drm_i915_private *dev_priv)
return false;
return (DISPLAY_VER(dev_priv) >= 10 ||
- IS_GEMINILAKE(dev_priv) ||
IS_KABYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv) ||
IS_COMETLAKE(dev_priv));
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index b122c46a5657..4f285c7d54c4 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -583,7 +583,7 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10)
mask |= VIDEO_DIP_ENABLE_DRM_GLK;
return val & mask;
@@ -839,7 +839,7 @@ intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
int ret;
- if (!(DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
+ if (!(DISPLAY_VER(dev_priv) >= 10))
return true;
if (!crtc_state->has_infoframe)
@@ -2157,7 +2157,7 @@ static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
int max_tmds_clock, vbt_max_tmds_clock;
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10)
max_tmds_clock = 594000;
else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
max_tmds_clock = 300000;
@@ -2546,8 +2546,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
pipe_config->lane_count = 4;
- if (scdc->scrambling.supported && (DISPLAY_VER(dev_priv) >= 10 ||
- IS_GEMINILAKE(dev_priv))) {
+ if (scdc->scrambling.supported && (DISPLAY_VER(dev_priv) >= 10)) {
if (scdc->scrambling.low_rates)
pipe_config->hdmi_scrambling = true;
@@ -2965,7 +2964,7 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *c
intel_attach_hdmi_colorspace_property(connector);
drm_connector_attach_content_type_property(connector);
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10)
drm_object_attach_property(&connector->base,
connector->dev->mode_config.hdr_output_metadata_property, 0);
@@ -3320,7 +3319,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
connector->doublescan_allowed = 0;
connector->stereo_allowed = 1;
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10)
connector->ycbcr_420_allowed = true;
intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index f6d1bc3269b2..e71d2dd6a4a5 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -524,7 +524,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10)
val |= EDP_Y_COORDINATE_ENABLE;
val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1);
@@ -765,7 +765,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
psr_max_h = 5120;
psr_max_v = 3200;
max_bpp = 30;
- } else if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ } else if (DISPLAY_VER(dev_priv) >= 10) {
psr_max_h = 4096;
psr_max_v = 2304;
max_bpp = 24;
@@ -909,8 +909,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
hsw_psr_setup_aux(intel_dp);
- if (intel_dp->psr.psr2_enabled && (DISPLAY_VER(dev_priv) == 9 &&
- !IS_GEMINILAKE(dev_priv))) {
+ if (intel_dp->psr.psr2_enabled && (DISPLAY_VER(dev_priv) == 9)) {
i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
u32 chicken = intel_de_read(dev_priv, reg);
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 91e5d8a5d4a9..f24aaadec70d 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -294,7 +294,7 @@ skl_plane_ratio(const struct intel_crtc_state *crtc_state,
const struct drm_framebuffer *fb = plane_state->hw.fb;
if (fb->format->cpp[0] == 8) {
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 10) {
*num = 10;
*den = 8;
} else {
@@ -317,7 +317,7 @@ static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
skl_plane_ratio(crtc_state, plane_state, &num, &den);
/* two pixels per clock on glk+ */
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10)
den *= 2;
return DIV_ROUND_UP(pixel_rate * num, den);
@@ -810,7 +810,7 @@ static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
u32 plane_ctl = 0;
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10)
return plane_ctl;
if (crtc_state->gamma_enable)
@@ -834,7 +834,7 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
plane_ctl = PLANE_CTL_ENABLE;
- if (DISPLAY_VER(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) < 10) {
plane_ctl |= skl_plane_ctl_alpha(plane_state);
plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
@@ -976,7 +976,7 @@ skl_program_plane(struct intel_plane *plane,
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10)
plane_color_ctl = plane_state->color_ctl |
glk_plane_color_ctl_crtc(crtc_state);
@@ -1017,7 +1017,7 @@ skl_program_plane(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
plane_state->cus_ctl);
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10)
intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
plane_color_ctl);
@@ -1222,7 +1222,7 @@ static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_s
* than the cursor ending less than 4 pixels from the left edge of the
* screen may cause FIFO underflow and display corruption.
*/
- if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
+ if ((DISPLAY_VER(dev_priv) == 10) &&
(crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) {
drm_dbg_kms(&dev_priv->drm,
"requested plane X %s position %d invalid (valid range %d-%d)\n",
@@ -1262,7 +1262,7 @@ static int skl_plane_max_scale(struct drm_i915_private *dev_priv,
* the best case.
* FIXME need to properly check this later.
*/
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
+ if (DISPLAY_VER(dev_priv) >= 10 ||
!intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
return 0x30000 - 1;
else
@@ -1687,7 +1687,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10)
plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
plane_state);
@@ -1719,7 +1719,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
return false;
- if (DISPLAY_VER(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
+ if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C)
return false;
if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
@@ -2013,7 +2013,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->min_width = icl_plane_min_width;
plane->max_width = icl_plane_max_width;
plane->max_height = icl_plane_max_height;
- } else if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ } else if (DISPLAY_VER(dev_priv) >= 10) {
plane->max_width = glk_plane_max_width;
plane->max_height = skl_plane_max_height;
} else {
@@ -2038,7 +2038,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
if (DISPLAY_VER(dev_priv) >= 11)
formats = icl_get_plane_formats(dev_priv, pipe,
plane_id, &num_formats);
- else if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ else if (DISPLAY_VER(dev_priv) >= 10)
formats = glk_get_plane_formats(dev_priv, pipe,
plane_id, &num_formats);
else
@@ -2084,7 +2084,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709);
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 10)
supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020);
drm_plane_create_color_properties(&plane->base,
@@ -2164,7 +2164,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
else
pixel_format = val & PLANE_CTL_FORMAT_MASK;
- if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 10) {
alpha = intel_de_read(dev_priv,
PLANE_COLOR_CTL(pipe, plane_id));
alpha &= PLANE_COLOR_ALPHA_MASK;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 3543611cf0fc..5bfd94e2cc6f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -723,6 +723,7 @@ static const struct intel_device_info bxt_info = {
static const struct intel_device_info glk_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_GEMINILAKE),
+ .display_ver = 10,
.ddb_size = 1024,
GLK_COLORS,
};
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Intel-gfx] [PATCH 06/56] drm/i915/display: Simplify GLK display version tests
2021-03-11 22:35 ` [Intel-gfx] [PATCH 06/56] drm/i915/display: Simplify GLK display version tests Matt Roper
@ 2021-03-12 18:52 ` Ville Syrjälä
0 siblings, 0 replies; 74+ messages in thread
From: Ville Syrjälä @ 2021-03-12 18:52 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Thu, Mar 11, 2021 at 02:35:42PM -0800, Matt Roper wrote:
> GLK has always been a bit of a special case since it reports INTEL_GEN()
> as 9, but has version 10 display IP. Now we can properly represent the
> display version as 10 and simplify the display generation tests
> throughout the display code.
There are differences between GLK and CNL, and I suspect we just
check for gen==10/gen>=10/etc. in some cases where GLK should be
excluded. So I think in order to not break GLK we need to first
convert all those to use IS_CNL.
>
> Aside from manually adding the version to the glk_info structure, the
> rest of this patch is generated with a Coccinelle semantic patch:
>
> @@ expression dev_priv; @@
> - DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)
> + DISPLAY_VER(dev_priv) >= 10
>
> @@ expression dev_priv, E; @@
> - E || DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)
> + E || DISPLAY_VER(dev_priv) >= 10
>
> @@ expression dev_priv; @@
> - IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 10
> + DISPLAY_VER(dev_priv) >= 10
>
> @@ expression dev_priv; @@
> - IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) == 10
> + DISPLAY_VER(dev_priv) == 10
>
> @@ expression dev_priv; @@
> - DISPLAY_VER(dev_priv) > 9 || IS_GEMINILAKE(dev_priv)
> + DISPLAY_VER(dev_priv) > 9
>
> @@ expression dev_priv; @@
> - IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)
> + DISPLAY_VER(dev_priv) == 10
>
> @@ expression dev_priv; @@
> - IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)
> + DISPLAY_VER(dev_priv) == 10
>
> @@ expression dev_priv; @@
> - DISPLAY_VER(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)
> + DISPLAY_VER(dev_priv) < 10
>
> @@ expression dev_priv; @@
> - (DISPLAY_VER(dev_priv) == 9) && !IS_GEMINILAKE(dev_priv)
> + DISPLAY_VER(dev_priv) == 9
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 7 ++---
> drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
> drivers/gpu/drm/i915/display/intel_cdclk.c | 10 +++----
> drivers/gpu/drm/i915/display/intel_color.c | 8 +++---
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 7 ++---
> drivers/gpu/drm/i915/display/intel_dp.c | 4 +--
> drivers/gpu/drm/i915/display/intel_fbc.c | 4 +--
> drivers/gpu/drm/i915/display/intel_hdcp.c | 1 -
> drivers/gpu/drm/i915/display/intel_hdmi.c | 13 ++++-----
> drivers/gpu/drm/i915/display/intel_psr.c | 7 ++---
> .../drm/i915/display/skl_universal_plane.c | 28 +++++++++----------
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> 13 files changed, 45 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 8b1ecd86a688..d0b5414127df 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -332,8 +332,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
> plane_state->hw.fb->format->is_yuv &&
> plane_state->hw.fb->format->num_planes > 1) {
> struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> - if (DISPLAY_VER(dev_priv) == 9 &&
> - !IS_GEMINILAKE(dev_priv)) {
> + if (DISPLAY_VER(dev_priv) == 9) {
> mode = SKL_PS_SCALER_MODE_NV12;
> } else if (icl_is_hdr_plane(dev_priv, plane->id)) {
> /*
> @@ -351,7 +350,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
> if (linked)
> mode |= PS_PLANE_Y_SEL(linked->id);
> }
> - } else if (DISPLAY_VER(dev_priv) > 9 || IS_GEMINILAKE(dev_priv)) {
> + } else if (DISPLAY_VER(dev_priv) > 9) {
> mode = PS_SCALER_MODE_NORMAL;
> } else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
> /*
> @@ -460,7 +459,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> * isn't necessary to change between HQ and dyn mode
> * on those platforms.
> */
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 10)
> continue;
>
> plane = drm_plane_from_index(&dev_priv->drm, i);
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index eefe211ed958..2d21a7796598 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -1022,7 +1022,7 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
> if (IS_GEMINILAKE(dev_priv))
> glk_force_audio_cdclk(dev_priv, true);
>
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 10)
> intel_de_write(dev_priv, AUD_PIN_BUF_CTL,
> (intel_de_read(dev_priv, AUD_PIN_BUF_CTL) | AUD_PIN_BUF_ENABLE));
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 640b6423f23b..1c7cdd17f89a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1433,7 +1433,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> break;
> case BXT_CDCLK_CD2X_DIV_SEL_1_5:
> drm_WARN(&dev_priv->drm,
> - IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 10,
> + DISPLAY_VER(dev_priv) >= 10,
> "Unsupported divider\n");
> div = 3;
> break;
> @@ -1592,7 +1592,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> break;
> case 3:
> drm_WARN(&dev_priv->drm,
> - IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 10,
> + DISPLAY_VER(dev_priv) >= 10,
> "Unsupported divider\n");
> divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
> break;
> @@ -2000,7 +2000,7 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> int pixel_rate = crtc_state->pixel_rate;
>
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 10)
> return DIV_ROUND_UP(pixel_rate, 2);
> else if (DISPLAY_VER(dev_priv) == 9 ||
> IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> @@ -2050,7 +2050,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> crtc_state->has_audio &&
> crtc_state->port_clock >= 540000 &&
> crtc_state->lane_count == 4) {
> - if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> + if (DISPLAY_VER(dev_priv) == 10) {
> /* Display WA #1145: glk,cnl */
> min_cdclk = max(316800, min_cdclk);
> } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) {
> @@ -2590,7 +2590,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> {
> int max_cdclk_freq = dev_priv->max_cdclk_freq;
>
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 10)
> return 2 * max_cdclk_freq;
> else if (DISPLAY_VER(dev_priv) == 9 ||
> IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 558f21c6803b..c7cf7360309c 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -737,7 +737,7 @@ static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state)
> * ToDo: Extend the ABI to be able to program values
> * from 3.0 to 7.0
> */
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> + if (DISPLAY_VER(dev_priv) >= 10) {
> intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0),
> 1 << 16);
> intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1),
> @@ -1711,7 +1711,7 @@ int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_stat
> } else {
> if (DISPLAY_VER(dev_priv) >= 11)
> return icl_gamma_precision(crtc_state);
> - else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> + else if (DISPLAY_VER(dev_priv) == 10)
> return glk_gamma_precision(crtc_state);
> else if (IS_IRONLAKE(dev_priv))
> return ilk_gamma_precision(crtc_state);
> @@ -2119,7 +2119,7 @@ void intel_color_init(struct intel_crtc *crtc)
> } else {
> if (DISPLAY_VER(dev_priv) >= 11)
> dev_priv->display.color_check = icl_color_check;
> - else if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + else if (DISPLAY_VER(dev_priv) >= 10)
> dev_priv->display.color_check = glk_color_check;
> else if (DISPLAY_VER(dev_priv) >= 7)
> dev_priv->display.color_check = ivb_color_check;
> @@ -2136,7 +2136,7 @@ void intel_color_init(struct intel_crtc *crtc)
> if (DISPLAY_VER(dev_priv) >= 11) {
> dev_priv->display.load_luts = icl_load_luts;
> dev_priv->display.read_luts = icl_read_luts;
> - } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> + } else if (DISPLAY_VER(dev_priv) == 10) {
> dev_priv->display.load_luts = glk_load_luts;
> dev_priv->display.read_luts = glk_read_luts;
> } else if (DISPLAY_VER(dev_priv) >= 8) {
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3e641b36bbd3..9e677220f276 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -174,7 +174,7 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
> enum port port)
> {
> /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
> - if (DISPLAY_VER(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
> + if (DISPLAY_VER(dev_priv) < 10) {
> usleep_range(518, 1000);
> return;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 933b9d791691..10cedd4d6828 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3257,7 +3257,7 @@ static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
> return false;
>
> /* WA Display #0827: Gen9:all */
> - if (DISPLAY_VER(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) == 9)
> return true;
>
> return false;
> @@ -3987,7 +3987,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> crtc->active = true;
>
> /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
> - psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> + psl_clkgate_wa = (DISPLAY_VER(dev_priv) == 10) &&
> new_crtc_state->pch_pfit.enabled;
> if (psl_clkgate_wa)
> glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
> @@ -13327,8 +13327,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> * use plane->min_cdclk() :(
> */
> if (plane_state->uapi.visible && plane->min_cdclk) {
> - if (crtc_state->double_wide ||
> - DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10)
> crtc_state->min_cdclk[plane->id] =
> DIV_ROUND_UP(crtc_state->pixel_rate, 2);
> else
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 04bf536f6a12..95c1f25e1bf3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -823,7 +823,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
> * Output bpp is stored in 6.4 format so right shift by 4 to get the
> * integer value since we support only integer values of bpp.
> */
> - if ((DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
> + if ((DISPLAY_VER(dev_priv) >= 10) &&
> drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
> if (intel_dp_is_edp(intel_dp)) {
> dsc_max_output_bpp =
> @@ -3681,7 +3681,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
> intel_dp_set_common_rates(intel_dp);
>
> /* Read the eDP DSC DPCD registers */
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 10)
> intel_dp_get_dsc_sink_cap(intel_dp);
>
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index f888e1c6ff7a..2abb03cf0e71 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -653,7 +653,7 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
> struct intel_fbc *fbc = &dev_priv->fbc;
> unsigned int effective_w, effective_h, max_w, max_h;
>
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> + if (DISPLAY_VER(dev_priv) >= 10) {
> max_w = 5120;
> max_h = 4096;
> } else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
> @@ -1036,7 +1036,7 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state,
> * if at least one frame has already passed.
> */
> if (fbc->activated &&
> - (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
> + (DISPLAY_VER(dev_priv) >= 10))
> need_vblank_wait = true;
> fbc->activated = false;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index d418fe796263..f13704562049 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2177,7 +2177,6 @@ static bool is_hdcp2_supported(struct drm_i915_private *dev_priv)
> return false;
>
> return (DISPLAY_VER(dev_priv) >= 10 ||
> - IS_GEMINILAKE(dev_priv) ||
> IS_KABYLAKE(dev_priv) ||
> IS_COFFEELAKE(dev_priv) ||
> IS_COMETLAKE(dev_priv));
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index b122c46a5657..4f285c7d54c4 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -583,7 +583,7 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
> VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
> VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
>
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 10)
> mask |= VIDEO_DIP_ENABLE_DRM_GLK;
>
> return val & mask;
> @@ -839,7 +839,7 @@ intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> int ret;
>
> - if (!(DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
> + if (!(DISPLAY_VER(dev_priv) >= 10))
> return true;
>
> if (!crtc_state->has_infoframe)
> @@ -2157,7 +2157,7 @@ static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> int max_tmds_clock, vbt_max_tmds_clock;
>
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 10)
> max_tmds_clock = 594000;
> else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
> max_tmds_clock = 300000;
> @@ -2546,8 +2546,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
>
> pipe_config->lane_count = 4;
>
> - if (scdc->scrambling.supported && (DISPLAY_VER(dev_priv) >= 10 ||
> - IS_GEMINILAKE(dev_priv))) {
> + if (scdc->scrambling.supported && (DISPLAY_VER(dev_priv) >= 10)) {
> if (scdc->scrambling.low_rates)
> pipe_config->hdmi_scrambling = true;
>
> @@ -2965,7 +2964,7 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *c
> intel_attach_hdmi_colorspace_property(connector);
> drm_connector_attach_content_type_property(connector);
>
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 10)
> drm_object_attach_property(&connector->base,
> connector->dev->mode_config.hdr_output_metadata_property, 0);
>
> @@ -3320,7 +3319,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
> connector->doublescan_allowed = 0;
> connector->stereo_allowed = 1;
>
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 10)
> connector->ycbcr_420_allowed = true;
>
> intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index f6d1bc3269b2..e71d2dd6a4a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -524,7 +524,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
>
> val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 10)
> val |= EDP_Y_COORDINATE_ENABLE;
>
> val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1);
> @@ -765,7 +765,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> psr_max_h = 5120;
> psr_max_v = 3200;
> max_bpp = 30;
> - } else if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> + } else if (DISPLAY_VER(dev_priv) >= 10) {
> psr_max_h = 4096;
> psr_max_v = 2304;
> max_bpp = 24;
> @@ -909,8 +909,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> hsw_psr_setup_aux(intel_dp);
>
> - if (intel_dp->psr.psr2_enabled && (DISPLAY_VER(dev_priv) == 9 &&
> - !IS_GEMINILAKE(dev_priv))) {
> + if (intel_dp->psr.psr2_enabled && (DISPLAY_VER(dev_priv) == 9)) {
> i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
> u32 chicken = intel_de_read(dev_priv, reg);
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 91e5d8a5d4a9..f24aaadec70d 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -294,7 +294,7 @@ skl_plane_ratio(const struct intel_crtc_state *crtc_state,
> const struct drm_framebuffer *fb = plane_state->hw.fb;
>
> if (fb->format->cpp[0] == 8) {
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> + if (DISPLAY_VER(dev_priv) >= 10) {
> *num = 10;
> *den = 8;
> } else {
> @@ -317,7 +317,7 @@ static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
> skl_plane_ratio(crtc_state, plane_state, &num, &den);
>
> /* two pixels per clock on glk+ */
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 10)
> den *= 2;
>
> return DIV_ROUND_UP(pixel_rate * num, den);
> @@ -810,7 +810,7 @@ static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> u32 plane_ctl = 0;
>
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 10)
> return plane_ctl;
>
> if (crtc_state->gamma_enable)
> @@ -834,7 +834,7 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>
> plane_ctl = PLANE_CTL_ENABLE;
>
> - if (DISPLAY_VER(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
> + if (DISPLAY_VER(dev_priv) < 10) {
> plane_ctl |= skl_plane_ctl_alpha(plane_state);
> plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
>
> @@ -976,7 +976,7 @@ skl_program_plane(struct intel_plane *plane,
>
> plane_ctl |= skl_plane_ctl_crtc(crtc_state);
>
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 10)
> plane_color_ctl = plane_state->color_ctl |
> glk_plane_color_ctl_crtc(crtc_state);
>
> @@ -1017,7 +1017,7 @@ skl_program_plane(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
> plane_state->cus_ctl);
>
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 10)
> intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
> plane_color_ctl);
>
> @@ -1222,7 +1222,7 @@ static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_s
> * than the cursor ending less than 4 pixels from the left edge of the
> * screen may cause FIFO underflow and display corruption.
> */
> - if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> + if ((DISPLAY_VER(dev_priv) == 10) &&
> (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) {
> drm_dbg_kms(&dev_priv->drm,
> "requested plane X %s position %d invalid (valid range %d-%d)\n",
> @@ -1262,7 +1262,7 @@ static int skl_plane_max_scale(struct drm_i915_private *dev_priv,
> * the best case.
> * FIXME need to properly check this later.
> */
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
> + if (DISPLAY_VER(dev_priv) >= 10 ||
> !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
> return 0x30000 - 1;
> else
> @@ -1687,7 +1687,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
>
> plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
>
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 10)
> plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
> plane_state);
>
> @@ -1719,7 +1719,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
> if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> return false;
>
> - if (DISPLAY_VER(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
> + if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C)
> return false;
>
> if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
> @@ -2013,7 +2013,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> plane->min_width = icl_plane_min_width;
> plane->max_width = icl_plane_max_width;
> plane->max_height = icl_plane_max_height;
> - } else if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> + } else if (DISPLAY_VER(dev_priv) >= 10) {
> plane->max_width = glk_plane_max_width;
> plane->max_height = skl_plane_max_height;
> } else {
> @@ -2038,7 +2038,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> if (DISPLAY_VER(dev_priv) >= 11)
> formats = icl_get_plane_formats(dev_priv, pipe,
> plane_id, &num_formats);
> - else if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + else if (DISPLAY_VER(dev_priv) >= 10)
> formats = glk_get_plane_formats(dev_priv, pipe,
> plane_id, &num_formats);
> else
> @@ -2084,7 +2084,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>
> supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709);
>
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 10)
> supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020);
>
> drm_plane_create_color_properties(&plane->base,
> @@ -2164,7 +2164,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> else
> pixel_format = val & PLANE_CTL_FORMAT_MASK;
>
> - if (DISPLAY_VER(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> + if (DISPLAY_VER(dev_priv) >= 10) {
> alpha = intel_de_read(dev_priv,
> PLANE_COLOR_CTL(pipe, plane_id));
> alpha &= PLANE_COLOR_ALPHA_MASK;
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 3543611cf0fc..5bfd94e2cc6f 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -723,6 +723,7 @@ static const struct intel_device_info bxt_info = {
> static const struct intel_device_info glk_info = {
> GEN9_LP_FEATURES,
> PLATFORM(INTEL_GEMINILAKE),
> + .display_ver = 10,
> .ddb_size = 1024,
> GLK_COLORS,
> };
> --
> 2.25.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Intel-gfx] [PATCH 07/56] drm/i915/xelpd: add XE_LPD display characteristics
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (5 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 06/56] drm/i915/display: Simplify GLK display version tests Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 08/56] drm/i915/xelpd: Handle proper AUX interrupt bits Matt Roper
` (51 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx
Let's start preparing for upcoming platforms that will use an XE_LPD
design.
v2:
- Use the now-preferred "XE_LPD" term to refer to this design
- Utilize DISPLAY_VER() rather than a feature flag
- Drop unused mbus_size field (Lucas)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 5bfd94e2cc6f..3f06502e1d85 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -936,6 +936,16 @@ static const struct intel_device_info adl_s_info = {
.dma_mask_size = 46,
};
+#define XE_LPD_FEATURES \
+ .display_ver = 13, \
+ .display.has_psr_hw_tracking = 0, \
+ .abox_mask = GENMASK(1, 0), \
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
+ .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
+ .ddb_size = 4096, \
+ .num_supported_dbuf_slices = 4
+
#undef GEN
#undef PLATFORM
--
2.25.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 08/56] drm/i915/xelpd: Handle proper AUX interrupt bits
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (6 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 07/56] drm/i915/xelpd: add XE_LPD display characteristics Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-12 22:41 ` Srivatsa, Anusha
2021-03-11 22:35 ` [Intel-gfx] [PATCH 09/56] drm/i915/xelpd: Enhanced pipe underrun reporting Matt Roper
` (50 subsequent siblings)
58 siblings, 1 reply; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
XE_LPD has new AUX interrupt bits for DDI-D and DDI-E that take the
spots that were used by TC5/TC6 on Display12 platforms.
While we're at it, let's convert the bit definitions for all TGL+ aux
bits over to the modern REG_BIT() notation.
v2:
- Maintain bit order rather than logical order. (Lucas)
- Convert surrounding code to REG_BIT() notation. (Lucas)
Bspec: 50064
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 12 +++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 20 +++++++++++---------
2 files changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 23be88d59055..c9e03973502c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2269,7 +2269,17 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
{
u32 mask;
- if (DISPLAY_VER(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 13)
+ return TGL_DE_PORT_AUX_DDIA |
+ TGL_DE_PORT_AUX_DDIB |
+ TGL_DE_PORT_AUX_DDIC |
+ XELPD_DE_PORT_AUX_DDID |
+ XELPD_DE_PORT_AUX_DDIE |
+ TGL_DE_PORT_AUX_USBC1 |
+ TGL_DE_PORT_AUX_USBC2 |
+ TGL_DE_PORT_AUX_USBC3 |
+ TGL_DE_PORT_AUX_USBC4;
+ else if (DISPLAY_VER(dev_priv) >= 12)
return TGL_DE_PORT_AUX_DDIA |
TGL_DE_PORT_AUX_DDIB |
TGL_DE_PORT_AUX_DDIC |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e5dd0203991b..475d14db2844 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7855,15 +7855,17 @@ enum {
#define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
#define BXT_DE_PORT_GMBUS (1 << 1)
#define GEN8_AUX_CHANNEL_A (1 << 0)
-#define TGL_DE_PORT_AUX_USBC6 (1 << 13)
-#define TGL_DE_PORT_AUX_USBC5 (1 << 12)
-#define TGL_DE_PORT_AUX_USBC4 (1 << 11)
-#define TGL_DE_PORT_AUX_USBC3 (1 << 10)
-#define TGL_DE_PORT_AUX_USBC2 (1 << 9)
-#define TGL_DE_PORT_AUX_USBC1 (1 << 8)
-#define TGL_DE_PORT_AUX_DDIC (1 << 2)
-#define TGL_DE_PORT_AUX_DDIB (1 << 1)
-#define TGL_DE_PORT_AUX_DDIA (1 << 0)
+#define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
+#define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
+#define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
+#define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
+#define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
+#define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
+#define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
+#define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
+#define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
+#define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
+#define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
#define GEN8_DE_MISC_ISR _MMIO(0x44460)
#define GEN8_DE_MISC_IMR _MMIO(0x44464)
--
2.25.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Intel-gfx] [PATCH 08/56] drm/i915/xelpd: Handle proper AUX interrupt bits
2021-03-11 22:35 ` [Intel-gfx] [PATCH 08/56] drm/i915/xelpd: Handle proper AUX interrupt bits Matt Roper
@ 2021-03-12 22:41 ` Srivatsa, Anusha
0 siblings, 0 replies; 74+ messages in thread
From: Srivatsa, Anusha @ 2021-03-12 22:41 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx; +Cc: De Marchi, Lucas
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D <matthew.d.roper@intel.com>; Srivatsa, Anusha
> <anusha.srivatsa@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [PATCH 08/56] drm/i915/xelpd: Handle proper AUX interrupt bits
>
> XE_LPD has new AUX interrupt bits for DDI-D and DDI-E that take the spots
> that were used by TC5/TC6 on Display12 platforms.
>
> While we're at it, let's convert the bit definitions for all TGL+ aux bits over to
> the modern REG_BIT() notation.
>
> v2:
> - Maintain bit order rather than logical order. (Lucas)
> - Convert surrounding code to REG_BIT() notation. (Lucas)
>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Bspec: 50064
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 12 +++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 20 +++++++++++---------
> 2 files changed, 22 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c index 23be88d59055..c9e03973502c
> 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2269,7 +2269,17 @@ static u32 gen8_de_port_aux_mask(struct
> drm_i915_private *dev_priv) {
> u32 mask;
>
> - if (DISPLAY_VER(dev_priv) >= 12)
> + if (DISPLAY_VER(dev_priv) >= 13)
> + return TGL_DE_PORT_AUX_DDIA |
> + TGL_DE_PORT_AUX_DDIB |
> + TGL_DE_PORT_AUX_DDIC |
> + XELPD_DE_PORT_AUX_DDID |
> + XELPD_DE_PORT_AUX_DDIE |
> + TGL_DE_PORT_AUX_USBC1 |
> + TGL_DE_PORT_AUX_USBC2 |
> + TGL_DE_PORT_AUX_USBC3 |
> + TGL_DE_PORT_AUX_USBC4;
> + else if (DISPLAY_VER(dev_priv) >= 12)
> return TGL_DE_PORT_AUX_DDIA |
> TGL_DE_PORT_AUX_DDIB |
> TGL_DE_PORT_AUX_DDIC |
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index e5dd0203991b..475d14db2844
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7855,15 +7855,17 @@ enum {
> #define BDW_DE_PORT_HOTPLUG_MASK
> GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
> #define BXT_DE_PORT_GMBUS (1 << 1)
> #define GEN8_AUX_CHANNEL_A (1 << 0)
> -#define TGL_DE_PORT_AUX_USBC6 (1 << 13)
> -#define TGL_DE_PORT_AUX_USBC5 (1 << 12)
> -#define TGL_DE_PORT_AUX_USBC4 (1 << 11)
> -#define TGL_DE_PORT_AUX_USBC3 (1 << 10)
> -#define TGL_DE_PORT_AUX_USBC2 (1 << 9)
> -#define TGL_DE_PORT_AUX_USBC1 (1 << 8)
> -#define TGL_DE_PORT_AUX_DDIC (1 << 2)
> -#define TGL_DE_PORT_AUX_DDIB (1 << 1)
> -#define TGL_DE_PORT_AUX_DDIA (1 << 0)
> +#define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
> +#define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
> +#define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
> +#define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
> +#define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
> +#define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
> +#define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
> +#define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
> +#define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
> +#define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
> +#define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
>
> #define GEN8_DE_MISC_ISR _MMIO(0x44460) #define GEN8_DE_MISC_IMR
> _MMIO(0x44464)
> --
> 2.25.4
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^ permalink raw reply [flat|nested] 74+ messages in thread
* [Intel-gfx] [PATCH 09/56] drm/i915/xelpd: Enhanced pipe underrun reporting
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (7 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 08/56] drm/i915/xelpd: Handle proper AUX interrupt bits Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 10/56] drm/i915/xelpd: Define plane capabilities Matt Roper
` (49 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
XE_LPD brings enhanced underrun recovery: the hardware can somewhat
mitigate underruns by using an interpolated replacement pixel (soft
underrun) or the previous pixel (hard underrun). Furthermore, underruns
can now be caused downstream by the port, even if the pipe itself is
operating properly. The interrupt register and PIPE_STATUS register
give us extra bits to recognize hard/soft underruns and determine
whether the underrun was caused by the port, so we'll use that
information to print some more descriptive errors when underruns occur.
v2:
- Keep ICL's PIPE_STATUS defined separately from the old GMCH pipe
status register. (Ville)
- Only read/clear the PIPE_STATUS register on platforms with
display ver >= 11. (Lucas)
Bspec: 50335
Bspec: 50366
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
.../drm/i915/display/intel_fifo_underrun.c | 65 ++++++++++++++++++-
drivers/gpu/drm/i915/i915_irq.c | 14 +++-
drivers/gpu/drm/i915/i915_reg.h | 8 +++
3 files changed, 84 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index 5b1136838b9c..fe9315a9fc51 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -359,6 +359,39 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
return old;
}
+static u32
+underrun_pipestat_mask(struct drm_i915_private *dev_priv)
+{
+ u32 mask = PIPE_FIFO_UNDERRUN_STATUS;
+
+ if (DISPLAY_VER(dev_priv) >= 13)
+ mask |= PIPE_STAT_SOFT_UNDERRUN_XELPD |
+ PIPE_STAT_HARD_UNDERRUN_XELPD |
+ PIPE_STAT_PORT_UNDERRUN_XELPD;
+
+ return mask;
+}
+
+static const char *
+pipe_underrun_reason(u32 pipestat_underruns)
+{
+ if (pipestat_underruns & PIPE_STAT_SOFT_UNDERRUN_XELPD)
+ /*
+ * Hardware used replacement/interpolated pixels at
+ * underrun locations.
+ */
+ return "soft";
+ else if (pipestat_underruns & PIPE_STAT_HARD_UNDERRUN_XELPD)
+ /*
+ * Hardware used previous pixel value at underrun
+ * locations.
+ */
+ return "hard";
+ else
+ /* Old platform or no extra soft/hard bit set */
+ return "FIFO";
+}
+
/**
* intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
* @dev_priv: i915 device instance
@@ -372,6 +405,7 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
+ u32 underruns = 0;
/* We may be called too early in init, thanks BIOS! */
if (crtc == NULL)
@@ -382,10 +416,37 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
crtc->cpu_fifo_underrun_disabled)
return;
+ /*
+ * Starting with display version 11, the PIPE_STAT register records
+ * whether an underrun has happened, and on XELPD+, it will also record
+ * whether the underrun was soft/hard and whether it was triggered by
+ * the downstream port logic. We should clear these bits (which use
+ * write-1-to-clear logic) too.
+ *
+ * Note that although the IIR gives us the same underrun and soft/hard
+ * information, PIPE_STAT is the only place we can find out whether
+ * the underrun was caused by the downstream port.
+ */
+ if (DISPLAY_VER(dev_priv) >= 11) {
+ underruns = intel_uncore_read(&dev_priv->uncore,
+ ICL_PIPESTATUS(pipe)) &
+ underrun_pipestat_mask(dev_priv);
+ intel_uncore_write(&dev_priv->uncore, ICL_PIPESTATUS(pipe),
+ underruns);
+ }
+
if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {
trace_intel_cpu_fifo_underrun(dev_priv, pipe);
- drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n",
- pipe_name(pipe));
+
+ if (underruns & PIPE_STAT_PORT_UNDERRUN_XELPD)
+ /* Underrun was caused downstream from the pipes */
+ drm_err(&dev_priv->drm, "Port triggered a %s underrun on pipe %c\n",
+ pipe_underrun_reason(underruns),
+ pipe_name(pipe));
+ else
+ drm_err(&dev_priv->drm, "CPU pipe %c %s underrun\n",
+ pipe_name(pipe),
+ pipe_underrun_reason(underruns));
}
intel_fbc_handle_fifo_underrun_irq(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c9e03973502c..8beb5e193ba5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2424,6 +2424,18 @@ static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915)
return GEN8_PIPE_PRIMARY_FLIP_DONE;
}
+static u32
+underrun_iir_mask(struct drm_i915_private *dev_priv)
+{
+ u32 mask = GEN8_PIPE_FIFO_UNDERRUN;
+
+ if (DISPLAY_VER(dev_priv) >= 13)
+ mask |= XELPD_PIPE_SOFT_UNDERRUN |
+ XELPD_PIPE_HARD_UNDERRUN;
+
+ return mask;
+}
+
static irqreturn_t
gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
{
@@ -2532,7 +2544,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
hsw_pipe_crc_irq_handler(dev_priv, pipe);
- if (iir & GEN8_PIPE_FIFO_UNDERRUN)
+ if (iir & underrun_iir_mask(dev_priv))
intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 475d14db2844..9bbe94cddd93 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6139,6 +6139,12 @@ enum {
#define SKL_BOTTOM_COLOR_CSC_ENABLE (1 << 30)
#define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
+#define _ICL_PIPE_A_STATUS 0x70058
+#define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS)
+#define PIPE_STAT_SOFT_UNDERRUN_XELPD REG_BIT(28)
+#define PIPE_STAT_HARD_UNDERRUN_XELPD REG_BIT(27)
+#define PIPE_STAT_PORT_UNDERRUN_XELPD REG_BIT(26)
+
#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
#define PIPEB_LINE_COMPARE_INT_EN (1 << 29)
#define PIPEB_HLINE_INT_EN (1 << 28)
@@ -7792,6 +7798,8 @@ enum {
#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
+#define XELPD_PIPE_SOFT_UNDERRUN (1 << 22)
+#define XELPD_PIPE_HARD_UNDERRUN (1 << 21)
#define GEN8_PIPE_CURSOR_FAULT (1 << 10)
#define GEN8_PIPE_SPRITE_FAULT (1 << 9)
#define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 10/56] drm/i915/xelpd: Define plane capabilities
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (8 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 09/56] drm/i915/xelpd: Enhanced pipe underrun reporting Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 11/56] drm/i915/xelpd: Support 128k plane stride Matt Roper
` (48 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
XE_LPD's plane support is identical to RKL and ADL-S --- 5 universal + 1
cursor with NV12 UV support on planes 1-3 and NV12 Y support on planes
4-5.
v2:
- Drop the extra 90/270 rotation check in skl_plane_check_fb(); the DRM
property code will already prevent userspace from passing us values
that weren't advertised. (Lucas)
Bspec: 53657
Bspec: 49251
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 11 +++++++----
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
3 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index f24aaadec70d..2280694f19c7 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -266,7 +266,7 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
{
- if (HAS_D12_PLANE_MINIMIZATION(i915))
+ if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915))
return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
else
return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
@@ -2071,9 +2071,12 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
if (ret)
goto fail;
- supported_rotations =
- DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
- DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
+ if (DISPLAY_VER(dev_priv) >= 13)
+ supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
+ else
+ supported_rotations =
+ DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
+ DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
if (DISPLAY_VER(dev_priv) >= 10)
supported_rotations |= DRM_MODE_REFLECT_X;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8beb5e193ba5..a1ac15f972ee 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2308,7 +2308,7 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
{
- if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
else if (DISPLAY_VER(dev_priv) >= 11)
return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index aeb28d589b2b..8a55cdfc802c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -265,7 +265,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
- if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
for_each_pipe(dev_priv, pipe)
runtime->num_sprites[pipe] = 4;
else if (INTEL_GEN(dev_priv) >= 11)
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 11/56] drm/i915/xelpd: Support 128k plane stride
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (9 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 10/56] drm/i915/xelpd: Define plane capabilities Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 12/56] drm/i915/xelpd: Handle new location of outputs D and E Matt Roper
` (47 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Juha-Pekka Heikkilä
From: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
XE_LPD supports plane strides up to 128KB.
v2:
- Drop a duplicated comment
- Add missing horizontal pixels for cpp!=8 case (Lucas)
- Take into account larger possible offsets for warnings
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../drm/i915/display/skl_universal_plane.c | 46 +++++++++++++++----
drivers/gpu/drm/i915/i915_reg.h | 2 +
2 files changed, 39 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 2280694f19c7..cc36917b459c 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -456,17 +456,35 @@ skl_plane_max_stride(struct intel_plane *plane,
u32 pixel_format, u64 modifier,
unsigned int rotation)
{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
const struct drm_format_info *info = drm_format_info(pixel_format);
int cpp = info->cpp[0];
+ int max_horizontal_pixels = 8192;
+ int max_stride_bytes;
+
+ if (DISPLAY_VER(i915) >= 13) {
+ /*
+ * The stride in bytes must not exceed of the size
+ * of 128K bytes. For pixel formats of 64bpp will allow
+ * for a 16K pixel surface.
+ */
+ max_stride_bytes = 131072;
+ if (cpp == 8)
+ max_horizontal_pixels = 16384;
+ else
+ max_horizontal_pixels = 65536;
+ } else {
+ /*
+ * "The stride in bytes must not exceed the
+ * of the size of 8K pixels and 32K bytes."
+ */
+ max_stride_bytes = 32768;
+ }
- /*
- * "The stride in bytes must not exceed the
- * of the size of 8K pixels and 32K bytes."
- */
if (drm_rotation_90_or_270(rotation))
- return min(8192, 32768 / cpp);
+ return min(max_horizontal_pixels, max_stride_bytes / cpp);
else
- return min(8192 * cpp, 32768);
+ return min(max_horizontal_pixels * cpp, max_stride_bytes);
}
@@ -1450,7 +1468,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
}
}
- drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191);
+ if (DISPLAY_VER(dev_priv) >= 13)
+ drm_WARN_ON(&dev_priv->drm, x > 65535 || y > 65535);
+ else
+ drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191);
plane_state->color_plane[0].offset = offset;
plane_state->color_plane[0].x = x;
@@ -1524,7 +1545,10 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
}
}
- drm_WARN_ON(&i915->drm, x > 8191 || y > 8191);
+ if (DISPLAY_VER(i915) >= 13)
+ drm_WARN_ON(&i915->drm, x > 65535 || y > 65535);
+ else
+ drm_WARN_ON(&i915->drm, x > 8191 || y > 8191);
plane_state->color_plane[uv_plane].offset = offset;
plane_state->color_plane[uv_plane].x = x;
@@ -2248,7 +2272,11 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
- fb->pitches[0] = (val & 0x3ff) * stride_mult;
+
+ if (DISPLAY_VER(dev_priv) >= 13)
+ fb->pitches[0] = (val & PLANE_STRIDE_MASK_XELPD) * stride_mult;
+ else
+ fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
aligned_height = intel_fb_align_height(fb, 0, fb->height);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9bbe94cddd93..59291d6a702e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7202,6 +7202,8 @@ enum {
_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
#define PLANE_STRIDE(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
+#define PLANE_STRIDE_MASK REG_GENMASK(10, 0)
+#define PLANE_STRIDE_MASK_XELPD REG_GENMASK(11, 0)
#define _PLANE_POS_1_B 0x7118c
#define _PLANE_POS_2_B 0x7128c
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 12/56] drm/i915/xelpd: Handle new location of outputs D and E
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (10 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 11/56] drm/i915/xelpd: Support 128k plane stride Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 13/56] drm/i915/xelpd: Add XE_LPD power wells Matt Roper
` (46 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx
The DDI naming template for display version 12 went A-C, TC1-TC6. With
XE_LPD, that naming scheme for DDI's has now changed to A-E, TC1-TC4.
The XE_LPD design keeps the register offsets and bitfields relating to
the TC outputs in the same location they were previously. The new "D"
and "E" outputs now take the locations that were previously used by TC5
and TC6 outputs, or what we would have considered to be outputs "H" and
"I" under the legacy lettering scheme.
For the most part everything will just work as long as we initialize the
output with the proper 'enum port' value. However we do need to take
care to pick the correct AUX channel when parsing the VBT (e.g., a
reference to 'AUX D' is actually asking us to use the 8th aux channel,
not the fourth). We should also make sure that our encoders and aux
channels are named appropriately so that it's easier to correlate driver
debug messages with the bspec instructions.
v2:
- Update handling of TGL_TRANS_CLK_SEL_PORT. (Jose)
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 8 +++++--
drivers/gpu/drm/i915/display/intel_ddi.c | 25 +++++++++++++-------
drivers/gpu/drm/i915/display/intel_display.c | 6 ++++-
drivers/gpu/drm/i915/display/intel_display.h | 8 +++++++
drivers/gpu/drm/i915/display/intel_dp_aux.c | 14 +++++++----
5 files changed, 44 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 7d438d16973c..e4cef54726b4 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2770,7 +2770,9 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
aux_ch = AUX_CH_C;
break;
case DP_AUX_D:
- if (IS_ALDERLAKE_S(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 13)
+ aux_ch = AUX_CH_D_XELPD;
+ else if (IS_ALDERLAKE_S(dev_priv))
aux_ch = AUX_CH_USBC3;
else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
aux_ch = AUX_CH_USBC2;
@@ -2778,7 +2780,9 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
aux_ch = AUX_CH_D;
break;
case DP_AUX_E:
- if (IS_ALDERLAKE_S(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 13)
+ aux_ch = AUX_CH_E_XELPD;
+ else if (IS_ALDERLAKE_S(dev_priv))
aux_ch = AUX_CH_USBC4;
else
aux_ch = AUX_CH_E;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9e677220f276..f404547bb95a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -850,18 +850,19 @@ void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum port port = encoder->port;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ u32 val;
if (cpu_transcoder != TRANSCODER_EDP) {
- if (DISPLAY_VER(dev_priv) >= 12)
- intel_de_write(dev_priv,
- TRANS_CLK_SEL(cpu_transcoder),
- TGL_TRANS_CLK_SEL_PORT(port));
+ if (DISPLAY_VER(dev_priv) >= 13)
+ val = TGL_TRANS_CLK_SEL_PORT(phy);
+ else if (DISPLAY_VER(dev_priv) >= 12)
+ val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
else
- intel_de_write(dev_priv,
- TRANS_CLK_SEL(cpu_transcoder),
- TRANS_CLK_SEL_PORT(port));
+ val = TRANS_CLK_SEL_PORT(encoder->port);
+
+ intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
}
}
@@ -4461,7 +4462,13 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder = &dig_port->base;
- if (DISPLAY_VER(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) {
+ drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
+ DRM_MODE_ENCODER_TMDS,
+ "DDI %c/PHY %c",
+ port_name(port - PORT_D_XELPD + PORT_D),
+ phy_name(phy));
+ } else if (DISPLAY_VER(dev_priv) >= 12) {
enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 10cedd4d6828..926707fd00e3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4174,7 +4174,11 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
{
- if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
+ if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
+ return PHY_D + port - PORT_D_XELPD;
+ else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
+ return PHY_F + port - PORT_TC1;
+ else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
return PHY_B + port - PORT_TC1;
else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
return PHY_C + port - PORT_TC1;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 431770eeadb4..13d5d7909411 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -217,6 +217,10 @@ enum port {
PORT_TC5,
PORT_TC6,
+ /* XE_LPD repositions D/E offsets and bitfields */
+ PORT_D_XELPD = PORT_TC5,
+ PORT_E_XELPD,
+
I915_MAX_PORTS
};
@@ -300,6 +304,10 @@ enum aux_ch {
AUX_CH_USBC4,
AUX_CH_USBC5,
AUX_CH_USBC6,
+
+ /* XE_LPD repositions D/E offsets and bitfields */
+ AUX_CH_D_XELPD = AUX_CH_USBC5,
+ AUX_CH_E_XELPD,
};
#define aux_ch_name(a) ((a) + 'A')
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index b7eee37d040a..42eaf6acc9c4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -600,8 +600,8 @@ static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
case AUX_CH_USBC2:
case AUX_CH_USBC3:
case AUX_CH_USBC4:
- case AUX_CH_USBC5:
- case AUX_CH_USBC6:
+ case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */
+ case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */
return DP_AUX_CH_CTL(aux_ch);
default:
MISSING_CASE(aux_ch);
@@ -623,8 +623,8 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
case AUX_CH_USBC2:
case AUX_CH_USBC3:
case AUX_CH_USBC4:
- case AUX_CH_USBC5:
- case AUX_CH_USBC6:
+ case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */
+ case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */
return DP_AUX_CH_DATA(aux_ch, index);
default:
MISSING_CASE(aux_ch);
@@ -678,7 +678,11 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
drm_dp_aux_init(&intel_dp->aux);
/* Failure to allocate our preferred name is not critical */
- if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
+ if (DISPLAY_VER(dev_priv) >= 13 && aux_ch >= AUX_CH_D_XELPD)
+ intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
+ aux_ch_name(aux_ch - AUX_CH_D_XELPD + AUX_CH_D),
+ encoder->base.name);
+ else if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
aux_ch - AUX_CH_USBC1 + '1',
encoder->base.name);
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 13/56] drm/i915/xelpd: Add XE_LPD power wells
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (11 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 12/56] drm/i915/xelpd: Handle new location of outputs D and E Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 14/56] drm/i915/xelpd: Handle LPSP for XE_LPD Matt Roper
` (45 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
Aside from the hardware-managed PG0, XE_LPD has power wells 1-2 and
A-D. These power wells should be enabled/disabled according to the
following dependency tree (enable top to bottom, disable bottom to top):
PG0
|
--PG1--
/ \
PGA --PG2--
/ | \
PGB PGC PGD
PWR_WELL_CTL follows the general ICL/TGL design and places PG A-D in the
bits that would have been PG 6-9 under the old scheme.
PWR_WELL_CTL_{DDI,AUX}'s bit indexing for DDI's A-C and TC1 is the same
as TGL, but DDI-D is placed at index 7 (bits 14 & 15).
Bspec: 49233
Bspec: 49503
Bspec: 49504
Bspec: 49505
Bspec: 49296
Bspec: 50090
Bspec: 53920
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../drm/i915/display/intel_display_power.c | 426 +++++++++++++++++-
.../drm/i915/display/intel_display_power.h | 9 +
drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 10 +
4 files changed, 445 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index e7546dc5caac..2cccf45837d3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1035,7 +1035,7 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
enum i915_power_well_id high_pg;
/* Power wells at this level and above must be disabled for DC5 entry */
- if (DISPLAY_VER(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) == 12)
high_pg = ICL_DISP_PW_3;
else
high_pg = SKL_DISP_PW_2;
@@ -3012,6 +3012,113 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
+/*
+ * XE_LPD Power Domains
+ *
+ * Previous platforms required that PG(n-1) be enabled before PG(n). That
+ * dependency chain turns into a dependency tree on XE_LPD:
+ *
+ * PG0
+ * |
+ * --PG1--
+ * / \
+ * PGA --PG2--
+ * / | \
+ * PGB PGC PGD
+ *
+ * Power wells must be enabled from top to bottom and disabled from bottom
+ * to top. This allows pipes to be power gated independently.
+ */
+
+#define XELPD_PW_D_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_D) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define XELPD_PW_C_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define XELPD_PW_B_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define XELPD_PW_A_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define XELPD_PW_2_POWER_DOMAINS ( \
+ XELPD_PW_B_POWER_DOMAINS | \
+ XELPD_PW_C_POWER_DOMAINS | \
+ XELPD_PW_D_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_AUDIO) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E_XELPD) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+/*
+ * XELPD PW_1/PG_1 domains (under HW/DMC control):
+ * - DBUF function (registers are in PW0)
+ * - Transcoder A
+ * - DDI_A and DDI_B
+ *
+ * XELPD PW_0/PW_1 domains (under HW/DMC control):
+ * - PCI
+ * - Clocks except port PLL
+ * - Shared functions:
+ * * interrupts except pipe interrupts
+ * * MBus except PIPE_MBUS_DBOX_CTL
+ * * DBUF registers
+ * - Central power except FBC
+ * - Top-level GTC (DDI-level GTC is in the well associated with the DDI)
+ */
+
+#define XELPD_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ XELPD_PW_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)
+#define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_XELPD)
+#define XELPD_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
+#define XELPD_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
+#define XELPD_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
+#define XELPD_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
+
+#define XELPD_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
+#define XELPD_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
+#define XELPD_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
+#define XELPD_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
+
+#define XELPD_DDI_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D_XELPD)
+#define XELPD_DDI_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E_XELPD)
+#define XELPD_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
+#define XELPD_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
+#define XELPD_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
+#define XELPD_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
+
static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = i9xx_always_on_power_well_noop,
@@ -4516,6 +4623,319 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
};
+static const struct i915_power_well_desc xelpd_power_wells[] = {
+ {
+ .name = "always-on",
+ .always_on = true,
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ },
+ {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .always_on = true,
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "DC off",
+ .domains = XELPD_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ },
+ {
+ .name = "power well 2",
+ .domains = XELPD_PW_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "power well A",
+ .domains = XELPD_PW_A_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_A,
+ .hsw.irq_pipe_mask = BIT(PIPE_A),
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "power well B",
+ .domains = XELPD_PW_B_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_B,
+ .hsw.irq_pipe_mask = BIT(PIPE_B),
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "power well C",
+ .domains = XELPD_PW_C_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_C,
+ .hsw.irq_pipe_mask = BIT(PIPE_C),
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "power well D",
+ .domains = XELPD_PW_D_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_D,
+ .hsw.irq_pipe_mask = BIT(PIPE_D),
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "DDI A IO",
+ .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+ }
+ },
+ {
+ .name = "DDI B IO",
+ .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+ }
+ },
+ {
+ .name = "DDI C IO",
+ .domains = ICL_DDI_IO_C_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
+ }
+ },
+ {
+ .name = "DDI IO D_XELPD",
+ .domains = XELPD_DDI_IO_D_XELPD_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = XELPD_PW_CTL_IDX_DDI_D,
+ }
+ },
+ {
+ .name = "DDI IO E_XELPD",
+ .domains = XELPD_DDI_IO_E_XELPD_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = XELPD_PW_CTL_IDX_DDI_E,
+ }
+ },
+ {
+ .name = "DDI IO TC1",
+ .domains = XELPD_DDI_IO_TC1_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
+ }
+ },
+ {
+ .name = "DDI IO TC2",
+ .domains = XELPD_DDI_IO_TC2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
+ }
+ },
+ {
+ .name = "DDI IO TC3",
+ .domains = XELPD_DDI_IO_TC3_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
+ }
+ },
+ {
+ .name = "DDI IO TC4",
+ .domains = XELPD_DDI_IO_TC4_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
+ }
+ },
+ {
+ .name = "AUX A",
+ .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+ },
+ },
+ {
+ .name = "AUX B",
+ .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+ },
+ },
+ {
+ .name = "AUX C",
+ .domains = TGL_AUX_C_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
+ },
+ },
+ {
+ .name = "AUX D_XELPD",
+ .domains = XELPD_AUX_IO_D_XELPD_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = XELPD_PW_CTL_IDX_AUX_D,
+ },
+ },
+ {
+ .name = "AUX E_XELPD",
+ .domains = XELPD_AUX_IO_E_XELPD_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = XELPD_PW_CTL_IDX_AUX_E,
+ },
+ },
+ {
+ .name = "AUX USBC1",
+ .domains = XELPD_AUX_IO_USBC1_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
+ },
+ },
+ {
+ .name = "AUX USBC2",
+ .domains = XELPD_AUX_IO_USBC2_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
+ },
+ },
+ {
+ .name = "AUX USBC3",
+ .domains = XELPD_AUX_IO_USBC3_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
+ },
+ },
+ {
+ .name = "AUX USBC4",
+ .domains = XELPD_AUX_IO_USBC4_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
+ },
+ },
+ {
+ .name = "AUX TBT1",
+ .domains = XELPD_AUX_IO_TBT1_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
+ .hsw.is_tc_tbt = true,
+ },
+ },
+ {
+ .name = "AUX TBT2",
+ .domains = XELPD_AUX_IO_TBT2_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
+ .hsw.is_tc_tbt = true,
+ },
+ },
+ {
+ .name = "AUX TBT3",
+ .domains = XELPD_AUX_IO_TBT3_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
+ .hsw.is_tc_tbt = true,
+ },
+ },
+ {
+ .name = "AUX TBT4",
+ .domains = XELPD_AUX_IO_TBT4_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
+ .hsw.is_tc_tbt = true,
+ },
+ },
+};
+
static int
sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
int disable_power_well)
@@ -4673,7 +5093,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
* The enabling order will be from lower to higher indexed wells,
* the disabling order is reversed.
*/
- if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 13) {
+ err = set_power_wells(power_domains, xelpd_power_wells);
+ } else if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
err = set_power_wells_mask(power_domains, tgl_power_wells,
BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
} else if (IS_ROCKETLAKE(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index f3ca5d5c9778..f20d22b09a65 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -49,6 +49,9 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_LANES_TC5,
POWER_DOMAIN_PORT_DDI_LANES_TC6,
+ POWER_DOMAIN_PORT_DDI_LANES_D_XELPD = POWER_DOMAIN_PORT_DDI_LANES_TC5, /* XELPD */
+ POWER_DOMAIN_PORT_DDI_LANES_E_XELPD,
+
POWER_DOMAIN_PORT_DDI_A_IO,
POWER_DOMAIN_PORT_DDI_B_IO,
POWER_DOMAIN_PORT_DDI_C_IO,
@@ -66,6 +69,9 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_IO_TC5,
POWER_DOMAIN_PORT_DDI_IO_TC6,
+ POWER_DOMAIN_PORT_DDI_IO_D_XELPD = POWER_DOMAIN_PORT_DDI_IO_TC5, /* XELPD */
+ POWER_DOMAIN_PORT_DDI_IO_E_XELPD,
+
POWER_DOMAIN_PORT_DSI,
POWER_DOMAIN_PORT_CRT,
POWER_DOMAIN_PORT_OTHER,
@@ -88,6 +94,9 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_USBC5,
POWER_DOMAIN_AUX_USBC6,
+ POWER_DOMAIN_AUX_D_XELPD = POWER_DOMAIN_AUX_USBC5, /* XELPD */
+ POWER_DOMAIN_AUX_E_XELPD,
+
POWER_DOMAIN_AUX_IO_A,
POWER_DOMAIN_AUX_C_TBT,
POWER_DOMAIN_AUX_D_TBT,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 1ccef159a9a0..0696c76646df 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -473,13 +473,13 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
* POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases:
*
* - ICL eDP/DSI transcoder
- * - Gen12+ (except RKL) pipe A
+ * - Display version 12 (except RKL) pipe A
*
* For any other pipe, VDSC/joining uses the power well associated with
* the pipe in use. Hence another reference on the pipe power domain
* will suffice. (Except no VDSC/joining on ICL pipe A.)
*/
- if (DISPLAY_VER(i915) >= 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
+ if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
else if (is_pipe_dsc(crtc_state))
return POWER_DOMAIN_PIPE(pipe);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 59291d6a702e..981901b67916 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9623,6 +9623,12 @@ enum {
#define ICL_PW_CTL_IDX_PW_2 1
#define ICL_PW_CTL_IDX_PW_1 0
+/* XE_LPD - power wells */
+#define XELPD_PW_CTL_IDX_PW_D 8
+#define XELPD_PW_CTL_IDX_PW_C 7
+#define XELPD_PW_CTL_IDX_PW_B 6
+#define XELPD_PW_CTL_IDX_PW_A 5
+
#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
@@ -9637,7 +9643,9 @@ enum {
#define TGL_PW_CTL_IDX_AUX_TBT1 9
#define ICL_PW_CTL_IDX_AUX_TBT1 8
#define TGL_PW_CTL_IDX_AUX_TC6 8
+#define XELPD_PW_CTL_IDX_AUX_E 8
#define TGL_PW_CTL_IDX_AUX_TC5 7
+#define XELPD_PW_CTL_IDX_AUX_D 7
#define TGL_PW_CTL_IDX_AUX_TC4 6
#define ICL_PW_CTL_IDX_AUX_F 5
#define TGL_PW_CTL_IDX_AUX_TC3 5
@@ -9652,7 +9660,9 @@ enum {
#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
+#define XELPD_PW_CTL_IDX_DDI_E 8
#define TGL_PW_CTL_IDX_DDI_TC6 8
+#define XELPD_PW_CTL_IDX_DDI_D 7
#define TGL_PW_CTL_IDX_DDI_TC5 7
#define TGL_PW_CTL_IDX_DDI_TC4 6
#define ICL_PW_CTL_IDX_DDI_F 5
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 14/56] drm/i915/xelpd: Handle LPSP for XE_LPD
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (12 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 13/56] drm/i915/xelpd: Add XE_LPD power wells Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 15/56] drm/i915/xelpd: Increase maximum watermark lines to 255 Matt Roper
` (44 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Uma Shankar <uma.shankar@intel.com>
Enable LPSP for XE_LPD and get the proper power well
enable check in place. For XE_LPD it is PW2 which
need to check for LPSP.
v2:
- Move the XE_LPD check outside of the switch. (Lucas)
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 1666aa23092b..a5338dbb4503 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1339,6 +1339,12 @@ static int i915_lpsp_status(struct seq_file *m, void *unused)
{
struct drm_i915_private *i915 = node_to_i915(m->private);
+ if (DISPLAY_VER(i915) >= 13) {
+ LPSP_STATUS(!intel_lpsp_power_well_enabled(i915,
+ SKL_DISP_PW_2));
+ return 0;
+ }
+
switch (DISPLAY_VER(i915)) {
case 12:
case 11:
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 15/56] drm/i915/xelpd: Increase maximum watermark lines to 255
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (13 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 14/56] drm/i915/xelpd: Handle LPSP for XE_LPD Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 16/56] drm/i915/xelpd: Required bandwidth increases when VT-d is active Matt Roper
` (43 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx
XE_LPD continues to use the same "skylake-style" watermark
programming as other recent platforms. The only change to the watermark
calculations compared to Display12 is that XE_LPD now allows a
maximum of 255 lines vs the old limit of 31.
Due to the larger possible lines value, the corresponding bits
representing the value in PLANE_WM are also extended, so make sure we
read/write enough bits. Let's also take this opportunity to switch over
to the REG_FIELD notation.
Bspec: 49325
Bspec: 50419
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +--
drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++----
2 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 981901b67916..348b94a69b96 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6425,8 +6425,7 @@ enum {
#define _CUR_WM_TRANS_B_0 0x71168
#define PLANE_WM_EN (1 << 31)
#define PLANE_WM_IGNORE_LINES (1 << 30)
-#define PLANE_WM_LINES_SHIFT 14
-#define PLANE_WM_LINES_MASK 0x1f
+#define PLANE_WM_LINES_MASK REG_GENMASK(21, 14)
#define PLANE_WM_BLOCKS_MASK 0x7ff /* skl+: 10 bits, icl+ 11 bits */
#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2616b1845719..0bad9cc76505 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5176,6 +5176,14 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
return level > 0;
}
+static int skl_wm_max_lines(struct drm_i915_private *dev_priv)
+{
+ if (DISPLAY_VER(dev_priv) >= 13)
+ return 255;
+ else
+ return 31;
+}
+
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
unsigned int latency,
@@ -5284,7 +5292,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
if (!skl_wm_has_lines(dev_priv, level))
res_lines = 0;
- if (res_lines > 31) {
+ if (res_lines > skl_wm_max_lines(dev_priv)) {
/* reject it */
result->min_ddb_alloc = U16_MAX;
return;
@@ -5579,7 +5587,7 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv,
if (level->ignore_lines)
val |= PLANE_WM_IGNORE_LINES;
val |= level->plane_res_b;
- val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
+ val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->plane_res_l);
intel_de_write_fw(dev_priv, reg, val);
}
@@ -6187,8 +6195,7 @@ static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
level->plane_en = val & PLANE_WM_EN;
level->ignore_lines = val & PLANE_WM_IGNORE_LINES;
level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
- level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
- PLANE_WM_LINES_MASK;
+ level->plane_res_l = REG_FIELD_GET(PLANE_WM_LINES_MASK, val);
}
void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 16/56] drm/i915/xelpd: Required bandwidth increases when VT-d is active
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (14 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 15/56] drm/i915/xelpd: Increase maximum watermark lines to 255 Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-12 23:03 ` Srivatsa, Anusha
2021-03-11 22:35 ` [Intel-gfx] [PATCH 17/56] drm/i915/xelpd: Add Wa_14011503030 Matt Roper
` (42 subsequent siblings)
58 siblings, 1 reply; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx
If VT-d is active, the memory bandwidth usage of the display is 5%
higher. Take this into account when determining whether we can support
a display configuration.
Bspec: 64631
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 20dbc3759d27..23cf9bf31e41 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -344,6 +344,9 @@ static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
for_each_pipe(dev_priv, pipe)
data_rate += bw_state->data_rate[pipe];
+ if (DISPLAY_VER(dev_priv) >= 13 && intel_vtd_active())
+ data_rate = data_rate * 105 / 100;
+
return data_rate;
}
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Intel-gfx] [PATCH 16/56] drm/i915/xelpd: Required bandwidth increases when VT-d is active
2021-03-11 22:35 ` [Intel-gfx] [PATCH 16/56] drm/i915/xelpd: Required bandwidth increases when VT-d is active Matt Roper
@ 2021-03-12 23:03 ` Srivatsa, Anusha
0 siblings, 0 replies; 74+ messages in thread
From: Srivatsa, Anusha @ 2021-03-12 23:03 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt
> Roper
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 16/56] drm/i915/xelpd: Required bandwidth
> increases when VT-d is active
>
> If VT-d is active, the memory bandwidth usage of the display is 5% higher.
> Take this into account when determining whether we can support a display
> configuration.
>
> Bspec: 64631
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 20dbc3759d27..23cf9bf31e41 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -344,6 +344,9 @@ static unsigned int intel_bw_data_rate(struct
> drm_i915_private *dev_priv,
> for_each_pipe(dev_priv, pipe)
> data_rate += bw_state->data_rate[pipe];
>
> + if (DISPLAY_VER(dev_priv) >= 13 && intel_vtd_active())
> + data_rate = data_rate * 105 / 100;
> +
> return data_rate;
> }
>
> --
> 2.25.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 74+ messages in thread
* [Intel-gfx] [PATCH 17/56] drm/i915/xelpd: Add Wa_14011503030
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (15 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 16/56] drm/i915/xelpd: Required bandwidth increases when VT-d is active Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 18/56] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp Matt Roper
` (41 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4 ++++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 2cccf45837d3..8bb5203dd2da 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5840,6 +5840,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR;
intel_uncore_rmw(&dev_priv->uncore, GEN11_CHICKEN_DCPR_2, 0, val);
}
+
+ /* Wa_14011503030:xelpd */
+ if (DISPLAY_VER(dev_priv) >= 13)
+ intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
}
static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 348b94a69b96..95fd6bb8f0ff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7780,6 +7780,8 @@ enum {
#define GEN8_GT_BCS_IRQ (1 << 1)
#define GEN8_GT_RCS_IRQ (1 << 0)
+#define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c)
+
#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 18/56] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (16 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 17/56] drm/i915/xelpd: Add Wa_14011503030 Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 19/56] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
` (40 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
Move the platform specific max bpc calculation into
intel_dp_dsc_compute_bpp function
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 95c1f25e1bf3..f64098cd1273 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1213,10 +1213,18 @@ intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
return -EINVAL;
}
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
+static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i, num_bpc;
u8 dsc_bpc[3] = {0};
+ u8 dsc_max_bpc;
+
+ /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
+ if (DISPLAY_VER(i915) >= 12)
+ dsc_max_bpc = min_t(u8, 12, max_req_bpc);
+ else
+ dsc_max_bpc = min_t(u8, 10, max_req_bpc);
num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
dsc_bpc);
@@ -1304,7 +1312,6 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
- u8 dsc_max_bpc;
int pipe_bpp;
int ret;
@@ -1314,14 +1321,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
- /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
- if (DISPLAY_VER(dev_priv) >= 12)
- dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
- else
- dsc_max_bpc = min_t(u8, 10,
- conn_state->max_requested_bpc);
-
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
/* Min Input BPC for ICL+ is 8 */
if (pipe_bpp < 8 * 3) {
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 19/56] drm/i915/xelpd: Support DP1.4 compression BPPs
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (17 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 18/56] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 20/56] drm/i915: Get slice height before computing rc params Matt Roper
` (39 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
Support compression BPPs from bpc to uncompressed BPP -1.
So far we have 8,10,12 as valid compressed BPPS now the
support is extended.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 32 ++++++++++++++++++-------
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f64098cd1273..792797cda914 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -154,6 +154,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
static void intel_dp_link_down(struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state);
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
+static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
/* update sink rates from dpcd */
static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
@@ -539,7 +540,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner)
+ bool bigjoiner,
+ u32 pipe_bpp)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -564,6 +566,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
max_bpp_small_joiner_ram);
+
/*
* Greatest allowed DSC BPP = MIN (output BPP from available Link BW
* check, output bpp from small joiner RAM check)
@@ -586,12 +589,17 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
return 0;
}
- /* Find the nearest match in the array of known BPPs from VESA */
- for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
- if (bits_per_pixel < valid_dsc_bpp[i + 1])
- break;
+ /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
+ if (DISPLAY_VER(i915) >= 13) {
+ bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
+ } else {
+ /* Find the nearest match in the array of known BPPs from VESA */
+ for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
+ if (bits_per_pixel < valid_dsc_bpp[i + 1])
+ break;
+ }
+ bits_per_pixel = valid_dsc_bpp[i];
}
- bits_per_pixel = valid_dsc_bpp[i];
/*
* Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
@@ -825,6 +833,12 @@ intel_dp_mode_valid(struct drm_connector *connector,
*/
if ((DISPLAY_VER(dev_priv) >= 10) &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+ /*
+ * TBD pass the connector BPC,
+ * for now U8_MAX so that max BPC on that platform would be picked
+ */
+ int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+
if (intel_dp_is_edp(intel_dp)) {
dsc_max_output_bpp =
drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
@@ -838,7 +852,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
max_lanes,
target_clock,
mode->hdisplay,
- bigjoiner) >> 4;
+ bigjoiner,
+ pipe_bpp) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1356,7 +1371,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->lane_count,
adjusted_mode->crtc_clock,
adjusted_mode->crtc_hdisplay,
- pipe_config->bigjoiner);
+ pipe_config->bigjoiner,
+ pipe_bpp);
dsc_dp_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
adjusted_mode->crtc_clock,
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 20/56] drm/i915: Get slice height before computing rc params
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (18 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 19/56] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 21/56] drm/i915/xelpd: Calculate VDSC RC parameters Matt Roper
` (38 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
We need slice height to calculate few RC parameters
hence assign slice height first.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 792797cda914..5dc1b49cbb67 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1270,10 +1270,6 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
*/
vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
- ret = intel_dsc_compute_params(encoder, crtc_state);
- if (ret)
- return ret;
-
/*
* Slice Height of 8 works for all currently available panels. So start
* with that if pic_height is an integral multiple of 8. Eventually add
@@ -1286,6 +1282,10 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
else
vdsc_cfg->slice_height = 2;
+ ret = intel_dsc_compute_params(encoder, crtc_state);
+ if (ret)
+ return ret;
+
vdsc_cfg->dsc_version_major =
(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 21/56] drm/i915/xelpd: Calculate VDSC RC parameters
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (19 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 20/56] drm/i915: Get slice height before computing rc params Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 22/56] drm/i915/xelpd: Add rc_qp_table for rcparams calculation Matt Roper
` (37 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Juha-Pekka Heikkil, Mohammed Khajapasha
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
Add methods to calculate rc parameters for all bpps, against the fixed
arrays that we already have for 8,10,12 valid o/p bpps, to cover RGB 444
formats. Our hw doesn't support YUV compression yet. The calculations
used here are from VESA C model for DSC 1.1
v2:
- Checkpatch fixes
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Juha-Pekka Heikkil <juha-pekka.heikkila@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Mohammed Khajapasha <mohammed.khajapasha@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 96 ++++++++++++++++++++---
1 file changed, 86 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 0696c76646df..db1a64222e7d 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -5,7 +5,7 @@
* Author: Gaurav K Singh <gaurav.k.singh@intel.com>
* Manasi Navare <manasi.d.navare@intel.com>
*/
-
+#include <linux/limits.h>
#include "i915_drv.h"
#include "intel_display_types.h"
#include "intel_dsi.h"
@@ -376,12 +376,73 @@ static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state)
return true;
}
+static void
+calculate_rc_params(struct rc_parameters *rc,
+ struct drm_dsc_config *vdsc_cfg)
+{
+ int bpc = vdsc_cfg->bits_per_component;
+ int bpp = vdsc_cfg->bits_per_pixel >> 4;
+ int ofs_und6[] = { 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 };
+ int ofs_und8[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
+ int ofs_und12[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
+ int ofs_und15[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 };
+ int qp_bpc_modifier = (bpc - 8) * 2;
+ u32 res, buf_i;
+
+ if (vdsc_cfg->slice_height >= 8)
+ rc->first_line_bpg_offset = 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
+ else
+ rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
+
+ /* Our hw supports only 444 modes as of today */
+ if (bpp >= 12)
+ rc->initial_offset = 2048;
+ else if (bpp >= 10)
+ rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
+ else if (bpp >= 8)
+ rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
+ else
+ rc->initial_offset = 6144;
+
+ /* initial_xmit_delay = rc_model_size/2/compression_bpp */
+ rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
+
+ rc->flatness_min_qp = 3 + qp_bpc_modifier;
+ rc->flatness_max_qp = 12 + qp_bpc_modifier;
+
+ rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
+ rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
+
+ for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
+ /* Calculate range_bgp_offset */
+ if (bpp <= 6) {
+ rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
+ } else if (bpp <= 8) {
+ res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
+ rc->rc_range_params[buf_i].range_bpg_offset =
+ ofs_und6[buf_i] + res;
+ } else if (bpp <= 12) {
+ rc->rc_range_params[buf_i].range_bpg_offset =
+ ofs_und8[buf_i];
+ } else if (bpp <= 15) {
+ res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
+ rc->rc_range_params[buf_i].range_bpg_offset =
+ ofs_und12[buf_i] + res;
+ } else {
+ rc->rc_range_params[buf_i].range_bpg_offset =
+ ofs_und15[buf_i];
+ }
+ }
+}
+
int intel_dsc_compute_params(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
const struct rc_parameters *rc_params;
+ struct rc_parameters *rc = NULL;
u8 i = 0;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
@@ -416,9 +477,24 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
vdsc_cfg->rc_buf_thresh[13] = 0x7D;
}
- rc_params = get_rc_params(compressed_bpp, vdsc_cfg->bits_per_component);
- if (!rc_params)
- return -EINVAL;
+ /*
+ * From XE_LPD onwards we supports compression bpps in steps of 1
+ * upto uncompressed bpp-1, hence add calculations for all the rc
+ * parameters
+ */
+ if (DISPLAY_VER(dev_priv) >= 13) {
+ rc = kmalloc(sizeof(*rc), GFP_KERNEL);
+ if (!rc)
+ return -ENOMEM;
+
+ calculate_rc_params(rc, vdsc_cfg);
+ rc_params = rc;
+ } else {
+ rc_params = get_rc_params(compressed_bpp,
+ vdsc_cfg->bits_per_component);
+ if (!rc_params)
+ return -EINVAL;
+ }
vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
@@ -444,20 +520,20 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
/*
* BitsPerComponent value determines mux_word_size:
- * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits
- * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to
- * 48 bits
+ * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
+ * 48 bits otherwise 64
*/
- if (vdsc_cfg->bits_per_component == 8 ||
- vdsc_cfg->bits_per_component == 10)
+ if (vdsc_cfg->bits_per_component <= 10)
vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
- else if (vdsc_cfg->bits_per_component == 12)
+ else
vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
/* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
+ kfree(rc);
+
return 0;
}
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 22/56] drm/i915/xelpd: Add rc_qp_table for rcparams calculation
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (20 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 21/56] drm/i915/xelpd: Calculate VDSC RC parameters Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-11 22:35 ` [Intel-gfx] [PATCH 23/56] drm/i915/xelpd: Add VRR guardband for VRR CTL Matt Roper
` (36 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
Add the qp table for 444 formats, for 8bpc, 10bpc and 12bpc, as given by
the VESA C model for DSC 1.1
v2:
- Add include guard to header (Jani)
- Move the big tables to a .c file (Chris, Jani, Lucas)
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
.../gpu/drm/i915/display/intel_qp_tables.c | 272 ++++++++++++++++++
.../gpu/drm/i915/display/intel_qp_tables.h | 34 +++
drivers/gpu/drm/i915/display/intel_vdsc.c | 22 +-
3 files changed, 327 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_qp_tables.c
create mode 100644 drivers/gpu/drm/i915/display/intel_qp_tables.h
diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c b/drivers/gpu/drm/i915/display/intel_qp_tables.c
new file mode 100644
index 000000000000..cc1d3493bc9d
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
@@ -0,0 +1,272 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include "intel_qp_tables.h"
+
+/*
+ * These qp tables are as per the C model
+ * and it has the rows pointing to bpps which increment
+ * in steps of 0.5
+ * We do not support fractional bpps as of today,
+ * hence we would skip the fractional bpps during
+ * our references for qp calclulations.
+ */
+const u8 rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },
+ { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },
+ { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+ { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
+ { 6, 5, 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
+ { 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3,
+ 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 0 },
+ { 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4,
+ 4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 0 },
+ { 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4,
+ 4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 0 },
+ { 9, 9, 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5,
+ 5, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 1, 1, 1 },
+ { 14, 14, 13, 13, 12, 12, 12, 12, 11, 11, 10, 10, 10, 10, 9, 9, 9, 8, 8,
+ 8, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3 }
+};
+
+const u8 rc_range_maxqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {
+ { 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 6, 6, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+ { 8, 7, 7, 6, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 3, 2, 2, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+ { 8, 8, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 4, 3, 3, 2, 2, 2, 2, 2,
+ 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0 },
+ { 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 4, 4, 3, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 0 },
+ { 9, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 5, 4, 4, 3, 3, 3, 3, 3,
+ 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1 },
+ { 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 4, 4, 3, 3, 3, 3, 3,
+ 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1 },
+ { 10, 10, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 6, 5, 5, 4, 4, 4, 4, 3,
+ 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1 },
+ { 11, 11, 10, 10, 9, 9, 9, 9, 9, 9, 8, 8, 8, 7, 7, 6, 6, 5, 5, 5, 5, 5,
+ 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1 },
+ { 12, 11, 11, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 8, 8, 7, 6, 6, 5, 5, 5,
+ 5, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1 },
+ { 12, 12, 11, 11, 10, 10, 10, 10, 10, 10, 9, 9, 9, 8, 8, 7, 7, 6, 6, 6,
+ 5, 5, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1 },
+ { 12, 12, 12, 11, 11, 11, 10, 10, 10, 10, 9, 9, 9, 9, 8, 8, 8, 7, 7, 7,
+ 6, 6, 5, 5, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 1 },
+ { 12, 12, 12, 12, 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 8, 8, 8, 7, 7, 7,
+ 6, 6, 5, 5, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 1 },
+ { 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 10, 10, 10, 10, 9, 9, 8, 8, 8,
+ 8, 7, 7, 6, 6, 6, 6, 5, 5, 4, 4, 4, 4, 3, 3, 2, 2, 2 },
+ { 15, 15, 14, 14, 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 10, 10, 10, 9,
+ 9, 9, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 5, 4, 4, 4, 4 }
+};
+
+const u8 rc_range_minqp444_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_10BPC_MAX_NUM_BPP] = {
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0 },
+ { 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0 },
+ { 7, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2,
+ 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0 },
+ { 7, 7, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3,
+ 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0 },
+ { 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 3,
+ 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0 },
+ { 9, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 4,
+ 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 0, 0, 0,
+ 0, 0, 0 },
+ { 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 5, 5, 5, 5, 5,
+ 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 0, 0,
+ 0, 0, 0 },
+ { 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 5,
+ 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 0,
+ 0, 0, 0 },
+ { 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 5,
+ 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1,
+ 1, 0, 0 },
+ { 10, 9, 9, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6,
+ 6, 6, 6, 6, 6, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1,
+ 1, 1, 0 },
+ { 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 7, 7, 7, 7, 7, 6,
+ 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 2, 2, 2, 1,
+ 1, 1, 1 },
+ { 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8,
+ 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 2,
+ 2, 1, 1, 1 },
+ { 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8,
+ 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 2,
+ 2, 2, 2, 1 },
+ { 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11,
+ 11, 11, 11, 10, 10, 9, 9, 9, 9, 8, 8, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4,
+ 4, 3, 3, 3, 3, 2, 2, 2, 2, 1 },
+ { 18, 18, 17, 17, 16, 16, 16, 16, 15, 15, 14, 14, 14, 14, 13, 13, 13,
+ 12, 12, 12, 11, 11, 11, 11, 10, 10, 9, 9, 9, 9, 9, 8, 8, 7, 7, 7, 7,
+ 7, 6, 6, 5, 5, 5, 5, 4, 4, 3, 3, 3 }
+};
+
+const u8 rc_range_maxqp444_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_10BPC_MAX_NUM_BPP] = {
+ { 8, 8, 8, 8, 8, 8, 7, 7, 7, 6, 5, 5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0 },
+ { 10, 10, 9, 9, 8, 8, 8, 8, 8, 8, 7, 7, 6, 6, 6, 5, 5, 4, 4, 4, 4, 3, 3,
+ 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0 },
+ { 12, 11, 11, 10, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 8, 7, 6, 6, 5, 5, 5, 4,
+ 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0,
+ 0, 0, 0, 0 },
+ { 12, 12, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 9, 9, 9, 8, 7, 7, 6,
+ 6, 6, 5, 5, 5, 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1,
+ 1, 0, 0, 0, 0, 0, 0 },
+ { 13, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 8, 8, 7,
+ 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1,
+ 1, 1, 1, 0, 0, 0, 0, 0 },
+ { 13, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 10, 9, 8, 8,
+ 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 5, 5, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2,
+ 2, 2, 1, 1, 1, 1, 0, 0 },
+ { 13, 13, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 8, 8,
+ 7, 7, 7, 7, 7, 6, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 2,
+ 2, 2, 2, 1, 1, 1, 1, 1 },
+ { 14, 14, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 12, 11, 11, 10, 9, 9,
+ 8, 8, 8, 8, 7, 7, 7, 7, 6, 6, 6, 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 3, 3,
+ 3, 2, 2, 2, 1, 1, 1, 1 },
+ { 15, 15, 14, 14, 13, 13, 13, 13, 13, 13, 12, 12, 12, 11, 11, 10, 10, 9,
+ 9, 9, 9, 9, 8, 8, 8, 8, 7, 7, 6, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 3,
+ 3, 3, 2, 2, 2, 2, 1, 1 },
+ { 16, 15, 15, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 12, 12, 11, 10,
+ 10, 9, 9, 9, 9, 8, 8, 8, 8, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4,
+ 4, 3, 3, 3, 2, 2, 2, 2, 1 },
+ { 16, 16, 15, 15, 14, 14, 14, 14, 14, 14, 13, 13, 13, 12, 12, 11, 11,
+ 10, 10, 10, 9, 9, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5,
+ 4, 4, 4, 3, 3, 3, 2, 2, 2, 2 },
+ { 16, 16, 16, 15, 15, 15, 14, 14, 14, 14, 13, 13, 13, 13, 12, 12, 12,
+ 11, 11, 11, 10, 10, 9, 9, 9, 9, 8, 8, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 5,
+ 5, 4, 4, 4, 4, 3, 3, 2, 2, 2 },
+ { 16, 16, 16, 16, 15, 15, 15, 15, 15, 14, 14, 13, 13, 13, 12, 12, 12,
+ 11, 11, 11, 10, 10, 9, 9, 9, 9, 8, 8, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 5,
+ 5, 4, 4, 4, 4, 3, 3, 3, 3, 2 },
+ { 17, 17, 17, 17, 16, 16, 15, 15, 15, 15, 14, 14, 14, 14, 13, 13, 12,
+ 12, 12, 12, 11, 11, 10, 10, 10, 10, 9, 9, 8, 8, 8, 8, 7, 7, 6, 6, 6,
+ 6, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 2 },
+ { 19, 19, 18, 18, 17, 17, 17, 17, 16, 16, 15, 15, 15, 15, 14, 14, 14,
+ 13, 13, 13, 12, 12, 12, 12, 11, 11, 10, 10, 10, 10, 10, 9, 9, 8, 8, 8,
+ 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 4, 4, 4 }
+};
+
+const u8 rc_range_minqp444_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_12BPC_MAX_NUM_BPP] = {
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 11, 10, 10, 9, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 6, 5, 5, 4, 4, 4, 3, 3, 3, 3,
+ 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 11, 11, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 8, 7, 6, 6, 6, 6, 6, 5, 5, 5,
+ 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 13, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 8, 7, 7, 7,
+ 7, 5, 5, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1,
+ 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 13, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 9, 9, 8, 8,
+ 8, 8, 6, 6, 6, 6, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 2, 2, 2,
+ 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 13, 13, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 9, 9, 9, 9,
+ 9, 9, 9, 8, 8, 8, 7, 7, 7, 6, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 3, 3,
+ 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+ { 13, 13, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 10,
+ 10, 10, 10, 9, 9, 9, 9, 8, 8, 8, 7, 7, 7, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 4, 4,
+ 4, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0 },
+ { 13, 13, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,
+ 11, 11, 11, 10, 10, 10, 10, 9, 9, 8, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 5, 5,
+ 5, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0 },
+ { 14, 13, 13, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,
+ 11, 11, 11, 10, 10, 10, 10, 9, 9, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 6, 6, 5,
+ 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 0 },
+ { 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 12,
+ 12, 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 8, 7, 7, 7,
+ 6, 6, 6, 5, 5, 5, 5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1 },
+ { 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13,
+ 13, 12, 12, 11, 11, 11, 11, 11, 11, 10, 10, 10, 10, 9, 9, 9, 9, 8, 8, 8, 8,
+ 7, 7, 7, 7, 6, 6, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1, 1, 1 },
+ { 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13,
+ 13, 12, 12, 12, 12, 12, 12, 11, 11, 10, 10, 10, 10, 9, 9, 9, 9, 8, 8, 8, 8,
+ 7, 7, 7, 7, 6, 6, 6, 6, 5, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1, 1, 1 },
+ { 17, 17, 17, 17, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15,
+ 15, 14, 14, 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 10, 10, 9, 9, 9, 9, 8, 8,
+ 7, 7, 7, 7, 7, 6, 6, 6, 5, 5, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 1 },
+ { 22, 22, 21, 21, 20, 20, 20, 20, 19, 19, 18, 18, 18, 18, 17, 17, 17, 16, 16,
+ 16, 15, 15, 15, 15, 14, 14, 13, 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 11,
+ 10, 10, 9, 9, 9, 9, 9, 8, 8, 7, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 3 }
+};
+
+const u8 rc_range_maxqp444_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_12BPC_MAX_NUM_BPP] = {
+ { 12, 12, 12, 12, 12, 12, 11, 11, 11, 10, 9, 9, 6, 6, 5, 5, 5, 4, 4, 4, 4, 4,
+ 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 14, 14, 13, 13, 12, 12, 12, 12, 12, 12, 11, 11, 9, 9, 9, 8, 8, 7, 7, 7, 7, 5,
+ 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 16, 15, 15, 14, 13, 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 11, 10, 10, 9, 9,
+ 9, 7, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1,
+ 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 16, 16, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 13, 13, 13, 12, 11, 11, 10,
+ 10, 10, 8, 8, 8, 8, 8, 7, 7, 6, 5, 5, 5, 5, 5, 5, 5, 4, 4, 3, 3, 3, 3, 3, 2,
+ 2, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 17, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 15, 14, 14, 13, 12, 12, 11, 10,
+ 10, 10, 10, 8, 8, 8, 8, 8, 8, 7, 7, 7, 6, 6, 5, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3,
+ 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
+ { 17, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 14, 14, 14, 13, 12, 12, 11,
+ 11, 11, 11, 9, 9, 9, 9, 8, 8, 8, 8, 7, 6, 6, 6, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3,
+ 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0 },
+ { 17, 17, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 15, 14, 14, 13, 12, 12, 11,
+ 11, 11, 11, 11, 10, 10, 10, 9, 9, 9, 8, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 5, 5,
+ 5, 5, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 0 },
+ { 18, 18, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 16, 15, 15, 14, 13, 13, 12,
+ 12, 12, 12, 11, 11, 11, 11, 10, 10, 10, 8, 8, 8, 7, 7, 7, 7, 7, 7, 6, 6, 6,
+ 6, 5, 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1 },
+ { 19, 19, 18, 18, 17, 17, 17, 17, 17, 17, 16, 16, 16, 15, 15, 14, 14, 13, 13,
+ 13, 13, 13, 12, 12, 12, 12, 11, 11, 10, 9, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 6,
+ 6, 6, 5, 5, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1 },
+ { 20, 19, 19, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 16, 16, 15, 14, 14, 13,
+ 13, 13, 13, 12, 12, 12, 12, 11, 11, 10, 10, 9, 9, 9, 9, 8, 8, 8, 8, 8, 7, 7,
+ 6, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 1 },
+ { 20, 20, 19, 19, 18, 18, 18, 18, 18, 18, 17, 17, 17, 16, 16, 15, 15, 14, 14,
+ 14, 13, 13, 12, 12, 12, 12, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 9, 9, 9,
+ 8, 8, 8, 7, 7, 7, 6, 6, 6, 6, 5, 5, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2 },
+ { 20, 20, 20, 19, 19, 19, 18, 18, 18, 18, 17, 17, 17, 17, 16, 16, 16, 15, 15,
+ 15, 14, 14, 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 10, 10, 10, 10, 9, 9, 9,
+ 9, 8, 8, 8, 8, 7, 7, 6, 6, 6, 5, 5, 5, 4, 4, 4, 4, 3, 3, 2, 2, 2 },
+ { 20, 20, 20, 20, 19, 19, 19, 19, 19, 18, 18, 17, 17, 17, 16, 16, 16, 15, 15,
+ 15, 14, 14, 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 10, 10, 10, 10, 9, 9, 9,
+ 9, 8, 8, 8, 8, 7, 7, 7, 7, 6, 5, 5, 5, 4, 4, 4, 4, 3, 3, 2, 2, 2 },
+ { 21, 21, 21, 21, 20, 20, 19, 19, 19, 19, 18, 18, 18, 18, 17, 17, 16, 16, 16,
+ 16, 15, 15, 14, 14, 14, 14, 13, 13, 12, 12, 12, 12, 11, 11, 10, 10, 10, 10,
+ 9, 9, 8, 8, 8, 8, 8, 7, 7, 7, 6, 6, 6, 6, 5, 5, 4, 4, 4, 4, 3, 3, 2 },
+ { 23, 23, 22, 22, 21, 21, 21, 21, 20, 20, 19, 19, 19, 19, 18, 18, 18, 17, 17,
+ 17, 16, 16, 16, 16, 15, 15, 14, 14, 14, 14, 14, 13, 13, 12, 12, 12, 12, 12,
+ 11, 11, 10, 10, 10, 10, 10, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 4 }
+};
diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.h b/drivers/gpu/drm/i915/display/intel_qp_tables.h
new file mode 100644
index 000000000000..ca8f1b1a1960
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef _INTEL_QP_TABLES_H_
+#define _INTEL_QP_TABLES_H_
+
+#include <linux/types.h>
+
+#define RC_RANGE_QP(min_max, bpp, row, col) \
+ rc_range_##min_max##qp444_##bpp##bpc[row][col]
+
+#ifndef DSC_NUM_BUF_RANGES
+#define DSC_NUM_BUF_RANGES 15
+#endif
+
+/* from BPP 6 to 24 in steps of 0.5 */
+#define RC_RANGE_QP444_8BPC_MAX_NUM_BPP 37
+
+/* from BPP 6 to 30 in steps of 0.5 */
+#define RC_RANGE_QP444_10BPC_MAX_NUM_BPP 49
+
+/* from BPP 6 to 36 in steps of 0.5 */
+#define RC_RANGE_QP444_12BPC_MAX_NUM_BPP 61
+
+const u8 rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP];
+const u8 rc_range_maxqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP];
+const u8 rc_range_minqp444_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_10BPC_MAX_NUM_BPP];
+const u8 rc_range_maxqp444_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_10BPC_MAX_NUM_BPP];
+const u8 rc_range_minqp444_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_12BPC_MAX_NUM_BPP];
+const u8 rc_range_maxqp444_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_12BPC_MAX_NUM_BPP];
+
+#endif
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index db1a64222e7d..28bd32bc74ba 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -10,6 +10,7 @@
#include "intel_display_types.h"
#include "intel_dsi.h"
#include "intel_vdsc.h"
+#include "intel_qp_tables.h"
enum ROW_INDEX_BPP {
ROW_INDEX_6BPP = 0,
@@ -387,7 +388,7 @@ calculate_rc_params(struct rc_parameters *rc,
int ofs_und12[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
int ofs_und15[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 };
int qp_bpc_modifier = (bpc - 8) * 2;
- u32 res, buf_i;
+ u32 res, buf_i, bpp_i;
if (vdsc_cfg->slice_height >= 8)
rc->first_line_bpg_offset = 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
@@ -413,7 +414,26 @@ calculate_rc_params(struct rc_parameters *rc,
rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
+ bpp_i = (2 * (bpp - 6));
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
+ /* Read range_minqp and range_max_qp from qp tables */
+ switch (bpc) {
+ case 8:
+ rc->rc_range_params[buf_i].range_min_qp = RC_RANGE_QP(min, 8, buf_i, bpp_i);
+ rc->rc_range_params[buf_i].range_max_qp = RC_RANGE_QP(max, 8, buf_i, bpp_i);
+ break;
+ case 10:
+ rc->rc_range_params[buf_i].range_min_qp = RC_RANGE_QP(min, 10, buf_i, bpp_i);
+ rc->rc_range_params[buf_i].range_max_qp = RC_RANGE_QP(max, 10, buf_i, bpp_i);
+ break;
+ case 12:
+ rc->rc_range_params[buf_i].range_min_qp = RC_RANGE_QP(min, 12, buf_i, bpp_i);
+ rc->rc_range_params[buf_i].range_max_qp = RC_RANGE_QP(max, 12, buf_i, bpp_i);
+ break;
+ default:
+ break;
+ }
+
/* Calculate range_bgp_offset */
if (bpp <= 6) {
rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 23/56] drm/i915/xelpd: Add VRR guardband for VRR CTL
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (21 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 22/56] drm/i915/xelpd: Add rc_qp_table for rcparams calculation Matt Roper
@ 2021-03-11 22:35 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 24/56] drm/i915/adl_p: Add PCI Devices IDs Matt Roper
` (35 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:35 UTC (permalink / raw)
To: intel-gfx
From: Manasi Navare <manasi.d.navare@intel.com>
On XE_LPD, VRR CTL register adds a new VRR Guardband bitfield
replacing the pipeline full and deprecating the pipeline override
bit.
This patch adds this corresponding bitfield in the register defs,
crtc state vrr structure and populates this in vrr compute
config and vrr enable functions. It also adds the corresponding
HW state readout for this field.
Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 8 ++-
.../drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_vrr.c | 56 +++++++++++++------
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_reg.h | 2 +
5 files changed, 51 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 926707fd00e3..d032f1782bcb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8127,10 +8127,11 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
intel_hdmi_infoframe_enable(DP_SDP_VSC))
intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
- drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
+ drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
yesno(pipe_config->vrr.enable),
pipe_config->vrr.vmin, pipe_config->vrr.vmax,
- pipe_config->vrr.pipeline_full, pipe_config->vrr.flipline,
+ pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
+ pipe_config->vrr.flipline,
intel_vrr_vmin_vblank_start(pipe_config),
intel_vrr_vmax_vblank_start(pipe_config));
@@ -9136,6 +9137,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(vrr.vmax);
PIPE_CONF_CHECK_I(vrr.flipline);
PIPE_CONF_CHECK_I(vrr.pipeline_full);
+ PIPE_CONF_CHECK_I(vrr.guardband);
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
@@ -12608,6 +12610,8 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
i915->framestart_delay = 1; /* 1-4 */
+ i915->window2_delay = 0; /* No DSB so no window2 delay */
+
intel_mode_config_init(i915);
ret = intel_cdclk_init(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f159dce0f744..b2257213b8e8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1171,7 +1171,7 @@ struct intel_crtc_state {
struct {
bool enable;
u8 pipeline_full;
- u16 flipline, vmin, vmax;
+ u16 flipline, vmin, vmax, guardband;
} vrr;
/* Stream Splitter for eDP MSO */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index a9c2b2fd9252..7013163f4978 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -67,7 +67,10 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
/* The hw imposes the extra scanline before frame start */
- return crtc_state->vrr.pipeline_full + i915->framestart_delay + 1;
+ if (DISPLAY_VER(i915) >= 13)
+ return crtc_state->vrr.guardband + i915->framestart_delay + 1;
+ else
+ return crtc_state->vrr.pipeline_full + i915->framestart_delay + 1;
}
int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
@@ -85,6 +88,8 @@ void
intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
@@ -123,17 +128,26 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
/*
- * FIXME: s/4/framestart_delay+1/ to get consistent
- * earliest/latest points for register latching regardless
- * of the framestart_delay used?
- *
- * FIXME: this really needs the extra scanline to provide consistent
- * behaviour for all framestart_delay values. Otherwise with
- * framestart_delay==3 we will end up extending the min vblank by
- * one extra line.
+ * For XE_LPD+, we use guardband and pipeline override
+ * is deprecated.
*/
- crtc_state->vrr.pipeline_full =
- min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1);
+ if (DISPLAY_VER(i915) >= 13)
+ crtc_state->vrr.guardband =
+ crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay -
+ i915->window2_delay;
+ else
+ /*
+ * FIXME: s/4/framestart_delay+1/ to get consistent
+ * earliest/latest points for register latching regardless
+ * of the framestart_delay used?
+ *
+ * FIXME: this really needs the extra scanline to provide consistent
+ * behaviour for all framestart_delay values. Otherwise with
+ * framestart_delay==3 we will end up extending the min vblank by
+ * one extra line.
+ */
+ crtc_state->vrr.pipeline_full =
+ min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1);
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}
@@ -148,10 +162,15 @@ void intel_vrr_enable(struct intel_encoder *encoder,
if (!crtc_state->vrr.enable)
return;
- trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
- VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
- VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) |
- VRR_CTL_PIPELINE_FULL_OVERRIDE;
+ if (DISPLAY_VER(dev_priv) >= 13)
+ trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
+ VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
+ XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
+ else
+ trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
+ VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
+ VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) |
+ VRR_CTL_PIPELINE_FULL_OVERRIDE;
intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
@@ -198,8 +217,11 @@ void intel_vrr_get_config(struct intel_crtc *crtc,
if (!crtc_state->vrr.enable)
return;
- if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
- crtc_state->vrr.pipeline_full = REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
+ if (DISPLAY_VER(dev_priv) >= 13)
+ crtc_state->vrr.guardband = REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
+ else
+ if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
+ crtc_state->vrr.pipeline_full = REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN)
crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5ec0524d3418..30103b22c086 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1139,6 +1139,9 @@ struct drm_i915_private {
u8 framestart_delay;
+ /* Window2 specifies time required to program DSB (Window2) in number of scan lines */
+ u8 window2_delay;
+
u8 pch_ssc_use;
/* For i915gm/i945gm vblank irq workaround */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 95fd6bb8f0ff..6a48e046dedf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4356,6 +4356,8 @@ enum {
#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
+#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
+#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
#define _TRANS_VRR_VMAX_A 0x60424
#define _TRANS_VRR_VMAX_B 0x61424
--
2.25.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 24/56] drm/i915/adl_p: Add PCI Devices IDs
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (22 preceding siblings ...)
2021-03-11 22:35 ` [Intel-gfx] [PATCH 23/56] drm/i915/xelpd: Add VRR guardband for VRR CTL Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-12 23:20 ` Srivatsa, Anusha
2021-03-17 18:04 ` Jani Nikula
2021-03-11 22:36 ` [Intel-gfx] [PATCH 25/56] drm/i915/adl_p: ADL_P device info enabling Matt Roper
` (34 subsequent siblings)
58 siblings, 2 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: Clinton Taylor <Clinton.A.Taylor@intel.com>
Add 12 known PCI device IDs
Bspec: 55376
Cc: Caz Yokoyama <caz.yokoyama@intel.com>
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
include/drm/i915_pciids.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index ebd0dd1c35b3..6607b65e7ae2 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -645,4 +645,24 @@
INTEL_VGA_DEVICE(0x4692, info), \
INTEL_VGA_DEVICE(0x4693, info)
+/* ADL-P */
+#define INTEL_ADLP_IDS(info) \
+ INTEL_VGA_DEVICE(0x46A0, info), \
+ INTEL_VGA_DEVICE(0x46A1, info), \
+ INTEL_VGA_DEVICE(0x46A2, info), \
+ INTEL_VGA_DEVICE(0x46A3, info), \
+ INTEL_VGA_DEVICE(0x46A6, info), \
+ INTEL_VGA_DEVICE(0x46A8, info), \
+ INTEL_VGA_DEVICE(0x46AA, info), \
+ INTEL_VGA_DEVICE(0x462A, info), \
+ INTEL_VGA_DEVICE(0x4626, info), \
+ INTEL_VGA_DEVICE(0x4628, info), \
+ INTEL_VGA_DEVICE(0x46B0, info), \
+ INTEL_VGA_DEVICE(0x46B1, info), \
+ INTEL_VGA_DEVICE(0x46B2, info), \
+ INTEL_VGA_DEVICE(0x46B3, info), \
+ INTEL_VGA_DEVICE(0x46C0, info), \
+ INTEL_VGA_DEVICE(0x46C1, info), \
+ INTEL_VGA_DEVICE(0x46C2, info), \
+ INTEL_VGA_DEVICE(0x46C3, info)
#endif /* _I915_PCIIDS_H */
--
2.25.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Intel-gfx] [PATCH 24/56] drm/i915/adl_p: Add PCI Devices IDs
2021-03-11 22:36 ` [Intel-gfx] [PATCH 24/56] drm/i915/adl_p: Add PCI Devices IDs Matt Roper
@ 2021-03-12 23:20 ` Srivatsa, Anusha
2021-03-17 18:04 ` Jani Nikula
1 sibling, 0 replies; 74+ messages in thread
From: Srivatsa, Anusha @ 2021-03-12 23:20 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt
> Roper
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 24/56] drm/i915/adl_p: Add PCI Devices IDs
>
> From: Clinton Taylor <Clinton.A.Taylor@intel.com>
>
> Add 12 known PCI device IDs
>
> Bspec: 55376
> Cc: Caz Yokoyama <caz.yokoyama@intel.com>
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> include/drm/i915_pciids.h | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> ebd0dd1c35b3..6607b65e7ae2 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -645,4 +645,24 @@
> INTEL_VGA_DEVICE(0x4692, info), \
> INTEL_VGA_DEVICE(0x4693, info)
>
> +/* ADL-P */
> +#define INTEL_ADLP_IDS(info) \
> + INTEL_VGA_DEVICE(0x46A0, info), \
> + INTEL_VGA_DEVICE(0x46A1, info), \
> + INTEL_VGA_DEVICE(0x46A2, info), \
> + INTEL_VGA_DEVICE(0x46A3, info), \
> + INTEL_VGA_DEVICE(0x46A6, info), \
> + INTEL_VGA_DEVICE(0x46A8, info), \
> + INTEL_VGA_DEVICE(0x46AA, info), \
> + INTEL_VGA_DEVICE(0x462A, info), \
> + INTEL_VGA_DEVICE(0x4626, info), \
> + INTEL_VGA_DEVICE(0x4628, info), \
> + INTEL_VGA_DEVICE(0x46B0, info), \
> + INTEL_VGA_DEVICE(0x46B1, info), \
> + INTEL_VGA_DEVICE(0x46B2, info), \
> + INTEL_VGA_DEVICE(0x46B3, info), \
> + INTEL_VGA_DEVICE(0x46C0, info), \
> + INTEL_VGA_DEVICE(0x46C1, info), \
> + INTEL_VGA_DEVICE(0x46C2, info), \
> + INTEL_VGA_DEVICE(0x46C3, info)
> #endif /* _I915_PCIIDS_H */
> --
> 2.25.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Intel-gfx] [PATCH 24/56] drm/i915/adl_p: Add PCI Devices IDs
2021-03-11 22:36 ` [Intel-gfx] [PATCH 24/56] drm/i915/adl_p: Add PCI Devices IDs Matt Roper
2021-03-12 23:20 ` Srivatsa, Anusha
@ 2021-03-17 18:04 ` Jani Nikula
1 sibling, 0 replies; 74+ messages in thread
From: Jani Nikula @ 2021-03-17 18:04 UTC (permalink / raw)
To: Matt Roper, intel-gfx
On Thu, 11 Mar 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
> From: Clinton Taylor <Clinton.A.Taylor@intel.com>
>
> Add 12 known PCI device IDs
>
> Bspec: 55376
> Cc: Caz Yokoyama <caz.yokoyama@intel.com>
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> include/drm/i915_pciids.h | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index ebd0dd1c35b3..6607b65e7ae2 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -645,4 +645,24 @@
> INTEL_VGA_DEVICE(0x4692, info), \
> INTEL_VGA_DEVICE(0x4693, info)
>
> +/* ADL-P */
> +#define INTEL_ADLP_IDS(info) \
> + INTEL_VGA_DEVICE(0x46A0, info), \
> + INTEL_VGA_DEVICE(0x46A1, info), \
> + INTEL_VGA_DEVICE(0x46A2, info), \
> + INTEL_VGA_DEVICE(0x46A3, info), \
> + INTEL_VGA_DEVICE(0x46A6, info), \
> + INTEL_VGA_DEVICE(0x46A8, info), \
> + INTEL_VGA_DEVICE(0x46AA, info), \
> + INTEL_VGA_DEVICE(0x462A, info), \
> + INTEL_VGA_DEVICE(0x4626, info), \
> + INTEL_VGA_DEVICE(0x4628, info), \
> + INTEL_VGA_DEVICE(0x46B0, info), \
> + INTEL_VGA_DEVICE(0x46B1, info), \
> + INTEL_VGA_DEVICE(0x46B2, info), \
> + INTEL_VGA_DEVICE(0x46B3, info), \
> + INTEL_VGA_DEVICE(0x46C0, info), \
> + INTEL_VGA_DEVICE(0x46C1, info), \
> + INTEL_VGA_DEVICE(0x46C2, info), \
> + INTEL_VGA_DEVICE(0x46C3, info)
Nitpick, this loses the blank line here.
> #endif /* _I915_PCIIDS_H */
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Intel-gfx] [PATCH 25/56] drm/i915/adl_p: ADL_P device info enabling
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (23 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 24/56] drm/i915/adl_p: Add PCI Devices IDs Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 26/56] drm/i915/adl_p: Add PCH support Matt Roper
` (33 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: Clinton Taylor <Clinton.A.Taylor@intel.com>
Add ADL-P to the device_info table and support MACROS.
Bspec: 49185, 55372, 55373
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
arch/x86/kernel/early-quirks.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
5 files changed, 16 insertions(+)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 6edd1e2ee8af..b553ffe9b985 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -552,6 +552,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
INTEL_TGL_12_IDS(&gen11_early_ops),
INTEL_RKL_IDS(&gen11_early_ops),
INTEL_ADLS_IDS(&gen11_early_ops),
+ INTEL_ADLP_IDS(&gen11_early_ops),
};
struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 30103b22c086..b702e4f02ae7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1383,6 +1383,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
+#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 3f06502e1d85..dba6bedd258e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -946,6 +946,17 @@ static const struct intel_device_info adl_s_info = {
.ddb_size = 4096, \
.num_supported_dbuf_slices = 4
+static const struct intel_device_info adl_p_info = {
+ GEN12_FEATURES,
+ XE_LPD_FEATURES,
+ PLATFORM(INTEL_ALDERLAKE_P),
+ .require_force_probe = 1,
+ .platform_engine_mask =
+ BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+ .ppgtt_size = 48,
+ .dma_mask_size = 46,
+};
+
#undef GEN
#undef PLATFORM
@@ -1023,6 +1034,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_TGL_12_IDS(&tgl_info),
INTEL_RKL_IDS(&rkl_info),
INTEL_ADLS_IDS(&adl_s_info),
+ INTEL_ADLP_IDS(&adl_p_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 8a55cdfc802c..16d8be7f734f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -67,6 +67,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(ROCKETLAKE),
PLATFORM_NAME(DG1),
PLATFORM_NAME(ALDERLAKE_S),
+ PLATFORM_NAME(ALDERLAKE_P),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 3c7db9c690f4..626cd11dab12 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -85,6 +85,7 @@ enum intel_platform {
INTEL_ROCKETLAKE,
INTEL_DG1,
INTEL_ALDERLAKE_S,
+ INTEL_ALDERLAKE_P,
INTEL_MAX_PLATFORMS
};
--
2.25.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 26/56] drm/i915/adl_p: Add PCH support
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (24 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 25/56] drm/i915/adl_p: ADL_P device info enabling Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-12 23:52 ` Srivatsa, Anusha
2021-03-11 22:36 ` [Intel-gfx] [PATCH 27/56] drm/i915/adl_p: Add dedicated SAGV watermarks Matt Roper
` (32 subsequent siblings)
58 siblings, 1 reply; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: Clinton Taylor <Clinton.A.Taylor@intel.com>
Add ADP-P PCH device ID and assign as ADL PCH if found. Previously we
would assign the DDC pin map based on the PCH, but it can also change
based on the CPU. From Bspec 20124: "The physical port to pin pair
mapping are defined in the Bspec per PCH. Mapping can further change
based on CPU Si used as CPU and PCH can be mixed and matched".
Bspec: 20124
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/intel_pch.c | 6 ++++--
drivers/gpu/drm/i915/intel_pch.h | 1 +
4 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index e4cef54726b4..5f8d14be1265 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1649,7 +1649,7 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
const u8 *ddc_pin_map;
int n_entries;
- if (HAS_PCH_ADP(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv)) {
ddc_pin_map = adls_ddc_pin_map;
n_entries = ARRAY_SIZE(adls_ddc_pin_map);
} else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 4f285c7d54c4..2a2b01026564 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3213,7 +3213,7 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
return ddc_pin;
}
- if (HAS_PCH_ADP(dev_priv))
+ if (IS_ALDERLAKE_S(dev_priv))
ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index 7476f0e063c6..98a17dd1bda4 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -130,8 +130,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
return PCH_JSP;
case INTEL_PCH_ADP_DEVICE_ID_TYPE:
+ case INTEL_PCH_ADP2_DEVICE_ID_TYPE:
drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n");
- drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv));
+ drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv) &&
+ !IS_ALDERLAKE_P(dev_priv));
return PCH_ADP;
default:
return PCH_NONE;
@@ -161,7 +163,7 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv,
* make an educated guess as to which PCH is really there.
*/
- if (IS_ALDERLAKE_S(dev_priv))
+ if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index 7318377503b0..e2f3f30c6445 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -55,6 +55,7 @@ enum intel_pch {
#define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80
#define INTEL_PCH_JSP2_DEVICE_ID_TYPE 0x3880
#define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80
+#define INTEL_PCH_ADP2_DEVICE_ID_TYPE 0x5180
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
--
2.25.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Intel-gfx] [PATCH 26/56] drm/i915/adl_p: Add PCH support
2021-03-11 22:36 ` [Intel-gfx] [PATCH 26/56] drm/i915/adl_p: Add PCH support Matt Roper
@ 2021-03-12 23:52 ` Srivatsa, Anusha
0 siblings, 0 replies; 74+ messages in thread
From: Srivatsa, Anusha @ 2021-03-12 23:52 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt
> Roper
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 26/56] drm/i915/adl_p: Add PCH support
>
> From: Clinton Taylor <Clinton.A.Taylor@intel.com>
>
> Add ADP-P PCH device ID and assign as ADL PCH if found. Previously we
> would assign the DDC pin map based on the PCH, but it can also change
> based on the CPU. From Bspec 20124: "The physical port to pin pair mapping
> are defined in the Bspec per PCH. Mapping can further change based on CPU
> Si used as CPU and PCH can be mixed and matched".
>
> Bspec: 20124
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> drivers/gpu/drm/i915/intel_pch.c | 6 ++++--
> drivers/gpu/drm/i915/intel_pch.h | 1 +
> 4 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index e4cef54726b4..5f8d14be1265 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1649,7 +1649,7 @@ static u8 map_ddc_pin(struct drm_i915_private
> *dev_priv, u8 vbt_pin)
> const u8 *ddc_pin_map;
> int n_entries;
>
> - if (HAS_PCH_ADP(dev_priv)) {
> + if (IS_ALDERLAKE_S(dev_priv)) {
> ddc_pin_map = adls_ddc_pin_map;
> n_entries = ARRAY_SIZE(adls_ddc_pin_map);
> } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) { diff --git
> a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 4f285c7d54c4..2a2b01026564 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3213,7 +3213,7 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder
> *encoder)
> return ddc_pin;
> }
>
> - if (HAS_PCH_ADP(dev_priv))
> + if (IS_ALDERLAKE_S(dev_priv))
> ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); diff --git
> a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
> index 7476f0e063c6..98a17dd1bda4 100644
> --- a/drivers/gpu/drm/i915/intel_pch.c
> +++ b/drivers/gpu/drm/i915/intel_pch.c
> @@ -130,8 +130,10 @@ intel_pch_type(const struct drm_i915_private
> *dev_priv, unsigned short id)
> drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
> return PCH_JSP;
> case INTEL_PCH_ADP_DEVICE_ID_TYPE:
> + case INTEL_PCH_ADP2_DEVICE_ID_TYPE:
> drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n");
> - drm_WARN_ON(&dev_priv->drm,
> !IS_ALDERLAKE_S(dev_priv));
> + drm_WARN_ON(&dev_priv->drm,
> !IS_ALDERLAKE_S(dev_priv) &&
> + !IS_ALDERLAKE_P(dev_priv));
> return PCH_ADP;
> default:
> return PCH_NONE;
> @@ -161,7 +163,7 @@ intel_virt_detect_pch(const struct drm_i915_private
> *dev_priv,
> * make an educated guess as to which PCH is really there.
> */
>
> - if (IS_ALDERLAKE_S(dev_priv))
> + if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
> id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
> else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
> id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
> diff --git a/drivers/gpu/drm/i915/intel_pch.h
> b/drivers/gpu/drm/i915/intel_pch.h
> index 7318377503b0..e2f3f30c6445 100644
> --- a/drivers/gpu/drm/i915/intel_pch.h
> +++ b/drivers/gpu/drm/i915/intel_pch.h
> @@ -55,6 +55,7 @@ enum intel_pch {
> #define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80
> #define INTEL_PCH_JSP2_DEVICE_ID_TYPE 0x3880
> #define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80
> +#define INTEL_PCH_ADP2_DEVICE_ID_TYPE 0x5180
> #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
> #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
> #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35
> has 2918 */
> --
> 2.25.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Intel-gfx] [PATCH 27/56] drm/i915/adl_p: Add dedicated SAGV watermarks
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (25 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 26/56] drm/i915/adl_p: Add PCH support Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 28/56] drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines Matt Roper
` (31 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
XE_LPD reduces the number of regular watermark latency levels from 8
to 6 on non-dgfx platforms. However the hardware also adds a special
purpose SAGV wateramrk (and an accompanying transition watermark) that
will be used by the hardware in place of the level 0 values during SAGV
transitions.
Bspec: 49325, 49326, 50419
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 32 +++++++++++
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_reg.h | 59 ++++++++++++++------
drivers/gpu/drm/i915/intel_pm.c | 56 +++++++++++++++++--
4 files changed, 128 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d032f1782bcb..f0a0390f8497 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9243,6 +9243,38 @@ static void verify_wm_state(struct intel_crtc *crtc,
hw_wm_level->plane_res_l);
}
+ hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;
+ sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;
+
+ if (HAS_HW_SAGV_WM(dev_priv) &&
+ !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
+ drm_err(&dev_priv->drm,
+ "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+ plane->base.base.id, plane->base.name,
+ sw_wm_level->plane_en,
+ sw_wm_level->plane_res_b,
+ sw_wm_level->plane_res_l,
+ hw_wm_level->plane_en,
+ hw_wm_level->plane_res_b,
+ hw_wm_level->plane_res_l);
+ }
+
+ hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm;
+ sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm;
+
+ if (HAS_HW_SAGV_WM(dev_priv) &&
+ !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
+ drm_err(&dev_priv->drm,
+ "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+ plane->base.base.id, plane->base.name,
+ sw_wm_level->plane_en,
+ sw_wm_level->plane_res_b,
+ sw_wm_level->plane_res_l,
+ hw_wm_level->plane_en,
+ hw_wm_level->plane_res_b,
+ hw_wm_level->plane_res_l);
+ }
+
/* DDB */
hw_ddb_entry = &hw->ddb_y[plane->id];
sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id];
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b702e4f02ae7..10b99f9e380b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -582,6 +582,8 @@ i915_fence_timeout(const struct drm_i915_private *i915)
/* Amount of SAGV/QGV points, BSpec precisely defines this */
#define I915_NUM_QGV_POINTS 8
+#define HAS_HW_SAGV_WM(i915) ((DISPLAY_VER(i915) == 13) && !IS_DGFX(i915))
+
struct ddi_vbt_port_info {
/* Non-NULL if port present. */
const struct child_device_config *child;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6a48e046dedf..cdb2f7b136a9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6415,16 +6415,28 @@ enum {
/* Watermark register definitions for SKL */
#define _CUR_WM_A_0 0x70140
#define _CUR_WM_B_0 0x71140
+#define _CUR_WM_SAGV_A 0x70158
+#define _CUR_WM_SAGV_B 0x71158
+#define _CUR_WM_SAGV_TRANS_A 0x7015C
+#define _CUR_WM_SAGV_TRANS_B 0x7115C
+#define _CUR_WM_TRANS_A 0x70168
+#define _CUR_WM_TRANS_B 0x71168
#define _PLANE_WM_1_A_0 0x70240
#define _PLANE_WM_1_B_0 0x71240
#define _PLANE_WM_2_A_0 0x70340
#define _PLANE_WM_2_B_0 0x71340
-#define _PLANE_WM_TRANS_1_A_0 0x70268
-#define _PLANE_WM_TRANS_1_B_0 0x71268
-#define _PLANE_WM_TRANS_2_A_0 0x70368
-#define _PLANE_WM_TRANS_2_B_0 0x71368
-#define _CUR_WM_TRANS_A_0 0x70168
-#define _CUR_WM_TRANS_B_0 0x71168
+#define _PLANE_WM_SAGV_1_A 0x70258
+#define _PLANE_WM_SAGV_1_B 0x71258
+#define _PLANE_WM_SAGV_2_A 0x70358
+#define _PLANE_WM_SAGV_2_B 0x71358
+#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C
+#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C
+#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C
+#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C
+#define _PLANE_WM_TRANS_1_A 0x70268
+#define _PLANE_WM_TRANS_1_B 0x71268
+#define _PLANE_WM_TRANS_2_A 0x70368
+#define _PLANE_WM_TRANS_2_B 0x71368
#define PLANE_WM_EN (1 << 31)
#define PLANE_WM_IGNORE_LINES (1 << 30)
#define PLANE_WM_LINES_MASK REG_GENMASK(21, 14)
@@ -6432,19 +6444,32 @@ enum {
#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
-#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
-
+#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
+#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
+#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
-#define _PLANE_WM_BASE(pipe, plane) \
- _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
-#define PLANE_WM(pipe, plane, level) \
- _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
-#define _PLANE_WM_TRANS_1(pipe) \
- _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
-#define _PLANE_WM_TRANS_2(pipe) \
- _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
-#define PLANE_WM_TRANS(pipe, plane) \
+#define _PLANE_WM_BASE(pipe, plane) \
+ _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
+#define PLANE_WM(pipe, plane, level) \
+ _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
+#define _PLANE_WM_SAGV_1(pipe) \
+ _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
+#define _PLANE_WM_SAGV_2(pipe) \
+ _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
+#define PLANE_WM_SAGV(pipe, plane) \
+ _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
+#define _PLANE_WM_SAGV_TRANS_1(pipe) \
+ _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
+#define _PLANE_WM_SAGV_TRANS_2(pipe) \
+ _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
+#define PLANE_WM_SAGV_TRANS(pipe, plane) \
+ _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
+#define _PLANE_WM_TRANS_1(pipe) \
+ _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
+#define _PLANE_WM_TRANS_2(pipe) \
+ _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
+#define PLANE_WM_TRANS(pipe, plane) \
_MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
/* define the Watermark register on Ironlake */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0bad9cc76505..0052630fd9dd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2982,7 +2982,9 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
{
/* how many WM levels are we expecting */
- if (DISPLAY_VER(dev_priv) >= 9)
+ if (HAS_HW_SAGV_WM(dev_priv))
+ return 5;
+ else if (DISPLAY_VER(dev_priv) >= 9)
return 7;
else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
return 4;
@@ -3998,8 +4000,10 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
* latter from the plane commit hooks (especially in the legacy
* cursor case)
*/
- pipe_wm->use_sagv_wm = DISPLAY_VER(dev_priv) >= 12 &&
- intel_can_enable_sagv(dev_priv, new_bw_state);
+
+ pipe_wm->use_sagv_wm = !HAS_HW_SAGV_WM(dev_priv) &&
+ DISPLAY_VER(dev_priv) >= 12 &&
+ intel_can_enable_sagv(dev_priv, new_bw_state);
}
if (intel_can_enable_sagv(dev_priv, new_bw_state) !=
@@ -5613,6 +5617,13 @@ void skl_write_plane_wm(struct intel_plane *plane,
skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
skl_plane_trans_wm(pipe_wm, plane_id));
+ if (HAS_HW_SAGV_WM(dev_priv)) {
+ skl_write_wm_level(dev_priv, PLANE_WM_SAGV(pipe, plane_id),
+ &wm->sagv.wm0);
+ skl_write_wm_level(dev_priv, PLANE_WM_SAGV_TRANS(pipe, plane_id),
+ &wm->sagv.trans_wm);
+ }
+
if (DISPLAY_VER(dev_priv) >= 11) {
skl_ddb_entry_write(dev_priv,
PLANE_BUF_CFG(pipe, plane_id), ddb_y);
@@ -5646,6 +5657,15 @@ void skl_write_cursor_wm(struct intel_plane *plane,
skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe),
skl_plane_trans_wm(pipe_wm, plane_id));
+ if (HAS_HW_SAGV_WM(dev_priv)) {
+ const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
+
+ skl_write_wm_level(dev_priv, CUR_WM_SAGV(pipe),
+ &wm->sagv.wm0);
+ skl_write_wm_level(dev_priv, CUR_WM_SAGV_TRANS(pipe),
+ &wm->sagv.trans_wm);
+ }
+
skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);
}
@@ -6010,6 +6030,15 @@ static bool skl_plane_selected_wm_equals(struct intel_plane *plane,
return false;
}
+ if (HAS_HW_SAGV_WM(i915)) {
+ const struct skl_plane_wm *old_wm = &old_pipe_wm->planes[plane->id];
+ const struct skl_plane_wm *new_wm = &new_pipe_wm->planes[plane->id];
+
+ if (!skl_wm_level_equals(&old_wm->sagv.wm0, &new_wm->sagv.wm0) ||
+ !skl_wm_level_equals(&old_wm->sagv.trans_wm, &new_wm->sagv.trans_wm))
+ return false;
+ }
+
return skl_wm_level_equals(skl_plane_trans_wm(old_pipe_wm, plane->id),
skl_plane_trans_wm(new_pipe_wm, plane->id));
}
@@ -6228,7 +6257,26 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
skl_wm_level_from_reg_val(val, &wm->trans_wm);
- if (DISPLAY_VER(dev_priv) >= 12) {
+
+ if (HAS_HW_SAGV_WM(dev_priv)) {
+ if (plane_id != PLANE_CURSOR)
+ val = intel_uncore_read(&dev_priv->uncore,
+ PLANE_WM_SAGV(pipe, plane_id));
+ else
+ val = intel_uncore_read(&dev_priv->uncore,
+ CUR_WM_SAGV(pipe));
+
+ skl_wm_level_from_reg_val(val, &wm->sagv.wm0);
+
+ if (plane_id != PLANE_CURSOR)
+ val = intel_uncore_read(&dev_priv->uncore,
+ PLANE_WM_SAGV_TRANS(pipe, plane_id));
+ else
+ val = intel_uncore_read(&dev_priv->uncore,
+ CUR_WM_SAGV_TRANS(pipe));
+
+ skl_wm_level_from_reg_val(val, &wm->sagv.trans_wm);
+ } else if (DISPLAY_VER(dev_priv) >= 12) {
wm->sagv.wm0 = wm->wm[0];
wm->sagv.trans_wm = wm->trans_wm;
}
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 28/56] drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (26 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 27/56] drm/i915/adl_p: Add dedicated SAGV watermarks Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-12 23:59 ` Srivatsa, Anusha
2021-03-11 22:36 ` [Intel-gfx] [PATCH 29/56] drm/i915/adl_p: Load DMC Matt Roper
` (30 subsequent siblings)
58 siblings, 1 reply; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
ADL-P further extends the bits in PLANE_WM that represent blocks and
lines; we need to extend our masks accordingly. Since these bits are
reserved and MBZ on earlier platforms, it's safe to use the larger
bitmask on all platforms.
Bspec: 50419
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cdb2f7b136a9..1d0cb423720e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6439,8 +6439,8 @@ enum {
#define _PLANE_WM_TRANS_2_B 0x71368
#define PLANE_WM_EN (1 << 31)
#define PLANE_WM_IGNORE_LINES (1 << 30)
-#define PLANE_WM_LINES_MASK REG_GENMASK(21, 14)
-#define PLANE_WM_BLOCKS_MASK 0x7ff /* skl+: 10 bits, icl+ 11 bits */
+#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
+#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Intel-gfx] [PATCH 28/56] drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines
2021-03-11 22:36 ` [Intel-gfx] [PATCH 28/56] drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines Matt Roper
@ 2021-03-12 23:59 ` Srivatsa, Anusha
0 siblings, 0 replies; 74+ messages in thread
From: Srivatsa, Anusha @ 2021-03-12 23:59 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt
> Roper
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 28/56] drm/i915/adl_p: Extend PLANE_WM bits
> for blocks & lines
>
> ADL-P further extends the bits in PLANE_WM that represent blocks and lines;
> we need to extend our masks accordingly. Since these bits are reserved and
> MBZ on earlier platforms, it's safe to use the larger bitmask on all platforms.
>
> Bspec: 50419
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index cdb2f7b136a9..1d0cb423720e
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6439,8 +6439,8 @@ enum {
> #define _PLANE_WM_TRANS_2_B 0x71368
> #define PLANE_WM_EN (1 << 31)
> #define PLANE_WM_IGNORE_LINES (1 << 30)
> -#define PLANE_WM_LINES_MASK REG_GENMASK(21, 14)
> -#define PLANE_WM_BLOCKS_MASK 0x7ff /* skl+: 10 bits, icl+ 11 bits */
> +#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
> +#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
>
> #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
> #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
> --
> 2.25.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 74+ messages in thread
* [Intel-gfx] [PATCH 29/56] drm/i915/adl_p: Load DMC
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (27 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 28/56] drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 30/56] drm/i915/adl_p: Setup ports/phys Matt Roper
` (29 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
Load DMC v2.08 on ADLP. The release notes mention that
this version enables few power savings features.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_csr.c | 10 +++++++++-
.../gpu/drm/i915/display/intel_display_power.c | 16 +++++++++++++++-
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index 82360593b0a6..863e4566e645 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -40,6 +40,10 @@
#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
+#define ADLP_CSR_PATH "i915/adlp_dmc_ver2_08.bin"
+#define ADLP_CSR_VERSION_REQUIRED CSR_VERSION(2, 8)
+MODULE_FIRMWARE(ADLP_CSR_PATH);
+
#define ADLS_CSR_PATH "i915/adls_dmc_ver2_01.bin"
#define ADLS_CSR_VERSION_REQUIRED CSR_VERSION(2, 1)
MODULE_FIRMWARE(ADLS_CSR_PATH);
@@ -693,7 +697,11 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
*/
intel_csr_runtime_pm_get(dev_priv);
- if (IS_ALDERLAKE_S(dev_priv)) {
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ csr->fw_path = ADLP_CSR_PATH;
+ csr->required_version = ADLP_CSR_VERSION_REQUIRED;
+ csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ } else if (IS_ALDERLAKE_S(dev_priv)) {
csr->fw_path = ADLS_CSR_PATH;
csr->required_version = ADLS_CSR_VERSION_REQUIRED;
csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 8bb5203dd2da..3b30604e850a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4953,7 +4953,21 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
int requested_dc;
int max_dc;
- if (IS_DG1(dev_priv))
+ if (!HAS_DISPLAY(dev_priv))
+ return 0;
+
+ if (DISPLAY_VER(dev_priv) == 13)
+ /*
+ * FIXME: We need to disable DC-states for two reasons:
+ *
+ * - Although not documented in the bspec, we've been told
+ * that we need to upload Pipe DMC firmwares in addition
+ * to the main DMC firmware for DC5 to work properly.
+ * We need proper bspec documentation before we can handle
+ * this.
+ */
+ max_dc = 0;
+ else if (IS_DG1(dev_priv))
max_dc = 3;
else if (DISPLAY_VER(dev_priv) >= 12)
max_dc = 4;
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 30/56] drm/i915/adl_p: Setup ports/phys
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (28 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 29/56] drm/i915/adl_p: Load DMC Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 31/56] drm/i915/adl_p: Add cdclk support for ADL-P Matt Roper
` (28 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
The SoC has 6 DDI ports(DDI A,DDI B and DDI TC1-4.
The first two are connected to combo phys while
the rest are connected to TC phys.
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f0a0390f8497..0f8092cd3a2d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4164,7 +4164,9 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
- if (IS_TIGERLAKE(dev_priv))
+ if (IS_ALDERLAKE_P(dev_priv))
+ return phy >= PHY_F && phy <= PHY_I;
+ else if (IS_TIGERLAKE(dev_priv))
return phy >= PHY_D && phy <= PHY_I;
else if (IS_ICELAKE(dev_priv))
return phy >= PHY_C && phy <= PHY_F;
@@ -11675,7 +11677,14 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_ALDERLAKE_S(dev_priv)) {
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ intel_ddi_init(dev_priv, PORT_TC1);
+ intel_ddi_init(dev_priv, PORT_TC2);
+ intel_ddi_init(dev_priv, PORT_TC3);
+ intel_ddi_init(dev_priv, PORT_TC4);
+ } else if (IS_ALDERLAKE_S(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_TC1);
intel_ddi_init(dev_priv, PORT_TC2);
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 31/56] drm/i915/adl_p: Add cdclk support for ADL-P
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (29 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 30/56] drm/i915/adl_p: Setup ports/phys Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 32/56] drm/i915/display/tc: Rename safe_mode functions ownership Matt Roper
` (27 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
ADL-P has 3 possible refclk frequencies: 19.2MHz,
24MHz and 38.4MHz
BSpec: 55409, 49208
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 29 +++++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 1c7cdd17f89a..c5fdf688fc89 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1257,6 +1257,27 @@ static const struct intel_cdclk_vals rkl_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals adlp_cdclk_table[] = {
+ { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
+ { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
+ { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
+ { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
+ { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
+
+ { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
+ { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
+ { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
+ { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
+ { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
+
+ { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
@@ -2848,7 +2869,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_ROCKETLAKE(dev_priv)) {
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ dev_priv->display.set_cdclk = bxt_set_cdclk;
+ dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk.table = adlp_cdclk_table;
+ } else if (IS_ROCKETLAKE(dev_priv)) {
dev_priv->display.set_cdclk = bxt_set_cdclk;
dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 32/56] drm/i915/display/tc: Rename safe_mode functions ownership
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (30 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 31/56] drm/i915/adl_p: Add cdclk support for ADL-P Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 33/56] drm/i915/adl_p: Handle TC cold Matt Roper
` (26 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
When DP_PHY_MODE_STATUS_NOT_SAFE is set, it means that display
has the control over the TC phy.
The "not safe" naming is confusing using ownership make it easier
to read also future platforms will have a new register that does the
same job as DP_PHY_MODE_STATUS_NOT_SAFE but with the onwership name.
BSpec: 49294
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_tc.c | 35 ++++++++++++-------------
1 file changed, 17 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 88085486ee59..d2d524329509 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -256,8 +256,8 @@ static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
return val & DP_PHY_MODE_STATUS_COMPLETED(dig_port->tc_phy_fia_idx);
}
-static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
- bool enable)
+static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
+ bool take)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct intel_uncore *uncore = &i915->uncore;
@@ -267,20 +267,20 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
if (val == 0xffffffff) {
drm_dbg_kms(&i915->drm,
- "Port %s: PHY in TCCOLD, can't set safe-mode to %s\n",
- dig_port->tc_port_name, enableddisabled(enable));
+ "Port %s: PHY in TCCOLD, can't %s ownership\n",
+ dig_port->tc_port_name, take ? "take" : "release");
return false;
}
val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
- if (!enable)
+ if (take)
val |= DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
intel_uncore_write(uncore,
PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
- if (enable && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
+ if (!take && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
drm_dbg_kms(&i915->drm,
"Port %s: PHY complete clear timed out\n",
dig_port->tc_port_name);
@@ -288,7 +288,7 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
return true;
}
-static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port)
+static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct intel_uncore *uncore = &i915->uncore;
@@ -303,7 +303,7 @@ static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port)
return true;
}
- return !(val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx));
+ return val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
}
/*
@@ -329,7 +329,7 @@ static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
goto out_set_tbt_alt_mode;
}
- if (!icl_tc_phy_set_safe_mode(dig_port, false) &&
+ if (!icl_tc_phy_take_ownership(dig_port, true) &&
!drm_WARN_ON(&i915->drm, dig_port->tc_legacy_port))
goto out_set_tbt_alt_mode;
@@ -348,7 +348,7 @@ static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
if (!(tc_port_live_status_mask(dig_port) & BIT(TC_PORT_DP_ALT))) {
drm_dbg_kms(&i915->drm, "Port %s: PHY sudden disconnect\n",
dig_port->tc_port_name);
- goto out_set_safe_mode;
+ goto out_release_phy;
}
if (max_lanes < required_lanes) {
@@ -356,15 +356,15 @@ static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
"Port %s: PHY max lanes %d < required lanes %d\n",
dig_port->tc_port_name,
max_lanes, required_lanes);
- goto out_set_safe_mode;
+ goto out_release_phy;
}
dig_port->tc_mode = TC_PORT_DP_ALT;
return;
-out_set_safe_mode:
- icl_tc_phy_set_safe_mode(dig_port, true);
+out_release_phy:
+ icl_tc_phy_take_ownership(dig_port, false);
out_set_tbt_alt_mode:
dig_port->tc_mode = TC_PORT_TBT_ALT;
}
@@ -380,7 +380,7 @@ static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port)
/* Nothing to do, we never disconnect from legacy mode */
break;
case TC_PORT_DP_ALT:
- icl_tc_phy_set_safe_mode(dig_port, true);
+ icl_tc_phy_take_ownership(dig_port, false);
dig_port->tc_mode = TC_PORT_TBT_ALT;
break;
case TC_PORT_TBT_ALT:
@@ -401,8 +401,8 @@ static bool icl_tc_phy_is_connected(struct intel_digital_port *dig_port)
return dig_port->tc_mode == TC_PORT_TBT_ALT;
}
- if (icl_tc_phy_is_in_safe_mode(dig_port)) {
- drm_dbg_kms(&i915->drm, "Port %s: PHY still in safe mode\n",
+ if (!icl_tc_phy_is_owned(dig_port)) {
+ drm_dbg_kms(&i915->drm, "Port %s: PHY not owned\n",
dig_port->tc_port_name);
return false;
@@ -417,10 +417,9 @@ intel_tc_port_get_current_mode(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
u32 live_status_mask = tc_port_live_status_mask(dig_port);
- bool in_safe_mode = icl_tc_phy_is_in_safe_mode(dig_port);
enum tc_port_mode mode;
- if (in_safe_mode ||
+ if (!icl_tc_phy_is_owned(dig_port) ||
drm_WARN_ON(&i915->drm, !icl_tc_phy_status_complete(dig_port)))
return TC_PORT_TBT_ALT;
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 33/56] drm/i915/adl_p: Handle TC cold
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (31 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 32/56] drm/i915/display/tc: Rename safe_mode functions ownership Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 34/56] drm/i915/adl_p: Implement TC sequences Matt Roper
` (25 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
On ADL-P TC cold is exited and blocked when legacy aux is powered,
that is exacly the same of what ICL need for static TC ports.
TODO: When a TBT hub or monitor is connected it will cause TBT and
legacy aux to be powered at the same time, hopefully this will not
cause any issues but if it do, some rework will be needed.
BSpec: 55480
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 3b30604e850a..19d20a8c278c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -550,7 +550,8 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
if (drm_WARN_ON(&dev_priv->drm, !dig_port))
return;
- if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port)
+ if (IS_ALDERLAKE_P(dev_priv) ||
+ (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port))
return;
drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 34/56] drm/i915/adl_p: Implement TC sequences
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (32 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 33/56] drm/i915/adl_p: Handle TC cold Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 35/56] drm/i915/adl_p: Enable modular fia Matt Roper
` (24 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
ADL-P have basically the same TC connection and disconnection
sequences as ICL and TGL, the major difference is the new registers.
So here adding functions without the icl prefix in the name and
making the new functions call the platform specific function to access
the correct register.
BSpec: 55480
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_tc.c | 132 ++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 10 ++
2 files changed, 131 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index d2d524329509..85952f39a13d 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -205,7 +205,7 @@ static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
dig_port->tc_legacy_port = !dig_port->tc_legacy_port;
}
-static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
+static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct intel_uncore *uncore = &i915->uncore;
@@ -238,6 +238,40 @@ static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
return mask;
}
+static u32 adl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+ u32 isr_bit = i915->hotplug.pch_hpd[dig_port->base.hpd_pin];
+ struct intel_uncore *uncore = &i915->uncore;
+ u32 val, mask = 0;
+
+ val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port));
+ if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT)
+ mask |= BIT(TC_PORT_DP_ALT);
+ if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT)
+ mask |= BIT(TC_PORT_TBT_ALT);
+
+ if (intel_uncore_read(uncore, SDEISR) & isr_bit)
+ mask |= BIT(TC_PORT_LEGACY);
+
+ /* The sink can be connected only in a single mode. */
+ if (!drm_WARN_ON(&i915->drm, hweight32(mask) > 1))
+ tc_port_fixup_legacy_flag(dig_port, mask);
+
+ return mask;
+}
+
+static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
+ if (IS_ALDERLAKE_P(i915))
+ return adl_tc_port_live_status_mask(dig_port);
+
+ return icl_tc_port_live_status_mask(dig_port);
+}
+
static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -256,6 +290,33 @@ static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
return val & DP_PHY_MODE_STATUS_COMPLETED(dig_port->tc_phy_fia_idx);
}
+static bool adl_tc_phy_status_complete(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_uncore *uncore = &i915->uncore;
+ u32 val;
+
+ val = intel_uncore_read(uncore, TCSS_DDI_STATUS(dig_port->tc_phy_fia_idx));
+ if (val == 0xffffffff) {
+ drm_dbg_kms(&i915->drm,
+ "Port %s: PHY in TCCOLD, assuming not complete\n",
+ dig_port->tc_port_name);
+ return false;
+ }
+
+ return val & TCSS_DDI_STATUS_READY;
+}
+
+static bool tc_phy_status_complete(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
+ if (IS_ALDERLAKE_P(i915))
+ return adl_tc_phy_status_complete(dig_port);
+
+ return icl_tc_phy_status_complete(dig_port);
+}
+
static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
bool take)
{
@@ -280,7 +341,7 @@ static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
intel_uncore_write(uncore,
PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
- if (!take && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
+ if (!take && wait_for(!tc_phy_status_complete(dig_port), 10))
drm_dbg_kms(&i915->drm,
"Port %s: PHY complete clear timed out\n",
dig_port->tc_port_name);
@@ -288,6 +349,34 @@ static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
return true;
}
+static bool adl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
+ bool take)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_uncore *uncore = &i915->uncore;
+ enum port port = dig_port->base.port;
+ u32 val;
+
+ val = intel_uncore_read(uncore, DDI_BUF_CTL(port));
+ if (take)
+ val |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+ else
+ val &= ~DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+ intel_uncore_write(uncore, DDI_BUF_CTL(port), val);
+
+ return true;
+}
+
+static bool tc_phy_take_ownership(struct intel_digital_port *dig_port, bool take)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
+ if (IS_ALDERLAKE_P(i915))
+ return adl_tc_phy_take_ownership(dig_port, take);
+
+ return icl_tc_phy_take_ownership(dig_port, take);
+}
+
static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -306,6 +395,27 @@ static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port)
return val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
}
+static bool adl_tc_phy_is_owned(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_uncore *uncore = &i915->uncore;
+ enum port port = dig_port->base.port;
+ u32 val;
+
+ val = intel_uncore_read(uncore, DDI_BUF_CTL(port));
+ return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+}
+
+static bool tc_phy_is_owned(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
+ if (IS_ALDERLAKE_P(i915))
+ return adl_tc_phy_is_owned(dig_port);
+
+ return icl_tc_phy_is_owned(dig_port);
+}
+
/*
* This function implements the first part of the Connect Flow described by our
* specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
@@ -323,13 +433,13 @@ static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
int max_lanes;
- if (!icl_tc_phy_status_complete(dig_port)) {
+ if (!tc_phy_status_complete(dig_port)) {
drm_dbg_kms(&i915->drm, "Port %s: PHY not ready\n",
dig_port->tc_port_name);
goto out_set_tbt_alt_mode;
}
- if (!icl_tc_phy_take_ownership(dig_port, true) &&
+ if (!tc_phy_take_ownership(dig_port, true) &&
!drm_WARN_ON(&i915->drm, dig_port->tc_legacy_port))
goto out_set_tbt_alt_mode;
@@ -364,7 +474,7 @@ static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
return;
out_release_phy:
- icl_tc_phy_take_ownership(dig_port, false);
+ tc_phy_take_ownership(dig_port, false);
out_set_tbt_alt_mode:
dig_port->tc_mode = TC_PORT_TBT_ALT;
}
@@ -380,7 +490,7 @@ static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port)
/* Nothing to do, we never disconnect from legacy mode */
break;
case TC_PORT_DP_ALT:
- icl_tc_phy_take_ownership(dig_port, false);
+ tc_phy_take_ownership(dig_port, false);
dig_port->tc_mode = TC_PORT_TBT_ALT;
break;
case TC_PORT_TBT_ALT:
@@ -395,13 +505,13 @@ static bool icl_tc_phy_is_connected(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- if (!icl_tc_phy_status_complete(dig_port)) {
+ if (!tc_phy_status_complete(dig_port)) {
drm_dbg_kms(&i915->drm, "Port %s: PHY status not complete\n",
dig_port->tc_port_name);
return dig_port->tc_mode == TC_PORT_TBT_ALT;
}
- if (!icl_tc_phy_is_owned(dig_port)) {
+ if (!tc_phy_is_owned(dig_port)) {
drm_dbg_kms(&i915->drm, "Port %s: PHY not owned\n",
dig_port->tc_port_name);
@@ -419,8 +529,8 @@ intel_tc_port_get_current_mode(struct intel_digital_port *dig_port)
u32 live_status_mask = tc_port_live_status_mask(dig_port);
enum tc_port_mode mode;
- if (!icl_tc_phy_is_owned(dig_port) ||
- drm_WARN_ON(&i915->drm, !icl_tc_phy_status_complete(dig_port)))
+ if (!tc_phy_is_owned(dig_port) ||
+ drm_WARN_ON(&i915->drm, !tc_phy_status_complete(dig_port)))
return TC_PORT_TBT_ALT;
mode = dig_port->tc_legacy_port ? TC_PORT_LEGACY : TC_PORT_DP_ALT;
@@ -442,7 +552,7 @@ intel_tc_port_get_target_mode(struct intel_digital_port *dig_port)
if (live_status_mask)
return fls(live_status_mask) - 1;
- return icl_tc_phy_status_complete(dig_port) &&
+ return tc_phy_status_complete(dig_port) &&
dig_port->tc_legacy_port ? TC_PORT_LEGACY :
TC_PORT_TBT_ALT;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1d0cb423720e..ce8f1e892523 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10130,6 +10130,7 @@ enum skl_power_gate {
#define DDI_BUF_EMP_MASK (0xf << 24)
#define DDI_BUF_PORT_REVERSAL (1 << 16)
#define DDI_BUF_IS_IDLE (1 << 7)
+#define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
#define DDI_A_4_LANES (1 << 4)
#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
#define DDI_PORT_WIDTH_MASK (7 << 1)
@@ -12562,6 +12563,15 @@ enum skl_power_gate {
#define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
#define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4))
+#define _TCSS_DDI_STATUS_1 0x161500
+#define _TCSS_DDI_STATUS_2 0x161504
+#define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
+ _TCSS_DDI_STATUS_1, \
+ _TCSS_DDI_STATUS_2))
+#define TCSS_DDI_STATUS_READY REG_BIT(2)
+#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
+#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
+
/* This register controls the Display State Buffer (DSB) engines. */
#define _DSBSL_INSTANCE_BASE 0x70B00
#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
--
2.25.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 35/56] drm/i915/adl_p: Enable modular fia
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (33 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 34/56] drm/i915/adl_p: Implement TC sequences Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 36/56] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization Matt Roper
` (23 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
Alderlake P have modular FIA like TGL but it is always modular in all
skus, not like TGL that we had to read a register to check if it is
monolithic or modular.
BSpec: 55480
BSpec: 50572
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_tc.c | 4 ++++
drivers/gpu/drm/i915/i915_pci.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 85952f39a13d..5f03215a03e4 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -734,6 +734,10 @@ tc_has_modular_fia(struct drm_i915_private *i915, struct intel_digital_port *dig
if (!INTEL_INFO(i915)->display.has_modular_fia)
return false;
+ /* TODO: check if in real HW MODULAR_FIA_MASK is set, if so remove this block */
+ if (IS_ALDERLAKE_P(i915))
+ return true;
+
wakeref = tc_cold_block(dig_port);
val = intel_uncore_read(&i915->uncore, PORT_TX_DFLEXDPSP(FIA1));
tc_cold_unblock(dig_port, wakeref);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index dba6bedd258e..722ed730128b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -951,6 +951,7 @@ static const struct intel_device_info adl_p_info = {
XE_LPD_FEATURES,
PLATFORM(INTEL_ALDERLAKE_P),
.require_force_probe = 1,
+ .display.has_modular_fia = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.ppgtt_size = 48,
--
2.25.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 36/56] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (34 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 35/56] drm/i915/adl_p: Enable modular fia Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 37/56] drm/i915/adl_p: Add ddb allocation support Matt Roper
` (22 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
Alderlake-P don't have programing sequences for MBUS or DBUF during
display initializaiton, instead it requires programing to those
registers during modeset because it to depend on the pipes left
enabled.
Bspec: 49213
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 19d20a8c278c..e6edd5272072 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5249,6 +5249,9 @@ static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
const int num_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
enum dbuf_slice slice;
+ if (IS_ALDERLAKE_P(dev_priv))
+ return;
+
for (slice = DBUF_S1; slice < (DBUF_S1 + num_slices); slice++)
intel_de_rmw(dev_priv, DBUF_CTL_S(slice),
DBUF_TRACKER_STATE_SERVICE_MASK,
@@ -5260,6 +5263,9 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
unsigned long abox_regs = INTEL_INFO(dev_priv)->abox_mask;
u32 mask, val, i;
+ if (IS_ALDERLAKE_P(dev_priv))
+ return;
+
mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK |
MBUS_ABOX_BT_CREDIT_POOL2_MASK |
MBUS_ABOX_B_CREDIT_MASK |
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 37/56] drm/i915/adl_p: Add ddb allocation support
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (35 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 36/56] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 38/56] drm/i915: Introduce MBUS relative dbuf offsets Matt Roper
` (21 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
On adlp the two mbuses have two display pipes and
two DBUFS, Pipe A and D on Mbus1 and Pipe B and C on
Mbus2. The Mbus can be joined and all the DBUFS can be
used on Pipe A or B.
Bspec: 49255
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
.../drm/i915/display/intel_display_power.h | 2 +
drivers/gpu/drm/i915/i915_reg.h | 22 +++-
drivers/gpu/drm/i915/intel_pm.c | 121 +++++++++++++++++-
3 files changed, 140 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index f20d22b09a65..4f0917df4375 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -389,6 +389,8 @@ intel_display_power_put_all_in_set(struct drm_i915_private *i915,
enum dbuf_slice {
DBUF_S1,
DBUF_S2,
+ DBUF_S3,
+ DBUF_S4,
I915_MAX_DBUF_SLICES
};
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ce8f1e892523..70b097ddae28 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7288,7 +7288,7 @@ enum {
#define _PLANE_BUF_CFG_1_B 0x7127c
#define _PLANE_BUF_CFG_2_B 0x7137c
-#define DDB_ENTRY_MASK 0x7FF /* skl+: 10 bits, icl+ 11 bits */
+#define DDB_ENTRY_MASK 0xFFF /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
#define DDB_ENTRY_END_SHIFT 16
#define _PLANE_BUF_CFG_1(pipe) \
_PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
@@ -8115,9 +8115,23 @@ enum {
#define DISP_DATA_PARTITION_5_6 (1 << 6)
#define DISP_IPC_ENABLE (1 << 3)
-#define _DBUF_CTL_S1 0x45008
-#define _DBUF_CTL_S2 0x44FE8
-#define DBUF_CTL_S(slice) _MMIO(_PICK_EVEN(slice, _DBUF_CTL_S1, _DBUF_CTL_S2))
+/*
+ * The below are numbered starting from "S1" on gen11/gen12, but starting
+ * with gen13 display, the bspec switches to a 0-based numbering scheme
+ * (although the addresses stay the same so new S0 = old S1, new S1 = old S2).
+ * We'll just use the 0-based numbering here for all platforms since it's the
+ * way things will be named by the hardware team going forward, plus it's more
+ * consistent with how most of the rest of our registers are named.
+ */
+#define _DBUF_CTL_S0 0x45008
+#define _DBUF_CTL_S1 0x44FE8
+#define _DBUF_CTL_S2 0x44300
+#define _DBUF_CTL_S3 0x44304
+#define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \
+ _DBUF_CTL_S0, \
+ _DBUF_CTL_S1, \
+ _DBUF_CTL_S2, \
+ _DBUF_CTL_S3))
#define DBUF_POWER_REQUEST REG_BIT(31)
#define DBUF_POWER_STATE REG_BIT(30)
#define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0052630fd9dd..4f2b28c0b30b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4561,6 +4561,118 @@ static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] =
{}
};
+static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = {
+ {
+ .active_pipes = BIT(PIPE_A),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_B),
+ .dbuf_mask = {
+ [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_C),
+ .dbuf_mask = {
+ [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
+ .dbuf_mask = {
+ [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ },
+ },
+ {}
+
+};
+
static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes,
const struct dbuf_slice_conf_entry *dbuf_slices)
{
@@ -4600,12 +4712,19 @@ static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes)
return compute_dbuf_slices(pipe, active_pipes, tgl_allowed_dbufs);
}
+static u32 adlp_compute_dbuf_slices(enum pipe pipe, u32 active_pipes)
+{
+ return compute_dbuf_slices(pipe, active_pipes, adlp_allowed_dbufs);
+}
+
static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- if (DISPLAY_VER(dev_priv) == 12)
+ if (IS_ALDERLAKE_P(dev_priv))
+ return adlp_compute_dbuf_slices(pipe, active_pipes);
+ else if (DISPLAY_VER(dev_priv) == 12)
return tgl_compute_dbuf_slices(pipe, active_pipes);
else if (DISPLAY_VER(dev_priv) == 11)
return icl_compute_dbuf_slices(pipe, active_pipes);
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 38/56] drm/i915: Introduce MBUS relative dbuf offsets
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (36 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 37/56] drm/i915/adl_p: Add ddb allocation support Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 39/56] drm/i915: Move intel_modeset_all_pipes() Matt Roper
` (20 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The dbuf slices are going to be split across several MBUS units.
The actual dbuf programming will use offsets relative to the
MBUS unit. To accomodate that we shall store the MBUS relative
offsets into the dbuf_state->ddb[] and crtc_state->plane_ddb*[].
For crtc_state->wm.skl.ddb however we want to stick to global
offsets as we use this to sanity check that the ddb allocations
don't overlap between pipes.
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 40 ++++++++++++++++++++++++++++-----
1 file changed, 34 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4f2b28c0b30b..e9a8fb1773f3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4057,6 +4057,20 @@ skl_ddb_entry_for_slices(struct drm_i915_private *dev_priv, u8 slice_mask,
WARN_ON(ddb->end > intel_dbuf_size(dev_priv));
}
+static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask)
+{
+ struct skl_ddb_entry ddb;
+
+ if (slice_mask & (BIT(DBUF_S1) | BIT(DBUF_S2)))
+ slice_mask = BIT(DBUF_S1);
+ else if (slice_mask & (BIT(DBUF_S3) | BIT(DBUF_S4)))
+ slice_mask = BIT(DBUF_S3);
+
+ skl_ddb_entry_for_slices(i915, slice_mask, &ddb);
+
+ return ddb.start;
+}
+
u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
const struct skl_ddb_entry *entry)
{
@@ -4152,6 +4166,7 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
struct intel_crtc_state *crtc_state;
struct skl_ddb_entry ddb_slices;
enum pipe pipe = crtc->pipe;
+ unsigned int mbus_offset;
u32 ddb_range_size;
u32 dbuf_slice_mask;
u32 start, end;
@@ -4166,6 +4181,7 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
dbuf_slice_mask = new_dbuf_state->slices[pipe];
skl_ddb_entry_for_slices(dev_priv, dbuf_slice_mask, &ddb_slices);
+ mbus_offset = mbus_ddb_offset(dev_priv, dbuf_slice_mask);
ddb_range_size = skl_ddb_entry_size(&ddb_slices);
intel_crtc_dbuf_weights(new_dbuf_state, pipe,
@@ -4174,11 +4190,11 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
start = ddb_range_size * weight_start / weight_total;
end = ddb_range_size * weight_end / weight_total;
- new_dbuf_state->ddb[pipe].start = ddb_slices.start + start;
- new_dbuf_state->ddb[pipe].end = ddb_slices.start + end;
-
+ new_dbuf_state->ddb[pipe].start = ddb_slices.start - mbus_offset + start;
+ new_dbuf_state->ddb[pipe].end = ddb_slices.start - mbus_offset + end;
out:
- if (skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe],
+ if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] &&
+ skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe],
&new_dbuf_state->ddb[pipe]))
return 0;
@@ -4190,7 +4206,12 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
if (IS_ERR(crtc_state))
return PTR_ERR(crtc_state);
- crtc_state->wm.skl.ddb = new_dbuf_state->ddb[pipe];
+ /*
+ * Used for checking overlaps, so we need absolute
+ * offsets instead of MBUS relative offsets.
+ */
+ crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start;
+ crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end;
drm_dbg_kms(&dev_priv->drm,
"[CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) -> (%d - %d), active pipes 0x%x -> 0x%x\n",
@@ -6412,6 +6433,7 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
enum pipe pipe = crtc->pipe;
+ unsigned int mbus_offset;
enum plane_id plane_id;
skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
@@ -6437,7 +6459,13 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state);
- crtc_state->wm.skl.ddb = dbuf_state->ddb[pipe];
+ /*
+ * Used for checking overlaps, so we need absolute
+ * offsets instead of MBUS relative offsets.
+ */
+ mbus_offset = mbus_ddb_offset(dev_priv, dbuf_state->slices[pipe]);
+ crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start;
+ crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end;
drm_dbg_kms(&dev_priv->drm,
"[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x\n",
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 39/56] drm/i915: Move intel_modeset_all_pipes()
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (37 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 38/56] drm/i915: Introduce MBUS relative dbuf offsets Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 40/56] drm/i915/adl_p: MBUS programming Matt Roper
` (19 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move intel_modeset_all_pipes() to a central place so that we can
use it elsewhere as well. No functional changes.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 38 --------------------
drivers/gpu/drm/i915/display/intel_display.c | 38 ++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_display.h | 1 +
3 files changed, 39 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c5fdf688fc89..42c462cae032 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2410,44 +2410,6 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
return 0;
}
-static int intel_modeset_all_pipes(struct intel_atomic_state *state)
-{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_crtc *crtc;
-
- /*
- * Add all pipes to the state, and force
- * a modeset on all the active ones.
- */
- for_each_intel_crtc(&dev_priv->drm, crtc) {
- struct intel_crtc_state *crtc_state;
- int ret;
-
- crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
- if (IS_ERR(crtc_state))
- return PTR_ERR(crtc_state);
-
- if (!crtc_state->hw.active ||
- drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
- continue;
-
- crtc_state->uapi.mode_changed = true;
-
- ret = drm_atomic_add_affected_connectors(&state->base,
- &crtc->base);
- if (ret)
- return ret;
-
- ret = intel_atomic_add_affected_planes(state, crtc);
- if (ret)
- return ret;
-
- crtc_state->update_planes |= crtc_state->active_planes;
- }
-
- return 0;
-}
-
static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
{
int min_cdclk;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0f8092cd3a2d..cbad75deadd0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9566,6 +9566,44 @@ intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
verify_disabled_dpll_state(dev_priv);
}
+int intel_modeset_all_pipes(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+
+ /*
+ * Add all pipes to the state, and force
+ * a modeset on all the active ones.
+ */
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ struct intel_crtc_state *crtc_state;
+ int ret;
+
+ crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
+ if (IS_ERR(crtc_state))
+ return PTR_ERR(crtc_state);
+
+ if (!crtc_state->hw.active ||
+ drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
+ continue;
+
+ crtc_state->uapi.mode_changed = true;
+
+ ret = drm_atomic_add_affected_connectors(&state->base,
+ &crtc->base);
+ if (ret)
+ return ret;
+
+ ret = intel_atomic_add_affected_planes(state, crtc);
+ if (ret)
+ return ret;
+
+ crtc_state->update_planes |= crtc_state->active_planes;
+ }
+
+ return 0;
+}
+
static void
intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
{
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 13d5d7909411..35e92747b7a9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -670,6 +670,7 @@ void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915);
void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915);
void intel_display_resume(struct drm_device *dev);
void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
+int intel_modeset_all_pipes(struct intel_atomic_state *state);
/* modesetting asserts */
void assert_panel_unlocked(struct drm_i915_private *dev_priv,
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 40/56] drm/i915/adl_p: MBUS programming
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (38 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 39/56] drm/i915: Move intel_modeset_all_pipes() Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 41/56] drm/i915/adl_p: Tx escape clock with DSI Matt Roper
` (18 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
Update MBUS_CTL register if the 2 mbus can be joined as per the current
DDB allocation and active pipes, also update hashing mode and pipe
select bits as per the sequence mentioned in the bspec.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 20 +++++
drivers/gpu/drm/i915/display/intel_atomic.h | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 3 +
drivers/gpu/drm/i915/i915_reg.h | 11 +++
drivers/gpu/drm/i915/intel_pm.c | 93 ++++++++++++++++++--
drivers/gpu/drm/i915/intel_pm.h | 2 +-
6 files changed, 121 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index d0b5414127df..580244abf62d 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -198,6 +198,26 @@ intel_connector_needs_modeset(struct intel_atomic_state *state,
new_conn_state->crtc)));
}
+/**
+ * intel_any_crtc_needs_modeset - check if any CRTC needs a modeset
+ * @state: the atomic state corresponding to this modeset
+ *
+ * Returns true if any CRTC in @state needs a modeset.
+ */
+bool intel_any_crtc_needs_modeset(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *crtc_state;
+ int i;
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ if (intel_crtc_needs_modeset(crtc_state))
+ return true;
+ }
+
+ return false;
+}
+
struct intel_digital_connector_state *
intel_atomic_get_digital_connector_state(struct intel_atomic_state *state,
struct intel_connector *connector)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
index 62a3365ed5e6..d2700c74c9da 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -35,6 +35,7 @@ struct drm_connector_state *
intel_digital_connector_duplicate_state(struct drm_connector *connector);
bool intel_connector_needs_modeset(struct intel_atomic_state *state,
struct drm_connector *connector);
+bool intel_any_crtc_needs_modeset(struct intel_atomic_state *state);
struct intel_digital_connector_state *
intel_atomic_get_digital_connector_state(struct intel_atomic_state *state,
struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index cbad75deadd0..d779c1c38a41 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10456,6 +10456,9 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
+ if (intel_any_crtc_needs_modeset(state))
+ any_ms = true;
+
if (any_ms) {
ret = intel_modeset_checks(state);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 70b097ddae28..a447f3882bd7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2929,6 +2929,15 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
+#define MBUS_CTL _MMIO(0x4438C)
+#define MBUS_JOIN REG_BIT(31)
+#define MBUS_HASHING_MODE_MASK REG_BIT(30)
+#define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
+#define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
+#define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26)
+#define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
+#define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7)
+
#define HDPORT_STATE _MMIO(0x45050)
#define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12)
#define HDPORT_DDI_USED(phy) REG_BIT(2 * (phy) + 1)
@@ -8136,6 +8145,8 @@ enum {
#define DBUF_POWER_STATE REG_BIT(30)
#define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19)
#define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
+#define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */
+#define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
#define GEN7_MSG_CTL _MMIO(0x45010)
#define WAIT_FOR_PCH_RESET_ACK (1 << 1)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e9a8fb1773f3..7fae920fa6ae 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4269,7 +4269,6 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
struct skl_ddb_entry *entry, u32 reg)
{
-
entry->start = reg & DDB_ENTRY_MASK;
entry->end = (reg >> DDB_ENTRY_END_SHIFT) & DDB_ENTRY_MASK;
@@ -4394,6 +4393,7 @@ skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
struct dbuf_slice_conf_entry {
u8 active_pipes;
u8 dbuf_mask[I915_MAX_PIPES];
+ bool join_mbus;
};
/*
@@ -4586,14 +4586,16 @@ static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = {
{
.active_pipes = BIT(PIPE_A),
.dbuf_mask = {
- [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4),
},
+ .join_mbus = true,
},
{
.active_pipes = BIT(PIPE_B),
.dbuf_mask = {
- [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4),
},
+ .join_mbus = true,
},
{
.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
@@ -4694,6 +4696,23 @@ static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = {
};
+static bool check_mbus_joined(u8 active_pipes,
+ const struct dbuf_slice_conf_entry *dbuf_slices)
+{
+ int i;
+
+ for (i = 0; i < dbuf_slices[i].active_pipes; i++) {
+ if (dbuf_slices[i].active_pipes == active_pipes)
+ return dbuf_slices[i].join_mbus;
+ }
+ return false;
+}
+
+static bool adlp_check_mbus_joined(u8 active_pipes)
+{
+ return check_mbus_joined(active_pipes, adlp_allowed_dbufs);
+}
+
static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes,
const struct dbuf_slice_conf_entry *dbuf_slices)
{
@@ -5967,16 +5986,29 @@ skl_compute_ddb(struct intel_atomic_state *state)
new_dbuf_state->enabled_slices = intel_dbuf_enabled_slices(new_dbuf_state);
- if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices) {
+ if (IS_ALDERLAKE_P(dev_priv))
+ new_dbuf_state->joined_mbus = adlp_check_mbus_joined(new_dbuf_state->active_pipes);
+
+ if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices ||
+ old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
if (ret)
return ret;
+ if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
+ /* TODO: Implement vblank synchronized MBUS joining changes */
+ ret = intel_modeset_all_pipes(state);
+ if (ret)
+ return ret;
+ }
+
drm_dbg_kms(&dev_priv->drm,
- "Enabled dbuf slices 0x%x -> 0x%x (out of %d dbuf slices)\n",
+ "Enabled dbuf slices 0x%x -> 0x%x (out of %d dbuf slices), mbus joined? %s->%s\n",
old_dbuf_state->enabled_slices,
new_dbuf_state->enabled_slices,
- INTEL_INFO(dev_priv)->num_supported_dbuf_slices);
+ INTEL_INFO(dev_priv)->num_supported_dbuf_slices,
+ yesno(old_dbuf_state->joined_mbus),
+ yesno(new_dbuf_state->joined_mbus));
}
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
@@ -6429,6 +6461,9 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
to_intel_dbuf_state(dev_priv->dbuf.obj.state);
struct intel_crtc *crtc;
+ if (IS_ALDERLAKE_P(dev_priv))
+ dbuf_state->joined_mbus = intel_de_read(dev_priv, MBUS_CTL) & MBUS_JOIN;
+
for_each_intel_crtc(&dev_priv->drm, crtc) {
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
@@ -6468,10 +6503,11 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end;
drm_dbg_kms(&dev_priv->drm,
- "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x\n",
+ "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x, mbus joined: %s\n",
crtc->base.base.id, crtc->base.name,
dbuf_state->slices[pipe], dbuf_state->ddb[pipe].start,
- dbuf_state->ddb[pipe].end, dbuf_state->active_pipes);
+ dbuf_state->ddb[pipe].end, dbuf_state->active_pipes,
+ yesno(dbuf_state->joined_mbus));
}
dbuf_state->enabled_slices = dev_priv->dbuf.enabled_slices;
@@ -7976,6 +8012,46 @@ int intel_dbuf_init(struct drm_i915_private *dev_priv)
return 0;
}
+/*
+ * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
+ * update the request state of all DBUS slices.
+ */
+static void update_mbus_pre_enable(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const int num_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
+ u32 mbus_ctl, dbuf_min_tracker_val;
+ enum dbuf_slice slice;
+ const struct intel_dbuf_state *dbuf_state =
+ intel_atomic_get_new_dbuf_state(state);
+
+ if (!IS_ALDERLAKE_P(dev_priv))
+ return;
+
+ /*
+ * TODO: Implement vblank synchronized MBUS joining changes.
+ * Must be properly coordinated with dbuf reprogramming.
+ */
+ if (dbuf_state->joined_mbus) {
+ mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
+ MBUS_JOIN_PIPE_SELECT_NONE;
+ dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
+ } else {
+ mbus_ctl = MBUS_HASHING_MODE_2x2 |
+ MBUS_JOIN_PIPE_SELECT_NONE;
+ dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
+ }
+
+ intel_de_rmw(dev_priv, MBUS_CTL,
+ MBUS_HASHING_MODE_MASK | MBUS_JOIN |
+ MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
+
+ for (slice = DBUF_S1; slice < (num_slices + DBUF_S1); slice++)
+ intel_de_rmw(dev_priv, DBUF_CTL_S(slice),
+ DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
+ dbuf_min_tracker_val);
+}
+
void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
@@ -7990,6 +8066,7 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
+ update_mbus_pre_enable(state);
gen9_dbuf_slices_update(dev_priv,
old_dbuf_state->enabled_slices |
new_dbuf_state->enabled_slices);
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 669c8d505677..bac72c859a84 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -78,9 +78,9 @@ struct intel_dbuf_state {
struct skl_ddb_entry ddb[I915_MAX_PIPES];
unsigned int weight[I915_MAX_PIPES];
u8 slices[I915_MAX_PIPES];
-
u8 enabled_slices;
u8 active_pipes;
+ bool joined_mbus;
};
int intel_dbuf_init(struct drm_i915_private *dev_priv);
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 41/56] drm/i915/adl_p: Tx escape clock with DSI
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (39 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 40/56] drm/i915/adl_p: MBUS programming Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 42/56] drm/i915/adl_p: Add initial ADL_P Workarounds Matt Roper
` (17 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: Mika Kahola <mika.kahola@intel.com>
Today when the DSI controller is paired with the Combo-PHY it
uses the high-speed (HS) Word clock for its low power (LP)
transmit PPI communication to the DPHY. The interface signaling
only changes state at an Escape clock frequency (i.e. its
effectively running on a virtual Tx Escape clock that is controlled
by counters w/in the controller), but all the interface flops are
running off the HS clock.
This has the following drawbacks:
* It is a deviation from the PPI spec which assumes signaling is
running on a physical Escape clock
* The PV timings are over constrained (HS timed to 312.5MHz vs.
an Escape clock of 20MHz max)
This feature is proposing to change the LP Tx communication between
the controller and the DPHY from a virtual Tx Escape clock to a physical
clock.
To do this we need to program two "M" divisors. One for the usual
DSI_ESC_CLK_DIV and DPHY_ESC_CLK_DIV register and one for MIPIO_DWORD8.
For DSI_ESC_CLK_DIV and DPHY_ESC_CLK_DIV registers the "M" is calculated
as following
Nt = ceil(f_link/160) (theoretical word clock)
Nact = max[3, Nt + (Nt + 1)%2] (actual word clock)
M = Nact * 8
For MIPIO_DWORD8 register, the divisor "M" is calculated as following
M = (Nact - 1)/2
BSpec: 55171
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 21 +++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 37e2d93d064c..957bef1f8dba 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -361,10 +361,19 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
int afe_clk_khz;
- u32 esc_clk_div_m;
+ int theo_word_clk, act_word_clk;
+ u32 esc_clk_div_m, esc_clk_div_m_phy;
afe_clk_khz = afe_clk(encoder, crtc_state);
- esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
+
+ if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
+ theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK);
+ act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2);
+ esc_clk_div_m = act_word_clk * 8;
+ esc_clk_div_m_phy = (act_word_clk - 1)/2;
+ } else {
+ esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
+ }
for_each_dsi_port(port, intel_dsi->ports) {
intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port),
@@ -377,6 +386,14 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port));
}
+
+ if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
+ for_each_dsi_port(port, intel_dsi->ports) {
+ intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8),
+ esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY);
+ intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8));
+ }
+ }
}
static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a447f3882bd7..0adde69a60f4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11305,6 +11305,12 @@ enum skl_power_gate {
#define ICL_ESC_CLK_DIV_SHIFT 0
#define DSI_MAX_ESC_CLK 20000 /* in KHz */
+#define _ADL_MIPIO_REG 0x180
+#define ADL_MIPIO_DW(port, dw) _MMIO(_ICL_COMBOPHY(port) + _ADL_MIPIO_REG + 4 * (dw))
+#define TX_ESC_CLK_DIV_PHY_SEL REGBIT(16)
+#define TX_ESC_CLK_DIV_PHY_MASK REG_GENMASK(23, 16)
+#define TX_ESC_CLK_DIV_PHY REG_FIELD_PREP(TX_ESC_CLK_DIV_PHY_MASK, 0x7f)
+
#define _DSI_CMD_FRMCTL_0 0x6b034
#define _DSI_CMD_FRMCTL_1 0x6b834
#define DSI_CMD_FRMCTL(port) _MMIO_PORT(port, \
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 42/56] drm/i915/adl_p: Add initial ADL_P Workarounds
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (40 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 41/56] drm/i915/adl_p: Tx escape clock with DSI Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 43/56] drm/i915/adlp: Define GuC/HuC for Alderlake_P Matt Roper
` (16 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
Most of the context WA are already implemented for previous platforms.
Adding adl_p platform tag to reflect so.
BSpec: 54369
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 59 +++++++++++--------
drivers/gpu/drm/i915/intel_pm.c | 8 ++-
4 files changed, 43 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 2e08fbbab942..8c41f82bbdc1 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2650,7 +2650,7 @@ ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
{
return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER)) ||
- IS_TIGERLAKE(i915)) &&
+ IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
i915->dpll.ref_clks.nssc == 38400;
}
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index cac80af7ad1c..d179fe5a808f 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -208,7 +208,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
flags |= PIPE_CONTROL_FLUSH_L3;
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
- /* Wa_1409600907:tgl */
+ /* Wa_1409600907:tgl,adl_p */
flags |= PIPE_CONTROL_DEPTH_STALL;
flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
flags |= PIPE_CONTROL_FLUSH_ENABLE;
@@ -626,7 +626,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
PIPE_CONTROL_FLUSH_L3 |
PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- /* Wa_1409600907:tgl */
+ /* Wa_1409600907:tgl,adl_p */
PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_DC_FLUSH_ENABLE |
PIPE_CONTROL_FLUSH_ENABLE);
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3b4a7da60f0b..b4647f63ede5 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -650,15 +650,16 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
/*
- * Wa_1409142259:tgl
- * Wa_1409347922:tgl
- * Wa_1409252684:tgl
- * Wa_1409217633:tgl
- * Wa_1409207793:tgl
- * Wa_1409178076:tgl
- * Wa_1408979724:tgl
- * Wa_14010443199:rkl
- * Wa_14010698770:rkl
+ * Wa_1409142259:tgl, adl_p
+ * Wa_1409347922:tgl, adl_p
+ * Wa_1409252684:tgl, adl_p
+ * Wa_1409217633:tgl, adl_p
+ * Wa_1409207793:tgl, adl_p
+ * Wa_1409178076:tgl, adl_p
+ * Wa_1408979724:tgl, adl_p
+ * Wa_14010443199:rkl, adl_p
+ * Wa_14010698770:rkl, adl_p
+ * Wa_1409342910: adl_p
*/
wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
@@ -1644,31 +1645,32 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/* Wa_1606931601:tgl,rkl,dg1,adl-s */
wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
+ }
+
+ if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
+ IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+ /*
+ * Wa_1606700617:tgl,dg1,adlp
+ * Wa_22010271021:tgl,rkl,dg1,adls,adlp
+ * Wa_14010826681: tgl,dg1
+ */
+ wa_masked_en(wal,
+ GEN9_CS_DEBUG_MODE1,
+ FF_DOP_CLOCK_GATE_DISABLE);
/*
* Wa_1407928979:tgl A*
* Wa_18011464164:tgl[B0+],dg1[B0+]
* Wa_22010931296:tgl[B0+],dg1[B0+]
- * Wa_14010919138:rkl,dg1,adl-s
+ * Wa_14010919138:rkl,dg1,adl-s,adl-p
*/
wa_write_or(wal, GEN7_FF_THREAD_MODE,
GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
-
- /*
- * Wa_1606700617:tgl,dg1
- * Wa_22010271021:tgl,rkl,dg1, adl-s
- */
- wa_masked_en(wal,
- GEN9_CS_DEBUG_MODE1,
- FF_DOP_CLOCK_GATE_DISABLE);
}
- if (IS_ALDERLAKE_S(i915) || IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+ if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
+ IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
- /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s */
- wa_masked_en(wal, GEN7_ROW_CHICKEN2,
- GEN12_PUSH_CONST_DEREF_HOLD_DIS);
-
/*
* Wa_1409085225:tgl
* Wa_14010229206:tgl,rkl,dg1[a0],adl-s
@@ -1682,7 +1684,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
/*
* Wa_1607030317:tgl
* Wa_1607186500:tgl
- * Wa_1607297627:tgl,rkl,dg1[a0]
+ * Wa_1607297627:tgl,rkl,dg1[a0],adl-p
*
* On TGL and RKL there are multiple entries for this WA in the
* BSpec; some indicate this is an A0-only WA, others indicate
@@ -1695,6 +1697,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN8_RC_SEMA_IDLE_MSG_DISABLE);
}
+
if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/* Wa_1406941453:tgl,rkl,dg1 */
wa_masked_en(wal,
@@ -1702,6 +1705,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
ENABLE_SMALLPL);
}
+ if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
+ IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+ IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+ /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
+ wa_masked_en(wal, GEN7_ROW_CHICKEN2,
+ GEN12_PUSH_CONST_DEREF_HOLD_DIS);
+ }
+
if (IS_GEN(i915, 11)) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7fae920fa6ae..486086086205 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7348,15 +7348,17 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
{
/* Wa_1409120013:tgl,rkl,adl_s,dg1 */
- intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
- ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
+ if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
+ IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv))
+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
+ ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
/* Wa_1409825376:tgl (pre-prod)*/
if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B1))
intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
TGL_VRH_GATING_DIS);
- /* Wa_14011059788:tgl,rkl,adl_s,dg1 */
+ /* Wa_14011059788:tgl,rkl,adl_s,dg1,adl_p */
intel_uncore_rmw(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
0, DFR_DISABLE);
}
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 43/56] drm/i915/adlp: Define GuC/HuC for Alderlake_P
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (41 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 42/56] drm/i915/adl_p: Add initial ADL_P Workarounds Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 44/56] drm/i915/adl_p: Define and use ADL-P specific DP translation tables Matt Roper
` (15 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: Clint Taylor <clinton.a.taylor@intel.com>
Initial GuC/HuC definitions for ADL_P
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 984fa79e0fa7..95cdac785412 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -48,6 +48,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
* firmware as TGL.
*/
#define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
+ fw_def(ALDERLAKE_P, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \
fw_def(ALDERLAKE_S, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \
fw_def(ROCKETLAKE, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \
fw_def(TIGERLAKE, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 44/56] drm/i915/adl_p: Define and use ADL-P specific DP translation tables
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (42 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 43/56] drm/i915/adlp: Define GuC/HuC for Alderlake_P Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 45/56] drm/i915/adl_p: Enable/disable loadgen sharing Matt Roper
` (14 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: Mika Kahola <mika.kahola@intel.com>
Define and use DP voltage swing and pre-emphasis translation tables
for ADL-P.
BSpec: 54956
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++-
.../drm/i915/display/intel_ddi_buf_trans.c | 34 +++++++++++++++++++
.../drm/i915/display/intel_ddi_buf_trans.h | 4 +++
3 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index f404547bb95a..7a2a5c92899b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -975,6 +975,8 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
if (DISPLAY_VER(dev_priv) >= 12) {
if (intel_phy_is_combo(dev_priv, phy))
tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
+ else if (IS_ALDERLAKE_P(dev_priv))
+ adlp_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
else
tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
} else if (DISPLAY_VER(dev_priv) == 11) {
@@ -1421,7 +1423,10 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
return;
- ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
+ if (IS_ALDERLAKE_P(dev_priv))
+ ddi_translations = adlp_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
+ else
+ ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
return;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 50746e2725e8..11b5903dca67 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -734,6 +734,20 @@ static const struct cnl_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr
{ 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
};
+static const struct tgl_dkl_phy_ddi_buf_trans adlp_dkl_phy_dp_ddi_trans[] = {
+ /* VS pre-emp Non-trans mV Pre-emph dB */
+ { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */
+ { 0x5, 0x0, 0x03 }, /* 0 1 400mV 3.5 dB */
+ { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */
+ { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */
+ { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */
+ { 0x2, 0x0, 0x03 }, /* 1 1 600mV 3.5 dB */
+ { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */
+ { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */
+ { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */
+ { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB */
+};
+
bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table)
{
return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
@@ -1347,6 +1361,26 @@ tgl_get_dkl_buf_trans(struct intel_encoder *encoder,
return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
}
+static const struct tgl_dkl_phy_ddi_buf_trans *
+adlp_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries)
+{
+ *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
+ return adlp_dkl_phy_dp_ddi_trans;
+}
+
+const struct tgl_dkl_phy_ddi_buf_trans *
+adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries)
+{
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, n_entries);
+ else
+ return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
+}
+
int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *default_entry)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
index f8f0ef87e977..4c2efab38642 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
@@ -67,6 +67,10 @@ bxt_get_buf_trans(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries);
+const struct tgl_dkl_phy_ddi_buf_trans *
+adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries);
const struct cnl_ddi_buf_trans *
tgl_get_combo_buf_trans(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 45/56] drm/i915/adl_p: Enable/disable loadgen sharing
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (43 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 44/56] drm/i915/adl_p: Define and use ADL-P specific DP translation tables Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 46/56] drm/i915/adl_p: Add PLL Support Matt Roper
` (13 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: Mika Kahola <mika.kahola@intel.com>
Disable loadgen sharing for DP link rate 1.62 GHz and HDMI 5.94 GHz.
For all other modes, we can enable loadgen sharing feature.
BSpec: 55359
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7a2a5c92899b..f97d6c488fcd 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1460,6 +1460,14 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
val &= ~DKL_TX_DP20BITMODE;
intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
+
+ if ((intel_crtc_has_dp_encoder(crtc_state) &&
+ crtc_state->port_clock == 162000) ||
+ (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
+ crtc_state->port_clock == 594000))
+ val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
+ else
+ val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0adde69a60f4..275fd4b5c549 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10866,6 +10866,7 @@ enum skl_power_gate {
_DKL_TX_DPCNTL1)
#define _DKL_TX_DPCNTL2 0x2C8
+#define DKL_TX_LOADGEN_SHARING_PMD_DISABLE REG_BIT(12)
#define DKL_TX_DP20BITMODE (1 << 2)
#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
_DKL_PHY1_BASE, \
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 46/56] drm/i915/adl_p: Add PLL Support
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (44 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 45/56] drm/i915/adl_p: Enable/disable loadgen sharing Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 47/56] drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner Matt Roper
` (12 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
The clocks in ALD_P is similar to that of TGL.
The combo PLLs use the same DPLL0, DPLL1 and TBT_PLL.
This patch adds the helper function intel_mg_pll_enable_reg()
which is similar to intel_combo_pll_enable_reg() for being lookup
place for PLL_ENABLE register in combo phy cases.
Bspec: 55409,55316
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 69 ++++++++++++++-----
drivers/gpu/drm/i915/i915_reg.h | 8 +++
2 files changed, 60 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 8c41f82bbdc1..b5543cbe1e6c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -147,6 +147,16 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
pll->info->name, onoff(state), onoff(cur_state));
}
+static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
+{
+ return TC_PORT_1 + id - DPLL_ID_ICL_MGPLL1;
+}
+
+enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
+{
+ return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1;
+}
+
static i915_reg_t
intel_combo_pll_enable_reg(struct drm_i915_private *i915,
struct intel_shared_dpll *pll)
@@ -159,6 +169,19 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915,
return CNL_DPLL_ENABLE(pll->info->id);
}
+static i915_reg_t
+intel_tc_pll_enable_reg(struct drm_i915_private *i915,
+ struct intel_shared_dpll *pll)
+{
+ const enum intel_dpll_id id = pll->info->id;
+ enum tc_port tc_port = icl_pll_id_to_tc_port(id);
+
+ if (IS_ALDERLAKE_P(i915))
+ return ADLP_PORTTC_PLL_ENABLE(tc_port);
+
+ return MG_PLL_ENABLE(tc_port);
+}
+
/**
* intel_prepare_shared_dpll - call a dpll's prepare hook
* @crtc_state: CRTC, and its state, which has a shared dpll
@@ -3118,16 +3141,6 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
pll_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
}
-static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
-{
- return id - DPLL_ID_ICL_MGPLL1;
-}
-
-enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
-{
- return tc_port + DPLL_ID_ICL_MGPLL1;
-}
-
static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
u32 *target_dco_khz,
struct intel_dpll_hw_state *state,
@@ -3726,12 +3739,14 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
bool ret = false;
u32 val;
+ i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll);
+
wakeref = intel_display_power_get_if_enabled(dev_priv,
POWER_DOMAIN_DISPLAY_CORE);
if (!wakeref)
return false;
- val = intel_de_read(dev_priv, MG_PLL_ENABLE(tc_port));
+ val = intel_de_read(dev_priv, enable_reg);
if (!(val & PLL_ENABLE))
goto out;
@@ -3795,7 +3810,7 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv,
if (!wakeref)
return false;
- val = intel_de_read(dev_priv, MG_PLL_ENABLE(tc_port));
+ val = intel_de_read(dev_priv, intel_tc_pll_enable_reg(dev_priv, pll));
if (!(val & PLL_ENABLE))
goto out;
@@ -4167,8 +4182,7 @@ static void tbt_pll_enable(struct drm_i915_private *dev_priv,
static void mg_pll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg =
- MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
+ i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll);
icl_pll_power_enable(dev_priv, pll, enable_reg);
@@ -4247,8 +4261,7 @@ static void tbt_pll_disable(struct drm_i915_private *dev_priv,
static void mg_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg =
- MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
+ i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll);
icl_pll_disable(dev_priv, pll, enable_reg);
}
@@ -4414,6 +4427,26 @@ static const struct intel_dpll_mgr adls_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct dpll_info adlp_plls[] = {
+ { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+ { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+ { "TBT PLL", &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
+ { "TC PLL 1", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
+ { "TC PLL 2", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
+ { "TC PLL 3", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
+ { "TC PLL 4", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
+ { },
+};
+
+static const struct intel_dpll_mgr adlp_pll_mgr = {
+ .dpll_info = adlp_plls,
+ .get_dplls = icl_get_dplls,
+ .put_dplls = icl_put_dplls,
+ .update_active_dpll = icl_update_active_dpll,
+ .update_ref_clks = icl_update_dpll_ref_clks,
+ .dump_hw_state = icl_dump_hw_state,
+};
+
/**
* intel_shared_dpll_init - Initialize shared DPLLs
* @dev: drm device
@@ -4427,7 +4460,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (IS_ALDERLAKE_S(dev_priv))
+ if (IS_ALDERLAKE_P(dev_priv))
+ dpll_mgr = &adlp_pll_mgr;
+ else if (IS_ALDERLAKE_S(dev_priv))
dpll_mgr = &adls_pll_mgr;
else if (IS_DG1(dev_priv))
dpll_mgr = &dg1_pll_mgr;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 275fd4b5c549..0422593a93d3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10518,6 +10518,14 @@ enum skl_power_gate {
#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
_MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
+/* ADL-P Type C PLL */
+#define PORTTC1_PLL_ENABLE 0x46038
+#define PORTTC2_PLL_ENABLE 0x46040
+
+#define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \
+ PORTTC1_PLL_ENABLE, \
+ PORTTC2_PLL_ENABLE)
+
#define _MG_REFCLKIN_CTL_PORT1 0x16892C
#define _MG_REFCLKIN_CTL_PORT2 0x16992C
#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 47/56] drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (45 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 46/56] drm/i915/adl_p: Add PLL Support Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 48/56] drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner Matt Roper
` (11 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: Animesh Manna <animesh.manna@intel.com>
No need for checking dsc flag for uncompressed pipe joiner mode
validation.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5dc1b49cbb67..1641ed91f78c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -864,8 +864,11 @@ intel_dp_mode_valid(struct drm_connector *connector,
dsc = dsc_max_output_bpp && dsc_slice_count;
}
- /* big joiner configuration needs DSC */
- if (bigjoiner && !dsc)
+ /*
+ * Big joiner configuration needs DSC for TGL which is not true for
+ * ADLP where uncompressed joiner is supported.
+ */
+ if (!(DISPLAY_VER(dev_priv) == 13) && bigjoiner && !dsc)
return MODE_CLOCK_HIGH;
if (mode_rate > max_rate && !dsc)
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 48/56] drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (46 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 47/56] drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 49/56] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner Matt Roper
` (10 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: Animesh Manna <animesh.manna@intel.com>
For uncompressed big joiner DSC engine will not be used so will avoid
compute config of DSC.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 1641ed91f78c..b3820e19aac1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1498,9 +1498,13 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
/* Optimize for slow and wide. */
ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
- /* enable compression if the mode doesn't fit available BW */
+ /*
+ * Pipe joiner needs compression upto display12 due to BW limitation. DG2
+ * onwards pipe joiner can be enabled without compression.
+ */
drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
- if (ret || intel_dp->force_dsc_en || pipe_config->bigjoiner) {
+ if (ret || intel_dp->force_dsc_en || (!(DISPLAY_VER(i915) == 13) &&
+ pipe_config->bigjoiner)) {
ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
conn_state, &limits);
if (ret < 0)
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 49/56] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (47 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 48/56] drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 50/56] drm/i915/adlp: Add PIPE_MISC2 programming Matt Roper
` (9 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: Animesh Manna <animesh.manna@intel.com>
Respective bit for master or slave to be set for uncompressed
bigjoiner in dss_ctl1 register.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++
drivers/gpu/drm/i915/display/intel_vdsc.c | 40 +++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_vdsc.h | 2 +
drivers/gpu/drm/i915/i915_reg.h | 2 +
4 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d779c1c38a41..077f1100efa1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3904,6 +3904,7 @@ static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(master->base.dev);
struct intel_crtc_state *master_crtc_state;
struct drm_connector_state *conn_state;
struct drm_connector *conn;
@@ -3937,6 +3938,9 @@ static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
/* and DSC on slave */
intel_dsc_enable(NULL, crtc_state);
}
+
+ if (DISPLAY_VER(dev_priv) == 13)
+ intel_uncompressed_joiner_enable(crtc_state);
}
static void hsw_crtc_enable(struct intel_atomic_state *state,
@@ -6753,6 +6757,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
}
intel_dsc_get_config(pipe_config);
+ if ((DISPLAY_VER(dev_priv) == 13) && !pipe_config->dsc.compression_enable)
+ intel_uncompressed_joiner_get_config(pipe_config);
if (!active) {
/* bigjoiner slave doesn't enable transcoder */
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 28bd32bc74ba..3e0ef7c2e076 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -1126,6 +1126,22 @@ static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state)
return ICL_PIPE_DSS_CTL2(pipe);
}
+void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 dss_ctl1_val = 0;
+
+ if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) {
+ if (crtc_state->bigjoiner_slave)
+ dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE;
+ else
+ dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER;
+
+ intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val);
+ }
+}
+
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -1165,13 +1181,35 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- if (!old_crtc_state->dsc.compression_enable)
+ if (!(old_crtc_state->dsc.compression_enable &&
+ old_crtc_state->bigjoiner))
return;
intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
}
+void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 dss_ctl1;
+
+ dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
+ if (dss_ctl1 & UNCOMPRESSED_JOINER_MASTER) {
+ crtc_state->bigjoiner = true;
+ if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
+ crtc_state->bigjoiner_linked_crtc =
+ intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
+ } else if (dss_ctl1 & UNCOMPRESSED_JOINER_SLAVE) {
+ crtc_state->bigjoiner = true;
+ crtc_state->bigjoiner_slave = true;
+ if (!WARN_ON(crtc->pipe == PIPE_A))
+ crtc_state->bigjoiner_linked_crtc =
+ intel_get_crtc_for_pipe(dev_priv, crtc->pipe - 1);
+ }
+}
+
void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
{
struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index 65d301c23580..fe4d45561253 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -12,11 +12,13 @@ struct intel_encoder;
struct intel_crtc_state;
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state);
+void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state);
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
int intel_dsc_compute_params(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
+void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state);
void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
enum intel_display_power_domain
intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0422593a93d3..2ff740993d3d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11542,6 +11542,8 @@ enum skl_power_gate {
#define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
#define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
#define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
+#define UNCOMPRESSED_JOINER_MASTER (1 << 21)
+#define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
#define _ICL_PIPE_DSS_CTL2_PB 0x78204
#define _ICL_PIPE_DSS_CTL2_PC 0x78404
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 50/56] drm/i915/adlp: Add PIPE_MISC2 programming
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (48 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 49/56] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 51/56] drm/i915/adl_p: Update memory bandwidth parameters Matt Roper
` (8 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
When scalers are enabled, we need to program underrun
bubble counter to 0x50 to avoid Soft Pipe A underruns.
Make sure other bits dont get overwritten.
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
2 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 077f1100efa1..3883c6dee774 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6217,8 +6217,12 @@ static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ const struct intel_crtc_scaler_state *scaler_state =
+ &crtc_state->scaler_state;
+
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 val = 0;
+ int i;
switch (crtc_state->pipe_bpp) {
case 18:
@@ -6257,6 +6261,23 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
if (DISPLAY_VER(dev_priv) >= 12)
val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ bool scaler_in_use = false;
+
+ for (i = 0; i < crtc->num_scalers; i++) {
+ if (!scaler_state->scalers[i].in_use)
+ continue;
+
+ scaler_in_use = true;
+ break;
+ }
+
+ intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe),
+ PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK,
+ scaler_in_use ? PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN :
+ PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS);
+ }
+
intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2ff740993d3d..2d6cd5baf090 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6144,6 +6144,13 @@ enum {
#define PIPEMISC_DITHER_TYPE_SP (0 << 2)
#define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
+#define _PIPE_MISC2_A 0x7002C
+#define _PIPE_MISC2_B 0x7102C
+#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN (0x50 << 24)
+#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS (0x14 << 24)
+#define PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK (0xff << 24)
+#define PIPE_MISC2(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC2_A)
+
/* Skylake+ pipe bottom (background) color */
#define _SKL_BOTTOM_COLOR_A 0x70034
#define SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31)
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 51/56] drm/i915/adl_p: Update memory bandwidth parameters
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (49 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 50/56] drm/i915/adlp: Add PIPE_MISC2 programming Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 52/56] drm/i915/adl_p: Implement Wa_22011091694 Matt Roper
` (7 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
ADL_P has same memory characteristics as ADL_S platform.
Bspec: 64631
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 23cf9bf31e41..3338afa047d5 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -267,7 +267,7 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_ALDERLAKE_S(dev_priv))
+ if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
icl_get_bw_info(dev_priv, &adls_sa_info);
else if (IS_ROCKETLAKE(dev_priv))
icl_get_bw_info(dev_priv, &rkl_sa_info);
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 52/56] drm/i915/adl_p: Implement Wa_22011091694
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (50 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 51/56] drm/i915/adl_p: Update memory bandwidth parameters Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 53/56] drm/i915/display/adl_p: Implement Wa_22011320316 Matt Roper
` (6 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
Adding a new hook to ADL-P just to avoid another platform check in
gen12lp_init_clock_gating() but also open to it.
BSpec: 54369
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 12 +++++++++++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2d6cd5baf090..d48a9dec8476 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4168,6 +4168,9 @@ enum {
#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
#define BXT_GMBUS_GATING_DIS (1 << 14)
+#define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)
+#define DPCE_GATING_DIS REG_BIT(17)
+
#define _CLKGATE_DIS_PSL_A 0x46520
#define _CLKGATE_DIS_PSL_B 0x46524
#define _CLKGATE_DIS_PSL_C 0x46528
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 486086086205..a6e6ad1434d7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7363,6 +7363,14 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
0, DFR_DISABLE);
}
+static void adlp_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+ gen12lp_init_clock_gating(dev_priv);
+
+ /* Wa_22011091694:adlp */
+ intel_de_rmw(dev_priv, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
+}
+
static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
{
gen12lp_init_clock_gating(dev_priv);
@@ -7826,7 +7834,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_DG1(dev_priv))
+ if (IS_ALDERLAKE_P(dev_priv))
+ dev_priv->display.init_clock_gating = adlp_init_clock_gating;
+ else if (IS_DG1(dev_priv))
dev_priv->display.init_clock_gating = dg1_init_clock_gating;
else if (IS_GEN(dev_priv, 12))
dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
--
2.25.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 53/56] drm/i915/display/adl_p: Implement Wa_22011320316
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (51 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 52/56] drm/i915/adl_p: Implement Wa_22011091694 Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-11 22:36 ` [Intel-gfx] [PATCH 54/56] drm/i915/display/adl_p: Remove CCS support Matt Roper
` (5 subsequent siblings)
58 siblings, 0 replies; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
Implementation details are in the HSD 22011320316, requiring CD clock
to be at least 307MHz to make DC states to work.
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 21 ++++++++++++++++++++-
drivers/gpu/drm/i915/i915_drv.h | 7 +++++++
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 42c462cae032..09e55ae3c471 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1257,6 +1257,21 @@ static const struct intel_cdclk_vals rkl_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
+ { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
+ { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
+ { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
+
+ { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
+ { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
+ { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
+
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+ {}
+};
+
static const struct intel_cdclk_vals adlp_cdclk_table[] = {
{ .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
{ .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
@@ -2836,7 +2851,11 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
- dev_priv->cdclk.table = adlp_cdclk_table;
+ /* Wa_22011320316:adlp[a0] */
+ if (IS_ADLP_REVID(dev_priv, ADLP_REVID_A0, ADLP_REVID_A0))
+ dev_priv->cdclk.table = adlp_a_step_cdclk_table;
+ else
+ dev_priv->cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
dev_priv->display.set_cdclk = bxt_set_cdclk;
dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 10b99f9e380b..6ab27566b570 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1612,6 +1612,13 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
tgl_stepping_get(p)->gt_stepping >= (since) && \
tgl_stepping_get(p)->gt_stepping <= (until))
+#define ADLP_REVID_A0 0x0
+#define ADLP_REVID_B0 0x4
+#define ADLP_REVID_C0 0x8
+
+#define IS_ADLP_REVID(p, since, until) \
+ (IS_ALDERLAKE_P(p) && IS_REVID(p, since, until))
+
#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
--
2.25.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Intel-gfx] [PATCH 54/56] drm/i915/display/adl_p: Remove CCS support
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (52 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 53/56] drm/i915/display/adl_p: Implement Wa_22011320316 Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-13 0:24 ` Srivatsa, Anusha
2021-03-11 22:36 ` [Intel-gfx] [PATCH 55/56] drm/i915/perf: Enable OA formats for ADL_P Matt Roper
` (4 subsequent siblings)
58 siblings, 1 reply; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx; +Cc: Juha-Pekka Heikkilä
From: José Roberto de Souza <jose.souza@intel.com>
Buffer compression is not usable in A stepping.
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Clinton A Taylor <clinton.a.taylor@intel.com>
Cc: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
.../drm/i915/display/skl_universal_plane.c | 20 ++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index cc36917b459c..cdd61c11b9bb 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -197,6 +197,13 @@ static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
DRM_FORMAT_MOD_INVALID
};
+static const u64 adlp_step_a_plane_format_modifiers[] = {
+ I915_FORMAT_MOD_Y_TILED,
+ I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
{
switch (format) {
@@ -1885,6 +1892,10 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
return false;
+ /* Wa_22011186057 */
+ if (IS_ADLP_REVID(dev_priv, ADLP_REVID_A0, ADLP_REVID_A0))
+ return false;
+
return plane_id < PLANE_SPRITE4;
}
@@ -1902,8 +1913,12 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
+ break;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ /* Wa_22011186057 */
+ if (IS_ADLP_REVID(dev_priv, ADLP_REVID_A0, ADLP_REVID_A0))
+ return false;
break;
default:
return false;
@@ -1958,7 +1973,10 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
enum plane_id plane_id)
{
- if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
+ /* Wa_22011186057 */
+ if (IS_ADLP_REVID(dev_priv, ADLP_REVID_A0, ADLP_REVID_A0))
+ return adlp_step_a_plane_format_modifiers;
+ else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
return gen12_plane_format_modifiers_mc_ccs;
else
return gen12_plane_format_modifiers_rc_ccs;
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Intel-gfx] [PATCH 54/56] drm/i915/display/adl_p: Remove CCS support
2021-03-11 22:36 ` [Intel-gfx] [PATCH 54/56] drm/i915/display/adl_p: Remove CCS support Matt Roper
@ 2021-03-13 0:24 ` Srivatsa, Anusha
0 siblings, 0 replies; 74+ messages in thread
From: Srivatsa, Anusha @ 2021-03-13 0:24 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx; +Cc: Heikkila, Juha-pekka
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Thursday, March 11, 2021 2:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Souza, Jose <jose.souza@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; Srivatsa, Anusha
> <anusha.srivatsa@intel.com>; Taylor, Clinton A
> <clinton.a.taylor@intel.com>; Heikkila, Juha-pekka <juha-
> pekka.heikkila@intel.com>; Taylor, Clinton A <clinton.a.taylor@intel.com>
> Subject: [PATCH 54/56] drm/i915/display/adl_p: Remove CCS support
>
> From: José Roberto de Souza <jose.souza@intel.com>
>
> Buffer compression is not usable in A stepping.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Clinton A Taylor <clinton.a.taylor@intel.com>
> Cc: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> .../drm/i915/display/skl_universal_plane.c | 20 ++++++++++++++++++-
> 1 file changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index cc36917b459c..cdd61c11b9bb 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -197,6 +197,13 @@ static const u64
> gen12_plane_format_modifiers_rc_ccs[] = {
> DRM_FORMAT_MOD_INVALID
> };
>
> +static const u64 adlp_step_a_plane_format_modifiers[] = {
> + I915_FORMAT_MOD_Y_TILED,
> + I915_FORMAT_MOD_X_TILED,
> + DRM_FORMAT_MOD_LINEAR,
> + DRM_FORMAT_MOD_INVALID
> +};
> +
> int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) {
> switch (format) {
> @@ -1885,6 +1892,10 @@ static bool gen12_plane_supports_mc_ccs(struct
> drm_i915_private *dev_priv,
> IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
> return false;
>
> + /* Wa_22011186057 */
> + if (IS_ADLP_REVID(dev_priv, ADLP_REVID_A0, ADLP_REVID_A0))
> + return false;
> +
> return plane_id < PLANE_SPRITE4;
> }
>
> @@ -1902,8 +1913,12 @@ static bool
> gen12_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_MOD_LINEAR:
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> + break;
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> + /* Wa_22011186057 */
> + if (IS_ADLP_REVID(dev_priv, ADLP_REVID_A0,
> ADLP_REVID_A0))
> + return false;
> break;
> default:
> return false;
> @@ -1958,7 +1973,10 @@ static bool
> gen12_plane_format_mod_supported(struct drm_plane *_plane, static
> const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
> enum plane_id plane_id)
> {
> - if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
> + /* Wa_22011186057 */
> + if (IS_ADLP_REVID(dev_priv, ADLP_REVID_A0, ADLP_REVID_A0))
> + return adlp_step_a_plane_format_modifiers;
> + else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
> return gen12_plane_format_modifiers_mc_ccs;
> else
> return gen12_plane_format_modifiers_rc_ccs;
> --
> 2.25.4
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^ permalink raw reply [flat|nested] 74+ messages in thread
* [Intel-gfx] [PATCH 55/56] drm/i915/perf: Enable OA formats for ADL_P
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (53 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 54/56] drm/i915/display/adl_p: Remove CCS support Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-12 20:37 ` Dixit, Ashutosh
2021-03-11 22:36 ` [Intel-gfx] [PATCH 56/56] drm/i915/display/adl_p: Implement PSR changes Matt Roper
` (3 subsequent siblings)
58 siblings, 1 reply; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Enable relevant OA formats for ADL_P.
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index c15bead2dac7..e52b54ff0999 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4291,6 +4291,7 @@ static void oa_init_supported_formats(struct i915_perf *perf)
case INTEL_ROCKETLAKE:
case INTEL_DG1:
case INTEL_ALDERLAKE_S:
+ case INTEL_ALDERLAKE_P:
oa_format_add(perf, I915_OA_FORMAT_A12);
oa_format_add(perf, I915_OA_FORMAT_A12_B8_C8);
oa_format_add(perf, I915_OA_FORMAT_A32u40_A4u32_B8_C8);
--
2.25.4
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^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Intel-gfx] [PATCH 55/56] drm/i915/perf: Enable OA formats for ADL_P
2021-03-11 22:36 ` [Intel-gfx] [PATCH 55/56] drm/i915/perf: Enable OA formats for ADL_P Matt Roper
@ 2021-03-12 20:37 ` Dixit, Ashutosh
0 siblings, 0 replies; 74+ messages in thread
From: Dixit, Ashutosh @ 2021-03-12 20:37 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Thu, 11 Mar 2021 14:36:31 -0800, Matt Roper wrote:
>
> From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>
> Enable relevant OA formats for ADL_P.
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/i915_perf.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index c15bead2dac7..e52b54ff0999 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -4291,6 +4291,7 @@ static void oa_init_supported_formats(struct i915_perf *perf)
> case INTEL_ROCKETLAKE:
> case INTEL_DG1:
> case INTEL_ALDERLAKE_S:
> + case INTEL_ALDERLAKE_P:
> oa_format_add(perf, I915_OA_FORMAT_A12);
> oa_format_add(perf, I915_OA_FORMAT_A12_B8_C8);
> oa_format_add(perf, I915_OA_FORMAT_A32u40_A4u32_B8_C8);
> --
> 2.25.4
>
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Intel-gfx] [PATCH 56/56] drm/i915/display/adl_p: Implement PSR changes
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (54 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 55/56] drm/i915/perf: Enable OA formats for ADL_P Matt Roper
@ 2021-03-11 22:36 ` Matt Roper
2021-03-13 19:49 ` Mun, Gwan-gyeong
2021-03-11 22:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alder Lake-P Patchwork
` (2 subsequent siblings)
58 siblings, 1 reply; 74+ messages in thread
From: Matt Roper @ 2021-03-11 22:36 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
Implements changes around PSR for alderlake-P:
- EDP_SU_TRACK_ENABLE was removed and bit 30 now has other function
- Some bits of PSR2_MAN_TRK_CTL moved and SF_PARTIAL_FRAME_UPDATE was
removed setting SU_REGION_START/END_ADDR will do this job
- SU_REGION_START/END_ADDR have now line granularity but will need to
be aligned with DSC when the PSRS + DSC support lands
BSpec: 50422
BSpec: 50424
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 51 +++++++++++++++++++-----
drivers/gpu/drm/i915/i915_reg.h | 26 +++++++-----
2 files changed, 56 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index e71d2dd6a4a5..752de6f8df61 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -519,11 +519,13 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
static void hsw_activate_psr2(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u32 val;
+ u32 val = EDP_PSR2_ENABLE;
val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
- val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
+ if (!IS_ALDERLAKE_P(dev_priv))
+ val |= EDP_SU_TRACK_ENABLE;
+
if (DISPLAY_VER(dev_priv) >= 10)
val |= EDP_Y_COORDINATE_ENABLE;
@@ -1245,21 +1247,32 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
struct drm_rect *clip, bool full_update)
{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 val = PSR2_MAN_TRK_CTL_ENABLE;
if (full_update) {
- val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
+ if (IS_ALDERLAKE_P(dev_priv))
+ val |= ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
+ else
+ val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
+
goto exit;
}
if (clip->y1 == -1)
goto exit;
- drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
+ val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2);
+ } else {
+ drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
- val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
- val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
- val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
+ val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
+ val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
+ val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
+ }
exit:
crtc_state->psr2_man_track_ctl = val;
}
@@ -1280,6 +1293,25 @@ static void clip_area_update(struct drm_rect *overlap_damage_area,
overlap_damage_area->y2 = damage_area->y2;
}
+static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state,
+ struct drm_rect *pipe_clip)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ /*
+ * TODO: ADL-P have line granularity but when DSC is enabled it
+ * needs to be aligned with DSC boundaries.
+ */
+ } else {
+ /* It must be aligned to 4 lines/1 block */
+ pipe_clip->y1 -= pipe_clip->y1 % 4;
+ if (pipe_clip->y2 % 4)
+ pipe_clip->y2 = ((pipe_clip->y2 / 4) + 1) * 4;
+ }
+}
+
int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -1388,10 +1420,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
if (full_update)
goto skip_sel_fetch_set_loop;
- /* It must be aligned to 4 lines */
- pipe_clip.y1 -= pipe_clip.y1 % 4;
- if (pipe_clip.y2 % 4)
- pipe_clip.y2 = ((pipe_clip.y2 / 4) + 1) * 4;
+ intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip);
/*
* Now that we have the pipe damaged area check if it intersect with
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d48a9dec8476..37caab2a4215 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4563,7 +4563,7 @@ enum {
#define _PSR2_CTL_EDP 0x6f900
#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A)
#define EDP_PSR2_ENABLE (1 << 31)
-#define EDP_SU_TRACK_ENABLE (1 << 30)
+#define EDP_SU_TRACK_ENABLE (1 << 30) /* up to adl-p */
#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28)
#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28)
#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */
@@ -4630,17 +4630,23 @@ enum {
#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
#define PSR2_SU_STATUS_FRAMES 8
-#define _PSR2_MAN_TRK_CTL_A 0x60910
-#define _PSR2_MAN_TRK_CTL_EDP 0x6f910
-#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
-#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
-#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
-#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
+#define _PSR2_MAN_TRK_CTL_A 0x60910
+#define _PSR2_MAN_TRK_CTL_EDP 0x6f910
+#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
+#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
+#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
+#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11)
#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
-#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
-#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
-#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
+#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
+#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
+#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
+#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16)
+#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
+#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0)
+#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
+#define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
+#define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
/* Icelake DSC Rate Control Range Parameter Registers */
#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
--
2.25.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Intel-gfx] [PATCH 56/56] drm/i915/display/adl_p: Implement PSR changes
2021-03-11 22:36 ` [Intel-gfx] [PATCH 56/56] drm/i915/display/adl_p: Implement PSR changes Matt Roper
@ 2021-03-13 19:49 ` Mun, Gwan-gyeong
0 siblings, 0 replies; 74+ messages in thread
From: Mun, Gwan-gyeong @ 2021-03-13 19:49 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx
On Thu, 2021-03-11 at 14:36 -0800, Matt Roper wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
>
> Implements changes around PSR for alderlake-P:
>
> - EDP_SU_TRACK_ENABLE was removed and bit 30 now has other function
> - Some bits of PSR2_MAN_TRK_CTL moved and SF_PARTIAL_FRAME_UPDATE was
> removed setting SU_REGION_START/END_ADDR will do this job
> - SU_REGION_START/END_ADDR have now line granularity but will need to
> be aligned with DSC when the PSRS + DSC support lands
>
> BSpec: 50422
> BSpec: 50424
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 51 +++++++++++++++++++---
> --
> drivers/gpu/drm/i915/i915_reg.h | 26 +++++++-----
> 2 files changed, 56 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index e71d2dd6a4a5..752de6f8df61 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -519,11 +519,13 @@ static u32 intel_psr2_get_tp_time(struct
> intel_dp *intel_dp)
> static void hsw_activate_psr2(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - u32 val;
> + u32 val = EDP_PSR2_ENABLE;
>
> val = psr_compute_idle_frames(intel_dp) <<
> EDP_PSR2_IDLE_FRAME_SHIFT;
It over-writes the variable val.
it also should be changed like this.
val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
>
> - val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
> + if (!IS_ALDERLAKE_P(dev_priv))
> + val |= EDP_SU_TRACK_ENABLE;
> +
> if (DISPLAY_VER(dev_priv) >= 10)
> val |= EDP_Y_COORDINATE_ENABLE;
>
> @@ -1245,21 +1247,32 @@ void
> intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state
> *crtc_st
> static void psr2_man_trk_ctl_calc(struct intel_crtc_state
> *crtc_state,
> struct drm_rect *clip, bool
> full_update)
> {
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state-
> >uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 val = PSR2_MAN_TRK_CTL_ENABLE;
>
> if (full_update) {
> - val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> + if (IS_ALDERLAKE_P(dev_priv))
> + val |=
> ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> + else
> + val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> +
> goto exit;
> }
>
> if (clip->y1 == -1)
> goto exit;
>
> - drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip-
> >y2 % 4);
> + if (IS_ALDERLAKE_P(dev_priv)) {
> + val |=
> ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
> + val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip-
> >y2);
> + } else {
> + drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4
> || clip->y2 % 4);
>
> - val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> - val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 +
> 1);
> - val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
> + val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> + val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1
> / 4 + 1);
> + val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 /
> 4 + 1);
> + }
> exit:
> crtc_state->psr2_man_track_ctl = val;
> }
> @@ -1280,6 +1293,25 @@ static void clip_area_update(struct drm_rect
> *overlap_damage_area,
> overlap_damage_area->y2 = damage_area->y2;
> }
>
> +static void intel_psr2_sel_fetch_pipe_alignment(const struct
> intel_crtc_state *crtc_state,
> + struct drm_rect
> *pipe_clip)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state-
> >uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +
> + if (IS_ALDERLAKE_P(dev_priv)) {
> + /*
> + * TODO: ADL-P have line granularity but when DSC is
> enabled it
> + * needs to be aligned with DSC boundaries.
> + */
> + } else {
> + /* It must be aligned to 4 lines/1 block */
> + pipe_clip->y1 -= pipe_clip->y1 % 4;
> + if (pipe_clip->y2 % 4)
> + pipe_clip->y2 = ((pipe_clip->y2 / 4) + 1) *
> 4;
> + }
> +}
> +
> int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> @@ -1388,10 +1420,7 @@ int intel_psr2_sel_fetch_update(struct
> intel_atomic_state *state,
> if (full_update)
> goto skip_sel_fetch_set_loop;
>
> - /* It must be aligned to 4 lines */
> - pipe_clip.y1 -= pipe_clip.y1 % 4;
> - if (pipe_clip.y2 % 4)
> - pipe_clip.y2 = ((pipe_clip.y2 / 4) + 1) * 4;
> + intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip);
>
> /*
> * Now that we have the pipe damaged area check if it
> intersect with
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index d48a9dec8476..37caab2a4215 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4563,7 +4563,7 @@ enum {
> #define _PSR2_CTL_EDP 0x6f900
> #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran,
> _PSR2_CTL_A)
> #define EDP_PSR2_ENABLE (1 << 31)
> -#define EDP_SU_TRACK_ENABLE (1 << 30)
> +#define EDP_SU_TRACK_ENABLE (1 << 30) /* up to
> adl-p */
> #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28)
> #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28)
> #define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and
> CNL+ */
> @@ -4630,17 +4630,23 @@ enum {
> #define PSR2_SU_STATUS_MASK(frame) (0x3ff <<
> PSR2_SU_STATUS_SHIFT(frame))
> #define PSR2_SU_STATUS_FRAMES 8
>
> -#define _PSR2_MAN_TRK_CTL_A 0x60910
> -#define _PSR2_MAN_TRK_CTL_EDP 0x6f910
> -#define
> PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran,
> _PSR2_MAN_TRK_CTL_A)
> -#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
> -#define
> PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
> -#define
> PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN
> _TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> +#define
> _PSR2_MAN_TRK_CTL_A 0x60910
> +#define
> _PSR2_MAN_TRK_CTL_EDP 0x6f910
> +#define
> PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(t
> ran, _PSR2_MAN_TRK_CTL_A)
> +#define
> PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
> +#define
> PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30,
> 21)
> +#define
> PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(
> PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> #define
> PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20,
> 11)
> #define
> PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(
> PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
> -#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
> -#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
> -#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
> +#define
> PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
> +#define
> PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
> +#define
> PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
> +#define
> ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28,
> 16)
> +#define
> ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(
> ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> +#define
> ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12,
> 0)
> +#define
> ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(
> ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
> +#define
> ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
> +#define
> ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
>
> /* Icelake DSC Rate Control Range Parameter Registers */
> #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alder Lake-P
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (55 preceding siblings ...)
2021-03-11 22:36 ` [Intel-gfx] [PATCH 56/56] drm/i915/display/adl_p: Implement PSR changes Matt Roper
@ 2021-03-11 22:48 ` Patchwork
2021-03-11 22:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-03-11 23:14 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
58 siblings, 0 replies; 74+ messages in thread
From: Patchwork @ 2021-03-11 22:48 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: Introduce Alder Lake-P
URL : https://patchwork.freedesktop.org/series/87897/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
545bd02e1c9a drm/i915/display: Convert gen5/gen6 tests to IS_IRONLAKE/IS_SANDYBRIDGE
-:100: CHECK:CAMELCASE: Avoid CamelCase: <ILK_eDP_A_DISABLE>
#100: FILE: drivers/gpu/drm/i915/display/intel_display.c:11602:
+ if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
total: 0 errors, 0 warnings, 1 checks, 216 lines checked
8e54a5e601c5 drm/i915: Add DISPLAY_VER()
-:59: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects?
#59: FILE: drivers/gpu/drm/i915/i915_pci.c:39:
+#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1), .display_ver = x
total: 0 errors, 0 warnings, 1 checks, 25 lines checked
4d46d9bc5a06 drm/i915/display: Eliminate most usage of INTEL_GEN()
-:35: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#35:
+ if (DISPLAY_VER(dev_priv) >= from && DISPLAY_VER(dev_priv) <= until) S
-:1222: CHECK:LINE_SPACING: Please don't use multiple blank lines
#1222: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:552:
+
-:2058: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'port == PORT_E'
#2058: FILE: drivers/gpu/drm/i915/display/intel_display.c:6715:
+ if (DISPLAY_VER(dev_priv) < 9 &&
(port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
-:2646: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 63)
#2646: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:153:
+ if (DISPLAY_VER(dev_priv) >= 9)
/* no global SR status; inspect per-plane WM */;
-:4192: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED'
#4192: FILE: drivers/gpu/drm/i915/display/intel_psr.c:324:
+ if (DISPLAY_VER(dev_priv) >= 9 &&
(intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
-:4808: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#4808: FILE: drivers/gpu/drm/i915/display/skl_universal_plane.c:2032:
+ plane->need_async_flip_disable_wa = (DISPLAY_VER(dev_priv) >= 9 && DISPLAY_VER(dev_priv) <= 10);
total: 0 errors, 3 warnings, 3 checks, 4213 lines checked
92d30df5de1c drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in intel_pm.c
dd05f3125c5b drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in i915_irq.c
a0318588a6b7 drm/i915/display: Simplify GLK display version tests
0afe26e7a99d drm/i915/xelpd: add XE_LPD display characteristics
2fd845823954 drm/i915/xelpd: Handle proper AUX interrupt bits
3e432180467c drm/i915/xelpd: Enhanced pipe underrun reporting
-:66: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#66: FILE: drivers/gpu/drm/i915/display/intel_fifo_underrun.c:390:
+ return "hard";
+ else
total: 0 errors, 1 warnings, 0 checks, 131 lines checked
a34d69c7ec8d drm/i915/xelpd: Define plane capabilities
19b0bb00151b drm/i915/xelpd: Support 128k plane stride
d770b6b8cd28 drm/i915/xelpd: Handle new location of outputs D and E
bc80bcbca1c1 drm/i915/xelpd: Add XE_LPD power wells
-:36: WARNING:BAD_SIGN_OFF: Duplicate signature
#36:
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
total: 0 errors, 1 warnings, 0 checks, 522 lines checked
206a1379e251 drm/i915/xelpd: Handle LPSP for XE_LPD
da736ae5f9ac drm/i915/xelpd: Increase maximum watermark lines to 255
e280eb022d6d drm/i915/xelpd: Required bandwidth increases when VT-d is active
40c5437f3499 drm/i915/xelpd: Add Wa_14011503030
c06f1cfdb54c drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp
ffeca9d43e30 drm/i915/xelpd: Support DP1.4 compression BPPs
-:40: CHECK:LINE_SPACING: Please don't use multiple blank lines
#40: FILE: drivers/gpu/drm/i915/display/intel_dp.c:569:
+
total: 0 errors, 0 warnings, 1 checks, 75 lines checked
c9b04c68d8a0 drm/i915: Get slice height before computing rc params
e1dce68d97ed drm/i915/xelpd: Calculate VDSC RC parameters
-:51: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#51: FILE: drivers/gpu/drm/i915/display/intel_vdsc.c:393:
+ rc->first_line_bpg_offset = 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
total: 0 errors, 1 warnings, 0 checks, 134 lines checked
e545fc603067 drm/i915/xelpd: Add rc_qp_table for rcparams calculation
-:18: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#18:
new file mode 100644
-:369: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#369: FILE: drivers/gpu/drm/i915/display/intel_vdsc.c:426:
+ rc->rc_range_params[buf_i].range_min_qp = RC_RANGE_QP(min, 10, buf_i, bpp_i);
-:370: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#370: FILE: drivers/gpu/drm/i915/display/intel_vdsc.c:427:
+ rc->rc_range_params[buf_i].range_max_qp = RC_RANGE_QP(max, 10, buf_i, bpp_i);
-:373: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#373: FILE: drivers/gpu/drm/i915/display/intel_vdsc.c:430:
+ rc->rc_range_params[buf_i].range_min_qp = RC_RANGE_QP(min, 12, buf_i, bpp_i);
-:374: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#374: FILE: drivers/gpu/drm/i915/display/intel_vdsc.c:431:
+ rc->rc_range_params[buf_i].range_max_qp = RC_RANGE_QP(max, 12, buf_i, bpp_i);
total: 0 errors, 5 warnings, 0 checks, 347 lines checked
1a36ab332c53 drm/i915/xelpd: Add VRR guardband for VRR CTL
-:156: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#156: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:221:
+ crtc_state->vrr.guardband = REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
-:159: WARNING:LONG_LINE: line length of 113 exceeds 100 columns
#159: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:224:
+ crtc_state->vrr.pipeline_full = REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
-:186: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#186: FILE: drivers/gpu/drm/i915/i915_reg.h:4360:
+#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
total: 0 errors, 3 warnings, 0 checks, 140 lines checked
7c90acb36f4d drm/i915/adl_p: Add PCI Devices IDs
-:24: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#24: FILE: include/drm/i915_pciids.h:649:
+#define INTEL_ADLP_IDS(info) \
+ INTEL_VGA_DEVICE(0x46A0, info), \
+ INTEL_VGA_DEVICE(0x46A1, info), \
+ INTEL_VGA_DEVICE(0x46A2, info), \
+ INTEL_VGA_DEVICE(0x46A3, info), \
+ INTEL_VGA_DEVICE(0x46A6, info), \
+ INTEL_VGA_DEVICE(0x46A8, info), \
+ INTEL_VGA_DEVICE(0x46AA, info), \
+ INTEL_VGA_DEVICE(0x462A, info), \
+ INTEL_VGA_DEVICE(0x4626, info), \
+ INTEL_VGA_DEVICE(0x4628, info), \
+ INTEL_VGA_DEVICE(0x46B0, info), \
+ INTEL_VGA_DEVICE(0x46B1, info), \
+ INTEL_VGA_DEVICE(0x46B2, info), \
+ INTEL_VGA_DEVICE(0x46B3, info), \
+ INTEL_VGA_DEVICE(0x46C0, info), \
+ INTEL_VGA_DEVICE(0x46C1, info), \
+ INTEL_VGA_DEVICE(0x46C2, info), \
+ INTEL_VGA_DEVICE(0x46C3, info)
-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#24: FILE: include/drm/i915_pciids.h:649:
+#define INTEL_ADLP_IDS(info) \
+ INTEL_VGA_DEVICE(0x46A0, info), \
+ INTEL_VGA_DEVICE(0x46A1, info), \
+ INTEL_VGA_DEVICE(0x46A2, info), \
+ INTEL_VGA_DEVICE(0x46A3, info), \
+ INTEL_VGA_DEVICE(0x46A6, info), \
+ INTEL_VGA_DEVICE(0x46A8, info), \
+ INTEL_VGA_DEVICE(0x46AA, info), \
+ INTEL_VGA_DEVICE(0x462A, info), \
+ INTEL_VGA_DEVICE(0x4626, info), \
+ INTEL_VGA_DEVICE(0x4628, info), \
+ INTEL_VGA_DEVICE(0x46B0, info), \
+ INTEL_VGA_DEVICE(0x46B1, info), \
+ INTEL_VGA_DEVICE(0x46B2, info), \
+ INTEL_VGA_DEVICE(0x46B3, info), \
+ INTEL_VGA_DEVICE(0x46C0, info), \
+ INTEL_VGA_DEVICE(0x46C1, info), \
+ INTEL_VGA_DEVICE(0x46C2, info), \
+ INTEL_VGA_DEVICE(0x46C3, info)
total: 1 errors, 0 warnings, 1 checks, 24 lines checked
3ca777b82d4f drm/i915/adl_p: ADL_P device info enabling
9a60ab0c7f6f drm/i915/adl_p: Add PCH support
e5d780a7e2c8 drm/i915/adl_p: Add dedicated SAGV watermarks
-:68: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#68: FILE: drivers/gpu/drm/i915/i915_drv.h:585:
+#define HAS_HW_SAGV_WM(i915) ((DISPLAY_VER(i915) == 13) && !IS_DGFX(i915))
-:132: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#132: FILE: drivers/gpu/drm/i915/i915_reg.h:6452:
+#define _PLANE_WM_BASE(pipe, plane) \
+ _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
-:140: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#140: FILE: drivers/gpu/drm/i915/i915_reg.h:6460:
+#define PLANE_WM_SAGV(pipe, plane) \
+ _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
-:146: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#146: FILE: drivers/gpu/drm/i915/i915_reg.h:6466:
+#define PLANE_WM_SAGV_TRANS(pipe, plane) \
+ _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
-:152: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#152: FILE: drivers/gpu/drm/i915/i915_reg.h:6472:
+#define PLANE_WM_TRANS(pipe, plane) \
_MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
-:235: CHECK:LINE_SPACING: Please don't use multiple blank lines
#235: FILE: drivers/gpu/drm/i915/intel_pm.c:6260:
+
total: 0 errors, 0 warnings, 6 checks, 215 lines checked
c8feb3de6d2f drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines
a31a27c201e3 drm/i915/adl_p: Load DMC
53cbbdc4ce2b drm/i915/adl_p: Setup ports/phys
b88ec5ff4cf4 drm/i915/adl_p: Add cdclk support for ADL-P
72da71eda198 drm/i915/display/tc: Rename safe_mode functions ownership
1cc279b9a9ae drm/i915/adl_p: Handle TC cold
-:32: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#32: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:554:
+ if (IS_ALDERLAKE_P(dev_priv) ||
+ (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port))
total: 0 errors, 0 warnings, 1 checks, 9 lines checked
d3d588966024 drm/i915/adl_p: Implement TC sequences
76d78f0a89b0 drm/i915/adl_p: Enable modular fia
7f6b13959baf drm/i915/adl_p: Don't config MBUS and DBUF during display initialization
d9c40cc5183b drm/i915/adl_p: Add ddb allocation support
-:39: WARNING:LONG_LINE_COMMENT: line length of 102 exceeds 100 columns
#39: FILE: drivers/gpu/drm/i915/i915_reg.h:7291:
+#define DDB_ENTRY_MASK 0xFFF /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
total: 0 errors, 1 warnings, 0 checks, 180 lines checked
ece44a3951a4 drm/i915: Introduce MBUS relative dbuf offsets
-:11: WARNING:TYPO_SPELLING: 'accomodate' may be misspelled - perhaps 'accommodate'?
#11:
MBUS unit. To accomodate that we shall store the MBUS relative
^^^^^^^^^^
total: 0 errors, 1 warnings, 0 checks, 83 lines checked
33b7d6985cbf drm/i915: Move intel_modeset_all_pipes()
b7078c173757 drm/i915/adl_p: MBUS programming
-:101: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#101: FILE: drivers/gpu/drm/i915/i915_reg.h:8149:
+#define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
total: 0 errors, 1 warnings, 0 checks, 237 lines checked
bed8e7bb8774 drm/i915/adl_p: Tx escape clock with DSI
-:65: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#65: FILE: drivers/gpu/drm/i915/display/icl_dsi.c:373:
+ esc_clk_div_m_phy = (act_word_clk - 1)/2;
^
total: 0 errors, 0 warnings, 1 checks, 47 lines checked
eaa274e708a8 drm/i915/adl_p: Add initial ADL_P Workarounds
-:148: CHECK:LINE_SPACING: Please don't use multiple blank lines
#148: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:1700:
+
total: 0 errors, 0 warnings, 1 checks, 144 lines checked
229748b64190 drm/i915/adlp: Define GuC/HuC for Alderlake_P
b304533d0f55 drm/i915/adl_p: Define and use ADL-P specific DP translation tables
-:82: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#82: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1375:
+adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
total: 0 errors, 0 warnings, 1 checks, 75 lines checked
4b31b97ab781 drm/i915/adl_p: Enable/disable loadgen sharing
-:26: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#26: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1465:
+ if ((intel_crtc_has_dp_encoder(crtc_state) &&
+ crtc_state->port_clock == 162000) ||
total: 0 errors, 0 warnings, 1 checks, 21 lines checked
24fddb894143 drm/i915/adl_p: Add PLL Support
f3adcffb1aee drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner
f6779a65ec33 drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner
-:31: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#31: FILE: drivers/gpu/drm/i915/display/intel_dp.c:1507:
+ if (ret || intel_dp->force_dsc_en || (!(DISPLAY_VER(i915) == 13) &&
+ pipe_config->bigjoiner)) {
total: 0 errors, 0 warnings, 1 checks, 15 lines checked
a967b8f0d577 drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
0f2911a4def4 drm/i915/adlp: Add PIPE_MISC2 programming
-:28: ERROR:CODE_INDENT: code indent should use tabs where possible
#28: FILE: drivers/gpu/drm/i915/display/intel_display.c:6220:
+ const struct intel_crtc_scaler_state *scaler_state =$
-:28: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#28: FILE: drivers/gpu/drm/i915/display/intel_display.c:6220:
+ const struct intel_crtc_scaler_state *scaler_state =$
-:29: ERROR:CODE_INDENT: code indent should use tabs where possible
#29: FILE: drivers/gpu/drm/i915/display/intel_display.c:6221:
+ &crtc_state->scaler_state;$
-:29: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#29: FILE: drivers/gpu/drm/i915/display/intel_display.c:6221:
+ &crtc_state->scaler_state;$
total: 2 errors, 2 warnings, 0 checks, 48 lines checked
7ae8fa32c79f drm/i915/adl_p: Update memory bandwidth parameters
338170857dd4 drm/i915/adl_p: Implement Wa_22011091694
80727a5175f3 drm/i915/display/adl_p: Implement Wa_22011320316
-:69: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#69: FILE: drivers/gpu/drm/i915/i915_drv.h:1619:
+#define IS_ADLP_REVID(p, since, until) \
+ (IS_ALDERLAKE_P(p) && IS_REVID(p, since, until))
total: 0 errors, 0 warnings, 1 checks, 46 lines checked
5f5ddd87a7d9 drm/i915/display/adl_p: Remove CCS support
8e8789fb3382 drm/i915/perf: Enable OA formats for ADL_P
ff4d1fd19abd drm/i915/display/adl_p: Implement PSR changes
-:146: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#146: FILE: drivers/gpu/drm/i915/i915_reg.h:4635:
+#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
-:149: WARNING:LONG_LINE: line length of 127 exceeds 100 columns
#149: FILE: drivers/gpu/drm/i915/i915_reg.h:4638:
+#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
-:159: WARNING:LONG_LINE: line length of 132 exceeds 100 columns
#159: FILE: drivers/gpu/drm/i915/i915_reg.h:4645:
+#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
-:161: WARNING:LONG_LINE: line length of 130 exceeds 100 columns
#161: FILE: drivers/gpu/drm/i915/i915_reg.h:4647:
+#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
total: 0 errors, 4 warnings, 0 checks, 128 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 74+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce Alder Lake-P
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (56 preceding siblings ...)
2021-03-11 22:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alder Lake-P Patchwork
@ 2021-03-11 22:50 ` Patchwork
2021-03-11 23:14 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
58 siblings, 0 replies; 74+ messages in thread
From: Patchwork @ 2021-03-11 22:50 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: Introduce Alder Lake-P
URL : https://patchwork.freedesktop.org/series/87897/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/display/intel_qp_tables.h:27:10: warning: symbol 'rc_range_minqp444_8bpc' was not declared. Should it be static?
+drivers/gpu/drm/i915/display/intel_qp_tables.h:28:10: warning: symbol 'rc_range_maxqp444_8bpc' was not declared. Should it be static?
+drivers/gpu/drm/i915/display/intel_qp_tables.h:29:10: warning: symbol 'rc_range_minqp444_10bpc' was not declared. Should it be static?
+drivers/gpu/drm/i915/display/intel_qp_tables.h:30:10: warning: symbol 'rc_range_maxqp444_10bpc' was not declared. Should it be static?
+drivers/gpu/drm/i915/display/intel_qp_tables.h:31:10: warning: symbol 'rc_range_minqp444_12bpc' was not declared. Should it be static?
+drivers/gpu/drm/i915/display/intel_qp_tables.h:32:10: warning: symbol 'rc_range_maxqp444_12bpc' was not declared. Should it be static?
+drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 74+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for Introduce Alder Lake-P
2021-03-11 22:35 [Intel-gfx] [PATCH 00/56] Introduce Alder Lake-P Matt Roper
` (57 preceding siblings ...)
2021-03-11 22:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-03-11 23:14 ` Patchwork
58 siblings, 0 replies; 74+ messages in thread
From: Patchwork @ 2021-03-11 23:14 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 8924 bytes --]
== Series Details ==
Series: Introduce Alder Lake-P
URL : https://patchwork.freedesktop.org/series/87897/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9851 -> Patchwork_19786
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_19786 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19786, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19786/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19786:
### IGT changes ###
#### Possible regressions ####
* igt@core_hotunplug@unbind-rebind:
- fi-bwr-2160: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9851/fi-bwr-2160/igt@core_hotunplug@unbind-rebind.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19786/fi-bwr-2160/igt@core_hotunplug@unbind-rebind.html
* igt@runner@aborted:
- fi-cml-u2: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19786/fi-cml-u2/igt@runner@aborted.html
- fi-tgl-u2: NOTRUN -> [FAIL][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19786/fi-tgl-u2/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_19786 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@userptr:
- fi-byt-j1900: NOTRUN -> [SKIP][5] ([fdo#109271]) +17 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19786/fi-byt-j1900/igt@amdgpu/amd_basic@userptr.html
* igt@gem_exec_gttfill@basic:
- fi-kbl-8809g: [PASS][6] -> [TIMEOUT][7] ([i915#3145])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9851/fi-kbl-8809g/igt@gem_exec_gttfill@basic.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19786/fi-kbl-8809g/igt@gem_exec_gttfill@basic.html
#### Possible fixes ####
* igt@gem_linear_blits@basic:
- fi-kbl-8809g: [TIMEOUT][8] ([i915#2502] / [i915#3145]) -> [PASS][9] +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9851/fi-kbl-8809g/igt@gem_linear_blits@basic.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19786/fi-kbl-8809g/igt@gem_linear_blits@basic.html
* igt@gem_tiled_fence_blits@basic:
- fi-kbl-8809g: [TIMEOUT][10] ([i915#3145]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9851/fi-kbl-8809g/igt@gem_tiled_fence_blits@basic.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19786/fi-kbl-8809g/igt@gem_tiled_fence_blits@basic.html
* igt@gem_wait@busy@all:
- fi-bsw-nick: [FAIL][12] ([i915#3177]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9851/fi-bsw-nick/igt@gem_wait@busy@all.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19786/fi-bsw-nick/igt@gem_wait@busy@all.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [INCOMPLETE][14] ([i915#142] / [i915#2405]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9851/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19786/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
#### Warnings ####
* igt@runner@aborted:
- fi-icl-u2: [FAIL][16] ([i915#1814]) -> [FAIL][17] ([i915#1569] / [k.org#202973])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9851/fi-icl-u2/igt@runner@aborted.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19786/fi-icl-u2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1222]: https://gitlab.freedesktop.org/drm/intel/issues/1222
[i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142
[i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
[i915#2502]: https://gitlab.freedesktop.org/drm/intel/issues/2502
[i915#3145]: https://gitlab.freedesktop.org/drm/intel/issues/3145
[i915#3177]: https://gitlab.freedesktop.org/drm/intel/issues/3177
[k.org#202973]: https://bugzilla.kernel.org/show_bug.cgi?id=202973
Participating hosts (46 -> 39)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050 fi-glk-dsi fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9851 -> Patchwork_19786
CI-20190529: 20190529
CI_DRM_9851: 3c654b84957a19021def19bba396189409f197ea @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6030: e11e4bfb91fec9af71c3909996c66e5666270e07 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19786: ff4d1fd19abda93fafaec66c226bd41895c64fff @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ff4d1fd19abd drm/i915/display/adl_p: Implement PSR changes
8e8789fb3382 drm/i915/perf: Enable OA formats for ADL_P
5f5ddd87a7d9 drm/i915/display/adl_p: Remove CCS support
80727a5175f3 drm/i915/display/adl_p: Implement Wa_22011320316
338170857dd4 drm/i915/adl_p: Implement Wa_22011091694
7ae8fa32c79f drm/i915/adl_p: Update memory bandwidth parameters
0f2911a4def4 drm/i915/adlp: Add PIPE_MISC2 programming
a967b8f0d577 drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
f6779a65ec33 drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner
f3adcffb1aee drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner
24fddb894143 drm/i915/adl_p: Add PLL Support
4b31b97ab781 drm/i915/adl_p: Enable/disable loadgen sharing
b304533d0f55 drm/i915/adl_p: Define and use ADL-P specific DP translation tables
229748b64190 drm/i915/adlp: Define GuC/HuC for Alderlake_P
eaa274e708a8 drm/i915/adl_p: Add initial ADL_P Workarounds
bed8e7bb8774 drm/i915/adl_p: Tx escape clock with DSI
b7078c173757 drm/i915/adl_p: MBUS programming
33b7d6985cbf drm/i915: Move intel_modeset_all_pipes()
ece44a3951a4 drm/i915: Introduce MBUS relative dbuf offsets
d9c40cc5183b drm/i915/adl_p: Add ddb allocation support
7f6b13959baf drm/i915/adl_p: Don't config MBUS and DBUF during display initialization
76d78f0a89b0 drm/i915/adl_p: Enable modular fia
d3d588966024 drm/i915/adl_p: Implement TC sequences
1cc279b9a9ae drm/i915/adl_p: Handle TC cold
72da71eda198 drm/i915/display/tc: Rename safe_mode functions ownership
b88ec5ff4cf4 drm/i915/adl_p: Add cdclk support for ADL-P
53cbbdc4ce2b drm/i915/adl_p: Setup ports/phys
a31a27c201e3 drm/i915/adl_p: Load DMC
c8feb3de6d2f drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines
e5d780a7e2c8 drm/i915/adl_p: Add dedicated SAGV watermarks
9a60ab0c7f6f drm/i915/adl_p: Add PCH support
3ca777b82d4f drm/i915/adl_p: ADL_P device info enabling
7c90acb36f4d drm/i915/adl_p: Add PCI Devices IDs
1a36ab332c53 drm/i915/xelpd: Add VRR guardband for VRR CTL
e545fc603067 drm/i915/xelpd: Add rc_qp_table for rcparams calculation
e1dce68d97ed drm/i915/xelpd: Calculate VDSC RC parameters
c9b04c68d8a0 drm/i915: Get slice height before computing rc params
ffeca9d43e30 drm/i915/xelpd: Support DP1.4 compression BPPs
c06f1cfdb54c drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp
40c5437f3499 drm/i915/xelpd: Add Wa_14011503030
e280eb022d6d drm/i915/xelpd: Required bandwidth increases when VT-d is active
da736ae5f9ac drm/i915/xelpd: Increase maximum watermark lines to 255
206a1379e251 drm/i915/xelpd: Handle LPSP for XE_LPD
bc80bcbca1c1 drm/i915/xelpd: Add XE_LPD power wells
d770b6b8cd28 drm/i915/xelpd: Handle new location of outputs D and E
19b0bb00151b drm/i915/xelpd: Support 128k plane stride
a34d69c7ec8d drm/i915/xelpd: Define plane capabilities
3e432180467c drm/i915/xelpd: Enhanced pipe underrun reporting
2fd845823954 drm/i915/xelpd: Handle proper AUX interrupt bits
0afe26e7a99d drm/i915/xelpd: add XE_LPD display characteristics
a0318588a6b7 drm/i915/display: Simplify GLK display version tests
dd05f3125c5b drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in i915_irq.c
92d30df5de1c drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in intel_pm.c
4d46d9bc5a06 drm/i915/display: Eliminate most usage of INTEL_GEN()
8e54a5e601c5 drm/i915: Add DISPLAY_VER()
545bd02e1c9a drm/i915/display: Convert gen5/gen6 tests to IS_IRONLAKE/IS_SANDYBRIDGE
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19786/index.html
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