All of lore.kernel.org
 help / color / mirror / Atom feed
From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, mike.leach@linaro.org,
	anshuman.khandual@arm.com, leo.yan@linaro.org,
	Linu Cherian <lcherian@marvell.com>
Subject: Re: [PATCH v4 10/19] coresight: etm-perf: Allow an event to use different sinks
Date: Tue, 16 Mar 2021 14:23:45 -0600	[thread overview]
Message-ID: <20210316202345.GE1387186@xps15> (raw)
In-Reply-To: <20210225193543.2920532-11-suzuki.poulose@arm.com>

On Thu, Feb 25, 2021 at 07:35:34PM +0000, Suzuki K Poulose wrote:
> When a sink is not specified by the user, the etm perf driver
> finds a suitable sink automatically, based on the first ETM
> where this event could be scheduled. Then we allocate the
> sink buffer based on the selected sink. This is fine for a
> CPU bound event as the "sink" is always guaranteed to be
> reachable from the ETM (as this is the only ETM where the
> event is going to be scheduled). However, if we have a thread
> bound event, the event could be scheduled on any of the ETMs
> on the system. In this case, currently we automatically select
> a sink and exclude any ETMs that cannot reach the selected
> sink. This is problematic especially for 1x1 configurations.
> We end up in tracing the event only on the "first" ETM,
> as the default sink is local to the first ETM and unreachable
> from the rest. However, we could allow the other ETMs to
> trace if they all have a sink that is compatible with the
> "selected" sink and can use the sink buffer. This can be
> easily done by verifying that they are all driven by the
> same driver and matches the same subtype. Please note
> that at anytime there can be only one ETM tracing the event.
> 
> Adding support for different types of sinks for a single
> event is complex and is not something that we expect
> on a sane configuration.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Tested-by: Linu Cherian <lcherian@marvell.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> Changes:
> - Rename sinks_match => sinks_compatible
> - Tighten the check by matching the sink subtype
> - Use user_sink instead of "sink_forced" and clean up the code (Mathieu)
> - More comments, better commit description
> ---
>  .../hwtracing/coresight/coresight-etm-perf.c  | 60 ++++++++++++++++---
>  1 file changed, 52 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
> index 0f603b4094f2..aa0974bd265b 100644
> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c
> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
> @@ -232,6 +232,25 @@ static void etm_free_aux(void *data)
>  	schedule_work(&event_data->work);
>  }
>  
> +/*
> + * Check if two given sinks are compatible with each other,
> + * so that they can use the same sink buffers, when an event
> + * moves around.
> + */
> +static bool sinks_compatible(struct coresight_device *a,
> +			     struct coresight_device *b)
> +{
> +	if (!a || !b)
> +		return false;
> +	/*
> +	 * If the sinks are of the same subtype and driven
> +	 * by the same driver, we can use the same buffer
> +	 * on these sinks.
> +	 */
> +	return (a->subtype.sink_subtype == b->subtype.sink_subtype) &&
> +	       (sink_ops(a) == sink_ops(b));

Ok

> +}
> +
>  static void *etm_setup_aux(struct perf_event *event, void **pages,
>  			   int nr_pages, bool overwrite)
>  {
> @@ -239,6 +258,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
>  	int cpu = event->cpu;
>  	cpumask_t *mask;
>  	struct coresight_device *sink = NULL;
> +	struct coresight_device *user_sink = NULL, *last_sink = NULL;
>  	struct etm_event_data *event_data = NULL;
>  
>  	event_data = alloc_event_data(cpu);
> @@ -249,7 +269,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
>  	/* First get the selected sink from user space. */
>  	if (event->attr.config2) {
>  		id = (u32)event->attr.config2;
> -		sink = coresight_get_sink_by_id(id);
> +		sink = user_sink = coresight_get_sink_by_id(id);
>  	}
>  
>  	mask = &event_data->mask;
> @@ -277,14 +297,33 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
>  		}
>  
>  		/*
> -		 * No sink provided - look for a default sink for one of the
> -		 * devices. At present we only support topology where all CPUs
> -		 * use the same sink [N:1], so only need to find one sink. The
> -		 * coresight_build_path later will remove any CPU that does not
> -		 * attach to the sink, or if we have not found a sink.
> +		 * No sink provided - look for a default sink for all the ETMs,
> +		 * where this event can be scheduled.
> +		 * We allocate the sink specific buffers only once for this
> +		 * event. If the ETMs have different default sink devices, we
> +		 * can only use a single "type" of sink as the event can carry
> +		 * only one sink specific buffer. Thus we have to make sure
> +		 * that the sinks are of the same type and driven by the same
> +		 * driver, as the one we allocate the buffer for. As such
> +		 * we choose the first sink and check if the remaining ETMs
> +		 * have a compatible default sink. We don't trace on a CPU
> +		 * if the sink is not compatible.
>  		 */
> -		if (!sink)
> +		if (!user_sink) {
> +			/* Find the default sink for this ETM */
>  			sink = coresight_find_default_sink(csdev);
> +			if (!sink) {
> +				cpumask_clear_cpu(cpu, mask);
> +				continue;
> +			}
> +
> +			/* Check if this sink compatible with the last sink */
> +			if (last_sink && !sinks_compatible(last_sink, sink)) {
> +				cpumask_clear_cpu(cpu, mask);
> +				continue;
> +			}
> +			last_sink = sink;

This is much better.

I thought about something when I first looked a this patch in the previous
revision...  With the above we are changing the behavior of the CS framework for
systems that have one sink per CPU _clusters_, but for once it is for the better.

With this patch coresight_find_default_sink() is called for every CPU,
allowing CPUs in the second cluster to find a valid path and be included in the
trace session.  Before this patch CPUs in the second cluster couldn't
establish a valid path to the sink since it was only reachable from the first
cluster.

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>

More comments to come tomorrow.

Thanks,
Mathieu

> +		}
>  
>  		/*
>  		 * Building a path doesn't enable it, it simply builds a
> @@ -312,7 +351,12 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
>  	if (!sink_ops(sink)->alloc_buffer || !sink_ops(sink)->free_buffer)
>  		goto err;
>  
> -	/* Allocate the sink buffer for this session */
> +	/*
> +	 * Allocate the sink buffer for this session. All the sinks
> +	 * where this event can be scheduled are ensured to be of the
> +	 * same type. Thus the same sink configuration is used by the
> +	 * sinks.
> +	 */
>  	event_data->snk_config =
>  			sink_ops(sink)->alloc_buffer(sink, event, pages,
>  						     nr_pages, overwrite);
> -- 
> 2.24.1
> 

WARNING: multiple messages have this Message-ID (diff)
From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, mike.leach@linaro.org,
	anshuman.khandual@arm.com, leo.yan@linaro.org,
	Linu Cherian <lcherian@marvell.com>
Subject: Re: [PATCH v4 10/19] coresight: etm-perf: Allow an event to use different sinks
Date: Tue, 16 Mar 2021 14:23:45 -0600	[thread overview]
Message-ID: <20210316202345.GE1387186@xps15> (raw)
In-Reply-To: <20210225193543.2920532-11-suzuki.poulose@arm.com>

On Thu, Feb 25, 2021 at 07:35:34PM +0000, Suzuki K Poulose wrote:
> When a sink is not specified by the user, the etm perf driver
> finds a suitable sink automatically, based on the first ETM
> where this event could be scheduled. Then we allocate the
> sink buffer based on the selected sink. This is fine for a
> CPU bound event as the "sink" is always guaranteed to be
> reachable from the ETM (as this is the only ETM where the
> event is going to be scheduled). However, if we have a thread
> bound event, the event could be scheduled on any of the ETMs
> on the system. In this case, currently we automatically select
> a sink and exclude any ETMs that cannot reach the selected
> sink. This is problematic especially for 1x1 configurations.
> We end up in tracing the event only on the "first" ETM,
> as the default sink is local to the first ETM and unreachable
> from the rest. However, we could allow the other ETMs to
> trace if they all have a sink that is compatible with the
> "selected" sink and can use the sink buffer. This can be
> easily done by verifying that they are all driven by the
> same driver and matches the same subtype. Please note
> that at anytime there can be only one ETM tracing the event.
> 
> Adding support for different types of sinks for a single
> event is complex and is not something that we expect
> on a sane configuration.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Tested-by: Linu Cherian <lcherian@marvell.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> Changes:
> - Rename sinks_match => sinks_compatible
> - Tighten the check by matching the sink subtype
> - Use user_sink instead of "sink_forced" and clean up the code (Mathieu)
> - More comments, better commit description
> ---
>  .../hwtracing/coresight/coresight-etm-perf.c  | 60 ++++++++++++++++---
>  1 file changed, 52 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
> index 0f603b4094f2..aa0974bd265b 100644
> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c
> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
> @@ -232,6 +232,25 @@ static void etm_free_aux(void *data)
>  	schedule_work(&event_data->work);
>  }
>  
> +/*
> + * Check if two given sinks are compatible with each other,
> + * so that they can use the same sink buffers, when an event
> + * moves around.
> + */
> +static bool sinks_compatible(struct coresight_device *a,
> +			     struct coresight_device *b)
> +{
> +	if (!a || !b)
> +		return false;
> +	/*
> +	 * If the sinks are of the same subtype and driven
> +	 * by the same driver, we can use the same buffer
> +	 * on these sinks.
> +	 */
> +	return (a->subtype.sink_subtype == b->subtype.sink_subtype) &&
> +	       (sink_ops(a) == sink_ops(b));

Ok

> +}
> +
>  static void *etm_setup_aux(struct perf_event *event, void **pages,
>  			   int nr_pages, bool overwrite)
>  {
> @@ -239,6 +258,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
>  	int cpu = event->cpu;
>  	cpumask_t *mask;
>  	struct coresight_device *sink = NULL;
> +	struct coresight_device *user_sink = NULL, *last_sink = NULL;
>  	struct etm_event_data *event_data = NULL;
>  
>  	event_data = alloc_event_data(cpu);
> @@ -249,7 +269,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
>  	/* First get the selected sink from user space. */
>  	if (event->attr.config2) {
>  		id = (u32)event->attr.config2;
> -		sink = coresight_get_sink_by_id(id);
> +		sink = user_sink = coresight_get_sink_by_id(id);
>  	}
>  
>  	mask = &event_data->mask;
> @@ -277,14 +297,33 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
>  		}
>  
>  		/*
> -		 * No sink provided - look for a default sink for one of the
> -		 * devices. At present we only support topology where all CPUs
> -		 * use the same sink [N:1], so only need to find one sink. The
> -		 * coresight_build_path later will remove any CPU that does not
> -		 * attach to the sink, or if we have not found a sink.
> +		 * No sink provided - look for a default sink for all the ETMs,
> +		 * where this event can be scheduled.
> +		 * We allocate the sink specific buffers only once for this
> +		 * event. If the ETMs have different default sink devices, we
> +		 * can only use a single "type" of sink as the event can carry
> +		 * only one sink specific buffer. Thus we have to make sure
> +		 * that the sinks are of the same type and driven by the same
> +		 * driver, as the one we allocate the buffer for. As such
> +		 * we choose the first sink and check if the remaining ETMs
> +		 * have a compatible default sink. We don't trace on a CPU
> +		 * if the sink is not compatible.
>  		 */
> -		if (!sink)
> +		if (!user_sink) {
> +			/* Find the default sink for this ETM */
>  			sink = coresight_find_default_sink(csdev);
> +			if (!sink) {
> +				cpumask_clear_cpu(cpu, mask);
> +				continue;
> +			}
> +
> +			/* Check if this sink compatible with the last sink */
> +			if (last_sink && !sinks_compatible(last_sink, sink)) {
> +				cpumask_clear_cpu(cpu, mask);
> +				continue;
> +			}
> +			last_sink = sink;

This is much better.

I thought about something when I first looked a this patch in the previous
revision...  With the above we are changing the behavior of the CS framework for
systems that have one sink per CPU _clusters_, but for once it is for the better.

With this patch coresight_find_default_sink() is called for every CPU,
allowing CPUs in the second cluster to find a valid path and be included in the
trace session.  Before this patch CPUs in the second cluster couldn't
establish a valid path to the sink since it was only reachable from the first
cluster.

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>

More comments to come tomorrow.

Thanks,
Mathieu

> +		}
>  
>  		/*
>  		 * Building a path doesn't enable it, it simply builds a
> @@ -312,7 +351,12 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
>  	if (!sink_ops(sink)->alloc_buffer || !sink_ops(sink)->free_buffer)
>  		goto err;
>  
> -	/* Allocate the sink buffer for this session */
> +	/*
> +	 * Allocate the sink buffer for this session. All the sinks
> +	 * where this event can be scheduled are ensured to be of the
> +	 * same type. Thus the same sink configuration is used by the
> +	 * sinks.
> +	 */
>  	event_data->snk_config =
>  			sink_ops(sink)->alloc_buffer(sink, event, pages,
>  						     nr_pages, overwrite);
> -- 
> 2.24.1
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-03-16 20:24 UTC|newest]

Thread overview: 132+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-25 19:35 [PATCH v4 00/19] arm64: coresight: Add support for ETE and TRBE Suzuki K Poulose
2021-02-25 19:35 ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 01/19] perf: aux: Add flags for the buffer format Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 02/19] perf: aux: Add CoreSight PMU buffer formats Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-03-16 17:04   ` Mathieu Poirier
2021-03-16 17:04     ` Mathieu Poirier
2021-03-22 12:29     ` Suzuki K Poulose
2021-03-22 12:29       ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 03/19] kvm: arm64: Hide system instruction access to Trace registers Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-03-22 22:21   ` Suzuki K Poulose
2021-03-22 22:21     ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 04/19] kvm: arm64: nvhe: Save the SPE context early Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-03-01 16:32   ` Alexandru Elisei
2021-03-01 16:32     ` Alexandru Elisei
2021-03-02 10:01     ` Suzuki K Poulose
2021-03-02 10:01       ` Suzuki K Poulose
2021-03-02 10:13       ` Marc Zyngier
2021-03-02 10:13         ` Marc Zyngier
2021-03-02 11:00       ` Alexandru Elisei
2021-03-02 11:00         ` Alexandru Elisei
2021-02-25 19:35 ` [PATCH v4 05/19] kvm: arm64: Disable guest access to trace filter controls Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-03-22 22:24   ` Suzuki K Poulose
2021-03-22 22:24     ` Suzuki K Poulose
2021-03-23  9:16     ` Marc Zyngier
2021-03-23  9:16       ` Marc Zyngier
2021-03-23  9:44       ` Suzuki K Poulose
2021-03-23  9:44         ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 06/19] arm64: Add support for trace synchronization barrier Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 07/19] arm64: Add TRBE definitions Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-03-16 17:46   ` Mathieu Poirier
2021-03-16 17:46     ` Mathieu Poirier
2021-02-25 19:35 ` [PATCH v4 08/19] arm64: kvm: Enable access to TRBE support for host Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-03-16 17:49   ` Mathieu Poirier
2021-03-16 17:49     ` Mathieu Poirier
2021-02-25 19:35 ` [PATCH v4 09/19] coresight: etm4x: Move ETM to prohibited region for disable Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-03-08 17:25   ` Mike Leach
2021-03-08 17:25     ` Mike Leach
2021-03-16 19:30   ` Mathieu Poirier
2021-03-16 19:30     ` Mathieu Poirier
2021-03-17 10:44     ` Suzuki K Poulose
2021-03-17 10:44       ` Suzuki K Poulose
2021-03-17 17:09       ` Mathieu Poirier
2021-03-17 17:09         ` Mathieu Poirier
2021-03-22 21:28   ` Mathieu Poirier
2021-03-22 21:28     ` Mathieu Poirier
2021-02-25 19:35 ` [PATCH v4 10/19] coresight: etm-perf: Allow an event to use different sinks Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-03-08 17:25   ` Mike Leach
2021-03-08 17:25     ` Mike Leach
2021-03-16 20:23   ` Mathieu Poirier [this message]
2021-03-16 20:23     ` Mathieu Poirier
2021-03-17 10:47     ` Suzuki K Poulose
2021-03-17 10:47       ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 11/19] coresight: Do not scan for graph if none is present Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 12/19] coresight: etm4x: Add support for PE OS lock Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 13/19] coresight: ete: Add support for ETE sysreg access Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-02-25 22:33   ` kernel test robot
2021-02-25 22:33     ` kernel test robot
2021-02-25 22:33     ` kernel test robot
2021-02-26  6:25   ` kernel test robot
2021-02-26  6:25     ` kernel test robot
2021-02-25 19:35 ` [PATCH v4 14/19] coresight: ete: Add support for ETE tracing Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 15/19] dts: bindings: Document device tree bindings for ETE Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-03-06 21:06   ` Rob Herring
2021-03-06 21:06     ` Rob Herring
2021-03-08 17:25     ` Mike Leach
2021-03-08 17:25       ` Mike Leach
2021-03-22 16:53     ` Suzuki K Poulose
2021-03-22 16:53       ` Suzuki K Poulose
2021-03-22 17:28       ` Rob Herring
2021-03-22 17:28         ` Rob Herring
2021-03-22 22:49         ` Suzuki K Poulose
2021-03-22 22:49           ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 16/19] coresight: etm-perf: Handle stale output handles Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 17/19] coresight: core: Add support for dedicated percpu sinks Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-02-26  6:34   ` kernel test robot
2021-02-26  6:34     ` kernel test robot
2021-02-26  6:34     ` kernel test robot
2021-03-01 13:54     ` Suzuki K Poulose
2021-03-01 13:54       ` Suzuki K Poulose
2021-03-01 13:54       ` Suzuki K Poulose
2021-03-02 10:21       ` Anshuman Khandual
2021-03-02 10:21         ` Anshuman Khandual
2021-03-02 10:21         ` Anshuman Khandual
2021-03-01 14:08   ` [PATCH v4.1 " Suzuki K Poulose
2021-03-01 14:08     ` Suzuki K Poulose
2021-03-08 17:26   ` [PATCH v4 " Mike Leach
2021-03-08 17:26     ` Mike Leach
2021-03-22 16:57     ` Suzuki K Poulose
2021-03-22 16:57       ` Suzuki K Poulose
2021-03-17 19:31   ` Mathieu Poirier
2021-03-17 19:31     ` Mathieu Poirier
2021-02-25 19:35 ` [PATCH v4 18/19] coresight: sink: Add TRBE driver Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-03-08 17:26   ` Mike Leach
2021-03-08 17:26     ` Mike Leach
2021-03-19 10:30     ` Suzuki K Poulose
2021-03-19 10:30       ` Suzuki K Poulose
2021-03-19 11:55       ` Mike Leach
2021-03-19 11:55         ` Mike Leach
2021-03-22 21:24         ` Mathieu Poirier
2021-03-22 21:24           ` Mathieu Poirier
2021-03-22 23:00           ` Suzuki K Poulose
2021-03-22 23:00             ` Suzuki K Poulose
2021-03-18 18:08   ` Mathieu Poirier
2021-03-18 18:08     ` Mathieu Poirier
2021-03-19 10:34     ` Suzuki K Poulose
2021-03-19 10:34       ` Suzuki K Poulose
2021-03-19 14:47       ` Mathieu Poirier
2021-03-19 14:47         ` Mathieu Poirier
2021-03-19 17:58   ` Mathieu Poirier
2021-03-19 17:58     ` Mathieu Poirier
2021-03-22 21:20   ` Mathieu Poirier
2021-03-22 21:20     ` Mathieu Poirier
2021-02-25 19:35 ` [PATCH v4 19/19] dts: bindings: Document device tree bindings for Arm TRBE Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210316202345.GE1387186@xps15 \
    --to=mathieu.poirier@linaro.org \
    --cc=anshuman.khandual@arm.com \
    --cc=lcherian@marvell.com \
    --cc=leo.yan@linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mike.leach@linaro.org \
    --cc=suzuki.poulose@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.