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From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, mike.leach@linaro.org,
	anshuman.khandual@arm.com, leo.yan@linaro.org
Subject: Re: [PATCH v4 18/19] coresight: sink: Add TRBE driver
Date: Mon, 22 Mar 2021 15:20:47 -0600	[thread overview]
Message-ID: <20210322212047.GA1684006@xps15> (raw)
In-Reply-To: <20210225193543.2920532-19-suzuki.poulose@arm.com>

On Thu, Feb 25, 2021 at 07:35:42PM +0000, Suzuki K Poulose wrote:
> From: Anshuman Khandual <anshuman.khandual@arm.com>
> 
> Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
> accessible via the system registers. The TRBE supports different addressing
> modes including CPU virtual address and buffer modes including the circular
> buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1),
> an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the
> access to the trace buffer could be prohibited by a higher exception level
> (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
> private interrupt (PPI) on address translation errors and when the buffer
> is full. Overall implementation here is inspired from the Arm SPE driver.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> Changes:
>  - Replaced TRBLIMITR_LIMIT_SHIFT with TRBBASER_BASE_SHIFT in set_trbe_base_pointer()
>  - Dropped TRBBASER_BASE_MASK and TRBBASER_BASE_SHIFT from get_trbe_base_pointer()
>  - Indentation changes for TRBE_BSC_NOT_[STOPPED|FILLED|TRIGGERED] definitions
>  - Moved DECLARE_PER_CPU(...., csdev_sink) into coresight-priv.h
>  - Moved isb() from trbe_enable_hw() into set_trbe_limit_pointer_enabled()
>  - Dropped the space after type casting before vmap()
>  - Return 0 instead of EINVAL in arm_trbe_update_buffer()
>  - Add a comment in trbe_handle_overflow()
>  - Add a comment in arm_trbe_cpu_startup()
>  - Unregister coresight TRBE device when not supported
>  - Fix potential NULL handle dereference in IRQ handler with a spurious IRQ
>  - Read TRBIDR after is_trbe_programmable() in arm_trbe_probe_coresight_cpu()
>  - Replaced and modified trbe_drain_and_disable_local() in IRQ handler
>  - Updated arm_trbe_update_buffer() for handling a missing interrupt
>  - Dropped kfree() for all devm_xxx() allocated buffer
>  - Dropped additional blank line in documentation coresight/coresight-trbe.rst
>  - Added Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe
>  - Changed CONFIG_CORESIGHT_TRBE options, dependencies and helper write up
>  - Added comment for irq_work_run()
>  - Updated comment for minumum buffer length in arm_trbe_alloc_buffer()
>  - Dropped redundant smp_processor_id() from arm_trbe_probe_coresight_cpu()
>  - Fixed indentation in arm_trbe_probe_cpuhp()
>  - Added static for arm_trbe_free_buffer()
>  - Added comment for trbe_base element in trbe_buf structure
>  - Dropped IS_ERR() check from vmap() returned pointer
>  - Added WARN_ON(trbe_csdev) in arm_trbe_probe_coresight_cpu()
>  - Changed TRBE device names from arm_trbeX to just trbeX
>  - Dropped unused argument perf_output_handle from trbe_get_fault_act()
>  - Dropped IS_ERR() from kzalloc_node()/kcalloc() buffer in arm_trbe_alloc_buffer()
>  - Dropped IS_ERR() and return -ENOMEM in arm_trbe_probe_coresight()
>  - Moved TRBE HW disabling before coresight cleanup in arm_trbe_remove_coresight_cpu()
>  - Changed error return codes from arm_trbe_probe_irq()
>  - Changed error return codes from arm_trbe_device_probe()
>  - Changed arm_trbe_remove_coresight() order in arm_trbe_device_remove()
>  - Changed TRBE CPU support probe/remove sequence with for_each_cpu() iterator
>  - Changed coresight_register() in arm_trbe_probe_coresight_cpu()
>  - Changed error return code when cpuhp_setup_state_multi() fails in arm_trbe_probe_cpuhp()
>  - Changed error return code when cpuhp_state_add_instance() fails in arm_trbe_probe_cpuhp()
>  - Changed trbe_dbm as trbe_flag including its sysfs interface
>  - Handle race between update_buffer & IRQ handler
>  - Rework and split the TRBE probe to avoid lockdep due to memory allocation
>    from IPI calls (via coresight_register())
>  - Fix handle->head updat for snapshot mode.

All of the above make this driver much easier to read.

> ---
>  .../testing/sysfs-bus-coresight-devices-trbe  |   14 +
>  .../trace/coresight/coresight-trbe.rst        |   38 +
>  drivers/hwtracing/coresight/Kconfig           |   14 +
>  drivers/hwtracing/coresight/Makefile          |    1 +
>  drivers/hwtracing/coresight/coresight-trbe.c  | 1149 +++++++++++++++++
>  drivers/hwtracing/coresight/coresight-trbe.h  |  153 +++
>  6 files changed, 1369 insertions(+)
>  create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe
>  create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h
>

[...]
 
> +
> +static void *arm_trbe_alloc_buffer(struct coresight_device *csdev,
> +				   struct perf_event *event, void **pages,
> +				   int nr_pages, bool snapshot)
> +{
> +	struct trbe_buf *buf;
> +	struct page **pglist;
> +	int i;
> +
> +	/*
> +	 * TRBE LIMIT and TRBE WRITE pointers must be page aligned. But with
> +	 * just a single page, there would not be any room left while writing
> +	 * into a partially filled TRBE buffer after the page size alignment.
> +	 * Hence restrict the minimum buffer size as two pages.
> +	 */
> +	if (nr_pages < 2)
> +		return NULL;
> +
> +	buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, trbe_alloc_node(event));
> +	if (!buf)
> +		return ERR_PTR(-ENOMEM);
> +
> +	pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
> +	if (!pglist) {
> +		kfree(buf);
> +		return ERR_PTR(-ENOMEM);
> +	}
> +
> +	for (i = 0; i < nr_pages; i++)
> +		pglist[i] = virt_to_page(pages[i]);
> +
> +	buf->trbe_base = (unsigned long)vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
> +	if (!buf->trbe_base) {
> +		kfree(pglist);
> +		kfree(buf);
> +		return ERR_PTR(buf->trbe_base);

return ERR_PTR(-ENOMEM); 

> +	}
> +	buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE;
> +	buf->trbe_write = buf->trbe_base;
> +	buf->snapshot = snapshot;
> +	buf->nr_pages = nr_pages;
> +	buf->pages = pages;
> +	kfree(pglist);
> +	return buf;
> +}
> +

WARNING: multiple messages have this Message-ID (diff)
From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, mike.leach@linaro.org,
	anshuman.khandual@arm.com, leo.yan@linaro.org
Subject: Re: [PATCH v4 18/19] coresight: sink: Add TRBE driver
Date: Mon, 22 Mar 2021 15:20:47 -0600	[thread overview]
Message-ID: <20210322212047.GA1684006@xps15> (raw)
In-Reply-To: <20210225193543.2920532-19-suzuki.poulose@arm.com>

On Thu, Feb 25, 2021 at 07:35:42PM +0000, Suzuki K Poulose wrote:
> From: Anshuman Khandual <anshuman.khandual@arm.com>
> 
> Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
> accessible via the system registers. The TRBE supports different addressing
> modes including CPU virtual address and buffer modes including the circular
> buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1),
> an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the
> access to the trace buffer could be prohibited by a higher exception level
> (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
> private interrupt (PPI) on address translation errors and when the buffer
> is full. Overall implementation here is inspired from the Arm SPE driver.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> Changes:
>  - Replaced TRBLIMITR_LIMIT_SHIFT with TRBBASER_BASE_SHIFT in set_trbe_base_pointer()
>  - Dropped TRBBASER_BASE_MASK and TRBBASER_BASE_SHIFT from get_trbe_base_pointer()
>  - Indentation changes for TRBE_BSC_NOT_[STOPPED|FILLED|TRIGGERED] definitions
>  - Moved DECLARE_PER_CPU(...., csdev_sink) into coresight-priv.h
>  - Moved isb() from trbe_enable_hw() into set_trbe_limit_pointer_enabled()
>  - Dropped the space after type casting before vmap()
>  - Return 0 instead of EINVAL in arm_trbe_update_buffer()
>  - Add a comment in trbe_handle_overflow()
>  - Add a comment in arm_trbe_cpu_startup()
>  - Unregister coresight TRBE device when not supported
>  - Fix potential NULL handle dereference in IRQ handler with a spurious IRQ
>  - Read TRBIDR after is_trbe_programmable() in arm_trbe_probe_coresight_cpu()
>  - Replaced and modified trbe_drain_and_disable_local() in IRQ handler
>  - Updated arm_trbe_update_buffer() for handling a missing interrupt
>  - Dropped kfree() for all devm_xxx() allocated buffer
>  - Dropped additional blank line in documentation coresight/coresight-trbe.rst
>  - Added Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe
>  - Changed CONFIG_CORESIGHT_TRBE options, dependencies and helper write up
>  - Added comment for irq_work_run()
>  - Updated comment for minumum buffer length in arm_trbe_alloc_buffer()
>  - Dropped redundant smp_processor_id() from arm_trbe_probe_coresight_cpu()
>  - Fixed indentation in arm_trbe_probe_cpuhp()
>  - Added static for arm_trbe_free_buffer()
>  - Added comment for trbe_base element in trbe_buf structure
>  - Dropped IS_ERR() check from vmap() returned pointer
>  - Added WARN_ON(trbe_csdev) in arm_trbe_probe_coresight_cpu()
>  - Changed TRBE device names from arm_trbeX to just trbeX
>  - Dropped unused argument perf_output_handle from trbe_get_fault_act()
>  - Dropped IS_ERR() from kzalloc_node()/kcalloc() buffer in arm_trbe_alloc_buffer()
>  - Dropped IS_ERR() and return -ENOMEM in arm_trbe_probe_coresight()
>  - Moved TRBE HW disabling before coresight cleanup in arm_trbe_remove_coresight_cpu()
>  - Changed error return codes from arm_trbe_probe_irq()
>  - Changed error return codes from arm_trbe_device_probe()
>  - Changed arm_trbe_remove_coresight() order in arm_trbe_device_remove()
>  - Changed TRBE CPU support probe/remove sequence with for_each_cpu() iterator
>  - Changed coresight_register() in arm_trbe_probe_coresight_cpu()
>  - Changed error return code when cpuhp_setup_state_multi() fails in arm_trbe_probe_cpuhp()
>  - Changed error return code when cpuhp_state_add_instance() fails in arm_trbe_probe_cpuhp()
>  - Changed trbe_dbm as trbe_flag including its sysfs interface
>  - Handle race between update_buffer & IRQ handler
>  - Rework and split the TRBE probe to avoid lockdep due to memory allocation
>    from IPI calls (via coresight_register())
>  - Fix handle->head updat for snapshot mode.

All of the above make this driver much easier to read.

> ---
>  .../testing/sysfs-bus-coresight-devices-trbe  |   14 +
>  .../trace/coresight/coresight-trbe.rst        |   38 +
>  drivers/hwtracing/coresight/Kconfig           |   14 +
>  drivers/hwtracing/coresight/Makefile          |    1 +
>  drivers/hwtracing/coresight/coresight-trbe.c  | 1149 +++++++++++++++++
>  drivers/hwtracing/coresight/coresight-trbe.h  |  153 +++
>  6 files changed, 1369 insertions(+)
>  create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe
>  create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h
>

[...]
 
> +
> +static void *arm_trbe_alloc_buffer(struct coresight_device *csdev,
> +				   struct perf_event *event, void **pages,
> +				   int nr_pages, bool snapshot)
> +{
> +	struct trbe_buf *buf;
> +	struct page **pglist;
> +	int i;
> +
> +	/*
> +	 * TRBE LIMIT and TRBE WRITE pointers must be page aligned. But with
> +	 * just a single page, there would not be any room left while writing
> +	 * into a partially filled TRBE buffer after the page size alignment.
> +	 * Hence restrict the minimum buffer size as two pages.
> +	 */
> +	if (nr_pages < 2)
> +		return NULL;
> +
> +	buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, trbe_alloc_node(event));
> +	if (!buf)
> +		return ERR_PTR(-ENOMEM);
> +
> +	pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
> +	if (!pglist) {
> +		kfree(buf);
> +		return ERR_PTR(-ENOMEM);
> +	}
> +
> +	for (i = 0; i < nr_pages; i++)
> +		pglist[i] = virt_to_page(pages[i]);
> +
> +	buf->trbe_base = (unsigned long)vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
> +	if (!buf->trbe_base) {
> +		kfree(pglist);
> +		kfree(buf);
> +		return ERR_PTR(buf->trbe_base);

return ERR_PTR(-ENOMEM); 

> +	}
> +	buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE;
> +	buf->trbe_write = buf->trbe_base;
> +	buf->snapshot = snapshot;
> +	buf->nr_pages = nr_pages;
> +	buf->pages = pages;
> +	kfree(pglist);
> +	return buf;
> +}
> +

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  parent reply	other threads:[~2021-03-22 21:21 UTC|newest]

Thread overview: 132+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-25 19:35 [PATCH v4 00/19] arm64: coresight: Add support for ETE and TRBE Suzuki K Poulose
2021-02-25 19:35 ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 01/19] perf: aux: Add flags for the buffer format Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 02/19] perf: aux: Add CoreSight PMU buffer formats Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-03-16 17:04   ` Mathieu Poirier
2021-03-16 17:04     ` Mathieu Poirier
2021-03-22 12:29     ` Suzuki K Poulose
2021-03-22 12:29       ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 03/19] kvm: arm64: Hide system instruction access to Trace registers Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-03-22 22:21   ` Suzuki K Poulose
2021-03-22 22:21     ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 04/19] kvm: arm64: nvhe: Save the SPE context early Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-03-01 16:32   ` Alexandru Elisei
2021-03-01 16:32     ` Alexandru Elisei
2021-03-02 10:01     ` Suzuki K Poulose
2021-03-02 10:01       ` Suzuki K Poulose
2021-03-02 10:13       ` Marc Zyngier
2021-03-02 10:13         ` Marc Zyngier
2021-03-02 11:00       ` Alexandru Elisei
2021-03-02 11:00         ` Alexandru Elisei
2021-02-25 19:35 ` [PATCH v4 05/19] kvm: arm64: Disable guest access to trace filter controls Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-03-22 22:24   ` Suzuki K Poulose
2021-03-22 22:24     ` Suzuki K Poulose
2021-03-23  9:16     ` Marc Zyngier
2021-03-23  9:16       ` Marc Zyngier
2021-03-23  9:44       ` Suzuki K Poulose
2021-03-23  9:44         ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 06/19] arm64: Add support for trace synchronization barrier Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 07/19] arm64: Add TRBE definitions Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-03-16 17:46   ` Mathieu Poirier
2021-03-16 17:46     ` Mathieu Poirier
2021-02-25 19:35 ` [PATCH v4 08/19] arm64: kvm: Enable access to TRBE support for host Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-03-16 17:49   ` Mathieu Poirier
2021-03-16 17:49     ` Mathieu Poirier
2021-02-25 19:35 ` [PATCH v4 09/19] coresight: etm4x: Move ETM to prohibited region for disable Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-03-08 17:25   ` Mike Leach
2021-03-08 17:25     ` Mike Leach
2021-03-16 19:30   ` Mathieu Poirier
2021-03-16 19:30     ` Mathieu Poirier
2021-03-17 10:44     ` Suzuki K Poulose
2021-03-17 10:44       ` Suzuki K Poulose
2021-03-17 17:09       ` Mathieu Poirier
2021-03-17 17:09         ` Mathieu Poirier
2021-03-22 21:28   ` Mathieu Poirier
2021-03-22 21:28     ` Mathieu Poirier
2021-02-25 19:35 ` [PATCH v4 10/19] coresight: etm-perf: Allow an event to use different sinks Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-03-08 17:25   ` Mike Leach
2021-03-08 17:25     ` Mike Leach
2021-03-16 20:23   ` Mathieu Poirier
2021-03-16 20:23     ` Mathieu Poirier
2021-03-17 10:47     ` Suzuki K Poulose
2021-03-17 10:47       ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 11/19] coresight: Do not scan for graph if none is present Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 12/19] coresight: etm4x: Add support for PE OS lock Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 13/19] coresight: ete: Add support for ETE sysreg access Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-02-25 22:33   ` kernel test robot
2021-02-25 22:33     ` kernel test robot
2021-02-25 22:33     ` kernel test robot
2021-02-26  6:25   ` kernel test robot
2021-02-26  6:25     ` kernel test robot
2021-02-25 19:35 ` [PATCH v4 14/19] coresight: ete: Add support for ETE tracing Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 15/19] dts: bindings: Document device tree bindings for ETE Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-03-06 21:06   ` Rob Herring
2021-03-06 21:06     ` Rob Herring
2021-03-08 17:25     ` Mike Leach
2021-03-08 17:25       ` Mike Leach
2021-03-22 16:53     ` Suzuki K Poulose
2021-03-22 16:53       ` Suzuki K Poulose
2021-03-22 17:28       ` Rob Herring
2021-03-22 17:28         ` Rob Herring
2021-03-22 22:49         ` Suzuki K Poulose
2021-03-22 22:49           ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 16/19] coresight: etm-perf: Handle stale output handles Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-02-25 19:35 ` [PATCH v4 17/19] coresight: core: Add support for dedicated percpu sinks Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-02-26  6:34   ` kernel test robot
2021-02-26  6:34     ` kernel test robot
2021-02-26  6:34     ` kernel test robot
2021-03-01 13:54     ` Suzuki K Poulose
2021-03-01 13:54       ` Suzuki K Poulose
2021-03-01 13:54       ` Suzuki K Poulose
2021-03-02 10:21       ` Anshuman Khandual
2021-03-02 10:21         ` Anshuman Khandual
2021-03-02 10:21         ` Anshuman Khandual
2021-03-01 14:08   ` [PATCH v4.1 " Suzuki K Poulose
2021-03-01 14:08     ` Suzuki K Poulose
2021-03-08 17:26   ` [PATCH v4 " Mike Leach
2021-03-08 17:26     ` Mike Leach
2021-03-22 16:57     ` Suzuki K Poulose
2021-03-22 16:57       ` Suzuki K Poulose
2021-03-17 19:31   ` Mathieu Poirier
2021-03-17 19:31     ` Mathieu Poirier
2021-02-25 19:35 ` [PATCH v4 18/19] coresight: sink: Add TRBE driver Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose
2021-03-08 17:26   ` Mike Leach
2021-03-08 17:26     ` Mike Leach
2021-03-19 10:30     ` Suzuki K Poulose
2021-03-19 10:30       ` Suzuki K Poulose
2021-03-19 11:55       ` Mike Leach
2021-03-19 11:55         ` Mike Leach
2021-03-22 21:24         ` Mathieu Poirier
2021-03-22 21:24           ` Mathieu Poirier
2021-03-22 23:00           ` Suzuki K Poulose
2021-03-22 23:00             ` Suzuki K Poulose
2021-03-18 18:08   ` Mathieu Poirier
2021-03-18 18:08     ` Mathieu Poirier
2021-03-19 10:34     ` Suzuki K Poulose
2021-03-19 10:34       ` Suzuki K Poulose
2021-03-19 14:47       ` Mathieu Poirier
2021-03-19 14:47         ` Mathieu Poirier
2021-03-19 17:58   ` Mathieu Poirier
2021-03-19 17:58     ` Mathieu Poirier
2021-03-22 21:20   ` Mathieu Poirier [this message]
2021-03-22 21:20     ` Mathieu Poirier
2021-02-25 19:35 ` [PATCH v4 19/19] dts: bindings: Document device tree bindings for Arm TRBE Suzuki K Poulose
2021-02-25 19:35   ` Suzuki K Poulose

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