* [PATCH 01/26] tools: imx image: fix write warning
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
@ 2021-03-19 7:56 ` Peng Fan
2021-03-19 7:56 ` [PATCH 02/26] imx8mm_evk: Update to latest LPDDR4 script Peng Fan
` (24 subsequent siblings)
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:56 UTC (permalink / raw)
To: u-boot
From: Peng Fan <peng.fan@nxp.com>
Fix the warning by set the variable zero to uint64_t
"warning: ?write? reading 5 bytes from a region of size 4"
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
tools/imx8image.c | 2 +-
tools/imx8mimage.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/imx8image.c b/tools/imx8image.c
index 133780f5ea..fa8f227487 100644
--- a/tools/imx8image.c
+++ b/tools/imx8image.c
@@ -365,7 +365,7 @@ static void copy_file (int ifd, const char *datafile, int pad, int offset)
struct stat sbuf;
unsigned char *ptr;
int tail;
- int zero = 0;
+ uint64_t zero = 0;
uint8_t zeros[4096];
int size, ret;
diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c
index 9985b95a98..11e40ccd94 100644
--- a/tools/imx8mimage.c
+++ b/tools/imx8mimage.c
@@ -248,7 +248,7 @@ static void copy_file(int ifd, const char *datafile, int pad, int offset,
struct stat sbuf;
unsigned char *ptr;
int tail;
- int zero = 0;
+ uint64_t zero = 0;
uint8_t zeros[4096];
int size, ret;
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 02/26] imx8mm_evk: Update to latest LPDDR4 script
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
2021-03-19 7:56 ` [PATCH 01/26] tools: imx image: fix write warning Peng Fan
@ 2021-03-19 7:56 ` Peng Fan
2021-03-24 21:19 ` Tim Harvey
2021-03-19 7:56 ` [PATCH 03/26] imx8mm_evk: Switch to new imx8mm evk board Peng Fan
` (23 subsequent siblings)
25 siblings, 1 reply; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:56 UTC (permalink / raw)
To: u-boot
From: Ye Li <ye.li@nxp.com>
Update LPDDR4 script to sync with v2020.04 u-boot
Signed-off-by: Ye Li <ye.li@nxp.com>
---
board/freescale/imx8mm_evk/lpddr4_timing.c | 692 +++++++++------------
1 file changed, 280 insertions(+), 412 deletions(-)
diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c b/board/freescale/imx8mm_evk/lpddr4_timing.c
index 8e48b9d81b..4373ca624e 100644
--- a/board/freescale/imx8mm_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mm_evk/lpddr4_timing.c
@@ -1,129 +1,162 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2018-2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
*/
#include <linux/kernel.h>
-#include <common.h>
#include <asm/arch/ddr.h>
-#include <asm/arch/lpddr4_define.h>
-struct dram_cfg_param lpddr4_ddrc_cfg[] = {
- /* Start to config, default 3200mbps */
- { DDRC_DBG1(0), 0x00000001 },
- { DDRC_PWRCTL(0), 0x00000001 },
- { DDRC_MSTR(0), 0xa1080020 },
- { DDRC_RFSHTMG(0), 0x005b00d2 },
- { DDRC_INIT0(0), 0xC003061B },
- { DDRC_INIT1(0), 0x009D0000 },
- { DDRC_INIT3(0), 0x00D4002D },
- { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
- { DDRC_INIT6(0), 0x0066004a },
- { DDRC_INIT7(0), 0x0006004a },
-
- { DDRC_DRAMTMG0(0), 0x1A201B22 },
- { DDRC_DRAMTMG1(0), 0x00060633 },
- { DDRC_DRAMTMG3(0), 0x00C0C000 },
- { DDRC_DRAMTMG4(0), 0x0F04080F },
- { DDRC_DRAMTMG5(0), 0x02040C0C },
- { DDRC_DRAMTMG6(0), 0x01010007 },
- { DDRC_DRAMTMG7(0), 0x00000401 },
- { DDRC_DRAMTMG12(0), 0x00020600 },
- { DDRC_DRAMTMG13(0), 0x0C100002 },
- { DDRC_DRAMTMG14(0), 0x000000E6 },
- { DDRC_DRAMTMG17(0), 0x00A00050 },
-
- { DDRC_ZQCTL0(0), 0x03200018 },
- { DDRC_ZQCTL1(0), 0x028061A8 },
- { DDRC_ZQCTL2(0), 0x00000000 },
-
- { DDRC_DFITMG0(0), 0x0497820A },
- { DDRC_DFITMG2(0), 0x0000170A },
- { DDRC_DRAMTMG2(0), 0x070E171a },
- { DDRC_DBICTL(0), 0x00000001 },
-
- { DDRC_DFITMG1(0), 0x00080303 },
- { DDRC_DFIUPD0(0), 0xE0400018 },
- { DDRC_DFIUPD1(0), 0x00DF00E4 },
- { DDRC_DFIUPD2(0), 0x80000000 },
- { DDRC_DFIMISC(0), 0x00000011 },
-
- { DDRC_DFIPHYMSTR(0), 0x00000000 },
- { DDRC_RANKCTL(0), 0x00000c99 },
-
- /* address mapping */
- { DDRC_ADDRMAP0(0), 0x0000001f },
- { DDRC_ADDRMAP1(0), 0x00080808 },
- { DDRC_ADDRMAP2(0), 0x00000000 },
- { DDRC_ADDRMAP3(0), 0x00000000 },
- { DDRC_ADDRMAP4(0), 0x00001f1f },
- { DDRC_ADDRMAP5(0), 0x07070707 },
- { DDRC_ADDRMAP6(0), 0x07070707 },
- { DDRC_ADDRMAP7(0), 0x00000f0f },
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /* Initialize DDRC registers */
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa1080020 },
+ { 0x3d400020, 0x223 },
+ { 0x3d400024, 0x16e3600 },
+ { 0x3d400064, 0x5b00d2 },
+ { 0x3d4000d0, 0xc00305ba },
+ { 0x3d4000d4, 0x940000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310000 },
+ { 0x3d4000e8, 0x66004d },
+ { 0x3d4000ec, 0x16004d },
+ { 0x3d400100, 0x191e1920 },
+ { 0x3d400104, 0x60630 },
+ { 0x3d40010c, 0xb0b000 },
+ { 0x3d400110, 0xe04080e },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0xd8 },
+ { 0x3d400144, 0x96004b },
+ { 0x3d400180, 0x2ee0017 },
+ { 0x3d400184, 0x2605b8e },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x0 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x1f },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
/* performance setting */
- { DDRC_SCHED(0), 0x29001701 },
- { DDRC_SCHED1(0), 0x0000002c },
- { DDRC_PERFHPR1(0), 0x04000030 },
- { DDRC_PERFLPR1(0), 0x900093e7 },
- { DDRC_PERFWR1(0), 0x20005574 },
- { DDRC_PCCFG(0), 0x00000111 },
- { DDRC_PCFGW_0(0), 0x000072ff },
- { DDRC_PCFGQOS0_0(0), 0x02100e07 },
- { DDRC_PCFGQOS1_0(0), 0x00620096 },
- { DDRC_PCFGWQOS0_0(0), 0x01100e07 },
- { DDRC_PCFGWQOS1_0(0), 0x00c8012c },
+ { 0x3d400250, 0x29001701 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
- /* frequency P1&P2 */
- /* Frequency 1: 400mbps */
- { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
- { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
- { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c },
- { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
- { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
- { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
- { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
- { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
- { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
- { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
- { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
- { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
- { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
- { DDRC_FREQ1_DFITMG2(0), 0x00000000 },
- { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
- { DDRC_FREQ1_INIT3(0), 0x00840000 },
- { DDRC_FREQ1_INIT4(0), 0x00310000 },
- { DDRC_FREQ1_INIT6(0), 0x0066004a },
- { DDRC_FREQ1_INIT7(0), 0x0006004a },
+ /* P1: 400mts */
+ { 0x3d402020, 0x21 },
+ { 0x3d402024, 0x30d400 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0xc001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004d },
+ { 0x3d4020ec, 0x16004d },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
- /* Frequency 2: 100mbps */
- { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
- { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
- { DDRC_FREQ2_DRAMTMG2(0), 0x0203090c },
- { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
- { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
- { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
- { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
- { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
- { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
- { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
- { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
- { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
- { DDRC_FREQ2_DFITMG2(0), 0x00000000 },
- { DDRC_FREQ2_RFSHTMG(0), 0x0003800c },
- { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
- { DDRC_FREQ2_INIT3(0), 0x00840000 },
- { DDRC_FREQ2_INIT4(0), 0x00310008 },
- { DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
- { DDRC_FREQ2_INIT6(0), 0x0066004a },
- { DDRC_FREQ2_INIT7(0), 0x0006004a },
+ /* p2: 100mts */
+ { 0x3d403020, 0x21 },
+ { 0x3d403024, 0xc3500 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x310000 },
+ { 0x3d4030e8, 0x66004d },
+ { 0x3d4030ec, 0x16004d },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
- /* boot start point */
- { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
+ /* default boot point */
+ { 0x3d400028, 0x0 },
};
/* PHY Initialize Configuration */
-struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
{ 0x1005f, 0x1ff },
{ 0x1015f, 0x1ff },
{ 0x1105f, 0x1ff },
@@ -132,7 +165,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x1215f, 0x1ff },
{ 0x1305f, 0x1ff },
{ 0x1315f, 0x1ff },
-
{ 0x11005f, 0x1ff },
{ 0x11015f, 0x1ff },
{ 0x11105f, 0x1ff },
@@ -141,7 +173,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x11215f, 0x1ff },
{ 0x11305f, 0x1ff },
{ 0x11315f, 0x1ff },
-
{ 0x21005f, 0x1ff },
{ 0x21015f, 0x1ff },
{ 0x21105f, 0x1ff },
@@ -150,7 +181,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x21215f, 0x1ff },
{ 0x21305f, 0x1ff },
{ 0x21315f, 0x1ff },
-
{ 0x55, 0x1ff },
{ 0x1055, 0x1ff },
{ 0x2055, 0x1ff },
@@ -161,32 +191,24 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x7055, 0x1ff },
{ 0x8055, 0x1ff },
{ 0x9055, 0x1ff },
-
{ 0x200c5, 0x19 },
{ 0x1200c5, 0x7 },
{ 0x2200c5, 0x7 },
-
{ 0x2002e, 0x2 },
{ 0x12002e, 0x2 },
{ 0x22002e, 0x2 },
-
{ 0x90204, 0x0 },
{ 0x190204, 0x0 },
{ 0x290204, 0x0 },
-
- { 0x20024, 0xab },
+ { 0x20024, 0x1ab },
{ 0x2003a, 0x0 },
-
- { 0x120024, 0xab },
+ { 0x120024, 0x1ab },
{ 0x2003a, 0x0 },
-
- { 0x220024, 0xab },
+ { 0x220024, 0x1ab },
{ 0x2003a, 0x0 },
-
{ 0x20056, 0x3 },
{ 0x120056, 0xa },
{ 0x220056, 0xa },
-
{ 0x1004d, 0xe00 },
{ 0x1014d, 0xe00 },
{ 0x1104d, 0xe00 },
@@ -195,7 +217,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x1214d, 0xe00 },
{ 0x1304d, 0xe00 },
{ 0x1314d, 0xe00 },
-
{ 0x11004d, 0xe00 },
{ 0x11014d, 0xe00 },
{ 0x11104d, 0xe00 },
@@ -204,7 +225,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x11214d, 0xe00 },
{ 0x11304d, 0xe00 },
{ 0x11314d, 0xe00 },
-
{ 0x21004d, 0xe00 },
{ 0x21014d, 0xe00 },
{ 0x21104d, 0xe00 },
@@ -213,34 +233,30 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x21214d, 0xe00 },
{ 0x21304d, 0xe00 },
{ 0x21314d, 0xe00 },
-
- { 0x10049, 0xfbe },
- { 0x10149, 0xfbe },
- { 0x11049, 0xfbe },
- { 0x11149, 0xfbe },
- { 0x12049, 0xfbe },
- { 0x12149, 0xfbe },
- { 0x13049, 0xfbe },
- { 0x13149, 0xfbe },
-
- { 0x110049, 0xfbe },
- { 0x110149, 0xfbe },
- { 0x111049, 0xfbe },
- { 0x111149, 0xfbe },
- { 0x112049, 0xfbe },
- { 0x112149, 0xfbe },
- { 0x113049, 0xfbe },
- { 0x113149, 0xfbe },
-
- { 0x210049, 0xfbe },
- { 0x210149, 0xfbe },
- { 0x211049, 0xfbe },
- { 0x211149, 0xfbe },
- { 0x212049, 0xfbe },
- { 0x212149, 0xfbe },
- { 0x213049, 0xfbe },
- { 0x213149, 0xfbe },
-
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
{ 0x43, 0x63 },
{ 0x1043, 0x63 },
{ 0x2043, 0x63 },
@@ -251,7 +267,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x7043, 0x63 },
{ 0x8043, 0x63 },
{ 0x9043, 0x63 },
-
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
@@ -259,8 +274,7 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x120008, 0x64 },
{ 0x220008, 0x19 },
{ 0x20088, 0x9 },
-
- { 0x200b2, 0x1d4 },
+ { 0x200b2, 0xdc },
{ 0x10043, 0x5a1 },
{ 0x10143, 0x5a1 },
{ 0x11043, 0x5a1 },
@@ -269,7 +283,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x12143, 0x5a1 },
{ 0x13043, 0x5a1 },
{ 0x13143, 0x5a1 },
-
{ 0x1200b2, 0xdc },
{ 0x110043, 0x5a1 },
{ 0x110143, 0x5a1 },
@@ -279,7 +292,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x112143, 0x5a1 },
{ 0x113043, 0x5a1 },
{ 0x113143, 0x5a1 },
-
{ 0x2200b2, 0xdc },
{ 0x210043, 0x5a1 },
{ 0x210143, 0x5a1 },
@@ -289,15 +301,12 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x212143, 0x5a1 },
{ 0x213043, 0x5a1 },
{ 0x213143, 0x5a1 },
-
{ 0x200fa, 0x1 },
{ 0x1200fa, 0x1 },
{ 0x2200fa, 0x1 },
-
{ 0x20019, 0x1 },
{ 0x120019, 0x1 },
{ 0x220019, 0x1 },
-
{ 0x200f0, 0x660 },
{ 0x200f1, 0x0 },
{ 0x200f2, 0x4444 },
@@ -306,21 +315,20 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x200f5, 0x0 },
{ 0x200f6, 0x0 },
{ 0x200f7, 0xf000 },
-
{ 0x20025, 0x0 },
- { 0x2002d, LPDDR4_PHY_DMIPinPresent },
- { 0x12002d, LPDDR4_PHY_DMIPinPresent },
- { 0x22002d, LPDDR4_PHY_DMIPinPresent },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
{ 0x200c7, 0x21 },
- { 0x200ca, 0x24 },
{ 0x1200c7, 0x21 },
- { 0x1200ca, 0x24 },
{ 0x2200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x1200ca, 0x24 },
{ 0x2200ca, 0x24 },
};
/* ddr phy trained csr */
-struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
{ 0x200b2, 0x0 },
{ 0x1200b2, 0x0 },
{ 0x2200b2, 0x0 },
@@ -1041,309 +1049,164 @@ struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
{ 0x13730, 0x0 },
{ 0x13830, 0x0 },
};
-
/* P0 message block paremeter for training firmware */
-struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54000, 0x0 },
- { 0x54001, 0x0 },
- { 0x54002, 0x0 },
{ 0x54003, 0xbb8 },
{ 0x54004, 0x2 },
- { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
- { 0x54006, LPDDR4_PHY_VREF_VALUE },
- { 0x54007, 0x0 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
{ 0x54008, 0x131f },
{ 0x54009, 0xc8 },
- { 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
- { 0x5400c, 0x0 },
- { 0x5400d, 0x0 },
- { 0x5400e, 0x0 },
- { 0x5400f, 0x0 },
- { 0x54010, 0x0 },
- { 0x54011, 0x0 },
- { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
- { 0x54013, 0x0 },
- { 0x54014, 0x0 },
- { 0x54015, 0x0 },
- { 0x54016, 0x0 },
- { 0x54017, 0x0 },
- { 0x54018, 0x0 },
+ { 0x54012, 0x110 },
{ 0x54019, 0x2dd4 },
- { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x5401a, 0x31 },
{ 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d08 },
- { 0x5401d, 0x0 },
- { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
{ 0x5401f, 0x2dd4 },
- { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x54020, 0x31 },
{ 0x54021, 0x4d66 },
- { 0x54022, 0x4d08 },
- { 0x54023, 0x0 },
- { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
- { 0x54025, 0x0 },
- { 0x54026, 0x0 },
- { 0x54027, 0x0 },
- { 0x54028, 0x0 },
- { 0x54029, 0x0 },
- { 0x5402a, 0x0 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
- { 0x5402c, LPDDR4_CS },
- { 0x5402d, 0x0 },
- { 0x5402e, 0x0 },
- { 0x5402f, 0x0 },
- { 0x54030, 0x0 },
- { 0x54031, 0x0 },
+ { 0x5402c, 0x1 },
{ 0x54032, 0xd400 },
- { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+ { 0x54033, 0x312d },
{ 0x54034, 0x6600 },
- { 0x54035, 0x84d },
+ { 0x54035, 0x4d },
{ 0x54036, 0x4d },
- { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+ { 0x54037, 0x1600 },
{ 0x54038, 0xd400 },
- { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+ { 0x54039, 0x312d },
{ 0x5403a, 0x6600 },
- { 0x5403b, 0x84d },
+ { 0x5403b, 0x4d },
{ 0x5403c, 0x4d },
- { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
- { 0x5403e, 0x0 },
- { 0x5403f, 0x0 },
- { 0x54040, 0x0 },
- { 0x54041, 0x0 },
- { 0x54042, 0x0 },
- { 0x54043, 0x0 },
- { 0x54044, 0x0 },
+ { 0x5403d, 0x1600 },
{ 0xd0000, 0x1 },
};
/* P1 message block paremeter for training firmware */
-struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54000, 0x0 },
- { 0x54001, 0x0 },
{ 0x54002, 0x101 },
{ 0x54003, 0x190 },
{ 0x54004, 0x2 },
- { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },/* PHY Ron/Rtt */
- { 0x54006, LPDDR4_PHY_VREF_VALUE },
- { 0x54007, 0x0 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
{ 0x54008, 0x121f },
{ 0x54009, 0xc8 },
- { 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
- { 0x5400c, 0x0 },
- { 0x5400d, 0x0 },
- { 0x5400e, 0x0 },
- { 0x5400f, 0x0 },
- { 0x54010, 0x0 },
- { 0x54011, 0x0 },
- { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
- { 0x54013, 0x0 },
- { 0x54014, 0x0 },
- { 0x54015, 0x0 },
- { 0x54016, 0x0 },
- { 0x54017, 0x0 },
- { 0x54018, 0x0 },
+ { 0x54012, 0x110 },
{ 0x54019, 0x84 },
- { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x5401a, 0x31 },
{ 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d08 },
- { 0x5401d, 0x0 },
- { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x54020, 0x31 },
{ 0x54021, 0x4d66 },
- { 0x54022, 0x4d08 },
- { 0x54023, 0x0 },
- { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
- { 0x54025, 0x0 },
- { 0x54026, 0x0 },
- { 0x54027, 0x0 },
- { 0x54028, 0x0 },
- { 0x54029, 0x0 },
- { 0x5402a, 0x0 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
- { 0x5402c, LPDDR4_CS },
- { 0x5402d, 0x0 },
- { 0x5402e, 0x0 },
- { 0x5402f, 0x0 },
- { 0x54030, 0x0 },
- { 0x54031, 0x0 },
+ { 0x5402c, 0x1 },
{ 0x54032, 0x8400 },
- { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+ { 0x54033, 0x3100 },
{ 0x54034, 0x6600 },
- { 0x54035, 0x84d },
+ { 0x54035, 0x4d },
{ 0x54036, 0x4d },
- { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+ { 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+ { 0x54039, 0x3100 },
{ 0x5403a, 0x6600 },
- { 0x5403b, 0x84d },
+ { 0x5403b, 0x4d },
{ 0x5403c, 0x4d },
- { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
- { 0x5403e, 0x0 },
- { 0x5403f, 0x0 },
- { 0x54040, 0x0 },
- { 0x54041, 0x0 },
- { 0x54042, 0x0 },
- { 0x54043, 0x0 },
- { 0x54044, 0x0 },
+ { 0x5403d, 0x1600 },
{ 0xd0000, 0x1 },
};
-/* P1 message block paremeter for training firmware */
-struct dram_cfg_param lpddr4_fsp2_cfg[] = {
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54000, 0x0 },
- { 0x54001, 0x0 },
{ 0x54002, 0x102 },
{ 0x54003, 0x64 },
{ 0x54004, 0x2 },
- { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
- { 0x54006, LPDDR4_PHY_VREF_VALUE },
- { 0x54007, 0x0 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
{ 0x54008, 0x121f },
{ 0x54009, 0xc8 },
- { 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
- { 0x5400c, 0x0 },
- { 0x5400d, 0x0 },
- { 0x5400e, 0x0 },
- { 0x5400f, 0x0 },
- { 0x54010, 0x0 },
- { 0x54011, 0x0 },
- { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
- { 0x54013, 0x0 },
- { 0x54014, 0x0 },
- { 0x54015, 0x0 },
- { 0x54016, 0x0 },
- { 0x54017, 0x0 },
- { 0x54018, 0x0 },
+ { 0x54012, 0x110 },
{ 0x54019, 0x84 },
- { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x5401a, 0x31 },
{ 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d08 },
- { 0x5401d, 0x0 },
- { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x54020, 0x31 },
{ 0x54021, 0x4d66 },
- { 0x54022, 0x4d08 },
- { 0x54023, 0x0 },
- { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
- { 0x54025, 0x0 },
- { 0x54026, 0x0 },
- { 0x54027, 0x0 },
- { 0x54028, 0x0 },
- { 0x54029, 0x0 },
- { 0x5402a, 0x0 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
- { 0x5402c, LPDDR4_CS },
- { 0x5402d, 0x0 },
- { 0x5402e, 0x0 },
- { 0x5402f, 0x0 },
- { 0x54030, 0x0 },
- { 0x54031, 0x0 },
+ { 0x5402c, 0x1 },
{ 0x54032, 0x8400 },
- { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+ { 0x54033, 0x3100 },
{ 0x54034, 0x6600 },
- { 0x54035, 0x84d },
+ { 0x54035, 0x4d },
{ 0x54036, 0x4d },
- { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+ { 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+ { 0x54039, 0x3100 },
{ 0x5403a, 0x6600 },
- { 0x5403b, 0x84d },
+ { 0x5403b, 0x4d },
{ 0x5403c, 0x4d },
- { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
- { 0x5403e, 0x0 },
- { 0x5403f, 0x0 },
- { 0x54040, 0x0 },
- { 0x54041, 0x0 },
- { 0x54042, 0x0 },
- { 0x54043, 0x0 },
- { 0x54044, 0x0 },
+ { 0x5403d, 0x1600 },
{ 0xd0000, 0x1 },
};
/* P0 2D message block paremeter for training firmware */
-struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54000, 0x0 },
- { 0x54001, 0x0 },
- { 0x54002, 0x0 },
{ 0x54003, 0xbb8 },
{ 0x54004, 0x2 },
- { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
- { 0x54006, LPDDR4_PHY_VREF_VALUE },
- { 0x54007, 0x0 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
{ 0x54008, 0x61 },
{ 0x54009, 0xc8 },
- { 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
- { 0x5400c, 0x0 },
- { 0x5400d, 0x0 },
- { 0x5400e, 0x0 },
{ 0x5400f, 0x100 },
{ 0x54010, 0x1f7f },
- { 0x54011, 0x0 },
- { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
- { 0x54013, 0x0 },
- { 0x54014, 0x0 },
- { 0x54015, 0x0 },
- { 0x54016, 0x0 },
- { 0x54017, 0x0 },
- { 0x54018, 0x0 },
+ { 0x54012, 0x110 },
{ 0x54019, 0x2dd4 },
- { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x5401a, 0x31 },
{ 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d08 },
- { 0x5401d, 0x0 },
- { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
{ 0x5401f, 0x2dd4 },
- { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+ { 0x54020, 0x31 },
{ 0x54021, 0x4d66 },
- { 0x54022, 0x4d08 },
- { 0x54023, 0x0 },
- { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
- { 0x54025, 0x0 },
- { 0x54026, 0x0 },
- { 0x54027, 0x0 },
- { 0x54028, 0x0 },
- { 0x54029, 0x0 },
- { 0x5402a, 0x0 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
- { 0x5402c, LPDDR4_CS },
- { 0x5402d, 0x0 },
- { 0x5402e, 0x0 },
- { 0x5402f, 0x0 },
- { 0x54030, 0x0 },
- { 0x54031, 0x0 },
+ { 0x5402c, 0x1 },
{ 0x54032, 0xd400 },
- { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+ { 0x54033, 0x312d },
{ 0x54034, 0x6600 },
- { 0x54035, 0x84d },
+ { 0x54035, 0x4d },
{ 0x54036, 0x4d },
- { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+ { 0x54037, 0x1600 },
{ 0x54038, 0xd400 },
- { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+ { 0x54039, 0x312d },
{ 0x5403a, 0x6600 },
- { 0x5403b, 0x84d },
+ { 0x5403b, 0x4d },
{ 0x5403c, 0x4d },
- { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
- { 0x5403e, 0x0 },
- { 0x5403f, 0x0 },
- { 0x54040, 0x0 },
- { 0x54041, 0x0 },
- { 0x54042, 0x0 },
- { 0x54043, 0x0 },
- { 0x54044, 0x0 },
+ { 0x5403d, 0x1600 },
{ 0xd0000, 0x1 },
};
/* DRAM PHY init engine image */
-struct dram_cfg_param lpddr4_phy_pie[] = {
+struct dram_cfg_param ddr_phy_pie[] = {
{ 0xd0000, 0x0 },
{ 0x90000, 0x10 },
{ 0x90001, 0x400 },
@@ -1854,6 +1717,10 @@ struct dram_cfg_param lpddr4_phy_pie[] = {
{ 0x90013, 0x6152 },
{ 0x20010, 0x5a },
{ 0x20011, 0x3 },
+ { 0x120010, 0x5a },
+ { 0x120011, 0x3 },
+ { 0x220010, 0x5a },
+ { 0x220011, 0x3 },
{ 0x40080, 0xe0 },
{ 0x40081, 0x12 },
{ 0x40082, 0xe0 },
@@ -1931,50 +1798,51 @@ struct dram_cfg_param lpddr4_phy_pie[] = {
{ 0x138b4, 0x1 },
{ 0x2003a, 0x2 },
{ 0xc0080, 0x2 },
- { 0xd0000, 0x1 },
+ { 0xd0000, 0x1 }
};
-struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
{
/* P0 3000mts 1D */
.drate = 3000,
.fw_type = FW_1D_IMAGE,
- .fsp_cfg = lpddr4_fsp0_cfg,
- .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
- },
- {
- /* P0 3000mts 2D */
- .drate = 3000,
- .fw_type = FW_2D_IMAGE,
- .fsp_cfg = lpddr4_fsp0_2d_cfg,
- .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
},
{
/* P1 400mts 1D */
.drate = 400,
.fw_type = FW_1D_IMAGE,
- .fsp_cfg = lpddr4_fsp1_cfg,
- .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
},
{
- /* P1 100mts 1D */
+ /* P2 100mts 1D */
.drate = 100,
.fw_type = FW_1D_IMAGE,
- .fsp_cfg = lpddr4_fsp2_cfg,
- .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
},
};
-/* lpddr4 timing config params on EVK board */
+/* ddr timing config params */
struct dram_timing_info dram_timing = {
- .ddrc_cfg = lpddr4_ddrc_cfg,
- .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
- .ddrphy_cfg = lpddr4_ddrphy_cfg,
- .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
- .fsp_msg = lpddr4_dram_fsp_msg,
- .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
- .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
- .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
- .ddrphy_pie = lpddr4_phy_pie,
- .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3000, 400, 100, },
};
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 02/26] imx8mm_evk: Update to latest LPDDR4 script
2021-03-19 7:56 ` [PATCH 02/26] imx8mm_evk: Update to latest LPDDR4 script Peng Fan
@ 2021-03-24 21:19 ` Tim Harvey
2021-03-25 1:15 ` Peng Fan
0 siblings, 1 reply; 42+ messages in thread
From: Tim Harvey @ 2021-03-24 21:19 UTC (permalink / raw)
To: u-boot
On Fri, Mar 19, 2021 at 12:26 AM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>
> From: Ye Li <ye.li@nxp.com>
>
> Update LPDDR4 script to sync with v2020.04 u-boot
>
> Signed-off-by: Ye Li <ye.li@nxp.com>
Peng,
The commit log does not make sense. I believe you want to say
something like 'Update LPDDR4 script to sync with <xyz> version of the
NXP MX8M_DDR_tool'.
> ---
> board/freescale/imx8mm_evk/lpddr4_timing.c | 692 +++++++++------------
> 1 file changed, 280 insertions(+), 412 deletions(-)
>
> diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c b/board/freescale/imx8mm_evk/lpddr4_timing.c
> index 8e48b9d81b..4373ca624e 100644
> --- a/board/freescale/imx8mm_evk/lpddr4_timing.c
> +++ b/board/freescale/imx8mm_evk/lpddr4_timing.c
> @@ -1,129 +1,162 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2019 NXP
> + * Copyright 2018-2019 NXP
> + *
> + * Generated code from MX8M_DDR_tool
> */
I understand that this file is a direct output of the NXP MX8M_DDR
tool but it would be nice to see you add to the comment above what
version of the tool you used to produce this what functional
differences it makes. If you knew what version of the tool produced
the original file one could compare versions.
As I am the maintainer of an IMX8M Mini board also, I try to pay
attention to NXP's updates to the DDR timing config files to let me
know if something important has changed.
Best Regards,
Tim
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 02/26] imx8mm_evk: Update to latest LPDDR4 script
2021-03-24 21:19 ` Tim Harvey
@ 2021-03-25 1:15 ` Peng Fan
0 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-25 1:15 UTC (permalink / raw)
To: u-boot
> Subject: Re: [PATCH 02/26] imx8mm_evk: Update to latest LPDDR4 script
>
> On Fri, Mar 19, 2021 at 12:26 AM Peng Fan (OSS) <peng.fan@oss.nxp.com>
> wrote:
> >
> > From: Ye Li <ye.li@nxp.com>
> >
> > Update LPDDR4 script to sync with v2020.04 u-boot
> >
> > Signed-off-by: Ye Li <ye.li@nxp.com>
>
> Peng,
>
> The commit log does not make sense. I believe you want to say something like
> 'Update LPDDR4 script to sync with <xyz> version of the NXP
> MX8M_DDR_tool'.
I directly cherry-pick this patch from downstream tree,
Ye could comment more here.
Regards,
Peng.
>
> > ---
> > board/freescale/imx8mm_evk/lpddr4_timing.c | 692
> > +++++++++------------
> > 1 file changed, 280 insertions(+), 412 deletions(-)
> >
> > diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c
> > b/board/freescale/imx8mm_evk/lpddr4_timing.c
> > index 8e48b9d81b..4373ca624e 100644
> > --- a/board/freescale/imx8mm_evk/lpddr4_timing.c
> > +++ b/board/freescale/imx8mm_evk/lpddr4_timing.c
> > @@ -1,129 +1,162 @@
> > // SPDX-License-Identifier: GPL-2.0+
> > /*
> > - * Copyright 2019 NXP
> > + * Copyright 2018-2019 NXP
> > + *
> > + * Generated code from MX8M_DDR_tool
> > */
>
> I understand that this file is a direct output of the NXP MX8M_DDR tool but it
> would be nice to see you add to the comment above what version of the tool
> you used to produce this what functional differences it makes. If you knew
> what version of the tool produced the original file one could compare versions.
>
> As I am the maintainer of an IMX8M Mini board also, I try to pay attention to
> NXP's updates to the DDR timing config files to let me know if something
> important has changed.
>
> Best Regards,
>
> Tim
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 03/26] imx8mm_evk: Switch to new imx8mm evk board
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
2021-03-19 7:56 ` [PATCH 01/26] tools: imx image: fix write warning Peng Fan
2021-03-19 7:56 ` [PATCH 02/26] imx8mm_evk: Update to latest LPDDR4 script Peng Fan
@ 2021-03-19 7:56 ` Peng Fan
2021-05-12 21:47 ` ZHIZHIKIN Andrey
2021-03-19 7:56 ` [PATCH 04/26] imx8mm/p: remove boot.cmd Peng Fan
` (22 subsequent siblings)
25 siblings, 1 reply; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:56 UTC (permalink / raw)
To: u-boot
From: Ye Li <ye.li@nxp.com>
Update PMIC to use PCA9540, the legacy board not supported by NXP
Signed-off-by: Ye Li <ye.li@nxp.com>
---
arch/arm/dts/imx8mm-evk-u-boot.dtsi | 4 +-
arch/arm/dts/imx8mm-evk.dtsi | 127 +++++++++++++++-------------
board/freescale/imx8mm_evk/spl.c | 33 ++++----
configs/imx8mm_evk_defconfig | 2 +-
4 files changed, 86 insertions(+), 80 deletions(-)
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
index e843a5648e..7f48912b49 100644
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -114,11 +114,11 @@
u-boot,dm-spl;
};
-&{/soc at 0/bus at 30800000/i2c at 30a20000/pmic at 4b} {
+&{/soc at 0/bus at 30800000/i2c at 30a20000/pca9450 at 25} {
u-boot,dm-spl;
};
-&{/soc at 0/bus at 30800000/i2c at 30a20000/pmic at 4b/regulators} {
+&{/soc at 0/bus at 30800000/i2c at 30a20000/pca9450 at 25/regulators} {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi
index 6518f088b2..60179e006d 100644
--- a/arch/arm/dts/imx8mm-evk.dtsi
+++ b/arch/arm/dts/imx8mm-evk.dtsi
@@ -126,115 +126,120 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
- pmic at 4b {
- compatible = "rohm,bd71847";
- reg = <0x4b>;
- pinctrl-names = "default";
+ pmic: pca9450 at 25 {
+ reg = <0x25>;
+ compatible = "nxp,pca9450a";
+ /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio1>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- rohm,reset-snvs-powered;
-
- #clock-cells = <0>;
- clocks = <&osc_32k 0>;
- clock-output-names = "clk-32k-out";
+ gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
regulators {
- buck1_reg: BUCK1 {
- regulator-name = "buck1";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9450,pmic-buck2-uses-i2c-dvs;
+ /* Run/Standby voltage */
+ pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
+
+ buck1_reg: regulator at 0 {
+ reg = <0>;
+ regulator-compatible = "buck1";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
- regulator-ramp-delay = <1250>;
+ regulator-ramp-delay = <3125>;
};
- buck2_reg: BUCK2 {
- regulator-name = "buck2";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
+ buck2_reg: regulator at 1 {
+ reg = <1>;
+ regulator-compatible = "buck2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
- regulator-ramp-delay = <1250>;
- rohm,dvs-run-voltage = <1000000>;
- rohm,dvs-idle-voltage = <900000>;
+ regulator-ramp-delay = <3125>;
};
- buck3_reg: BUCK3 {
- // BUCK5 in datasheet
- regulator-name = "buck3";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1350000>;
+ buck3_reg: regulator at 2 {
+ reg = <2>;
+ regulator-compatible = "buck3";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
};
- buck4_reg: BUCK4 {
- // BUCK6 in datasheet
- regulator-name = "buck4";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3300000>;
+ buck4_reg: regulator at 3 {
+ reg = <3>;
+ regulator-compatible = "buck4";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
- buck5_reg: BUCK5 {
- // BUCK7 in datasheet
- regulator-name = "buck5";
- regulator-min-microvolt = <1605000>;
- regulator-max-microvolt = <1995000>;
+ buck5_reg: regulator at 4 {
+ reg = <4>;
+ regulator-compatible = "buck5";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
- buck6_reg: BUCK6 {
- // BUCK8 in datasheet
- regulator-name = "buck6";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
+ buck6_reg: regulator at 5 {
+ reg = <5>;
+ regulator-compatible = "buck6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
- ldo1_reg: LDO1 {
- regulator-name = "ldo1";
+ ldo1_reg: regulator at 6 {
+ reg = <6>;
+ regulator-compatible = "ldo1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
- ldo2_reg: LDO2 {
- regulator-name = "ldo2";
+ ldo2_reg: regulator at 7 {
+ reg = <7>;
+ regulator-compatible = "ldo2";
regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <900000>;
+ regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
- ldo3_reg: LDO3 {
- regulator-name = "ldo3";
- regulator-min-microvolt = <1800000>;
+ ldo3_reg: regulator at 8 {
+ reg = <8>;
+ regulator-compatible = "ldo3";
+ regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
- ldo4_reg: LDO4 {
- regulator-name = "ldo4";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
+ ldo4_reg: regulator at 9 {
+ reg = <9>;
+ regulator-compatible = "ldo4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
- ldo6_reg: LDO6 {
- regulator-name = "ldo6";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
+ ldo5_reg: regulator at 10 {
+ reg = <10>;
+ regulator-compatible = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
};
+
};
};
};
diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c
index 64bc60651d..4ef7f6f180 100644
--- a/board/freescale/imx8mm_evk/spl.c
+++ b/board/freescale/imx8mm_evk/spl.c
@@ -26,7 +26,7 @@
#include <dm/device-internal.h>
#include <power/pmic.h>
-#include <power/bd71837.h>
+#include <power/pca9450.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -94,7 +94,7 @@ static int power_init_board(void)
struct udevice *dev;
int ret;
- ret = pmic_get("pmic at 4b", &dev);
+ ret = pmic_get("pca9450 at 25", &dev);
if (ret == -ENODEV) {
puts("No pmic\n");
return 0;
@@ -102,25 +102,26 @@ static int power_init_board(void)
if (ret != 0)
return ret;
- /* decrease RESET key long push time from the default 10s to 10ms */
- pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
+ /* BUCKxOUT_DVS0/1 control BUCK123 output */
+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
- /* unlock the PMIC regs */
- pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
+ /* Buck 1 DVS control through PMIC_STBY_REQ */
+ pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
- /* increase VDD_SOC to typical value 0.85v before first DRAM access */
- pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
+ /* Set DVS1 to 0.8v for suspend */
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10);
- /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
- pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
+ /* increase VDD_DRAM to 0.95v for 3Ghz DDR */
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C);
-#ifndef CONFIG_IMX8M_LPDDR4
- /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
- pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
-#endif
+ /* VDD_DRAM needs off in suspend, set B1_ENMODE=10 (ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L) */
+ pmic_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a);
+
+ /* set VDD_SNVS_0V8 from default 0.85V */
+ pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
- /* lock the PMIC regs */
- pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
+ /* set WDOG_B_CFG to cold reset */
+ pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
return 0;
}
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index e22b7de56f..ae9e0626dd 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -83,7 +83,7 @@ CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_PMIC=y
-CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 03/26] imx8mm_evk: Switch to new imx8mm evk board
2021-03-19 7:56 ` [PATCH 03/26] imx8mm_evk: Switch to new imx8mm evk board Peng Fan
@ 2021-05-12 21:47 ` ZHIZHIKIN Andrey
2021-05-14 12:30 ` Fabio Estevam
2021-05-17 0:34 ` Peng Fan
0 siblings, 2 replies; 42+ messages in thread
From: ZHIZHIKIN Andrey @ 2021-05-12 21:47 UTC (permalink / raw)
To: u-boot
Hello Peng,
> -----Original Message-----
> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Peng Fan (OSS)
> Sent: Friday, March 19, 2021 8:57 AM
> To: sbabic at denx.de; festevam at gmail.com
> Cc: u-boot at lists.denx.de; uboot-imx at nxp.com; Ye Li <ye.li@nxp.com>
> Subject: [PATCH 03/26] imx8mm_evk: Switch to new imx8mm evk board
>
> From: Ye Li <ye.li@nxp.com>
>
> Update PMIC to use PCA9540, the legacy board not supported by NXP
This commit seems rather a "nuclear" to me, as de-facto it drops the initialization of ROMH PMIC in
favor of PCA one, leaving all the previous board revisions not to be properly sourced.
I know that there might be no intention to provide a support for earlier revisions of i.MX8M Mini
EVKs from NXP, but providing no backward compatibility to those boards which are still in use by
a lot of people for development purposes is highly undesirable either.
TBH, I've tested this patch on the old EVK where ROMH PMIC is present, and apart from having some
error messages in SPL regarding the register writes - it does boots. What worries me the most though
is that DTS changes some voltage settings, which I'm not sure how the SOC would react on.
To my opinion, this patch should either be complemented with the mechanism to provide a
level of backward compatibility (where the PMIC can be dynamically identified and instantiated),
or the separate implementation should be presented which would make the old board type not to
be bootable at all if it is considered not to be supported any longer. Or this patch should be reverted
in an effort to come up with a solution which covers new revision without "damaging" the currently
integrated one.
Fabio / Stefano,
Do you have any thoughts here on how this should be handled further, considering the fact that the
backward compatibility of 2021.07 release is not kept for this board type across multiple revisions?
I'd really like to get your opinion here as I do have those boards in development and would need to
come up with the idea on what to do with them.
Also, this should be taken care of in the Yocto, since there is only one definition of the i.MX8MM EVK
machine which does not make any distinction regarding the revision.
Thanks a lot!
>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> ---
> arch/arm/dts/imx8mm-evk-u-boot.dtsi | 4 +-
> arch/arm/dts/imx8mm-evk.dtsi | 127 +++++++++++++++-------------
> board/freescale/imx8mm_evk/spl.c | 33 ++++----
> configs/imx8mm_evk_defconfig | 2 +-
> 4 files changed, 86 insertions(+), 80 deletions(-)
>
> diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-
> u-boot.dtsi
> index e843a5648e..7f48912b49 100644
> --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> @@ -114,11 +114,11 @@
> u-boot,dm-spl;
> };
>
> -&{/soc at 0/bus at 30800000/i2c at 30a20000/pmic at 4b} {
> +&{/soc at 0/bus at 30800000/i2c at 30a20000/pca9450 at 25} {
> u-boot,dm-spl;
> };
>
> -&{/soc at 0/bus at 30800000/i2c at 30a20000/pmic at 4b/regulators} {
> +&{/soc at 0/bus at 30800000/i2c at 30a20000/pca9450 at 25/regulators} {
> u-boot,dm-spl;
> };
>
> diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi
> index 6518f088b2..60179e006d 100644
> --- a/arch/arm/dts/imx8mm-evk.dtsi
> +++ b/arch/arm/dts/imx8mm-evk.dtsi
> @@ -126,115 +126,120 @@
> pinctrl-0 = <&pinctrl_i2c1>;
> status = "okay";
>
> - pmic at 4b {
> - compatible = "rohm,bd71847";
> - reg = <0x4b>;
> - pinctrl-names = "default";
> + pmic: pca9450 at 25 {
> + reg = <0x25>;
> + compatible = "nxp,pca9450a";
> + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
> pinctrl-0 = <&pinctrl_pmic>;
> - interrupt-parent = <&gpio1>;
> - interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> - rohm,reset-snvs-powered;
> -
> - #clock-cells = <0>;
> - clocks = <&osc_32k 0>;
> - clock-output-names = "clk-32k-out";
> + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
>
> regulators {
> - buck1_reg: BUCK1 {
> - regulator-name = "buck1";
> - regulator-min-microvolt = <700000>;
> - regulator-max-microvolt = <1300000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pca9450,pmic-buck2-uses-i2c-dvs;
> + /* Run/Standby voltage */
> + pca9450,pmic-buck2-dvs-voltage = <950000>,
> + <850000>;
> +
> + buck1_reg: regulator at 0 {
> + reg = <0>;
> + regulator-compatible = "buck1";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <2187500>;
> regulator-boot-on;
> regulator-always-on;
> - regulator-ramp-delay = <1250>;
> + regulator-ramp-delay = <3125>;
> };
>
> - buck2_reg: BUCK2 {
> - regulator-name = "buck2";
> - regulator-min-microvolt = <700000>;
> - regulator-max-microvolt = <1300000>;
> + buck2_reg: regulator at 1 {
> + reg = <1>;
> + regulator-compatible = "buck2";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <2187500>;
> regulator-boot-on;
> regulator-always-on;
> - regulator-ramp-delay = <1250>;
> - rohm,dvs-run-voltage = <1000000>;
> - rohm,dvs-idle-voltage = <900000>;
> + regulator-ramp-delay = <3125>;
> };
>
> - buck3_reg: BUCK3 {
> - // BUCK5 in datasheet
> - regulator-name = "buck3";
> - regulator-min-microvolt = <700000>;
> - regulator-max-microvolt = <1350000>;
> + buck3_reg: regulator at 2 {
> + reg = <2>;
> + regulator-compatible = "buck3";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <2187500>;
> regulator-boot-on;
> regulator-always-on;
> };
>
> - buck4_reg: BUCK4 {
> - // BUCK6 in datasheet
> - regulator-name = "buck4";
> - regulator-min-microvolt = <3000000>;
> - regulator-max-microvolt = <3300000>;
> + buck4_reg: regulator at 3 {
> + reg = <3>;
> + regulator-compatible = "buck4";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <3400000>;
> regulator-boot-on;
> regulator-always-on;
> };
>
> - buck5_reg: BUCK5 {
> - // BUCK7 in datasheet
> - regulator-name = "buck5";
> - regulator-min-microvolt = <1605000>;
> - regulator-max-microvolt = <1995000>;
> + buck5_reg: regulator at 4 {
> + reg = <4>;
> + regulator-compatible = "buck5";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <3400000>;
> regulator-boot-on;
> regulator-always-on;
> };
>
> - buck6_reg: BUCK6 {
> - // BUCK8 in datasheet
> - regulator-name = "buck6";
> - regulator-min-microvolt = <800000>;
> - regulator-max-microvolt = <1400000>;
> + buck6_reg: regulator at 5 {
> + reg = <5>;
> + regulator-compatible = "buck6";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <3400000>;
> regulator-boot-on;
> regulator-always-on;
> };
>
> - ldo1_reg: LDO1 {
> - regulator-name = "ldo1";
> + ldo1_reg: regulator at 6 {
> + reg = <6>;
> + regulator-compatible = "ldo1";
> regulator-min-microvolt = <1600000>;
> regulator-max-microvolt = <3300000>;
> regulator-boot-on;
> regulator-always-on;
> };
>
> - ldo2_reg: LDO2 {
> - regulator-name = "ldo2";
> + ldo2_reg: regulator at 7 {
> + reg = <7>;
> + regulator-compatible = "ldo2";
> regulator-min-microvolt = <800000>;
> - regulator-max-microvolt = <900000>;
> + regulator-max-microvolt = <1150000>;
> regulator-boot-on;
> regulator-always-on;
> };
>
> - ldo3_reg: LDO3 {
> - regulator-name = "ldo3";
> - regulator-min-microvolt = <1800000>;
> + ldo3_reg: regulator at 8 {
> + reg = <8>;
> + regulator-compatible = "ldo3";
> + regulator-min-microvolt = <800000>;
> regulator-max-microvolt = <3300000>;
> regulator-boot-on;
> regulator-always-on;
> };
>
> - ldo4_reg: LDO4 {
> - regulator-name = "ldo4";
> - regulator-min-microvolt = <900000>;
> - regulator-max-microvolt = <1800000>;
> + ldo4_reg: regulator at 9 {
> + reg = <9>;
> + regulator-compatible = "ldo4";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <3300000>;
> regulator-boot-on;
> regulator-always-on;
> };
>
> - ldo6_reg: LDO6 {
> - regulator-name = "ldo6";
> - regulator-min-microvolt = <900000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-boot-on;
> - regulator-always-on;
> + ldo5_reg: regulator at 10 {
> + reg = <10>;
> + regulator-compatible = "ldo5";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> };
> +
> };
> };
> };
> diff --git a/board/freescale/imx8mm_evk/spl.c
> b/board/freescale/imx8mm_evk/spl.c
> index 64bc60651d..4ef7f6f180 100644
> --- a/board/freescale/imx8mm_evk/spl.c
> +++ b/board/freescale/imx8mm_evk/spl.c
> @@ -26,7 +26,7 @@
> #include <dm/device-internal.h>
>
> #include <power/pmic.h>
> -#include <power/bd71837.h>
> +#include <power/pca9450.h>
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -94,7 +94,7 @@ static int power_init_board(void)
> struct udevice *dev;
> int ret;
>
> - ret = pmic_get("pmic at 4b", &dev);
> + ret = pmic_get("pca9450 at 25", &dev);
> if (ret == -ENODEV) {
> puts("No pmic\n");
> return 0;
> @@ -102,25 +102,26 @@ static int power_init_board(void)
> if (ret != 0)
> return ret;
>
> - /* decrease RESET key long push time from the default 10s to 10ms */
> - pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
> + /* BUCKxOUT_DVS0/1 control BUCK123 output */
> + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
>
> - /* unlock the PMIC regs */
> - pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
> + /* Buck 1 DVS control through PMIC_STBY_REQ */
> + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
>
> - /* increase VDD_SOC to typical value 0.85v before first DRAM access */
> - pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
> + /* Set DVS1 to 0.8v for suspend */
> + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10);
>
> - /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
> - pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
> + /* increase VDD_DRAM to 0.95v for 3Ghz DDR */
> + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C);
>
> -#ifndef CONFIG_IMX8M_LPDDR4
> - /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
> - pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
> -#endif
> + /* VDD_DRAM needs off in suspend, set B1_ENMODE=10 (ON by
> PMIC_ON_REQ = H && PMIC_STBY_REQ = L) */
> + pmic_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a);
> +
> + /* set VDD_SNVS_0V8 from default 0.85V */
> + pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
>
> - /* lock the PMIC regs */
> - pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
> + /* set WDOG_B_CFG to cold reset */
> + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
>
> return 0;
> }
> diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
> index e22b7de56f..ae9e0626dd 100644
> --- a/configs/imx8mm_evk_defconfig
> +++ b/configs/imx8mm_evk_defconfig
> @@ -83,7 +83,7 @@ CONFIG_PINCTRL=y
> CONFIG_SPL_PINCTRL=y
> CONFIG_PINCTRL_IMX8M=y
> CONFIG_DM_PMIC=y
> -CONFIG_SPL_DM_PMIC_BD71837=y
> +CONFIG_SPL_DM_PMIC_PCA9450=y
> CONFIG_DM_REGULATOR=y
> CONFIG_DM_REGULATOR_FIXED=y
> CONFIG_DM_REGULATOR_GPIO=y
> --
> 2.30.0
-- andrey
^ permalink raw reply [flat|nested] 42+ messages in thread* [PATCH 03/26] imx8mm_evk: Switch to new imx8mm evk board
2021-05-12 21:47 ` ZHIZHIKIN Andrey
@ 2021-05-14 12:30 ` Fabio Estevam
2021-05-14 15:29 ` Ricardo Salveti
2021-05-16 14:21 ` ZHIZHIKIN Andrey
2021-05-17 0:34 ` Peng Fan
1 sibling, 2 replies; 42+ messages in thread
From: Fabio Estevam @ 2021-05-14 12:30 UTC (permalink / raw)
To: u-boot
Hi Andrey,
On Wed, May 12, 2021 at 6:47 PM ZHIZHIKIN Andrey
<andrey.zhizhikin@leica-geosystems.com> wrote:
> > Update PMIC to use PCA9540, the legacy board not supported by NXP
>
> This commit seems rather a "nuclear" to me, as de-facto it drops the initialization of ROMH PMIC in
> favor of PCA one, leaving all the previous board revisions not to be properly sourced.
>
> I know that there might be no intention to provide a support for earlier revisions of i.MX8M Mini
> EVKs from NXP, but providing no backward compatibility to those boards which are still in use by
> a lot of people for development purposes is highly undesirable either.
>
> TBH, I've tested this patch on the old EVK where ROMH PMIC is present, and apart from having some
> error messages in SPL regarding the register writes - it does boots. What worries me the most though
> is that DTS changes some voltage settings, which I'm not sure how the SOC would react on.
>
> To my opinion, this patch should either be complemented with the mechanism to provide a
> level of backward compatibility (where the PMIC can be dynamically identified and instantiated),
> or the separate implementation should be presented which would make the old board type not to
> be bootable at all if it is considered not to be supported any longer. Or this patch should be reverted
> in an effort to come up with a solution which covers new revision without "damaging" the currently
> integrated one.
>
> Fabio / Stefano,
> Do you have any thoughts here on how this should be handled further, considering the fact that the
> backward compatibility of 2021.07 release is not kept for this board type across multiple revisions?
>
> I'd really like to get your opinion here as I do have those boards in development and would need to
> come up with the idea on what to do with them.
>
> Also, this should be taken care of in the Yocto, since there is only one definition of the i.MX8MM EVK
> machine which does not make any distinction regarding the revision.
You bring a good point.
What about adding a new defconfig to support the old imx8mm-evk with
the Rohm PMIC?
Then we could have imx8mm_evk_defconfig for the new version and
imx8mm_evk_rohm_defconfig for the old one.
What do you think?
Thanks
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 03/26] imx8mm_evk: Switch to new imx8mm evk board
2021-05-14 12:30 ` Fabio Estevam
@ 2021-05-14 15:29 ` Ricardo Salveti
2021-05-14 15:59 ` Fabio Estevam
2021-05-16 14:31 ` ZHIZHIKIN Andrey
2021-05-16 14:21 ` ZHIZHIKIN Andrey
1 sibling, 2 replies; 42+ messages in thread
From: Ricardo Salveti @ 2021-05-14 15:29 UTC (permalink / raw)
To: u-boot
Hi Fabio,
On Fri, May 14, 2021 at 9:30 AM Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi Andrey,
>
> On Wed, May 12, 2021 at 6:47 PM ZHIZHIKIN Andrey
> <andrey.zhizhikin@leica-geosystems.com> wrote:
>
> > > Update PMIC to use PCA9540, the legacy board not supported by NXP
> >
> > This commit seems rather a "nuclear" to me, as de-facto it drops the initialization of ROMH PMIC in
> > favor of PCA one, leaving all the previous board revisions not to be properly sourced.
> >
> > I know that there might be no intention to provide a support for earlier revisions of i.MX8M Mini
> > EVKs from NXP, but providing no backward compatibility to those boards which are still in use by
> > a lot of people for development purposes is highly undesirable either.
> >
> > TBH, I've tested this patch on the old EVK where ROMH PMIC is present, and apart from having some
> > error messages in SPL regarding the register writes - it does boots. What worries me the most though
> > is that DTS changes some voltage settings, which I'm not sure how the SOC would react on.
> >
> > To my opinion, this patch should either be complemented with the mechanism to provide a
> > level of backward compatibility (where the PMIC can be dynamically identified and instantiated),
> > or the separate implementation should be presented which would make the old board type not to
> > be bootable at all if it is considered not to be supported any longer. Or this patch should be reverted
> > in an effort to come up with a solution which covers new revision without "damaging" the currently
> > integrated one.
> >
> > Fabio / Stefano,
> > Do you have any thoughts here on how this should be handled further, considering the fact that the
> > backward compatibility of 2021.07 release is not kept for this board type across multiple revisions?
> >
> > I'd really like to get your opinion here as I do have those boards in development and would need to
> > come up with the idea on what to do with them.
> >
> > Also, this should be taken care of in the Yocto, since there is only one definition of the i.MX8MM EVK
> > machine which does not make any distinction regarding the revision.
>
> You bring a good point.
>
> What about adding a new defconfig to support the old imx8mm-evk with
> the Rohm PMIC?
>
> Then we could have imx8mm_evk_defconfig for the new version and
> imx8mm_evk_rohm_defconfig for the old one.
>
> What do you think?
Maybe a dynamic way to identify if BD71837 or PCA9450 (by probing i2c)
would work better?
Different configs would imply different builds and binaries, which is
a problem when trying to support a single build for both the old EVK
and EVKB (and the main difference is the PMIC, nothing really major).
I also share Andrey's concerns, as we do have several EVKs in hands,
and having one single build would facilitate quite a bit.
Cheers,
--
Ricardo Salveti de Araujo
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 03/26] imx8mm_evk: Switch to new imx8mm evk board
2021-05-14 15:29 ` Ricardo Salveti
@ 2021-05-14 15:59 ` Fabio Estevam
2021-05-16 14:31 ` ZHIZHIKIN Andrey
1 sibling, 0 replies; 42+ messages in thread
From: Fabio Estevam @ 2021-05-14 15:59 UTC (permalink / raw)
To: u-boot
Hi Ricardo,
On Fri, May 14, 2021 at 12:29 PM Ricardo Salveti <rsalveti@rsalveti.net> wrote:
> Maybe a dynamic way to identify if BD71837 or PCA9450 (by probing i2c)
> would work better?
Yes, agreed.
On imx53-qsb we support both Dialog and NXP PMICs in the same defconfig.
> Different configs would imply different builds and binaries, which is
> a problem when trying to support a single build for both the old EVK
> and EVKB (and the main difference is the PMIC, nothing really major).
>
> I also share Andrey's concerns, as we do have several EVKs in hands,
> and having one single build would facilitate quite a bit.
Agreed.
Thanks
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 03/26] imx8mm_evk: Switch to new imx8mm evk board
2021-05-14 15:29 ` Ricardo Salveti
2021-05-14 15:59 ` Fabio Estevam
@ 2021-05-16 14:31 ` ZHIZHIKIN Andrey
2021-05-18 13:14 ` Vanessa Maegima
1 sibling, 1 reply; 42+ messages in thread
From: ZHIZHIKIN Andrey @ 2021-05-16 14:31 UTC (permalink / raw)
To: u-boot
Hello Ricardo,
> -----Original Message-----
> From: Ricardo Salveti <rsalveti@rsalveti.net>
> Sent: Friday, May 14, 2021 5:29 PM
> To: Fabio Estevam <festevam@gmail.com>
> Cc: ZHIZHIKIN Andrey <andrey.zhizhikin@leica-geosystems.com>; Peng Fan
> (OSS) <peng.fan@oss.nxp.com>; sbabic at denx.de; u-boot at lists.denx.de; uboot-
> imx at nxp.com; Ye Li <ye.li@nxp.com>; vanessa.maegima at foundries.io;
> igor.opaniuk at foundries.io
> Subject: Re: [PATCH 03/26] imx8mm_evk: Switch to new imx8mm evk board
>
>
> Hi Fabio,
>
> On Fri, May 14, 2021 at 9:30 AM Fabio Estevam <festevam@gmail.com> wrote:
> >
> > Hi Andrey,
> >
> > On Wed, May 12, 2021 at 6:47 PM ZHIZHIKIN Andrey
> > <andrey.zhizhikin@leica-geosystems.com> wrote:
> >
> > > > Update PMIC to use PCA9540, the legacy board not supported by NXP
> > >
> > > This commit seems rather a "nuclear" to me, as de-facto it drops the
> initialization of ROMH PMIC in
> > > favor of PCA one, leaving all the previous board revisions not to be properly
> sourced.
> > >
> > > I know that there might be no intention to provide a support for earlier
> revisions of i.MX8M Mini
> > > EVKs from NXP, but providing no backward compatibility to those boards
> which are still in use by
> > > a lot of people for development purposes is highly undesirable either.
> > >
> > > TBH, I've tested this patch on the old EVK where ROMH PMIC is present, and
> apart from having some
> > > error messages in SPL regarding the register writes - it does boots. What
> worries me the most though
> > > is that DTS changes some voltage settings, which I'm not sure how the SOC
> would react on.
> > >
> > > To my opinion, this patch should either be complemented with the
> mechanism to provide a
> > > level of backward compatibility (where the PMIC can be dynamically
> identified and instantiated),
> > > or the separate implementation should be presented which would make the
> old board type not to
> > > be bootable at all if it is considered not to be supported any longer. Or this
> patch should be reverted
> > > in an effort to come up with a solution which covers new revision without
> "damaging" the currently
> > > integrated one.
> > >
> > > Fabio / Stefano,
> > > Do you have any thoughts here on how this should be handled further,
> considering the fact that the
> > > backward compatibility of 2021.07 release is not kept for this board type
> across multiple revisions?
> > >
> > > I'd really like to get your opinion here as I do have those boards in
> development and would need to
> > > come up with the idea on what to do with them.
> > >
> > > Also, this should be taken care of in the Yocto, since there is only one
> definition of the i.MX8MM EVK
> > > machine which does not make any distinction regarding the revision.
> >
> > You bring a good point.
> >
> > What about adding a new defconfig to support the old imx8mm-evk with
> > the Rohm PMIC?
> >
> > Then we could have imx8mm_evk_defconfig for the new version and
> > imx8mm_evk_rohm_defconfig for the old one.
> >
> > What do you think?
>
> Maybe a dynamic way to identify if BD71837 or PCA9450 (by probing i2c)
> would work better?
This might be solution given that there is an implementation in SPL which
can be used to query I2C to determine the PMIC type and get it dynamically.
I'm not aware if this functionality exist, I would need to search for the reference
in the U-Boot tree for this.
But still, as I previously replied to Fabio, it would still need to have 2 separate
entries in DTS for both PMICs, and SPL power_init_board(void) code should be
extended to request the PMIC based on the type detected.
I guess this can be done in 2 steps: first make the PMIC selection based on the
config option in SPL, and then - replace it with dynamic query (if possible).
>
> Different configs would imply different builds and binaries, which is
> a problem when trying to support a single build for both the old EVK
> and EVKB (and the main difference is the PMIC, nothing really major).
This is especially true for Yocto builds, but there would be a way to define
separate U-Boot config based on the type, so having 2 separate config files
would not be technically impossible to achieve.
However, I totally agree with you - one build for both revisions would be the
best solution here.
>
> I also share Andrey's concerns, as we do have several EVKs in hands,
> and having one single build would facilitate quite a bit.
>
> Cheers,
> --
> Ricardo Salveti de Araujo
-- andrey
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 03/26] imx8mm_evk: Switch to new imx8mm evk board
2021-05-16 14:31 ` ZHIZHIKIN Andrey
@ 2021-05-18 13:14 ` Vanessa Maegima
2021-05-18 19:51 ` ZHIZHIKIN Andrey
0 siblings, 1 reply; 42+ messages in thread
From: Vanessa Maegima @ 2021-05-18 13:14 UTC (permalink / raw)
To: u-boot
Hi Andrey,
On Sun, May 16, 2021 at 11:31 AM ZHIZHIKIN Andrey
<andrey.zhizhikin@leica-geosystems.com> wrote:
>
> Hello Ricardo,
>
> > -----Original Message-----
> > From: Ricardo Salveti <rsalveti@rsalveti.net>
> > Sent: Friday, May 14, 2021 5:29 PM
> > To: Fabio Estevam <festevam@gmail.com>
> > Cc: ZHIZHIKIN Andrey <andrey.zhizhikin@leica-geosystems.com>; Peng Fan
> > (OSS) <peng.fan@oss.nxp.com>; sbabic at denx.de; u-boot at lists.denx.de; uboot-
> > imx at nxp.com; Ye Li <ye.li@nxp.com>; vanessa.maegima at foundries.io;
> > igor.opaniuk at foundries.io
> > Subject: Re: [PATCH 03/26] imx8mm_evk: Switch to new imx8mm evk board
> >
> >
> > Hi Fabio,
> >
> > On Fri, May 14, 2021 at 9:30 AM Fabio Estevam <festevam@gmail.com> wrote:
> > >
> > > Hi Andrey,
> > >
> > > On Wed, May 12, 2021 at 6:47 PM ZHIZHIKIN Andrey
> > > <andrey.zhizhikin@leica-geosystems.com> wrote:
> > >
> > > > > Update PMIC to use PCA9540, the legacy board not supported by NXP
> > > >
> > > > This commit seems rather a "nuclear" to me, as de-facto it drops the
> > initialization of ROMH PMIC in
> > > > favor of PCA one, leaving all the previous board revisions not to be properly
> > sourced.
> > > >
> > > > I know that there might be no intention to provide a support for earlier
> > revisions of i.MX8M Mini
> > > > EVKs from NXP, but providing no backward compatibility to those boards
> > which are still in use by
> > > > a lot of people for development purposes is highly undesirable either.
> > > >
> > > > TBH, I've tested this patch on the old EVK where ROMH PMIC is present, and
> > apart from having some
> > > > error messages in SPL regarding the register writes - it does boots. What
> > worries me the most though
> > > > is that DTS changes some voltage settings, which I'm not sure how the SOC
> > would react on.
> > > >
> > > > To my opinion, this patch should either be complemented with the
> > mechanism to provide a
> > > > level of backward compatibility (where the PMIC can be dynamically
> > identified and instantiated),
> > > > or the separate implementation should be presented which would make the
> > old board type not to
> > > > be bootable at all if it is considered not to be supported any longer. Or this
> > patch should be reverted
> > > > in an effort to come up with a solution which covers new revision without
> > "damaging" the currently
> > > > integrated one.
> > > >
> > > > Fabio / Stefano,
> > > > Do you have any thoughts here on how this should be handled further,
> > considering the fact that the
> > > > backward compatibility of 2021.07 release is not kept for this board type
> > across multiple revisions?
> > > >
> > > > I'd really like to get your opinion here as I do have those boards in
> > development and would need to
> > > > come up with the idea on what to do with them.
> > > >
> > > > Also, this should be taken care of in the Yocto, since there is only one
> > definition of the i.MX8MM EVK
> > > > machine which does not make any distinction regarding the revision.
> > >
> > > You bring a good point.
> > >
> > > What about adding a new defconfig to support the old imx8mm-evk with
> > > the Rohm PMIC?
> > >
> > > Then we could have imx8mm_evk_defconfig for the new version and
> > > imx8mm_evk_rohm_defconfig for the old one.
> > >
> > > What do you think?
> >
> > Maybe a dynamic way to identify if BD71837 or PCA9450 (by probing i2c)
> > would work better?
>
> This might be solution given that there is an implementation in SPL which
> can be used to query I2C to determine the PMIC type and get it dynamically.
>
> I'm not aware if this functionality exist, I would need to search for the reference
> in the U-Boot tree for this.
>
> But still, as I previously replied to Fabio, it would still need to have 2 separate
> entries in DTS for both PMICs, and SPL power_init_board(void) code should be
> extended to request the PMIC based on the type detected.
>
> I guess this can be done in 2 steps: first make the PMIC selection based on the
> config option in SPL, and then - replace it with dynamic query (if possible).
>
> >
> > Different configs would imply different builds and binaries, which is
> > a problem when trying to support a single build for both the old EVK
> > and EVKB (and the main difference is the PMIC, nothing really major).
>
> This is especially true for Yocto builds, but there would be a way to define
> separate U-Boot config based on the type, so having 2 separate config files
> would not be technically impossible to achieve.
>
> However, I totally agree with you - one build for both revisions would be the
> best solution here.
Just as a reference, Toradex has worked around this issue for their
imx8mmevk-based design by implementing the dynamic board rev selection in their
tree ("verdin-imx8mm: implement hardware version detection"). With this patch,
they use the same Uboot defconfig with two different dtbs being selected
at runtime in board.c.
We have implemented a similar logic in our tree and it worked for both EVK and
EVKB versions.
>
> >
> > I also share Andrey's concerns, as we do have several EVKs in hands,
> > and having one single build would facilitate quite a bit.
> >
> > Cheers,
> > --
> > Ricardo Salveti de Araujo
>
> -- andrey
Regards,
Vanessa
^ permalink raw reply [flat|nested] 42+ messages in thread* [PATCH 03/26] imx8mm_evk: Switch to new imx8mm evk board
2021-05-18 13:14 ` Vanessa Maegima
@ 2021-05-18 19:51 ` ZHIZHIKIN Andrey
0 siblings, 0 replies; 42+ messages in thread
From: ZHIZHIKIN Andrey @ 2021-05-18 19:51 UTC (permalink / raw)
To: u-boot
Hello Vanessa,
> -----Original Message-----
> From: Vanessa Maegima <vanessa.maegima@foundries.io>
> Sent: Tuesday, May 18, 2021 3:15 PM
> To: ZHIZHIKIN Andrey <andrey.zhizhikin@leica-geosystems.com>
> Cc: Ricardo Salveti <rsalveti@rsalveti.net>; Fabio Estevam
> <festevam@gmail.com>; Peng Fan (OSS) <peng.fan@oss.nxp.com>;
> sbabic at denx.de; u-boot at lists.denx.de; uboot-imx at nxp.com; Ye Li
> <ye.li@nxp.com>; igor.opaniuk at foundries.io
> Subject: Re: [PATCH 03/26] imx8mm_evk: Switch to new imx8mm evk board
>
>
> Hi Andrey,
>
> On Sun, May 16, 2021 at 11:31 AM ZHIZHIKIN Andrey <andrey.zhizhikin@leica-
> geosystems.com> wrote:
> >
> > Hello Ricardo,
> >
> > > -----Original Message-----
> > > From: Ricardo Salveti <rsalveti@rsalveti.net>
> > > Sent: Friday, May 14, 2021 5:29 PM
> > > To: Fabio Estevam <festevam@gmail.com>
> > > Cc: ZHIZHIKIN Andrey <andrey.zhizhikin@leica-geosystems.com>; Peng
> > > Fan
> > > (OSS) <peng.fan@oss.nxp.com>; sbabic at denx.de; u-boot at lists.denx.de;
> > > uboot- imx at nxp.com; Ye Li <ye.li@nxp.com>;
> > > vanessa.maegima at foundries.io; igor.opaniuk at foundries.io
> > > Subject: Re: [PATCH 03/26] imx8mm_evk: Switch to new imx8mm evk
> > > board
> > >
> > >
> > > Hi Fabio,
> > >
> > > On Fri, May 14, 2021 at 9:30 AM Fabio Estevam <festevam@gmail.com>
> wrote:
> > > >
> > > > Hi Andrey,
> > > >
> > > > On Wed, May 12, 2021 at 6:47 PM ZHIZHIKIN Andrey
> > > > <andrey.zhizhikin@leica-geosystems.com> wrote:
> > > >
> > > > > > Update PMIC to use PCA9540, the legacy board not supported by
> > > > > > NXP
> > > > >
> > > > > This commit seems rather a "nuclear" to me, as de-facto it drops
> > > > > the
> > > initialization of ROMH PMIC in
> > > > > favor of PCA one, leaving all the previous board revisions not
> > > > > to be properly
> > > sourced.
> > > > >
> > > > > I know that there might be no intention to provide a support for
> > > > > earlier
> > > revisions of i.MX8M Mini
> > > > > EVKs from NXP, but providing no backward compatibility to those
> > > > > boards
> > > which are still in use by
> > > > > a lot of people for development purposes is highly undesirable either.
> > > > >
> > > > > TBH, I've tested this patch on the old EVK where ROMH PMIC is
> > > > > present, and
> > > apart from having some
> > > > > error messages in SPL regarding the register writes - it does
> > > > > boots. What
> > > worries me the most though
> > > > > is that DTS changes some voltage settings, which I'm not sure
> > > > > how the SOC
> > > would react on.
> > > > >
> > > > > To my opinion, this patch should either be complemented with the
> > > mechanism to provide a
> > > > > level of backward compatibility (where the PMIC can be
> > > > > dynamically
> > > identified and instantiated),
> > > > > or the separate implementation should be presented which would
> > > > > make the
> > > old board type not to
> > > > > be bootable at all if it is considered not to be supported any
> > > > > longer. Or this
> > > patch should be reverted
> > > > > in an effort to come up with a solution which covers new
> > > > > revision without
> > > "damaging" the currently
> > > > > integrated one.
> > > > >
> > > > > Fabio / Stefano,
> > > > > Do you have any thoughts here on how this should be handled
> > > > > further,
> > > considering the fact that the
> > > > > backward compatibility of 2021.07 release is not kept for this
> > > > > board type
> > > across multiple revisions?
> > > > >
> > > > > I'd really like to get your opinion here as I do have those
> > > > > boards in
> > > development and would need to
> > > > > come up with the idea on what to do with them.
> > > > >
> > > > > Also, this should be taken care of in the Yocto, since there is
> > > > > only one
> > > definition of the i.MX8MM EVK
> > > > > machine which does not make any distinction regarding the revision.
> > > >
> > > > You bring a good point.
> > > >
> > > > What about adding a new defconfig to support the old imx8mm-evk
> > > > with the Rohm PMIC?
> > > >
> > > > Then we could have imx8mm_evk_defconfig for the new version and
> > > > imx8mm_evk_rohm_defconfig for the old one.
> > > >
> > > > What do you think?
> > >
> > > Maybe a dynamic way to identify if BD71837 or PCA9450 (by probing
> > > i2c) would work better?
> >
> > This might be solution given that there is an implementation in SPL
> > which can be used to query I2C to determine the PMIC type and get it
> dynamically.
> >
> > I'm not aware if this functionality exist, I would need to search for
> > the reference in the U-Boot tree for this.
> >
> > But still, as I previously replied to Fabio, it would still need to
> > have 2 separate entries in DTS for both PMICs, and SPL
> > power_init_board(void) code should be extended to request the PMIC based
> on the type detected.
> >
> > I guess this can be done in 2 steps: first make the PMIC selection
> > based on the config option in SPL, and then - replace it with dynamic query (if
> possible).
> >
> > >
> > > Different configs would imply different builds and binaries, which
> > > is a problem when trying to support a single build for both the old
> > > EVK and EVKB (and the main difference is the PMIC, nothing really major).
> >
> > This is especially true for Yocto builds, but there would be a way to
> > define separate U-Boot config based on the type, so having 2 separate
> > config files would not be technically impossible to achieve.
> >
> > However, I totally agree with you - one build for both revisions would
> > be the best solution here.
>
> Just as a reference, Toradex has worked around this issue for their imx8mmevk-
> based design by implementing the dynamic board rev selection in their tree
> ("verdin-imx8mm: implement hardware version detection"). With this patch,
> they use the same Uboot defconfig with two different dtbs being selected at
> runtime in board.c.
I've also found this implementation for Toradex Verdin CoM, but did not track
which commit brought it.
Thanks for pointing out the commit message - I would certainly have a look
at it further!
>
> We have implemented a similar logic in our tree and it worked for both EVK and
> EVKB versions.
I was thinking that this would be done by NXP as well for the EVK they
distribute, but the statement was rather clear: No backward compatibility
is provided as the old EVK is not supported any longer.
>
> >
> > >
> > > I also share Andrey's concerns, as we do have several EVKs in hands,
> > > and having one single build would facilitate quite a bit.
> > >
> > > Cheers,
> > > --
> > > Ricardo Salveti de Araujo
> >
> > -- andrey
>
> Regards,
> Vanessa
-- andrey
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 03/26] imx8mm_evk: Switch to new imx8mm evk board
2021-05-14 12:30 ` Fabio Estevam
2021-05-14 15:29 ` Ricardo Salveti
@ 2021-05-16 14:21 ` ZHIZHIKIN Andrey
1 sibling, 0 replies; 42+ messages in thread
From: ZHIZHIKIN Andrey @ 2021-05-16 14:21 UTC (permalink / raw)
To: u-boot
Hello Fabio,
> -----Original Message-----
> From: Fabio Estevam <festevam@gmail.com>
> Sent: Friday, May 14, 2021 2:31 PM
> To: ZHIZHIKIN Andrey <andrey.zhizhikin@leica-geosystems.com>
> Cc: Peng Fan (OSS) <peng.fan@oss.nxp.com>; sbabic at denx.de; u-
> boot at lists.denx.de; uboot-imx at nxp.com; Ye Li <ye.li@nxp.com>
> Subject: Re: [PATCH 03/26] imx8mm_evk: Switch to new imx8mm evk board
>
>
> Hi Andrey,
>
> On Wed, May 12, 2021 at 6:47 PM ZHIZHIKIN Andrey <andrey.zhizhikin@leica-
> geosystems.com> wrote:
>
> > > Update PMIC to use PCA9540, the legacy board not supported by NXP
> >
> > This commit seems rather a "nuclear" to me, as de-facto it drops the
> > initialization of ROMH PMIC in favor of PCA one, leaving all the previous board
> revisions not to be properly sourced.
> >
> > I know that there might be no intention to provide a support for
> > earlier revisions of i.MX8M Mini EVKs from NXP, but providing no
> > backward compatibility to those boards which are still in use by a lot of people
> for development purposes is highly undesirable either.
> >
> > TBH, I've tested this patch on the old EVK where ROMH PMIC is present,
> > and apart from having some error messages in SPL regarding the
> > register writes - it does boots. What worries me the most though is that DTS
> changes some voltage settings, which I'm not sure how the SOC would react on.
> >
> > To my opinion, this patch should either be complemented with the
> > mechanism to provide a level of backward compatibility (where the PMIC
> > can be dynamically identified and instantiated), or the separate
> > implementation should be presented which would make the old board type
> > not to be bootable at all if it is considered not to be supported any
> > longer. Or this patch should be reverted in an effort to come up with a solution
> which covers new revision without "damaging" the currently integrated one.
> >
> > Fabio / Stefano,
> > Do you have any thoughts here on how this should be handled further,
> > considering the fact that the backward compatibility of 2021.07 release is not
> kept for this board type across multiple revisions?
> >
> > I'd really like to get your opinion here as I do have those boards in
> > development and would need to come up with the idea on what to do with
> them.
> >
> > Also, this should be taken care of in the Yocto, since there is only
> > one definition of the i.MX8MM EVK machine which does not make any
> distinction regarding the revision.
>
> You bring a good point.
>
> What about adding a new defconfig to support the old imx8mm-evk with the
> Rohm PMIC?
This would not be the only change that is necessary to provide support for both
ROMH and PCA PMIC ICs. From the commit, it seems that also the "duplication"
should be done in DTS and SPL PMIC code in power_init_board(void) should also
be adapted to get PMIC based on the config option.
I'm not saying it is not feasible - it is perfectly doable, but would require some
verification afterwards.
I can try to come up with the patch set for this but cannot commit to test the
change since I do not own a updated EVK board.
I guess an ideal situation would be that NXP can step in here to provide the better
version of this patch where both revisions are supported, and they can verify the
change on both EVK revisions.
>
> Then we could have imx8mm_evk_defconfig for the new version and
> imx8mm_evk_rohm_defconfig for the old one.
Yes, ultimately this would be possible provided that both DTS and SPL code are
made in a way to provide implementation for both PMIC types.
>
> What do you think?
>
> Thanks
-- andrey
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 03/26] imx8mm_evk: Switch to new imx8mm evk board
2021-05-12 21:47 ` ZHIZHIKIN Andrey
2021-05-14 12:30 ` Fabio Estevam
@ 2021-05-17 0:34 ` Peng Fan
1 sibling, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-05-17 0:34 UTC (permalink / raw)
To: u-boot
On 2021/5/13 5:47, ZHIZHIKIN Andrey wrote:
> Hello Peng,
>
>> -----Original Message-----
>> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Peng Fan (OSS)
>> Sent: Friday, March 19, 2021 8:57 AM
>> To: sbabic at denx.de; festevam at gmail.com
>> Cc: u-boot at lists.denx.de; uboot-imx at nxp.com; Ye Li <ye.li@nxp.com>
>> Subject: [PATCH 03/26] imx8mm_evk: Switch to new imx8mm evk board
>>
>> From: Ye Li <ye.li@nxp.com>
>>
>> Update PMIC to use PCA9540, the legacy board not supported by NXP
>
> This commit seems rather a "nuclear" to me, as de-facto it drops the initialization of ROMH PMIC in
> favor of PCA one, leaving all the previous board revisions not to be properly sourced.
>
> I know that there might be no intention to provide a support for earlier revisions of i.MX8M Mini
> EVKs from NXP, but providing no backward compatibility to those boards which are still in use by
> a lot of people for development purposes is highly undesirable either.
>
> TBH, I've tested this patch on the old EVK where ROMH PMIC is present, and apart from having some
> error messages in SPL regarding the register writes - it does boots. What worries me the most though
> is that DTS changes some voltage settings, which I'm not sure how the SOC would react on.
>
> To my opinion, this patch should either be complemented with the mechanism to provide a
> level of backward compatibility (where the PMIC can be dynamically identified and instantiated),
> or the separate implementation should be presented which would make the old board type not to
> be bootable at all if it is considered not to be supported any longer. Or this patch should be reverted
> in an effort to come up with a solution which covers new revision without "damaging" the currently
> integrated one.
The old evk board was no longer supported by NXP, all new boards using
new PMIC. No damage, just some default voltage settings different.
It is ok to add back the old pmic, but it finally will retire and no one
will use it in production I think.
Regards,
Peng.
>
> Fabio / Stefano,
> Do you have any thoughts here on how this should be handled further, considering the fact that the
> backward compatibility of 2021.07 release is not kept for this board type across multiple revisions?
>
> I'd really like to get your opinion here as I do have those boards in development and would need to
> come up with the idea on what to do with them.
>
> Also, this should be taken care of in the Yocto, since there is only one definition of the i.MX8MM EVK
> machine which does not make any distinction regarding the revision.
>
> Thanks a lot!
>
>>
>> Signed-off-by: Ye Li <ye.li@nxp.com>
>> ---
>> arch/arm/dts/imx8mm-evk-u-boot.dtsi | 4 +-
>> arch/arm/dts/imx8mm-evk.dtsi | 127 +++++++++++++++-------------
>> board/freescale/imx8mm_evk/spl.c | 33 ++++----
>> configs/imx8mm_evk_defconfig | 2 +-
>> 4 files changed, 86 insertions(+), 80 deletions(-)
>>
>> diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-
>> u-boot.dtsi
>> index e843a5648e..7f48912b49 100644
>> --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
>> +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
>> @@ -114,11 +114,11 @@
>> u-boot,dm-spl;
>> };
>>
>> -&{/soc at 0/bus at 30800000/i2c at 30a20000/pmic at 4b} {
>> +&{/soc at 0/bus at 30800000/i2c at 30a20000/pca9450 at 25} {
>> u-boot,dm-spl;
>> };
>>
>> -&{/soc at 0/bus at 30800000/i2c at 30a20000/pmic at 4b/regulators} {
>> +&{/soc at 0/bus at 30800000/i2c at 30a20000/pca9450 at 25/regulators} {
>> u-boot,dm-spl;
>> };
>>
>> diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi
>> index 6518f088b2..60179e006d 100644
>> --- a/arch/arm/dts/imx8mm-evk.dtsi
>> +++ b/arch/arm/dts/imx8mm-evk.dtsi
>> @@ -126,115 +126,120 @@
>> pinctrl-0 = <&pinctrl_i2c1>;
>> status = "okay";
>>
>> - pmic at 4b {
>> - compatible = "rohm,bd71847";
>> - reg = <0x4b>;
>> - pinctrl-names = "default";
>> + pmic: pca9450 at 25 {
>> + reg = <0x25>;
>> + compatible = "nxp,pca9450a";
>> + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
>> pinctrl-0 = <&pinctrl_pmic>;
>> - interrupt-parent = <&gpio1>;
>> - interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
>> - rohm,reset-snvs-powered;
>> -
>> - #clock-cells = <0>;
>> - clocks = <&osc_32k 0>;
>> - clock-output-names = "clk-32k-out";
>> + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
>>
>> regulators {
>> - buck1_reg: BUCK1 {
>> - regulator-name = "buck1";
>> - regulator-min-microvolt = <700000>;
>> - regulator-max-microvolt = <1300000>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + pca9450,pmic-buck2-uses-i2c-dvs;
>> + /* Run/Standby voltage */
>> + pca9450,pmic-buck2-dvs-voltage = <950000>,
>> + <850000>;
>> +
>> + buck1_reg: regulator at 0 {
>> + reg = <0>;
>> + regulator-compatible = "buck1";
>> + regulator-min-microvolt = <600000>;
>> + regulator-max-microvolt = <2187500>;
>> regulator-boot-on;
>> regulator-always-on;
>> - regulator-ramp-delay = <1250>;
>> + regulator-ramp-delay = <3125>;
>> };
>>
>> - buck2_reg: BUCK2 {
>> - regulator-name = "buck2";
>> - regulator-min-microvolt = <700000>;
>> - regulator-max-microvolt = <1300000>;
>> + buck2_reg: regulator at 1 {
>> + reg = <1>;
>> + regulator-compatible = "buck2";
>> + regulator-min-microvolt = <600000>;
>> + regulator-max-microvolt = <2187500>;
>> regulator-boot-on;
>> regulator-always-on;
>> - regulator-ramp-delay = <1250>;
>> - rohm,dvs-run-voltage = <1000000>;
>> - rohm,dvs-idle-voltage = <900000>;
>> + regulator-ramp-delay = <3125>;
>> };
>>
>> - buck3_reg: BUCK3 {
>> - // BUCK5 in datasheet
>> - regulator-name = "buck3";
>> - regulator-min-microvolt = <700000>;
>> - regulator-max-microvolt = <1350000>;
>> + buck3_reg: regulator at 2 {
>> + reg = <2>;
>> + regulator-compatible = "buck3";
>> + regulator-min-microvolt = <600000>;
>> + regulator-max-microvolt = <2187500>;
>> regulator-boot-on;
>> regulator-always-on;
>> };
>>
>> - buck4_reg: BUCK4 {
>> - // BUCK6 in datasheet
>> - regulator-name = "buck4";
>> - regulator-min-microvolt = <3000000>;
>> - regulator-max-microvolt = <3300000>;
>> + buck4_reg: regulator at 3 {
>> + reg = <3>;
>> + regulator-compatible = "buck4";
>> + regulator-min-microvolt = <600000>;
>> + regulator-max-microvolt = <3400000>;
>> regulator-boot-on;
>> regulator-always-on;
>> };
>>
>> - buck5_reg: BUCK5 {
>> - // BUCK7 in datasheet
>> - regulator-name = "buck5";
>> - regulator-min-microvolt = <1605000>;
>> - regulator-max-microvolt = <1995000>;
>> + buck5_reg: regulator at 4 {
>> + reg = <4>;
>> + regulator-compatible = "buck5";
>> + regulator-min-microvolt = <600000>;
>> + regulator-max-microvolt = <3400000>;
>> regulator-boot-on;
>> regulator-always-on;
>> };
>>
>> - buck6_reg: BUCK6 {
>> - // BUCK8 in datasheet
>> - regulator-name = "buck6";
>> - regulator-min-microvolt = <800000>;
>> - regulator-max-microvolt = <1400000>;
>> + buck6_reg: regulator at 5 {
>> + reg = <5>;
>> + regulator-compatible = "buck6";
>> + regulator-min-microvolt = <600000>;
>> + regulator-max-microvolt = <3400000>;
>> regulator-boot-on;
>> regulator-always-on;
>> };
>>
>> - ldo1_reg: LDO1 {
>> - regulator-name = "ldo1";
>> + ldo1_reg: regulator at 6 {
>> + reg = <6>;
>> + regulator-compatible = "ldo1";
>> regulator-min-microvolt = <1600000>;
>> regulator-max-microvolt = <3300000>;
>> regulator-boot-on;
>> regulator-always-on;
>> };
>>
>> - ldo2_reg: LDO2 {
>> - regulator-name = "ldo2";
>> + ldo2_reg: regulator at 7 {
>> + reg = <7>;
>> + regulator-compatible = "ldo2";
>> regulator-min-microvolt = <800000>;
>> - regulator-max-microvolt = <900000>;
>> + regulator-max-microvolt = <1150000>;
>> regulator-boot-on;
>> regulator-always-on;
>> };
>>
>> - ldo3_reg: LDO3 {
>> - regulator-name = "ldo3";
>> - regulator-min-microvolt = <1800000>;
>> + ldo3_reg: regulator at 8 {
>> + reg = <8>;
>> + regulator-compatible = "ldo3";
>> + regulator-min-microvolt = <800000>;
>> regulator-max-microvolt = <3300000>;
>> regulator-boot-on;
>> regulator-always-on;
>> };
>>
>> - ldo4_reg: LDO4 {
>> - regulator-name = "ldo4";
>> - regulator-min-microvolt = <900000>;
>> - regulator-max-microvolt = <1800000>;
>> + ldo4_reg: regulator at 9 {
>> + reg = <9>;
>> + regulator-compatible = "ldo4";
>> + regulator-min-microvolt = <800000>;
>> + regulator-max-microvolt = <3300000>;
>> regulator-boot-on;
>> regulator-always-on;
>> };
>>
>> - ldo6_reg: LDO6 {
>> - regulator-name = "ldo6";
>> - regulator-min-microvolt = <900000>;
>> - regulator-max-microvolt = <1800000>;
>> - regulator-boot-on;
>> - regulator-always-on;
>> + ldo5_reg: regulator at 10 {
>> + reg = <10>;
>> + regulator-compatible = "ldo5";
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <3300000>;
>> };
>> +
>> };
>> };
>> };
>> diff --git a/board/freescale/imx8mm_evk/spl.c
>> b/board/freescale/imx8mm_evk/spl.c
>> index 64bc60651d..4ef7f6f180 100644
>> --- a/board/freescale/imx8mm_evk/spl.c
>> +++ b/board/freescale/imx8mm_evk/spl.c
>> @@ -26,7 +26,7 @@
>> #include <dm/device-internal.h>
>>
>> #include <power/pmic.h>
>> -#include <power/bd71837.h>
>> +#include <power/pca9450.h>
>>
>> DECLARE_GLOBAL_DATA_PTR;
>>
>> @@ -94,7 +94,7 @@ static int power_init_board(void)
>> struct udevice *dev;
>> int ret;
>>
>> - ret = pmic_get("pmic at 4b", &dev);
>> + ret = pmic_get("pca9450 at 25", &dev);
>> if (ret == -ENODEV) {
>> puts("No pmic\n");
>> return 0;
>> @@ -102,25 +102,26 @@ static int power_init_board(void)
>> if (ret != 0)
>> return ret;
>>
>> - /* decrease RESET key long push time from the default 10s to 10ms */
>> - pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
>> + /* BUCKxOUT_DVS0/1 control BUCK123 output */
>> + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
>>
>> - /* unlock the PMIC regs */
>> - pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
>> + /* Buck 1 DVS control through PMIC_STBY_REQ */
>> + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
>>
>> - /* increase VDD_SOC to typical value 0.85v before first DRAM access */
>> - pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
>> + /* Set DVS1 to 0.8v for suspend */
>> + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10);
>>
>> - /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
>> - pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
>> + /* increase VDD_DRAM to 0.95v for 3Ghz DDR */
>> + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C);
>>
>> -#ifndef CONFIG_IMX8M_LPDDR4
>> - /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
>> - pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
>> -#endif
>> + /* VDD_DRAM needs off in suspend, set B1_ENMODE=10 (ON by
>> PMIC_ON_REQ = H && PMIC_STBY_REQ = L) */
>> + pmic_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a);
>> +
>> + /* set VDD_SNVS_0V8 from default 0.85V */
>> + pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
>>
>> - /* lock the PMIC regs */
>> - pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
>> + /* set WDOG_B_CFG to cold reset */
>> + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
>>
>> return 0;
>> }
>> diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
>> index e22b7de56f..ae9e0626dd 100644
>> --- a/configs/imx8mm_evk_defconfig
>> +++ b/configs/imx8mm_evk_defconfig
>> @@ -83,7 +83,7 @@ CONFIG_PINCTRL=y
>> CONFIG_SPL_PINCTRL=y
>> CONFIG_PINCTRL_IMX8M=y
>> CONFIG_DM_PMIC=y
>> -CONFIG_SPL_DM_PMIC_BD71837=y
>> +CONFIG_SPL_DM_PMIC_PCA9450=y
>> CONFIG_DM_REGULATOR=y
>> CONFIG_DM_REGULATOR_FIXED=y
>> CONFIG_DM_REGULATOR_GPIO=y
>> --
>> 2.30.0
>
> -- andrey
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 04/26] imx8mm/p: remove boot.cmd
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (2 preceding siblings ...)
2021-03-19 7:56 ` [PATCH 03/26] imx8mm_evk: Switch to new imx8mm evk board Peng Fan
@ 2021-03-19 7:56 ` Peng Fan
2021-03-19 7:56 ` [PATCH 05/26] imx8mm_evk: add/cleanup variable for distro Peng Fan
` (21 subsequent siblings)
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:56 UTC (permalink / raw)
To: u-boot
From: Peng Fan <peng.fan@nxp.com>
These files should not be in U-Boot repo
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
board/freescale/imx8mm_evk/boot.cmd | 35 -----------------------------
board/freescale/imx8mp_evk/boot.cmd | 25 ---------------------
2 files changed, 60 deletions(-)
delete mode 100644 board/freescale/imx8mm_evk/boot.cmd
delete mode 100644 board/freescale/imx8mp_evk/boot.cmd
diff --git a/board/freescale/imx8mm_evk/boot.cmd b/board/freescale/imx8mm_evk/boot.cmd
deleted file mode 100644
index fdfceec263..0000000000
--- a/board/freescale/imx8mm_evk/boot.cmd
+++ /dev/null
@@ -1,35 +0,0 @@
-setenv bootargs console=${console} root=${mmcroot};
-
-for boot_target in ${boot_targets};
-do
- if test "${boot_target}" = "mmc1" ; then
- if fatload mmc 1:${mmcpart} ${kernel_addr_r} ${image}; then
- if fatload mmc 1:${mmcpart} ${fdt_addr} ${fdt_file}; then
- echo Load image and .dtb from SD card(mmc1);
- booti ${kernel_addr_r} - ${fdt_addr};
- exit;
- fi
- fi
- fi
-
- if test "${boot_target}" = "mmc2" ; then
- if fatload mmc 2:${mmcpart} ${kernel_addr_r} ${image}; then
- if fatload mmc 2:${mmcpart} ${fdt_addr} ${fdt_file}; then
- echo Load image and .dtb from eMMC(mmc2);
- booti ${kernel_addr_r} - ${fdt_addr};
- exit;
- fi
- fi
- fi
-
- if test "${boot_target}" = "dhcp" ; then
- if dhcp ${kernel_addr_r} ${serverip}:${image}; then
- if dhcp ${fdt_addr} ${serverip}:${fdt_file}; then
- echo Load image and .dtb from net(dhcp);
- booti ${kernel_addr_r} - ${fdt_addr};
- exit;
- fi
- fi
- fi
-
-done
diff --git a/board/freescale/imx8mp_evk/boot.cmd b/board/freescale/imx8mp_evk/boot.cmd
deleted file mode 100644
index 10bcced774..0000000000
--- a/board/freescale/imx8mp_evk/boot.cmd
+++ /dev/null
@@ -1,25 +0,0 @@
-setenv bootargs console=${console} root=${mmcroot};
-
-for boot_target in ${boot_targets};
-do
- if test "${boot_target}" = "mmc1" ; then
- if fatload mmc 1:${mmcpart} ${kernel_addr_r} ${image}; then
- if fatload mmc 1:${mmcpart} ${fdt_addr} ${fdt_file}; then
- echo Load image and .dtb from SD card(mmc1);
- booti ${kernel_addr_r} - ${fdt_addr};
- exit;
- fi
- fi
- fi
-
- if test "${boot_target}" = "mmc2" ; then
- if fatload mmc 2:${mmcpart} ${kernel_addr_r} ${image}; then
- if fatload mmc 2:${mmcpart} ${fdt_addr} ${fdt_file}; then
- echo Load image and .dtb from eMMC(mmc2);
- booti ${kernel_addr_r} - ${fdt_addr};
- exit;
- fi
- fi
- fi
-
-done
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 05/26] imx8mm_evk: add/cleanup variable for distro
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (3 preceding siblings ...)
2021-03-19 7:56 ` [PATCH 04/26] imx8mm/p: remove boot.cmd Peng Fan
@ 2021-03-19 7:56 ` Peng Fan
2021-03-19 7:56 ` [PATCH 06/26] imx8mp_evk: " Peng Fan
` (20 subsequent siblings)
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:56 UTC (permalink / raw)
To: u-boot
From: Peng Fan <peng.fan@nxp.com>
Add fdt_addr_r fdtfile which used by distro boot
Clean up environment
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
include/configs/imx8mm_evk.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
index fd9a6cbb8c..8f3dd8fb61 100644
--- a/include/configs/imx8mm_evk.h
+++ b/include/configs/imx8mm_evk.h
@@ -44,13 +44,13 @@
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
- "scriptaddr=0x43500000\0" \
- "kernel_addr_r=0x40880000\0" \
+ "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"image=Image\0" \
"console=ttymxc1,115200\0" \
- "fdt_addr=0x43000000\0" \
+ "fdt_addr_r=0x43000000\0" \
"boot_fit=no\0" \
- "fdt_file=imx8mm-evk.dtb\0" \
+ "fdtfile=imx8mm-evk.dtb\0" \
"initrd_addr=0x43800000\0" \
"bootm_size=0x10000000\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 06/26] imx8mp_evk: add/cleanup variable for distro
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (4 preceding siblings ...)
2021-03-19 7:56 ` [PATCH 05/26] imx8mm_evk: add/cleanup variable for distro Peng Fan
@ 2021-03-19 7:56 ` Peng Fan
2021-03-19 7:56 ` [PATCH 07/26] imx8mp: ddr: Add inline ECC feature support Peng Fan
` (19 subsequent siblings)
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:56 UTC (permalink / raw)
To: u-boot
From: Peng Fan <peng.fan@nxp.com>
Add fdt_addr_r fdtfile which used by distro boot
Clean up environment
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
include/configs/imx8mp_evk.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h
index 61a5c6fb79..d1bc09e825 100644
--- a/include/configs/imx8mp_evk.h
+++ b/include/configs/imx8mp_evk.h
@@ -68,13 +68,13 @@
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
- "scriptaddr=0x43500000\0" \
- "kernel_addr_r=0x40880000\0" \
+ "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"image=Image\0" \
"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
- "fdt_addr=0x43000000\0" \
+ "fdt_addr_r=0x43000000\0" \
"boot_fdt=try\0" \
- "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
"initrd_addr=0x43800000\0" \
"bootm_size=0x10000000\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 07/26] imx8mp: ddr: Add inline ECC feature support
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (5 preceding siblings ...)
2021-03-19 7:56 ` [PATCH 06/26] imx8mp_evk: " Peng Fan
@ 2021-03-19 7:56 ` Peng Fan
2021-03-19 7:57 ` [PATCH 08/26] imx8mp_evk: Update LPDDR4 timing for new FW 202006 Peng Fan
` (18 subsequent siblings)
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:56 UTC (permalink / raw)
To: u-boot
From: Sherry Sun <sherry.sun@nxp.com>
Add inline ECC support for lpddr4 on imx8mp-evk. And add a config which
can enable/disable inline ECC feature for lpddr4 on imx8mp-evk board.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
board/freescale/imx8mp_evk/lpddr4_timing.c | 27 ++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c
index 7658262b37..cc9c6926be 100644
--- a/board/freescale/imx8mp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mp_evk/lpddr4_timing.c
@@ -14,6 +14,9 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400020, 0x1323 },
{ 0x3d400024, 0x1e84800 },
{ 0x3d400064, 0x7a0118 },
+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
+ { 0x3d400070, 0x01027f44 },
+#endif
{ 0x3d4000d0, 0xc00307a3 },
{ 0x3d4000d4, 0xc50000 },
{ 0x3d4000dc, 0xf4003f },
@@ -45,12 +48,21 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d4001c4, 0x1 },
{ 0x3d4000f4, 0xc99 },
{ 0x3d400108, 0x9121c1c },
+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
+ { 0x3d400200, 0x13 },
+ { 0x3d40020c, 0x13131300 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x50505 },
+ { 0x3d400214, 0x4040404 },
+ { 0x3d400218, 0x68040404 },
+#else
{ 0x3d400200, 0x16 },
{ 0x3d40020c, 0x0 },
{ 0x3d400210, 0x1f1f },
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0x68070707 },
+#endif
{ 0x3d40021c, 0xf08 },
{ 0x3d400250, 0x00001705 },
{ 0x3d400254, 0x2c },
@@ -1846,3 +1858,18 @@ struct dram_timing_info dram_timing = {
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 4000, 400, 100, },
};
+
+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
+void board_dram_ecc_scrub(void)
+{
+ /* add inline scrb function MPlus spcific */
+ /* scrub 0-1.75G */
+ ddrc_inline_ecc_scrub(0x0, 0x1bffffff);
+ /* scrub 2-3.75G */
+ ddrc_inline_ecc_scrub(0x20000000, 0x3bffffff);
+ /* scrub 4-5.75G */
+ ddrc_inline_ecc_scrub(0x40000000, 0x5bffffff);
+ /* set scruber read range 0-6G */
+ ddrc_inline_ecc_scrub_end(0x0, 0x5fffffff);
+}
+#endif
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 08/26] imx8mp_evk: Update LPDDR4 timing for new FW 202006
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (6 preceding siblings ...)
2021-03-19 7:56 ` [PATCH 07/26] imx8mp: ddr: Add inline ECC feature support Peng Fan
@ 2021-03-19 7:57 ` Peng Fan
2021-03-19 7:57 ` [PATCH 09/26] imx8mp_evk: Update LPDDR4 refresh time Peng Fan
` (17 subsequent siblings)
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:57 UTC (permalink / raw)
To: u-boot
From: Ye Li <ye.li@nxp.com>
After switching to new LPDDR4 firmware 202006 version, have to
update the LPDDR4 timing accordingly from RPA tool.
Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Sherry Sun <sherry.sun@nxp.com>
Tested-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
board/freescale/imx8mp_evk/lpddr4_timing.c | 189 +++++++++++----------
1 file changed, 99 insertions(+), 90 deletions(-)
diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c
index cc9c6926be..eff0a93860 100644
--- a/board/freescale/imx8mp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mp_evk/lpddr4_timing.c
@@ -15,14 +15,17 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400024, 0x1e84800 },
{ 0x3d400064, 0x7a0118 },
#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
- { 0x3d400070, 0x01027f44 },
+ { 0x3d400070, 0x1027f54 },
+#else
+ { 0x3d400070, 0x1027f10 },
#endif
+ { 0x3d400074, 0x7b0 },
{ 0x3d4000d0, 0xc00307a3 },
{ 0x3d4000d4, 0xc50000 },
{ 0x3d4000dc, 0xf4003f },
{ 0x3d4000e0, 0x330000 },
- { 0x3d4000e8, 0x460048 },
- { 0x3d4000ec, 0x150048 },
+ { 0x3d4000e8, 0x660048 },
+ { 0x3d4000ec, 0x160048 },
{ 0x3d400100, 0x2028222a },
{ 0x3d400104, 0x807bf },
{ 0x3d40010c, 0xe0e000 },
@@ -64,26 +67,26 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400218, 0x68070707 },
#endif
{ 0x3d40021c, 0xf08 },
- { 0x3d400250, 0x00001705 },
+ { 0x3d400250, 0x1705 },
{ 0x3d400254, 0x2c },
{ 0x3d40025c, 0x4000030 },
{ 0x3d400264, 0x900093e7 },
{ 0x3d40026c, 0x2005574 },
{ 0x3d400400, 0x111 },
- { 0x3d400404, 0x72ff },
+ { 0x3d400404, 0x72ff },
{ 0x3d400408, 0x72ff },
{ 0x3d400494, 0x2100e07 },
{ 0x3d400498, 0x620096 },
{ 0x3d40049c, 0x1100e07 },
{ 0x3d4004a0, 0xc8012c },
- { 0x3d402020, 0x21 },
- { 0x3d402024, 0x7d00 },
- { 0x3d402050, 0x20d040 },
+ { 0x3d402020, 0x1021 },
+ { 0x3d402024, 0x30d400 },
+ { 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc001c },
{ 0x3d4020dc, 0x840000 },
- { 0x3d4020e0, 0x310000 },
- { 0x3d4020e8, 0x66004d },
- { 0x3d4020ec, 0x16004d },
+ { 0x3d4020e0, 0x330000 },
+ { 0x3d4020e8, 0x660048 },
+ { 0x3d4020ec, 0x160048 },
{ 0x3d402100, 0xa040305 },
{ 0x3d402104, 0x30407 },
{ 0x3d402108, 0x203060b },
@@ -101,14 +104,14 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
{ 0x3d4020f4, 0xc99 },
- { 0x3d403020, 0x21 },
- { 0x3d403024, 0x30d400 },
- { 0x3d403050, 0x20d040 },
+ { 0x3d403020, 0x1021 },
+ { 0x3d403024, 0xc3500 },
+ { 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x30007 },
{ 0x3d4030dc, 0x840000 },
- { 0x3d4030e0, 0x310000 },
- { 0x3d4030e8, 0x66004d },
- { 0x3d4030ec, 0x16004d },
+ { 0x3d4030e0, 0x330000 },
+ { 0x3d4030e8, 0x660048 },
+ { 0x3d4030ec, 0x160048 },
{ 0x3d403100, 0xa010102 },
{ 0x3d403104, 0x30404 },
{ 0x3d403108, 0x203060b },
@@ -125,6 +128,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d403190, 0x3818200 },
{ 0x3d403194, 0x80303 },
{ 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
{ 0x3d400028, 0x0 },
};
@@ -1114,28 +1118,28 @@ struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0x54012, 0x310 },
{ 0x54019, 0x84 },
{ 0x5401a, 0x33 },
- { 0x5401b, 0x4846 },
+ { 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
- { 0x5401e, 0x15 },
+ { 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
{ 0x54020, 0x33 },
- { 0x54021, 0x4846 },
+ { 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
- { 0x54024, 0x15 },
+ { 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0x8400 },
{ 0x54033, 0x3300 },
- { 0x54034, 0x4600 },
+ { 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
- { 0x54037, 0x1500 },
+ { 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
{ 0x54039, 0x3300 },
- { 0x5403a, 0x4600 },
+ { 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
- { 0x5403d, 0x1500 },
+ { 0x5403d, 0x1600 },
{ 0xd0000, 0x1 },
};
@@ -1154,28 +1158,28 @@ struct dram_cfg_param ddr_fsp2_cfg[] = {
{ 0x54012, 0x310 },
{ 0x54019, 0x84 },
{ 0x5401a, 0x33 },
- { 0x5401b, 0x4846 },
+ { 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
- { 0x5401e, 0x15 },
+ { 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
{ 0x54020, 0x33 },
- { 0x54021, 0x4846 },
+ { 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
- { 0x54024, 0x15 },
+ { 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0x8400 },
{ 0x54033, 0x3300 },
- { 0x54034, 0x4600 },
+ { 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
- { 0x54037, 0x1500 },
+ { 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
{ 0x54039, 0x3300 },
- { 0x5403a, 0x4600 },
+ { 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
- { 0x5403d, 0x1500 },
+ { 0x5403d, 0x1600 },
{ 0xd0000, 0x1 },
};
@@ -1640,67 +1644,58 @@ struct dram_cfg_param ddr_phy_pie[] = {
{ 0x90155, 0x20 },
{ 0x90156, 0x2aa },
{ 0x90157, 0x9 },
- { 0x90158, 0x0 },
- { 0x90159, 0x400 },
- { 0x9015a, 0x10e },
- { 0x9015b, 0x8 },
- { 0x9015c, 0xe8 },
- { 0x9015d, 0x109 },
- { 0x9015e, 0x0 },
- { 0x9015f, 0x8140 },
- { 0x90160, 0x10c },
- { 0x90161, 0x10 },
- { 0x90162, 0x8138 },
- { 0x90163, 0x10c },
- { 0x90164, 0x8 },
- { 0x90165, 0x7c8 },
- { 0x90166, 0x101 },
- { 0x90167, 0x8 },
- { 0x90168, 0x448 },
+ { 0x90158, 0x8 },
+ { 0x90159, 0xe8 },
+ { 0x9015a, 0x109 },
+ { 0x9015b, 0x0 },
+ { 0x9015c, 0x8140 },
+ { 0x9015d, 0x10c },
+ { 0x9015e, 0x10 },
+ { 0x9015f, 0x8138 },
+ { 0x90160, 0x104 },
+ { 0x90161, 0x8 },
+ { 0x90162, 0x448 },
+ { 0x90163, 0x109 },
+ { 0x90164, 0xf },
+ { 0x90165, 0x7c0 },
+ { 0x90166, 0x109 },
+ { 0x90167, 0x0 },
+ { 0x90168, 0xe8 },
{ 0x90169, 0x109 },
- { 0x9016a, 0xf },
- { 0x9016b, 0x7c0 },
+ { 0x9016a, 0x47 },
+ { 0x9016b, 0x630 },
{ 0x9016c, 0x109 },
- { 0x9016d, 0x0 },
- { 0x9016e, 0xe8 },
+ { 0x9016d, 0x8 },
+ { 0x9016e, 0x618 },
{ 0x9016f, 0x109 },
- { 0x90170, 0x47 },
- { 0x90171, 0x630 },
+ { 0x90170, 0x8 },
+ { 0x90171, 0xe0 },
{ 0x90172, 0x109 },
- { 0x90173, 0x8 },
- { 0x90174, 0x618 },
+ { 0x90173, 0x0 },
+ { 0x90174, 0x7c8 },
{ 0x90175, 0x109 },
{ 0x90176, 0x8 },
- { 0x90177, 0xe0 },
- { 0x90178, 0x109 },
+ { 0x90177, 0x8140 },
+ { 0x90178, 0x10c },
{ 0x90179, 0x0 },
- { 0x9017a, 0x7c8 },
+ { 0x9017a, 0x478 },
{ 0x9017b, 0x109 },
- { 0x9017c, 0x8 },
- { 0x9017d, 0x8140 },
- { 0x9017e, 0x10c },
- { 0x9017f, 0x0 },
- { 0x90180, 0x478 },
- { 0x90181, 0x109 },
- { 0x90182, 0x0 },
- { 0x90183, 0x1 },
- { 0x90184, 0x8 },
- { 0x90185, 0x8 },
- { 0x90186, 0x4 },
- { 0x90187, 0x8 },
- { 0x90188, 0x8 },
- { 0x90189, 0x7c8 },
- { 0x9018a, 0x101 },
- { 0x90006, 0x0 },
- { 0x90007, 0x0 },
- { 0x90008, 0x8 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x1 },
+ { 0x9017e, 0x8 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x4 },
+ { 0x90181, 0x0 },
+ { 0x90006, 0x8 },
+ { 0x90007, 0x7c8 },
+ { 0x90008, 0x109 },
{ 0x90009, 0x0 },
- { 0x9000a, 0x0 },
- { 0x9000b, 0x0 },
+ { 0x9000a, 0x400 },
+ { 0x9000b, 0x106 },
{ 0xd00e7, 0x400 },
{ 0x90017, 0x0 },
{ 0x9001f, 0x29 },
- { 0x90026, 0x6a },
+ { 0x90026, 0x68 },
{ 0x400d0, 0x0 },
{ 0x400d1, 0x101 },
{ 0x400d2, 0x105 },
@@ -1710,6 +1705,7 @@ struct dram_cfg_param ddr_phy_pie[] = {
{ 0x400d6, 0x20a },
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
+ { 0x200be, 0x3 },
{ 0x2000b, 0x7d },
{ 0x2000c, 0xfa },
{ 0x2000d, 0x9c4 },
@@ -1862,14 +1858,27 @@ struct dram_timing_info dram_timing = {
#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
void board_dram_ecc_scrub(void)
{
- /* add inline scrb function MPlus spcific */
- /* scrub 0-1.75G */
- ddrc_inline_ecc_scrub(0x0, 0x1bffffff);
- /* scrub 2-3.75G */
- ddrc_inline_ecc_scrub(0x20000000, 0x3bffffff);
- /* scrub 4-5.75G */
- ddrc_inline_ecc_scrub(0x40000000, 0x5bffffff);
- /* set scruber read range 0-6G */
+ ddrc_inline_ecc_scrub(0x0, 0x3ffffff);
+ ddrc_inline_ecc_scrub(0x20000000, 0x23ffffff);
+ ddrc_inline_ecc_scrub(0x40000000, 0x43ffffff);
+ ddrc_inline_ecc_scrub(0x4000000, 0x7ffffff);
+ ddrc_inline_ecc_scrub(0x24000000, 0x27ffffff);
+ ddrc_inline_ecc_scrub(0x44000000, 0x47ffffff);
+ ddrc_inline_ecc_scrub(0x8000000, 0xbffffff);
+ ddrc_inline_ecc_scrub(0x28000000, 0x2bffffff);
+ ddrc_inline_ecc_scrub(0x48000000, 0x4bffffff);
+ ddrc_inline_ecc_scrub(0xc000000, 0xfffffff);
+ ddrc_inline_ecc_scrub(0x2c000000, 0x2fffffff);
+ ddrc_inline_ecc_scrub(0x4c000000, 0x4fffffff);
+ ddrc_inline_ecc_scrub(0x10000000, 0x13ffffff);
+ ddrc_inline_ecc_scrub(0x30000000, 0x33ffffff);
+ ddrc_inline_ecc_scrub(0x50000000, 0x53ffffff);
+ ddrc_inline_ecc_scrub(0x14000000, 0x17ffffff);
+ ddrc_inline_ecc_scrub(0x34000000, 0x37ffffff);
+ ddrc_inline_ecc_scrub(0x54000000, 0x57ffffff);
+ ddrc_inline_ecc_scrub(0x18000000, 0x1bffffff);
+ ddrc_inline_ecc_scrub(0x38000000, 0x3bffffff);
+ ddrc_inline_ecc_scrub(0x58000000, 0x5bffffff);
ddrc_inline_ecc_scrub_end(0x0, 0x5fffffff);
}
#endif
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 09/26] imx8mp_evk: Update LPDDR4 refresh time
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (7 preceding siblings ...)
2021-03-19 7:57 ` [PATCH 08/26] imx8mp_evk: Update LPDDR4 timing for new FW 202006 Peng Fan
@ 2021-03-19 7:57 ` Peng Fan
2021-03-19 7:57 ` [PATCH 10/26] imx8mp: refine power on imx8mp board Peng Fan
` (16 subsequent siblings)
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:57 UTC (permalink / raw)
To: u-boot
From: Ye Li <ye.li@nxp.com>
Use more safer refresh time value for 6GB LPDDR4 on this EVK board.
Update the parameters for every frequency point.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
board/freescale/imx8mp_evk/lpddr4_timing.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c
index eff0a93860..0759502ba3 100644
--- a/board/freescale/imx8mp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mp_evk/lpddr4_timing.c
@@ -13,7 +13,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400000, 0xa3080020 },
{ 0x3d400020, 0x1323 },
{ 0x3d400024, 0x1e84800 },
- { 0x3d400064, 0x7a0118 },
+ { 0x3d400064, 0x7a017c },
#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
{ 0x3d400070, 0x1027f54 },
#else
@@ -35,7 +35,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d40011c, 0x501 },
{ 0x3d400130, 0x20800 },
{ 0x3d400134, 0xe100002 },
- { 0x3d400138, 0x120 },
+ { 0x3d400138, 0x184 },
{ 0x3d400144, 0xc80064 },
{ 0x3d400180, 0x3e8001e },
{ 0x3d400184, 0x3207a12 },
@@ -82,7 +82,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d402020, 0x1021 },
{ 0x3d402024, 0x30d400 },
{ 0x3d402050, 0x20d000 },
- { 0x3d402064, 0xc001c },
+ { 0x3d402064, 0xc0026 },
{ 0x3d4020dc, 0x840000 },
{ 0x3d4020e0, 0x330000 },
{ 0x3d4020e8, 0x660048 },
@@ -97,7 +97,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d40211c, 0x301 },
{ 0x3d402130, 0x20300 },
{ 0x3d402134, 0xa100002 },
- { 0x3d402138, 0x1d },
+ { 0x3d402138, 0x27 },
{ 0x3d402144, 0x14000a },
{ 0x3d402180, 0x640004 },
{ 0x3d402190, 0x3818200 },
@@ -107,7 +107,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d403020, 0x1021 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
- { 0x3d403064, 0x30007 },
+ { 0x3d403064, 0x3000a },
{ 0x3d4030dc, 0x840000 },
{ 0x3d4030e0, 0x330000 },
{ 0x3d4030e8, 0x660048 },
@@ -122,7 +122,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d40311c, 0x301 },
{ 0x3d403130, 0x20300 },
{ 0x3d403134, 0xa100002 },
- { 0x3d403138, 0x8 },
+ { 0x3d403138, 0xa },
{ 0x3d403144, 0x50003 },
{ 0x3d403180, 0x190004 },
{ 0x3d403190, 0x3818200 },
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 10/26] imx8mp: refine power on imx8mp board
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (8 preceding siblings ...)
2021-03-19 7:57 ` [PATCH 09/26] imx8mp_evk: Update LPDDR4 refresh time Peng Fan
@ 2021-03-19 7:57 ` Peng Fan
2021-03-19 7:57 ` [PATCH 11/26] imx8mp_evk: spl: clean up including headers Peng Fan
` (15 subsequent siblings)
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:57 UTC (permalink / raw)
To: u-boot
From: "haidong.zheng" <haidong.zheng@nxp.com>
VDD SOC normal run changed to 0.85V
LPDDR4 freq0 change from 4000MTS to 2400MTS
Signed-off-by: haidong.zheng <haidong.zheng@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
board/freescale/imx8mp_evk/lpddr4_timing.c | 166 +++++++++++++++++++++
board/freescale/imx8mp_evk/spl.c | 5 +
drivers/ddr/imx/imx8m/Kconfig | 8 +
3 files changed, 179 insertions(+)
mode change 100644 => 100755 board/freescale/imx8mp_evk/lpddr4_timing.c
diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c
old mode 100644
new mode 100755
index 0759502ba3..9d069fc27a
--- a/board/freescale/imx8mp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mp_evk/lpddr4_timing.c
@@ -11,6 +11,16 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa3080020 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ { 0x3d400020, 0x223 },
+ { 0x3d400024, 0x124f800 },
+ { 0x3d400064, 0x4900a8 },
+ { 0x3d400070, 0x1027f90 },
+ { 0x3d400074, 0x790 },
+ { 0x3d4000d0, 0xc0030495 },
+ { 0x3d4000d4, 0x770000 },
+ { 0x3d4000dc, 0xc40024 },
+#else
{ 0x3d400020, 0x1323 },
{ 0x3d400024, 0x1e84800 },
{ 0x3d400064, 0x7a017c },
@@ -23,9 +33,29 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d4000d0, 0xc00307a3 },
{ 0x3d4000d4, 0xc50000 },
{ 0x3d4000dc, 0xf4003f },
+#endif
{ 0x3d4000e0, 0x330000 },
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ { 0x3d400100, 0x1618141a },
+ { 0x3d400104, 0x504a6 },
+ { 0x3d40010c, 0x909000 },
+ { 0x3d400110, 0xb04060b },
+ { 0x3d400114, 0x2030909 },
+ { 0x3d400118, 0x1010006 },
+ { 0x3d40011c, 0x301 },
+ { 0x3d400130, 0x20500 },
+ { 0x3d400134, 0xb100002 },
+ { 0x3d400138, 0xad },
+ { 0x3d400144, 0x78003c },
+ { 0x3d400180, 0x2580012 },
+ { 0x3d400184, 0x1e0493e },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x4938208 },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x1308 },
+#else
{ 0x3d400100, 0x2028222a },
{ 0x3d400104, 0x807bf },
{ 0x3d40010c, 0xe0e000 },
@@ -43,6 +73,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400190, 0x49f820e },
{ 0x3d400194, 0x80303 },
{ 0x3d4001b4, 0x1f0e },
+#endif
{ 0x3d4001a0, 0xe0400018 },
{ 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
@@ -50,6 +81,30 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d4001c0, 0x1 },
{ 0x3d4001c4, 0x1 },
{ 0x3d4000f4, 0xc99 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ { 0x3d400108, 0x60c1514 },
+ { 0x3d400200, 0x16 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x68070707 },
+ { 0x3d40021c, 0xf08 },
+ { 0x3d400250, 0x1f05 },
+ { 0x3d400254, 0x1f },
+ { 0x3d400264, 0x90003ff },
+ { 0x3d40026c, 0x20003ff },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x1000e00 },
+ { 0x3d400498, 0x3ff0000 },
+ { 0x3d40049c, 0x1000e00 },
+ { 0x3d4004a0, 0x3ff0000 },
+ { 0x3d402020, 0x21 },
+ { 0x3d402024, 0x30d400 },
+ { 0x3d402050, 0x20d000 },
+ { 0x3d402064, 0xc001c },
+#else
{ 0x3d400108, 0x9121c1c },
#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
{ 0x3d400200, 0x13 },
@@ -83,6 +138,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d402024, 0x30d400 },
{ 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc0026 },
+#endif
{ 0x3d4020dc, 0x840000 },
{ 0x3d4020e0, 0x330000 },
{ 0x3d4020e8, 0x660048 },
@@ -104,10 +160,17 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
{ 0x3d4020f4, 0xc99 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ { 0x3d403020, 0x21 },
+ { 0x3d403024, 0xc3500 },
+ { 0x3d403050, 0x20d000 },
+ { 0x3d403064, 0x30007 },
+#else
{ 0x3d403020, 0x1021 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x3000a },
+#endif
{ 0x3d4030dc, 0x840000 },
{ 0x3d4030e0, 0x330000 },
{ 0x3d4030e8, 0x660048 },
@@ -200,7 +263,11 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
{ 0x7055, 0x1ff },
{ 0x8055, 0x1ff },
{ 0x9055, 0x1ff },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ { 0x200c5, 0xa },
+#else
{ 0x200c5, 0x18 },
+#endif
{ 0x1200c5, 0x7 },
{ 0x2200c5, 0x7 },
{ 0x2002e, 0x2 },
@@ -279,7 +346,11 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ { 0x20008, 0x258 },
+#else
{ 0x20008, 0x3e8 },
+#endif
{ 0x120008, 0x64 },
{ 0x220008, 0x19 },
{ 0x20088, 0x9 },
@@ -1066,6 +1137,38 @@ struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
/* P0 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_cfg[] = {
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ { 0xd0000, 0x0 },
+ { 0x54003, 0x960 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x24c4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x24c4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xc400 },
+ { 0x54033, 0x3324 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xc400 },
+ { 0x54039, 0x3324 },
+#else
{ 0xd0000, 0x0 },
{ 0x54003, 0xfa0 },
{ 0x54004, 0x2 },
@@ -1096,6 +1199,7 @@ struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0x54037, 0x1600 },
{ 0x54038, 0xf400 },
{ 0x54039, 0x333f },
+#endif
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1186,6 +1290,39 @@ struct dram_cfg_param ddr_fsp2_cfg[] = {
/* P0 2D message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ { 0x54003, 0x960 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400d, 0x100 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x24c4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x24c4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xc400 },
+ { 0x54033, 0x3324 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xc400 },
+ { 0x54039, 0x3324 },
+#else
{ 0x54003, 0xfa0 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
@@ -1217,6 +1354,7 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0x54037, 0x1600 },
{ 0x54038, 0xf400 },
{ 0x54039, 0x333f },
+#endif
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1705,10 +1843,16 @@ struct dram_cfg_param ddr_phy_pie[] = {
{ 0x400d6, 0x20a },
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ { 0x2000b, 0x4b },
+ { 0x2000c, 0x96 },
+ { 0x2000d, 0x5dc },
+#else
{ 0x200be, 0x3 },
{ 0x2000b, 0x7d },
{ 0x2000c, 0xfa },
{ 0x2000d, 0x9c4 },
+#endif
{ 0x2000e, 0x2c },
{ 0x12000b, 0xc },
{ 0x12000c, 0x19 },
@@ -1728,6 +1872,12 @@ struct dram_cfg_param ddr_phy_pie[] = {
{ 0x90013, 0x6152 },
{ 0x20010, 0x5a },
{ 0x20011, 0x3 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ { 0x120010, 0x5a },
+ { 0x120011, 0x3 },
+ { 0x220010, 0x5a },
+ { 0x220011, 0x3 },
+#endif
{ 0x40080, 0xe0 },
{ 0x40081, 0x12 },
{ 0x40082, 0xe0 },
@@ -1811,8 +1961,13 @@ struct dram_cfg_param ddr_phy_pie[] = {
struct dram_fsp_msg ddr_dram_fsp_msg[] = {
{
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ /* P0 2400mts 1D */
+ .drate = 2400,
+#else
/* P0 4000mts 1D */
.drate = 4000,
+#endif
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
@@ -1832,8 +1987,13 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = {
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
},
{
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ /* P0 2400mts 2D */
+ .drate = 2400,
+#else
/* P0 4000mts 2D */
.drate = 4000,
+#endif
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
@@ -1852,9 +2012,14 @@ struct dram_timing_info dram_timing = {
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ .fsp_table = { 2400, 400, 100, },
+#else
.fsp_table = { 4000, 400, 100, },
+#endif
};
+#ifndef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
void board_dram_ecc_scrub(void)
{
@@ -1882,3 +2047,4 @@ void board_dram_ecc_scrub(void)
ddrc_inline_ecc_scrub_end(0x0, 0x5fffffff);
}
#endif
+#endif
diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c
index ebfd94dc1f..3f043c2b2e 100644
--- a/board/freescale/imx8mp_evk/spl.c
+++ b/board/freescale/imx8mp_evk/spl.c
@@ -84,7 +84,12 @@ int power_init_board(void)
* Enable DVS control through PMIC_STBY_REQ and
* set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
*/
+#ifdef CONFIG_IMX8M_VDD_SOC_850MV
+ /* set DVS0 to 0.85v for special case*/
+ pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
+#else
pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
+#endif
pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
diff --git a/drivers/ddr/imx/imx8m/Kconfig b/drivers/ddr/imx/imx8m/Kconfig
index a5f5524fbe..a90b7db494 100644
--- a/drivers/ddr/imx/imx8m/Kconfig
+++ b/drivers/ddr/imx/imx8m/Kconfig
@@ -36,4 +36,12 @@ config IMX8M_DRAM_INLINE_ECC
help
Select this config if you want to use inline ecc feature for
imx8mp-evk board.
+
+config IMX8M_VDD_SOC_850MV
+ bool "imx8mp change the vdd_soc voltage to 850mv"
+ depends on IMX8MP
+
+config IMX8M_LPDDR4_FREQ0_2400MTS
+ bool "imx8m PDDR4 freq0 change from 4000MTS to 2400MTS"
+
endmenu
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 11/26] imx8mp_evk: spl: clean up including headers
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (9 preceding siblings ...)
2021-03-19 7:57 ` [PATCH 10/26] imx8mp: refine power on imx8mp board Peng Fan
@ 2021-03-19 7:57 ` Peng Fan
2021-03-19 7:57 ` [PATCH 12/26] imx8mp_evk: Increase VDD_ARM to 0.95v Overdrive voltage Peng Fan
` (14 subsequent siblings)
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:57 UTC (permalink / raw)
To: u-boot
From: Peng Fan <peng.fan@nxp.com>
Clean up the including headers
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
board/freescale/imx8mp_evk/spl.c | 17 ++++-------------
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c
index 3f043c2b2e..ef14cfc227 100644
--- a/board/freescale/imx8mp_evk/spl.c
+++ b/board/freescale/imx8mp_evk/spl.c
@@ -5,30 +5,21 @@
*/
#include <common.h>
-#include <command.h>
-#include <cpu_func.h>
#include <hang.h>
-#include <image.h>
#include <init.h>
#include <log.h>
#include <spl.h>
#include <asm/global_data.h>
-#include <asm/io.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/clock.h>
#include <asm/arch/imx8mp_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
-#include <power/pmic.h>
-
-#include <power/pca9450.h>
-#include <asm/arch/clock.h>
#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
-#include <fsl_esdhc.h>
-#include <mmc.h>
#include <asm/arch/ddr.h>
+#include <power/pmic.h>
+#include <power/pca9450.h>
DECLARE_GLOBAL_DATA_PTR;
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 12/26] imx8mp_evk: Increase VDD_ARM to 0.95v Overdrive voltage
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (10 preceding siblings ...)
2021-03-19 7:57 ` [PATCH 11/26] imx8mp_evk: spl: clean up including headers Peng Fan
@ 2021-03-19 7:57 ` Peng Fan
2021-03-19 7:57 ` [PATCH 13/26] imx8mn: Update the DDR4 timing script on imx8mn ddr4 evk Peng Fan
` (13 subsequent siblings)
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:57 UTC (permalink / raw)
To: u-boot
From: Peng Fan <peng.fan@nxp.com>
There is a frequency/timing limitation for SOC and ARM, if SOC is OD
voltage/OD freq, then ARM can't run at ND voltage/1.2Ghz, it may have
timing risk from SOC to ARM.
Current VDD_SOC is set to 0.95v OD voltage in SPL, and kernel will
increase bus clocks to OD frequency before it increases ARM voltage.
So to conform to the limitation, we'd better increases VDD_ARM to OD
voltage in SPL.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
board/freescale/imx8mp_evk/spl.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c
index ef14cfc227..6ccf5ac8fa 100644
--- a/board/freescale/imx8mp_evk/spl.c
+++ b/board/freescale/imx8mp_evk/spl.c
@@ -35,6 +35,16 @@ void spl_dram_init(void)
void spl_board_init(void)
{
+ /*
+ * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
+ * not allow to change it. Should set the clock after PMIC
+ * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
+ * set by ROM for ND VDD_SOC
+ */
+ clock_enable(CCGR_GIC, 0);
+ clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
+ clock_enable(CCGR_GIC, 1);
+
puts("Normal Boot\n");
}
@@ -84,6 +94,10 @@ int power_init_board(void)
pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
+ /* Kernel uses OD/OD freq for SOC */
+ /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
+ pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
+
/* set WDOG_B_CFG to cold reset */
pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 13/26] imx8mn: Update the DDR4 timing script on imx8mn ddr4 evk
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (11 preceding siblings ...)
2021-03-19 7:57 ` [PATCH 12/26] imx8mp_evk: Increase VDD_ARM to 0.95v Overdrive voltage Peng Fan
@ 2021-03-19 7:57 ` Peng Fan
2021-03-19 7:57 ` [PATCH 14/26] power: pca9450: add a new parameter for power_pca9450_init Peng Fan
` (12 subsequent siblings)
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:57 UTC (permalink / raw)
To: u-boot
From: Jacky Bai <ping.bai@nxp.com>
On i.MX8MN, we can only support DLL-ON mode only, so update the timing
to support 2400mts & 1066mts setpoint.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
board/freescale/imx8mn_evk/ddr4_timing.c | 1057 +++++++++-------------
1 file changed, 449 insertions(+), 608 deletions(-)
diff --git a/board/freescale/imx8mn_evk/ddr4_timing.c b/board/freescale/imx8mn_evk/ddr4_timing.c
index cfd193a78d..f1509e2159 100644
--- a/board/freescale/imx8mn_evk/ddr4_timing.c
+++ b/board/freescale/imx8mn_evk/ddr4_timing.c
@@ -1,121 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
- *
* Generated code from MX8M_DDR_tool
- * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
*/
#include <linux/kernel.h>
#include <asm/arch/ddr.h>
struct dram_cfg_param ddr_ddrc_cfg[] = {
- {0x3d400000, 0x81040010},
- {0x3d400030, 0x00000020},
- {0x3d400034, 0x00221306},
- {0x3d400050, 0x00210070},
- {0x3d400054, 0x00010008},
- {0x3d400060, 0x00000000},
- {0x3d400064, 0x0092014a},
- {0x3d4000c0, 0x00000000},
- {0x3d4000c4, 0x00001000},
- {0x3d4000d0, 0xc0030126},
- {0x3d4000d4, 0x00770000},
- {0x3d4000dc, 0x08340105},
- {0x3d4000e0, 0x00180200},
- {0x3d4000e4, 0x00110000},
- {0x3d4000e8, 0x02000740},
- {0x3d4000ec, 0x00000850},
- {0x3d4000f4, 0x00000ec7},
- {0x3d400100, 0x11122914},
- {0x3d400104, 0x0004051c},
- {0x3d400108, 0x0608050d},
- {0x3d40010c, 0x0000400c},
- {0x3d400110, 0x08030409},
- {0x3d400114, 0x06060403},
- {0x3d40011c, 0x00000606},
- {0x3d400120, 0x07070d0c},
- {0x3d400124, 0x0002040a},
- {0x3d40012c, 0x1809010e},
- {0x3d400130, 0x00000008},
- {0x3d40013c, 0x00000000},
- {0x3d400180, 0x01000040},
- {0x3d400184, 0x0000493e},
- {0x3d400190, 0x038b8207},
- {0x3d400194, 0x02020303},
- {0x3d400198, 0x07f04011},
- {0x3d40019c, 0x000000b0},
- {0x3d4001a0, 0xe0400018},
- {0x3d4001a4, 0x0048005a},
- {0x3d4001a8, 0x80000000},
- {0x3d4001b0, 0x00000001},
- {0x3d4001b4, 0x00000b07},
- {0x3d4001b8, 0x00000004},
- {0x3d4001c0, 0x00000001},
- {0x3d4001c4, 0x00000000},
- {0x3d400240, 0x06000610},
- {0x3d400244, 0x00001323},
- {0x3d400200, 0x00003f1f},
- {0x3d400204, 0x003f0909},
- {0x3d400208, 0x01010100},
- {0x3d40020c, 0x01010101},
- {0x3d400210, 0x00001f1f},
- {0x3d400214, 0x07070707},
- {0x3d400218, 0x07070707},
- {0x3d40021c, 0x00000f07},
- {0x3d400220, 0x00003f01},
- {0x3d402050, 0x00210070},
- {0x3d402064, 0x00180037},
- {0x3d4020dc, 0x00000105},
- {0x3d4020e0, 0x00000000},
- {0x3d4020e8, 0x02000740},
- {0x3d4020ec, 0x00000050},
- {0x3d402100, 0x08030604},
- {0x3d402104, 0x00020205},
- {0x3d402108, 0x05050309},
- {0x3d40210c, 0x0000400c},
- {0x3d402110, 0x02030202},
- {0x3d402114, 0x03030202},
- {0x3d402118, 0x0a070008},
- {0x3d40211c, 0x00000d09},
- {0x3d402120, 0x08084b09},
- {0x3d402124, 0x00020308},
- {0x3d402128, 0x000f0d06},
- {0x3d40212c, 0x12060111},
- {0x3d402130, 0x00000008},
- {0x3d40213c, 0x00000000},
- {0x3d402180, 0x01000040},
- {0x3d402190, 0x03848204},
- {0x3d402194, 0x02020303},
- {0x3d4021b4, 0x00000404},
- {0x3d4021b8, 0x00000004},
- {0x3d402240, 0x07000600},
- {0x3d403050, 0x00210070},
- {0x3d403064, 0x0006000d},
- {0x3d4030dc, 0x00000105},
- {0x3d4030e0, 0x00000000},
- {0x3d4030e8, 0x02000740},
- {0x3d4030ec, 0x00000050},
- {0x3d403100, 0x07010101},
- {0x3d403104, 0x00020202},
- {0x3d403108, 0x05050309},
- {0x3d40310c, 0x0000400c},
- {0x3d403110, 0x01030201},
- {0x3d403114, 0x03030202},
- {0x3d40311c, 0x00000303},
- {0x3d403120, 0x02020d02},
- {0x3d403124, 0x00020208},
- {0x3d403128, 0x000f0d06},
- {0x3d40312c, 0x0e02010e},
- {0x3d403130, 0x00000008},
- {0x3d40313c, 0x00000000},
- {0x3d403180, 0x01000040},
- {0x3d403190, 0x03848204},
- {0x3d403194, 0x02020303},
- {0x3d4031b4, 0x00000404},
- {0x3d4031b8, 0x00000004},
- {0x3d403240, 0x07000600},
+ /** Initialize DDRC registers **/
+ { 0x3d400000, 0x81040010 },
+ { 0x3d400030, 0x20 },
+ { 0x3d400034, 0x221306 },
+ { 0x3d400050, 0x210070 },
+ { 0x3d400054, 0x10008 },
+ { 0x3d400060, 0x0 },
+ { 0x3d400064, 0x92014a },
+ { 0x3d4000c0, 0x0 },
+ { 0x3d4000c4, 0x1000 },
+ { 0x3d4000d0, 0xc0030126 },
+ { 0x3d4000d4, 0x770000 },
+ { 0x3d4000dc, 0x8340105 },
+ { 0x3d4000e0, 0x180200 },
+ { 0x3d4000e4, 0x110000 },
+ { 0x3d4000e8, 0x2000600 },
+ { 0x3d4000ec, 0x810 },
+ { 0x3d4000f0, 0x20 },
+ { 0x3d4000f4, 0xec7 },
+ { 0x3d400100, 0x11122914 },
+ { 0x3d400104, 0x4051c },
+ { 0x3d400108, 0x608050d },
+ { 0x3d40010c, 0x400c },
+ { 0x3d400110, 0x8030409 },
+ { 0x3d400114, 0x6060403 },
+ { 0x3d40011c, 0x606 },
+ { 0x3d400120, 0x7070d0c },
+ { 0x3d400124, 0x2040a },
+ { 0x3d40012c, 0x1809010e },
+ { 0x3d400130, 0x8 },
+ { 0x3d40013c, 0x0 },
+ { 0x3d400180, 0x1000040 },
+ { 0x3d400184, 0x493e },
+ { 0x3d400190, 0x38b8207 },
+ { 0x3d400194, 0x2020303 },
+ { 0x3d400198, 0x7f04011 },
+ { 0x3d40019c, 0xb0 },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0x48005a },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x1 },
+ { 0x3d4001b4, 0xb07 },
+ { 0x3d4001b8, 0x4 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x0 },
+ { 0x3d400200, 0x3f1f },
+ { 0x3d400204, 0x3f0909 },
+ { 0x3d400208, 0x700 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf07 },
+ { 0x3d400220, 0x3f01 },
+ { 0x3d400240, 0x6000610 },
+ { 0x3d400244, 0x1323 },
+ { 0x3d400400, 0x100 },
/* performance setting */
{ 0x3d400250, 0x00001f05 },
@@ -126,141 +78,136 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400498, 0x03ff0000 },
{ 0x3d40049c, 0x01000e00 },
{ 0x3d4004a0, 0x03ff0000 },
+
+ { 0x3d402050, 0x210070 },
+ { 0x3d402064, 0x400093 },
+ { 0x3d4020dc, 0x105 },
+ { 0x3d4020e0, 0x0 },
+ { 0x3d4020e8, 0x2000600 },
+ { 0x3d4020ec, 0x10 },
+ { 0x3d402100, 0xb081209 },
+ { 0x3d402104, 0x2020d },
+ { 0x3d402108, 0x5050309 },
+ { 0x3d40210c, 0x400c },
+ { 0x3d402110, 0x5030206 },
+ { 0x3d402114, 0x3030202 },
+ { 0x3d40211c, 0x303 },
+ { 0x3d402120, 0x4040d06 },
+ { 0x3d402124, 0x20208 },
+ { 0x3d40212c, 0x1205010e },
+ { 0x3d402130, 0x8 },
+ { 0x3d40213c, 0x0 },
+ { 0x3d402180, 0x1000040 },
+ { 0x3d402190, 0x3848204 },
+ { 0x3d402194, 0x2020303 },
+ { 0x3d4021b4, 0x404 },
+ { 0x3d4021b8, 0x4 },
+ { 0x3d402240, 0x6000600 },
+ { 0x3d4020f4, 0xec7 },
};
/* PHY Initialize Configuration */
struct dram_cfg_param ddr_ddrphy_cfg[] = {
- {0x0001005f, 0x000002fd},
- {0x0001015f, 0x000002fd},
- {0x0001105f, 0x000002fd},
- {0x0001115f, 0x000002fd},
- {0x0011005f, 0x000002fd},
- {0x0011015f, 0x000002fd},
- {0x0011105f, 0x000002fd},
- {0x0011115f, 0x000002fd},
- {0x0021005f, 0x000002fd},
- {0x0021015f, 0x000002fd},
- {0x0021105f, 0x000002fd},
- {0x0021115f, 0x000002fd},
- {0x00000055, 0x00000355},
- {0x00001055, 0x00000355},
- {0x00002055, 0x00000355},
- {0x00003055, 0x00000355},
- {0x00004055, 0x00000055},
- {0x00005055, 0x00000055},
- {0x00006055, 0x00000355},
- {0x00007055, 0x00000355},
- {0x00008055, 0x00000355},
- {0x00009055, 0x00000355},
- {0x000200c5, 0x0000000a},
- {0x001200c5, 0x00000007},
- {0x002200c5, 0x00000007},
- {0x0002002e, 0x00000002},
- {0x0012002e, 0x00000002},
- {0x0022002e, 0x00000002},
- {0x00020024, 0x00000008},
- {0x0002003a, 0x00000002},
- {0x0002007d, 0x00000212},
- {0x0002007c, 0x00000061},
- {0x00120024, 0x00000008},
- {0x0002003a, 0x00000002},
- {0x0012007d, 0x00000212},
- {0x0012007c, 0x00000061},
- {0x00220024, 0x00000008},
- {0x0002003a, 0x00000002},
- {0x0022007d, 0x00000212},
- {0x0022007c, 0x00000061},
- {0x00020056, 0x00000006},
- {0x00120056, 0x0000000a},
- {0x00220056, 0x0000000a},
- {0x0001004d, 0x0000001a},
- {0x0001014d, 0x0000001a},
- {0x0001104d, 0x0000001a},
- {0x0001114d, 0x0000001a},
- {0x0011004d, 0x0000001a},
- {0x0011014d, 0x0000001a},
- {0x0011104d, 0x0000001a},
- {0x0011114d, 0x0000001a},
- {0x0021004d, 0x0000001a},
- {0x0021014d, 0x0000001a},
- {0x0021104d, 0x0000001a},
- {0x0021114d, 0x0000001a},
- {0x00010049, 0x00000e38},
- {0x00010149, 0x00000e38},
- {0x00011049, 0x00000e38},
- {0x00011149, 0x00000e38},
- {0x00110049, 0x00000e38},
- {0x00110149, 0x00000e38},
- {0x00111049, 0x00000e38},
- {0x00111149, 0x00000e38},
- {0x00210049, 0x00000e38},
- {0x00210149, 0x00000e38},
- {0x00211049, 0x00000e38},
- {0x00211149, 0x00000e38},
- {0x00000043, 0x00000063},
- {0x00001043, 0x00000063},
- {0x00002043, 0x00000063},
- {0x00003043, 0x00000063},
- {0x00004043, 0x00000063},
- {0x00005043, 0x00000063},
- {0x00006043, 0x00000063},
- {0x00007043, 0x00000063},
- {0x00008043, 0x00000063},
- {0x00009043, 0x00000063},
- {0x00020018, 0x00000001},
- {0x00020075, 0x00000002},
- {0x00020050, 0x00000000},
- {0x00020008, 0x00000258},
- {0x00120008, 0x00000064},
- {0x00220008, 0x00000019},
- {0x00020088, 0x00000009},
- {0x000200b2, 0x00000268},
- {0x00010043, 0x000005b1},
- {0x00010143, 0x000005b1},
- {0x00011043, 0x000005b1},
- {0x00011143, 0x000005b1},
- {0x001200b2, 0x00000268},
- {0x00110043, 0x000005b1},
- {0x00110143, 0x000005b1},
- {0x00111043, 0x000005b1},
- {0x00111143, 0x000005b1},
- {0x002200b2, 0x00000268},
- {0x00210043, 0x000005b1},
- {0x00210143, 0x000005b1},
- {0x00211043, 0x000005b1},
- {0x00211143, 0x000005b1},
- {0x0002005b, 0x00007529},
- {0x0002005c, 0x00000000},
- {0x000200fa, 0x00000001},
- {0x001200fa, 0x00000001},
- {0x002200fa, 0x00000001},
- {0x00020019, 0x00000005},
- {0x00120019, 0x00000005},
- {0x00220019, 0x00000005},
- {0x000200f0, 0x00005665},
- {0x000200f1, 0x00005555},
- {0x000200f2, 0x00005555},
- {0x000200f3, 0x00005555},
- {0x000200f4, 0x00005555},
- {0x000200f5, 0x00005555},
- {0x000200f6, 0x00005555},
- {0x000200f7, 0x0000f000},
- {0x0001004a, 0x00000500},
- {0x0001104a, 0x00000500},
- {0x00020025, 0x00000000},
- {0x0002002d, 0x00000000},
- {0x0012002d, 0x00000000},
- {0x0022002d, 0x00000000},
- {0x0002002c, 0x00000000},
- {0x000200c7, 0x00000021},
- {0x000200ca, 0x00000024},
- {0x000200cc, 0x000001f7},
- {0x001200c7, 0x00000021},
- {0x001200ca, 0x00000024},
- {0x001200cc, 0x000001f7},
- {0x002200c7, 0x00000021},
- {0x002200ca, 0x00000024},
- {0x002200cc, 0x000001f7},
+ { 0x1005f, 0x2fd },
+ { 0x1015f, 0x2fd },
+ { 0x1105f, 0x2fd },
+ { 0x1115f, 0x2fd },
+ { 0x11005f, 0x2fd },
+ { 0x11015f, 0x2fd },
+ { 0x11105f, 0x2fd },
+ { 0x11115f, 0x2fd },
+ { 0x55, 0x355 },
+ { 0x1055, 0x355 },
+ { 0x2055, 0x355 },
+ { 0x3055, 0x355 },
+ { 0x4055, 0x55 },
+ { 0x5055, 0x55 },
+ { 0x6055, 0x355 },
+ { 0x7055, 0x355 },
+ { 0x8055, 0x355 },
+ { 0x9055, 0x355 },
+ { 0x200c5, 0xa },
+ { 0x1200c5, 0x6 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x1 },
+ { 0x20024, 0x8 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x8 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0x6 },
+ { 0x120056, 0xa },
+ { 0x1004d, 0x1a },
+ { 0x1014d, 0x1a },
+ { 0x1104d, 0x1a },
+ { 0x1114d, 0x1a },
+ { 0x11004d, 0x1a },
+ { 0x11014d, 0x1a },
+ { 0x11104d, 0x1a },
+ { 0x11114d, 0x1a },
+ { 0x10049, 0xe38 },
+ { 0x10149, 0xe38 },
+ { 0x11049, 0xe38 },
+ { 0x11149, 0xe38 },
+ { 0x110049, 0xe38 },
+ { 0x110149, 0xe38 },
+ { 0x111049, 0xe38 },
+ { 0x111149, 0xe38 },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x1 },
+ { 0x20075, 0x2 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x258 },
+ { 0x120008, 0x10a },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x268 },
+ { 0x10043, 0x5b1 },
+ { 0x10143, 0x5b1 },
+ { 0x11043, 0x5b1 },
+ { 0x11143, 0x5b1 },
+ { 0x1200b2, 0x268 },
+ { 0x110043, 0x5b1 },
+ { 0x110143, 0x5b1 },
+ { 0x111043, 0x5b1 },
+ { 0x111143, 0x5b1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x20019, 0x5 },
+ { 0x120019, 0x5 },
+ { 0x200f0, 0x5555 },
+ { 0x200f1, 0x5555 },
+ { 0x200f2, 0x5555 },
+ { 0x200f3, 0x5555 },
+ { 0x200f4, 0x5555 },
+ { 0x200f5, 0x5555 },
+ { 0x200f6, 0x5555 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x2005b, 0x7529 },
+ { 0x2005c, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x200cc, 0x1f7 },
+ { 0x1200c7, 0x21 },
+ { 0x1200ca, 0x24 },
+ { 0x1200cc, 0x1f7 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x2002c, 0x0 },
};
/* ddr phy trained csr */
@@ -792,378 +739,279 @@ struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
/* P0 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_cfg[] = {
- {0x000d0000, 0x00000000},
- {0x00020060, 0x00000002},
- {0x00054000, 0x00000000},
- {0x00054001, 0x00000000},
- {0x00054002, 0x00000000},
- {0x00054003, 0x00000960},
- {0x00054004, 0x00000002},
- {0x00054005, 0x00000000},
- {0x00054006, 0x0000025e},
- {0x00054007, 0x00001000},
- {0x00054008, 0x00000101},
- {0x00054009, 0x00000000},
- {0x0005400a, 0x00000000},
- {0x0005400b, 0x0000031f},
- {0x0005400c, 0x000000c8},
- {0x0005400d, 0x00000100},
- {0x0005400e, 0x00000000},
- {0x0005400f, 0x00000000},
- {0x00054010, 0x00000000},
- {0x00054011, 0x00000000},
- {0x00054012, 0x00000001},
- {0x0005402f, 0x00000834},
- {0x00054030, 0x00000105},
- {0x00054031, 0x00000018},
- {0x00054032, 0x00000200},
- {0x00054033, 0x00000200},
- {0x00054034, 0x00000740},
- {0x00054035, 0x00000850},
- {0x00054036, 0x00000103},
- {0x00054037, 0x00000000},
- {0x00054038, 0x00000000},
- {0x00054039, 0x00000000},
- {0x0005403a, 0x00000000},
- {0x0005403b, 0x00000000},
- {0x0005403c, 0x00000000},
- {0x0005403d, 0x00000000},
- {0x0005403e, 0x00000000},
- {0x0005403f, 0x00001221},
- {0x000541fc, 0x00000100},
- {0x000d0000, 0x00000001},
+ { 0xd0000, 0x0 },
+ { 0x54003, 0x960 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2830 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x31f },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x100 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x834 },
+ { 0x54030, 0x105 },
+ { 0x54031, 0x18 },
+ { 0x54032, 0x200 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x600 },
+ { 0x54035, 0x810 },
+ { 0x54036, 0x101 },
+ { 0x5403f, 0x1221 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 },
};
/* P1 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp1_cfg[] = {
- {0x000d0000, 0x00000000},
- {0x00054000, 0x00000000},
- {0x00054001, 0x00000000},
- {0x00054002, 0x00000101},
- {0x00054003, 0x00000190},
- {0x00054004, 0x00000002},
- {0x00054005, 0x00000000},
- {0x00054006, 0x0000025e},
- {0x00054007, 0x00001000},
- {0x00054008, 0x00000101},
- {0x00054009, 0x00000000},
- {0x0005400a, 0x00000000},
- {0x0005400b, 0x0000021f},
- {0x0005400c, 0x000000c8},
- {0x0005400d, 0x00000100},
- {0x0005400e, 0x00000000},
- {0x0005400f, 0x00000000},
- {0x00054010, 0x00000000},
- {0x00054011, 0x00000000},
- {0x00054012, 0x00000001},
- {0x0005402f, 0x00000000},
- {0x00054030, 0x00000105},
- {0x00054031, 0x00000000},
- {0x00054032, 0x00000000},
- {0x00054033, 0x00000200},
- {0x00054034, 0x00000740},
- {0x00054035, 0x00000050},
- {0x00054036, 0x00000103},
- {0x00054037, 0x00000000},
- {0x00054038, 0x00000000},
- {0x00054039, 0x00000000},
- {0x0005403a, 0x00000000},
- {0x0005403b, 0x00000000},
- {0x0005403c, 0x00000000},
- {0x0005403d, 0x00000000},
- {0x0005403e, 0x00000000},
- {0x0005403f, 0x00001221},
- {0x000541fc, 0x00000100},
- {0x000d0000, 0x00000001},
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x1 },
+ { 0x54003, 0x42a },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2830 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x21f },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x100 },
+ { 0x54012, 0x1 },
+ { 0x54030, 0x105 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x600 },
+ { 0x54035, 0x10 },
+ { 0x54036, 0x101 },
+ { 0x5403f, 0x1221 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 },
};
-/* P2 message block paremeter for training firmware */
-struct dram_cfg_param ddr_fsp2_cfg[] = {
- {0x000d0000, 0x00000000},
- {0x00054000, 0x00000000},
- {0x00054001, 0x00000000},
- {0x00054002, 0x00000102},
- {0x00054003, 0x00000064},
- {0x00054004, 0x00000002},
- {0x00054005, 0x00000000},
- {0x00054006, 0x0000025e},
- {0x00054007, 0x00001000},
- {0x00054008, 0x00000101},
- {0x00054009, 0x00000000},
- {0x0005400a, 0x00000000},
- {0x0005400b, 0x0000021f},
- {0x0005400c, 0x000000c8},
- {0x0005400d, 0x00000100},
- {0x0005400e, 0x00000000},
- {0x0005400f, 0x00000000},
- {0x00054010, 0x00000000},
- {0x00054011, 0x00000000},
- {0x00054012, 0x00000001},
- {0x0005402f, 0x00000000},
- {0x00054030, 0x00000105},
- {0x00054031, 0x00000000},
- {0x00054032, 0x00000000},
- {0x00054033, 0x00000200},
- {0x00054034, 0x00000740},
- {0x00054035, 0x00000050},
- {0x00054036, 0x00000103},
- {0x00054037, 0x00000000},
- {0x00054038, 0x00000000},
- {0x00054039, 0x00000000},
- {0x0005403a, 0x00000000},
- {0x0005403b, 0x00000000},
- {0x0005403c, 0x00000000},
- {0x0005403d, 0x00000000},
- {0x0005403e, 0x00000000},
- {0x0005403f, 0x00001221},
- {0x000541fc, 0x00000100},
- {0x000d0000, 0x00000001},
-};
/* P0 2D message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
- {0x000d0000, 0x00000000},
- {0x00054000, 0x00000000},
- {0x00054001, 0x00000000},
- {0x00054002, 0x00000000},
- {0x00054003, 0x00000960},
- {0x00054004, 0x00000002},
- {0x00054005, 0x00000000},
- {0x00054006, 0x0000025e},
- {0x00054007, 0x00001000},
- {0x00054008, 0x00000101},
- {0x00054009, 0x00000000},
- {0x0005400a, 0x00000000},
- {0x0005400b, 0x00000061},
- {0x0005400c, 0x000000c8},
- {0x0005400d, 0x00000100},
- {0x0005400e, 0x00001f7f},
- {0x0005400f, 0x00000000},
- {0x00054010, 0x00000000},
- {0x00054011, 0x00000000},
- {0x00054012, 0x00000001},
- {0x0005402f, 0x00000834},
- {0x00054030, 0x00000105},
- {0x00054031, 0x00000018},
- {0x00054032, 0x00000200},
- {0x00054033, 0x00000200},
- {0x00054034, 0x00000740},
- {0x00054035, 0x00000850},
- {0x00054036, 0x00000103},
- {0x00054037, 0x00000000},
- {0x00054038, 0x00000000},
- {0x00054039, 0x00000000},
- {0x0005403a, 0x00000000},
- {0x0005403b, 0x00000000},
- {0x0005403c, 0x00000000},
- {0x0005403d, 0x00000000},
- {0x0005403e, 0x00000000},
- {0x0005403f, 0x00001221},
- {0x000541fc, 0x00000100},
- {0x000d0000, 0x00000001},
+ { 0xd0000, 0x0 },
+ { 0x54003, 0x960 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2830 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x61 },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x100 },
+ { 0x5400e, 0x1f7f },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x834 },
+ { 0x54030, 0x105 },
+ { 0x54031, 0x18 },
+ { 0x54032, 0x200 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x600 },
+ { 0x54035, 0x810 },
+ { 0x54036, 0x101 },
+ { 0x5403f, 0x1221 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 },
};
/* DRAM PHY init engine image */
struct dram_cfg_param ddr_phy_pie[] = {
- {0xd0000, 0x0},
- {0x90000, 0x10},
- {0x90001, 0x400},
- {0x90002, 0x10e},
- {0x90003, 0x0},
- {0x90004, 0x0},
- {0x90005, 0x8},
- {0x90029, 0xb},
- {0x9002a, 0x480},
- {0x9002b, 0x109},
- {0x9002c, 0x8},
- {0x9002d, 0x448},
- {0x9002e, 0x139},
- {0x9002f, 0x8},
- {0x90030, 0x478},
- {0x90031, 0x109},
- {0x90032, 0x2},
- {0x90033, 0x10},
- {0x90034, 0x139},
- {0x90035, 0xb},
- {0x90036, 0x7c0},
- {0x90037, 0x139},
- {0x90038, 0x44},
- {0x90039, 0x633},
- {0x9003a, 0x159},
- {0x9003b, 0x14f},
- {0x9003c, 0x630},
- {0x9003d, 0x159},
- {0x9003e, 0x47},
- {0x9003f, 0x633},
- {0x90040, 0x149},
- {0x90041, 0x4f},
- {0x90042, 0x633},
- {0x90043, 0x179},
- {0x90044, 0x8},
- {0x90045, 0xe0},
- {0x90046, 0x109},
- {0x90047, 0x0},
- {0x90048, 0x7c8},
- {0x90049, 0x109},
- {0x9004a, 0x0},
- {0x9004b, 0x1},
- {0x9004c, 0x8},
- {0x9004d, 0x0},
- {0x9004e, 0x45a},
- {0x9004f, 0x9},
- {0x90050, 0x0},
- {0x90051, 0x448},
- {0x90052, 0x109},
- {0x90053, 0x40},
- {0x90054, 0x633},
- {0x90055, 0x179},
- {0x90056, 0x1},
- {0x90057, 0x618},
- {0x90058, 0x109},
- {0x90059, 0x40c0},
- {0x9005a, 0x633},
- {0x9005b, 0x149},
- {0x9005c, 0x8},
- {0x9005d, 0x4},
- {0x9005e, 0x48},
- {0x9005f, 0x4040},
- {0x90060, 0x633},
- {0x90061, 0x149},
- {0x90062, 0x0},
- {0x90063, 0x4},
- {0x90064, 0x48},
- {0x90065, 0x40},
- {0x90066, 0x633},
- {0x90067, 0x149},
- {0x90068, 0x10},
- {0x90069, 0x4},
- {0x9006a, 0x18},
- {0x9006b, 0x0},
- {0x9006c, 0x4},
- {0x9006d, 0x78},
- {0x9006e, 0x549},
- {0x9006f, 0x633},
- {0x90070, 0x159},
- {0x90071, 0xd49},
- {0x90072, 0x633},
- {0x90073, 0x159},
- {0x90074, 0x94a},
- {0x90075, 0x633},
- {0x90076, 0x159},
- {0x90077, 0x441},
- {0x90078, 0x633},
- {0x90079, 0x149},
- {0x9007a, 0x42},
- {0x9007b, 0x633},
- {0x9007c, 0x149},
- {0x9007d, 0x1},
- {0x9007e, 0x633},
- {0x9007f, 0x149},
- {0x90080, 0x0},
- {0x90081, 0xe0},
- {0x90082, 0x109},
- {0x90083, 0xa},
- {0x90084, 0x10},
- {0x90085, 0x109},
- {0x90086, 0x9},
- {0x90087, 0x3c0},
- {0x90088, 0x149},
- {0x90089, 0x9},
- {0x9008a, 0x3c0},
- {0x9008b, 0x159},
- {0x9008c, 0x18},
- {0x9008d, 0x10},
- {0x9008e, 0x109},
- {0x9008f, 0x0},
- {0x90090, 0x3c0},
- {0x90091, 0x109},
- {0x90092, 0x18},
- {0x90093, 0x4},
- {0x90094, 0x48},
- {0x90095, 0x18},
- {0x90096, 0x4},
- {0x90097, 0x58},
- {0x90098, 0xb},
- {0x90099, 0x10},
- {0x9009a, 0x109},
- {0x9009b, 0x1},
- {0x9009c, 0x10},
- {0x9009d, 0x109},
- {0x9009e, 0x5},
- {0x9009f, 0x7c0},
- {0x900a0, 0x109},
- {0x900a1, 0x0},
- {0x900a2, 0x8140},
- {0x900a3, 0x10c},
- {0x900a4, 0x10},
- {0x900a5, 0x8138},
- {0x900a6, 0x10c},
- {0x900a7, 0x8},
- {0x900a8, 0x7c8},
- {0x900a9, 0x101},
- {0x900aa, 0x8},
- {0x900ab, 0x448},
- {0x900ac, 0x109},
- {0x900ad, 0xf},
- {0x900ae, 0x7c0},
- {0x900af, 0x109},
- {0x900b0, 0x47},
- {0x900b1, 0x630},
- {0x900b2, 0x109},
- {0x900b3, 0x8},
- {0x900b4, 0x618},
- {0x900b5, 0x109},
- {0x900b6, 0x8},
- {0x900b7, 0xe0},
- {0x900b8, 0x109},
- {0x900b9, 0x0},
- {0x900ba, 0x7c8},
- {0x900bb, 0x109},
- {0x900bc, 0x8},
- {0x900bd, 0x8140},
- {0x900be, 0x10c},
- {0x900bf, 0x0},
- {0x900c0, 0x1},
- {0x900c1, 0x8},
- {0x900c2, 0x8},
- {0x900c3, 0x4},
- {0x900c4, 0x8},
- {0x900c5, 0x8},
- {0x900c6, 0x7c8},
- {0x900c7, 0x101},
- {0x90006, 0x0},
- {0x90007, 0x0},
- {0x90008, 0x8},
- {0x90009, 0x0},
- {0x9000a, 0x0},
- {0x9000b, 0x0},
- {0xd00e7, 0x400},
- {0x90017, 0x0},
- {0x90026, 0x2b},
- {0x2000b, 0x4b},
- {0x2000c, 0x96},
- {0x2000d, 0x5dc},
- {0x2000e, 0x2c},
- {0x12000b, 0xc},
- {0x12000c, 0x16},
- {0x12000d, 0xfa},
- {0x12000e, 0x10},
- {0x22000b, 0x3},
- {0x22000c, 0x3},
- {0x22000d, 0x3e},
- {0x22000e, 0x10},
- {0x9000c, 0x0},
- {0x9000d, 0x173},
- {0x9000e, 0x60},
- {0x9000f, 0x6110},
- {0x90010, 0x2152},
- {0x90011, 0xdfbd},
- {0x90012, 0xffff},
- {0x90013, 0x6152},
- {0x20089, 0x1},
- {0x20088, 0x19},
- {0xc0080, 0x0},
- {0xd0000, 0x1},
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x2 },
+ { 0x90033, 0x10 },
+ { 0x90034, 0x139 },
+ { 0x90035, 0xb },
+ { 0x90036, 0x7c0 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0x44 },
+ { 0x90039, 0x633 },
+ { 0x9003a, 0x159 },
+ { 0x9003b, 0x14f },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x47 },
+ { 0x9003f, 0x633 },
+ { 0x90040, 0x149 },
+ { 0x90041, 0x4f },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x179 },
+ { 0x90044, 0x8 },
+ { 0x90045, 0xe0 },
+ { 0x90046, 0x109 },
+ { 0x90047, 0x0 },
+ { 0x90048, 0x7c8 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x1 },
+ { 0x9004c, 0x8 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x45a },
+ { 0x9004f, 0x9 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x448 },
+ { 0x90052, 0x109 },
+ { 0x90053, 0x40 },
+ { 0x90054, 0x633 },
+ { 0x90055, 0x179 },
+ { 0x90056, 0x1 },
+ { 0x90057, 0x618 },
+ { 0x90058, 0x109 },
+ { 0x90059, 0x40c0 },
+ { 0x9005a, 0x633 },
+ { 0x9005b, 0x149 },
+ { 0x9005c, 0x8 },
+ { 0x9005d, 0x4 },
+ { 0x9005e, 0x48 },
+ { 0x9005f, 0x4040 },
+ { 0x90060, 0x633 },
+ { 0x90061, 0x149 },
+ { 0x90062, 0x0 },
+ { 0x90063, 0x4 },
+ { 0x90064, 0x48 },
+ { 0x90065, 0x40 },
+ { 0x90066, 0x633 },
+ { 0x90067, 0x149 },
+ { 0x90068, 0x10 },
+ { 0x90069, 0x4 },
+ { 0x9006a, 0x18 },
+ { 0x9006b, 0x0 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x78 },
+ { 0x9006e, 0x549 },
+ { 0x9006f, 0x633 },
+ { 0x90070, 0x159 },
+ { 0x90071, 0xd49 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0x94a },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x441 },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x149 },
+ { 0x9007a, 0x42 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x1 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x0 },
+ { 0x90081, 0xe0 },
+ { 0x90082, 0x109 },
+ { 0x90083, 0xa },
+ { 0x90084, 0x10 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0x9 },
+ { 0x90087, 0x3c0 },
+ { 0x90088, 0x149 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x159 },
+ { 0x9008c, 0x18 },
+ { 0x9008d, 0x10 },
+ { 0x9008e, 0x109 },
+ { 0x9008f, 0x0 },
+ { 0x90090, 0x3c0 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x18 },
+ { 0x90093, 0x4 },
+ { 0x90094, 0x48 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x58 },
+ { 0x90098, 0xb },
+ { 0x90099, 0x10 },
+ { 0x9009a, 0x109 },
+ { 0x9009b, 0x1 },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x5 },
+ { 0x9009f, 0x7c0 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x0 },
+ { 0x900a2, 0x8140 },
+ { 0x900a3, 0x10c },
+ { 0x900a4, 0x10 },
+ { 0x900a5, 0x8138 },
+ { 0x900a6, 0x10c },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7c8 },
+ { 0x900a9, 0x101 },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x448 },
+ { 0x900ac, 0x109 },
+ { 0x900ad, 0xf },
+ { 0x900ae, 0x7c0 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x47 },
+ { 0x900b1, 0x630 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x8 },
+ { 0x900b4, 0x618 },
+ { 0x900b5, 0x109 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0xe0 },
+ { 0x900b8, 0x109 },
+ { 0x900b9, 0x0 },
+ { 0x900ba, 0x7c8 },
+ { 0x900bb, 0x109 },
+ { 0x900bc, 0x8 },
+ { 0x900bd, 0x8140 },
+ { 0x900be, 0x10c },
+ { 0x900bf, 0x0 },
+ { 0x900c0, 0x1 },
+ { 0x900c1, 0x8 },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x8 },
+ { 0x900c5, 0x8 },
+ { 0x900c6, 0x7c8 },
+ { 0x900c7, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x90026, 0x2b },
+ { 0x2000b, 0x4b },
+ { 0x2000c, 0x96 },
+ { 0x2000d, 0x5dc },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0x21 },
+ { 0x12000c, 0x42 },
+ { 0x12000d, 0x29a },
+ { 0x12000e, 0x21 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0xffff },
+ { 0x90013, 0x6152 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x0 },
+ { 0xd0000, 0x1 }
};
struct dram_fsp_msg ddr_dram_fsp_msg[] = {
@@ -1175,19 +1023,12 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = {
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
},
{
- /* P1 400mts 1D */
- .drate = 400,
+ /* P1 1066mts 1D */
+ .drate = 1066,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp1_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
},
- {
- /* P2 100mts 1D */
- .drate = 100,
- .fw_type = FW_1D_IMAGE,
- .fsp_cfg = ddr_fsp2_cfg,
- .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
- },
{
/* P0 2400mts 2D */
.drate = 2400,
@@ -1209,6 +1050,6 @@ struct dram_timing_info dram_timing = {
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 2400, 400, 100,},
+ .fsp_table = { 2400, 1066, },
};
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 14/26] power: pca9450: add a new parameter for power_pca9450_init
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (12 preceding siblings ...)
2021-03-19 7:57 ` [PATCH 13/26] imx8mn: Update the DDR4 timing script on imx8mn ddr4 evk Peng Fan
@ 2021-03-19 7:57 ` Peng Fan
2021-03-21 22:41 ` Jaehoon Chung
2021-03-19 7:57 ` [PATCH 15/26] imx8mn_evk: drop duplicated code Peng Fan
` (11 subsequent siblings)
25 siblings, 1 reply; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:57 UTC (permalink / raw)
To: u-boot
From: Peng Fan <peng.fan@nxp.com>
Currently PCA9450 might have address 0x25 or 0x35, so let user
choose the address.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
board/freescale/imx8mp_evk/spl.c | 2 +-
board/phytec/phycore_imx8mp/spl.c | 2 +-
drivers/power/pmic/pmic_pca9450.c | 4 ++--
include/power/pca9450.h | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c
index 6ccf5ac8fa..a7564e9b1a 100644
--- a/board/freescale/imx8mp_evk/spl.c
+++ b/board/freescale/imx8mp_evk/spl.c
@@ -70,7 +70,7 @@ int power_init_board(void)
struct pmic *p;
int ret;
- ret = power_pca9450_init(I2C_PMIC);
+ ret = power_pca9450_init(I2C_PMIC, 0x25);
if (ret)
printf("power init failed");
p = pmic_get("PCA9450");
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c
index eefdd7fdda..f9fa8d1e12 100644
--- a/board/phytec/phycore_imx8mp/spl.c
+++ b/board/phytec/phycore_imx8mp/spl.c
@@ -53,7 +53,7 @@ int power_init_board(void)
struct pmic *p;
int ret;
- ret = power_pca9450_init(0);
+ ret = power_pca9450_init(0, 0x25);
if (ret)
printf("power init failed");
p = pmic_get("PCA9450");
diff --git a/drivers/power/pmic/pmic_pca9450.c b/drivers/power/pmic/pmic_pca9450.c
index d4f27428bd..8c4d0a9230 100644
--- a/drivers/power/pmic/pmic_pca9450.c
+++ b/drivers/power/pmic/pmic_pca9450.c
@@ -11,7 +11,7 @@
static const char pca9450_name[] = "PCA9450";
-int power_pca9450_init(unsigned char bus)
+int power_pca9450_init(unsigned char bus, unsigned char addr)
{
struct pmic *p = pmic_alloc();
@@ -23,7 +23,7 @@ int power_pca9450_init(unsigned char bus)
p->name = pca9450_name;
p->interface = PMIC_I2C;
p->number_of_regs = PCA9450_REG_NUM;
- p->hw.i2c.addr = 0x25;
+ p->hw.i2c.addr = addr;
p->hw.i2c.tx_num = 1;
p->bus = bus;
diff --git a/include/power/pca9450.h b/include/power/pca9450.h
index 5a9a697d62..27703bb1f9 100644
--- a/include/power/pca9450.h
+++ b/include/power/pca9450.h
@@ -54,6 +54,6 @@ enum {
PCA9450_REG_NUM,
};
-int power_pca9450_init(unsigned char bus);
+int power_pca9450_init(unsigned char bus, unsigned char addr);
#endif
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 14/26] power: pca9450: add a new parameter for power_pca9450_init
2021-03-19 7:57 ` [PATCH 14/26] power: pca9450: add a new parameter for power_pca9450_init Peng Fan
@ 2021-03-21 22:41 ` Jaehoon Chung
0 siblings, 0 replies; 42+ messages in thread
From: Jaehoon Chung @ 2021-03-21 22:41 UTC (permalink / raw)
To: u-boot
On 3/19/21 4:57 PM, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> Currently PCA9450 might have address 0x25 or 0x35, so let user
> choose the address.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Best Regards,
Jaehoon Chung
> ---
> board/freescale/imx8mp_evk/spl.c | 2 +-
> board/phytec/phycore_imx8mp/spl.c | 2 +-
> drivers/power/pmic/pmic_pca9450.c | 4 ++--
> include/power/pca9450.h | 2 +-
> 4 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c
> index 6ccf5ac8fa..a7564e9b1a 100644
> --- a/board/freescale/imx8mp_evk/spl.c
> +++ b/board/freescale/imx8mp_evk/spl.c
> @@ -70,7 +70,7 @@ int power_init_board(void)
> struct pmic *p;
> int ret;
>
> - ret = power_pca9450_init(I2C_PMIC);
> + ret = power_pca9450_init(I2C_PMIC, 0x25);
> if (ret)
> printf("power init failed");
> p = pmic_get("PCA9450");
> diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c
> index eefdd7fdda..f9fa8d1e12 100644
> --- a/board/phytec/phycore_imx8mp/spl.c
> +++ b/board/phytec/phycore_imx8mp/spl.c
> @@ -53,7 +53,7 @@ int power_init_board(void)
> struct pmic *p;
> int ret;
>
> - ret = power_pca9450_init(0);
> + ret = power_pca9450_init(0, 0x25);
> if (ret)
> printf("power init failed");
> p = pmic_get("PCA9450");
> diff --git a/drivers/power/pmic/pmic_pca9450.c b/drivers/power/pmic/pmic_pca9450.c
> index d4f27428bd..8c4d0a9230 100644
> --- a/drivers/power/pmic/pmic_pca9450.c
> +++ b/drivers/power/pmic/pmic_pca9450.c
> @@ -11,7 +11,7 @@
>
> static const char pca9450_name[] = "PCA9450";
>
> -int power_pca9450_init(unsigned char bus)
> +int power_pca9450_init(unsigned char bus, unsigned char addr)
> {
> struct pmic *p = pmic_alloc();
>
> @@ -23,7 +23,7 @@ int power_pca9450_init(unsigned char bus)
> p->name = pca9450_name;
> p->interface = PMIC_I2C;
> p->number_of_regs = PCA9450_REG_NUM;
> - p->hw.i2c.addr = 0x25;
> + p->hw.i2c.addr = addr;
> p->hw.i2c.tx_num = 1;
> p->bus = bus;
>
> diff --git a/include/power/pca9450.h b/include/power/pca9450.h
> index 5a9a697d62..27703bb1f9 100644
> --- a/include/power/pca9450.h
> +++ b/include/power/pca9450.h
> @@ -54,6 +54,6 @@ enum {
> PCA9450_REG_NUM,
> };
>
> -int power_pca9450_init(unsigned char bus);
> +int power_pca9450_init(unsigned char bus, unsigned char addr);
>
> #endif
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 15/26] imx8mn_evk: drop duplicated code
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (13 preceding siblings ...)
2021-03-19 7:57 ` [PATCH 14/26] power: pca9450: add a new parameter for power_pca9450_init Peng Fan
@ 2021-03-19 7:57 ` Peng Fan
2021-03-19 7:57 ` [PATCH 16/26] imx8mn: Add LPDDR4 EVK board support Peng Fan
` (10 subsequent siblings)
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:57 UTC (permalink / raw)
To: u-boot
From: Peng Fan <peng.fan@nxp.com>
uart clk has been enabled, no need enable again.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
board/freescale/imx8mn_evk/spl.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c
index 6d5c7a5b46..80f79ce888 100644
--- a/board/freescale/imx8mn_evk/spl.c
+++ b/board/freescale/imx8mn_evk/spl.c
@@ -84,8 +84,6 @@ int board_early_init_f(void)
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
- init_uart_clk(1);
-
return 0;
}
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 16/26] imx8mn: Add LPDDR4 EVK board support
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (14 preceding siblings ...)
2021-03-19 7:57 ` [PATCH 15/26] imx8mn_evk: drop duplicated code Peng Fan
@ 2021-03-19 7:57 ` Peng Fan
2021-03-19 7:57 ` [PATCH 17/26] imx8mn: Add low drive mode support for DDR4/LPDDR4 EVK Peng Fan
` (9 subsequent siblings)
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:57 UTC (permalink / raw)
To: u-boot
From: Peng Fan <peng.fan@nxp.com>
Add support for iMX8MN LPDDR4 EVK board which uses 2GB LPDDR4 and
PCA9450B PMIC.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 3 +
arch/arm/dts/imx8mn-evk-u-boot.dtsi | 26 +
arch/arm/dts/imx8mn-evk.dts | 128 ++
arch/arm/mach-imx/imx8m/Kconfig | 6 +
board/freescale/imx8mn_evk/Kconfig | 2 +-
board/freescale/imx8mn_evk/Makefile | 1 +
board/freescale/imx8mn_evk/lpddr4_timing.c | 1587 ++++++++++++++++++++
board/freescale/imx8mn_evk/spl.c | 43 +
configs/imx8mn_evk_defconfig | 93 ++
10 files changed, 1889 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx8mn-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-evk.dts
create mode 100644 board/freescale/imx8mn_evk/lpddr4_timing.c
create mode 100644 configs/imx8mn_evk_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c6710826a0..8cd7c5d2dc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -797,6 +797,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-verdin.dtb \
phycore-imx8mm.dtb \
imx8mn-ddr4-evk.dtb \
+ imx8mn-evk.dtb \
imx8mq-evk.dtb \
imx8mm-beacon-kit.dtb \
imx8mn-beacon-kit.dtb \
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 025090fff4..8cd15be7a8 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -19,6 +19,9 @@
&clk {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
};
&osc_24m {
diff --git a/arch/arm/dts/imx8mn-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
new file mode 100644
index 0000000000..2730ff6a81
--- /dev/null
+++ b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include "imx8mn-ddr4-evk-u-boot.dtsi"
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&{/soc at 0/bus at 30800000/i2c at 30a20000/pca9450 at 25} {
+ u-boot,dm-spl;
+};
+
+&{/soc at 0/bus at 30800000/i2c at 30a20000/pca9450 at 25/regulators} {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mn-evk.dts b/arch/arm/dts/imx8mn-evk.dts
new file mode 100644
index 0000000000..cd11fb28f5
--- /dev/null
+++ b/arch/arm/dts/imx8mn-evk.dts
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mn.dtsi"
+#include "imx8mn-evk.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "NXP i.MX8MNano EVK board";
+ compatible = "fsl,imx8mn-evk", "fsl,imx8mn";
+};
+
+&A53_0 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2>;
+};
+
+&i2c1 {
+ pmic: pca9450 at 25 {
+ compatible = "nxp,pca9450b";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ buck1: BUCK1{
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ };
+
+ buck4: BUCK4{
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: BUCK5{
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6: BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2: LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3: LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5: LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 12b8d0d831..59a45f7b01 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -49,6 +49,12 @@ config TARGET_IMX8MM_VENICE
select SUPPORT_SPL
select IMX8M_LPDDR4
+config TARGET_IMX8MN_EVK
+ bool "imx8mn LPDDR4 EVK board"
+ select IMX8MN
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
+
config TARGET_IMX8MN_DDR4_EVK
bool "imx8mn DDR4 EVK board"
select IMX8MN
diff --git a/board/freescale/imx8mn_evk/Kconfig b/board/freescale/imx8mn_evk/Kconfig
index 048fb7d97f..ace6fc1e39 100644
--- a/board/freescale/imx8mn_evk/Kconfig
+++ b/board/freescale/imx8mn_evk/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_IMX8MN_DDR4_EVK
+if TARGET_IMX8MN_EVK || TARGET_IMX8MN_DDR4_EVK
config SYS_BOARD
default "imx8mn_evk"
diff --git a/board/freescale/imx8mn_evk/Makefile b/board/freescale/imx8mn_evk/Makefile
index 9511a70c31..5d7dbe6628 100644
--- a/board/freescale/imx8mn_evk/Makefile
+++ b/board/freescale/imx8mn_evk/Makefile
@@ -8,5 +8,6 @@ obj-y += imx8mn_evk.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
endif
diff --git a/board/freescale/imx8mn_evk/lpddr4_timing.c b/board/freescale/imx8mn_evk/lpddr4_timing.c
new file mode 100644
index 0000000000..671e924132
--- /dev/null
+++ b/board/freescale/imx8mn_evk/lpddr4_timing.c
@@ -0,0 +1,1587 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ {0x3d400020, 0x00000213},
+ {0x3d400024, 0x0003e800},
+ {0x3d400030, 0x00000120},
+ {0x3d400000, 0xa3080020},
+ {0x3d400064, 0x006100e0},
+ {0x3d4000d0, 0xc003061c},
+ {0x3d4000d4, 0x009e0000},
+ {0x3d4000dc, 0x00d4002d},
+ {0x3d4000e0, 0x00310000},
+ {0x3d4000e8, 0x0066004d},
+ {0x3d4000ec, 0x0016004a},
+ {0x3d400100, 0x1a201b22},
+ {0x3d400104, 0x00060633},
+ {0x3d40010c, 0x00c0c000},
+ {0x3d400110, 0x0f04080f},
+ {0x3d400114, 0x02040c0c},
+ {0x3d400118, 0x01010007},
+ {0x3d40011c, 0x00000401},
+ {0x3d400130, 0x00020600},
+ {0x3d400134, 0x0c100002},
+ {0x3d400138, 0x000000e6},
+ {0x3d400144, 0x00a00050},
+ {0x3d400180, 0x03200018},
+ {0x3d400184, 0x028061a8},
+ {0x3d400188, 0x00000000},
+ {0x3d400190, 0x0497820a},
+ {0x3d4001b4, 0x0000170a},
+ {0x3d400108, 0x070e1617},
+ {0x3d4001c0, 0x00000001},
+ {0x3d400194, 0x00080303},
+ {0x3d4001a0, 0xe0400018},
+ {0x3d4001a4, 0x00df00e4},
+ {0x3d4001a8, 0x80000000},
+ {0x3d4001b0, 0x00000011},
+ {0x3d4001c4, 0x00000001},
+ {0x3d4000f4, 0x00000c99},
+ {0x3d400200, 0x00000017},
+ {0x3d400204, 0x00080808},
+ {0x3d400208, 0x00000000},
+ {0x3d40020c, 0x00000000},
+ {0x3d400210, 0x00001f1f},
+ {0x3d400214, 0x07070707},
+ {0x3d400218, 0x07070707},
+ {0x3d40021c, 0x00000f0f},
+ {0x3d400250, 0x29001701},
+ {0x3d400254, 0x0000002c},
+ {0x3d40025c, 0x04000030},
+ {0x3d400264, 0x900093e7},
+ {0x3d40026c, 0x20005574},
+ {0x3d400400, 0x00000111},
+ {0x3d400408, 0x000072ff},
+ {0x3d400494, 0x02100e07},
+ {0x3d400498, 0x00620096},
+ {0x3d40049c, 0x01100e07},
+ {0x3d4004a0, 0x00c8012c},
+ {0x3d402020, 0x00000011},
+ {0x3d402024, 0x00007d00},
+ {0x3d402050, 0x0020d040},
+ {0x3d402064, 0x000c001d},
+ {0x3d4020f4, 0x00000c99},
+ {0x3d402100, 0x0a040305},
+ {0x3d402104, 0x00030407},
+ {0x3d402108, 0x0203060b},
+ {0x3d40210c, 0x00505000},
+ {0x3d402110, 0x02040202},
+ {0x3d402114, 0x02030202},
+ {0x3d402118, 0x01010004},
+ {0x3d40211c, 0x00000301},
+ {0x3d402130, 0x00020300},
+ {0x3d402134, 0x0a100002},
+ {0x3d402138, 0x0000001d},
+ {0x3d402144, 0x0014000a},
+ {0x3d402180, 0x00650004},
+ {0x3d402190, 0x03818200},
+ {0x3d402194, 0x00080303},
+ {0x3d4021b4, 0x00000100},
+ {0x3d4020dc, 0x00840000},
+ {0x3d4020e0, 0x00310000},
+ {0x3d4020e8, 0x0066004d},
+ {0x3d4020ec, 0x0016004a},
+ {0x3d403020, 0x00000011},
+ {0x3d403024, 0x00001f40},
+ {0x3d403050, 0x0020d040},
+ {0x3d403064, 0x00030007},
+ {0x3d4030f4, 0x00000c99},
+ {0x3d403100, 0x0a010102},
+ {0x3d403104, 0x00030404},
+ {0x3d403108, 0x0203060b},
+ {0x3d40310c, 0x00505000},
+ {0x3d403110, 0x02040202},
+ {0x3d403114, 0x02030202},
+ {0x3d403118, 0x01010004},
+ {0x3d40311c, 0x00000301},
+ {0x3d403130, 0x00020300},
+ {0x3d403134, 0x0a100002},
+ {0x3d403138, 0x00000008},
+ {0x3d403144, 0x00050003},
+ {0x3d403180, 0x00190004},
+ {0x3d403190, 0x03818200},
+ {0x3d403194, 0x00080303},
+ {0x3d4031b4, 0x00000100},
+ {0x3d4030dc, 0x00840000},
+ {0x3d4030e0, 0x00310000},
+ {0x3d4030e8, 0x0066004d},
+ {0x3d4030ec, 0x0016004a},
+
+ /* default boot point */
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x000d0000, 0x00000000},
+ {0x000100a0, 0x00000000},
+ {0x000100a1, 0x00000001},
+ {0x000100a2, 0x00000002},
+ {0x000100a3, 0x00000003},
+ {0x000100a4, 0x00000004},
+ {0x000100a5, 0x00000005},
+ {0x000100a6, 0x00000006},
+ {0x000100a7, 0x00000007},
+ {0x000110a0, 0x00000000},
+ {0x000110a1, 0x00000001},
+ {0x000110a2, 0x00000003},
+ {0x000110a3, 0x00000004},
+ {0x000110a4, 0x00000005},
+ {0x000110a5, 0x00000002},
+ {0x000110a6, 0x00000007},
+ {0x000110a7, 0x00000006},
+ {0x0001005f, 0x0000015f},
+ {0x0001015f, 0x0000015f},
+ {0x0001105f, 0x0000015f},
+ {0x0001115f, 0x0000015f},
+ {0x0011005f, 0x0000015f},
+ {0x0011015f, 0x0000015f},
+ {0x0011105f, 0x0000015f},
+ {0x0011115f, 0x0000015f},
+ {0x0021005f, 0x0000015f},
+ {0x0021015f, 0x0000015f},
+ {0x0021105f, 0x0000015f},
+ {0x0021115f, 0x0000015f},
+ {0x00000055, 0x0000016f},
+ {0x00001055, 0x0000016f},
+ {0x00002055, 0x0000016f},
+ {0x00003055, 0x0000016f},
+ {0x00004055, 0x0000016f},
+ {0x00005055, 0x0000016f},
+ {0x00006055, 0x0000016f},
+ {0x00007055, 0x0000016f},
+ {0x00008055, 0x0000016f},
+ {0x00009055, 0x0000016f},
+ {0x000200c5, 0x00000019},
+ {0x001200c5, 0x00000007},
+ {0x002200c5, 0x00000007},
+ {0x0002002e, 0x00000002},
+ {0x0012002e, 0x00000002},
+ {0x0022002e, 0x00000002},
+ {0x00090204, 0x00000000},
+ {0x00190204, 0x00000000},
+ {0x00290204, 0x00000000},
+ {0x00020024, 0x000001a3},
+ {0x0002003a, 0x00000002},
+ {0x0002007d, 0x00000212},
+ {0x0002007c, 0x00000061},
+ {0x00120024, 0x000001a3},
+ {0x0002003a, 0x00000002},
+ {0x0012007d, 0x00000212},
+ {0x0012007c, 0x00000061},
+ {0x00220024, 0x000001a3},
+ {0x0002003a, 0x00000002},
+ {0x0022007d, 0x00000212},
+ {0x0022007c, 0x00000061},
+ {0x00020056, 0x00000003},
+ {0x00120056, 0x00000003},
+ {0x00220056, 0x00000003},
+ {0x0001004d, 0x00000f80},
+ {0x0001014d, 0x00000f80},
+ {0x0001104d, 0x00000f80},
+ {0x0001114d, 0x00000f80},
+ {0x0011004d, 0x00000f80},
+ {0x0011014d, 0x00000f80},
+ {0x0011104d, 0x00000f80},
+ {0x0011114d, 0x00000f80},
+ {0x0021004d, 0x00000f80},
+ {0x0021014d, 0x00000f80},
+ {0x0021104d, 0x00000f80},
+ {0x0021114d, 0x00000f80},
+ {0x00010049, 0x00000fbe},
+ {0x00010149, 0x00000fbe},
+ {0x00011049, 0x00000fbe},
+ {0x00011149, 0x00000fbe},
+ {0x00110049, 0x00000fbe},
+ {0x00110149, 0x00000fbe},
+ {0x00111049, 0x00000fbe},
+ {0x00111149, 0x00000fbe},
+ {0x00210049, 0x00000fbe},
+ {0x00210149, 0x00000fbe},
+ {0x00211049, 0x00000fbe},
+ {0x00211149, 0x00000fbe},
+ {0x00000043, 0x00000063},
+ {0x00001043, 0x00000063},
+ {0x00002043, 0x00000063},
+ {0x00003043, 0x00000063},
+ {0x00004043, 0x00000063},
+ {0x00005043, 0x00000063},
+ {0x00006043, 0x00000063},
+ {0x00007043, 0x00000063},
+ {0x00008043, 0x00000063},
+ {0x00009043, 0x00000063},
+ {0x00020018, 0x00000001},
+ {0x00020075, 0x00000004},
+ {0x00020050, 0x00000000},
+ {0x00020008, 0x00000320},
+ {0x00120008, 0x00000064},
+ {0x00220008, 0x00000019},
+ {0x00020088, 0x00000009},
+ {0x000200b2, 0x000000dc},
+ {0x00010043, 0x000005a1},
+ {0x00010143, 0x000005a1},
+ {0x00011043, 0x000005a1},
+ {0x00011143, 0x000005a1},
+ {0x001200b2, 0x000000dc},
+ {0x00110043, 0x000005a1},
+ {0x00110143, 0x000005a1},
+ {0x00111043, 0x000005a1},
+ {0x00111143, 0x000005a1},
+ {0x002200b2, 0x000000dc},
+ {0x00210043, 0x000005a1},
+ {0x00210143, 0x000005a1},
+ {0x00211043, 0x000005a1},
+ {0x00211143, 0x000005a1},
+ {0x000200fa, 0x00000001},
+ {0x001200fa, 0x00000001},
+ {0x002200fa, 0x00000001},
+ {0x00020019, 0x00000001},
+ {0x00120019, 0x00000001},
+ {0x00220019, 0x00000001},
+ {0x000200f0, 0x00000660},
+ {0x000200f1, 0x00000000},
+ {0x000200f2, 0x00004444},
+ {0x000200f3, 0x00008888},
+ {0x000200f4, 0x00005665},
+ {0x000200f5, 0x00000000},
+ {0x000200f6, 0x00000000},
+ {0x000200f7, 0x0000f000},
+ {0x0001004a, 0x00000500},
+ {0x0001104a, 0x00000500},
+ {0x00020025, 0x00000000},
+ {0x0002002d, 0x00000000},
+ {0x0012002d, 0x00000000},
+ {0x0022002d, 0x00000000},
+ {0x0002002c, 0x00000000},
+ {0x000200c7, 0x00000021},
+ {0x000200ca, 0x00000024},
+ {0x000200cc, 0x000001f7},
+ {0x001200c7, 0x00000021},
+ {0x001200ca, 0x00000024},
+ {0x001200cc, 0x000001f7},
+ {0x002200c7, 0x00000021},
+ {0x002200ca, 0x00000024},
+ {0x002200cc, 0x000001f7},
+ {0x00020060, 0x00000002},
+ {0x000d0000, 0x00000001},
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x0200b2, 0x0},
+ {0x1200b2, 0x0},
+ {0x2200b2, 0x0},
+ {0x0200cb, 0x0},
+ {0x010043, 0x0},
+ {0x110043, 0x0},
+ {0x210043, 0x0},
+ {0x010143, 0x0},
+ {0x110143, 0x0},
+ {0x210143, 0x0},
+ {0x011043, 0x0},
+ {0x111043, 0x0},
+ {0x211043, 0x0},
+ {0x011143, 0x0},
+ {0x111143, 0x0},
+ {0x211143, 0x0},
+ {0x000080, 0x0},
+ {0x100080, 0x0},
+ {0x200080, 0x0},
+ {0x001080, 0x0},
+ {0x101080, 0x0},
+ {0x201080, 0x0},
+ {0x002080, 0x0},
+ {0x102080, 0x0},
+ {0x202080, 0x0},
+ {0x003080, 0x0},
+ {0x103080, 0x0},
+ {0x203080, 0x0},
+ {0x004080, 0x0},
+ {0x104080, 0x0},
+ {0x204080, 0x0},
+ {0x005080, 0x0},
+ {0x105080, 0x0},
+ {0x205080, 0x0},
+ {0x006080, 0x0},
+ {0x106080, 0x0},
+ {0x206080, 0x0},
+ {0x007080, 0x0},
+ {0x107080, 0x0},
+ {0x207080, 0x0},
+ {0x008080, 0x0},
+ {0x108080, 0x0},
+ {0x208080, 0x0},
+ {0x009080, 0x0},
+ {0x109080, 0x0},
+ {0x209080, 0x0},
+ {0x010080, 0x0},
+ {0x110080, 0x0},
+ {0x210080, 0x0},
+ {0x010180, 0x0},
+ {0x110180, 0x0},
+ {0x210180, 0x0},
+ {0x011080, 0x0},
+ {0x111080, 0x0},
+ {0x211080, 0x0},
+ {0x011180, 0x0},
+ {0x111180, 0x0},
+ {0x211180, 0x0},
+ {0x010081, 0x0},
+ {0x110081, 0x0},
+ {0x210081, 0x0},
+ {0x010181, 0x0},
+ {0x110181, 0x0},
+ {0x210181, 0x0},
+ {0x011081, 0x0},
+ {0x111081, 0x0},
+ {0x211081, 0x0},
+ {0x011181, 0x0},
+ {0x111181, 0x0},
+ {0x211181, 0x0},
+ {0x0100d0, 0x0},
+ {0x1100d0, 0x0},
+ {0x2100d0, 0x0},
+ {0x0101d0, 0x0},
+ {0x1101d0, 0x0},
+ {0x2101d0, 0x0},
+ {0x0110d0, 0x0},
+ {0x1110d0, 0x0},
+ {0x2110d0, 0x0},
+ {0x0111d0, 0x0},
+ {0x1111d0, 0x0},
+ {0x2111d0, 0x0},
+ {0x0100d1, 0x0},
+ {0x1100d1, 0x0},
+ {0x2100d1, 0x0},
+ {0x0101d1, 0x0},
+ {0x1101d1, 0x0},
+ {0x2101d1, 0x0},
+ {0x0110d1, 0x0},
+ {0x1110d1, 0x0},
+ {0x2110d1, 0x0},
+ {0x0111d1, 0x0},
+ {0x1111d1, 0x0},
+ {0x2111d1, 0x0},
+ {0x010068, 0x0},
+ {0x010168, 0x0},
+ {0x010268, 0x0},
+ {0x010368, 0x0},
+ {0x010468, 0x0},
+ {0x010568, 0x0},
+ {0x010668, 0x0},
+ {0x010768, 0x0},
+ {0x010868, 0x0},
+ {0x011068, 0x0},
+ {0x011168, 0x0},
+ {0x011268, 0x0},
+ {0x011368, 0x0},
+ {0x011468, 0x0},
+ {0x011568, 0x0},
+ {0x011668, 0x0},
+ {0x011768, 0x0},
+ {0x011868, 0x0},
+ {0x010069, 0x0},
+ {0x010169, 0x0},
+ {0x010269, 0x0},
+ {0x010369, 0x0},
+ {0x010469, 0x0},
+ {0x010569, 0x0},
+ {0x010669, 0x0},
+ {0x010769, 0x0},
+ {0x010869, 0x0},
+ {0x011069, 0x0},
+ {0x011169, 0x0},
+ {0x011269, 0x0},
+ {0x011369, 0x0},
+ {0x011469, 0x0},
+ {0x011569, 0x0},
+ {0x011669, 0x0},
+ {0x011769, 0x0},
+ {0x011869, 0x0},
+ {0x01008c, 0x0},
+ {0x11008c, 0x0},
+ {0x21008c, 0x0},
+ {0x01018c, 0x0},
+ {0x11018c, 0x0},
+ {0x21018c, 0x0},
+ {0x01108c, 0x0},
+ {0x11108c, 0x0},
+ {0x21108c, 0x0},
+ {0x01118c, 0x0},
+ {0x11118c, 0x0},
+ {0x21118c, 0x0},
+ {0x01008d, 0x0},
+ {0x11008d, 0x0},
+ {0x21008d, 0x0},
+ {0x01018d, 0x0},
+ {0x11018d, 0x0},
+ {0x21018d, 0x0},
+ {0x01108d, 0x0},
+ {0x11108d, 0x0},
+ {0x21108d, 0x0},
+ {0x01118d, 0x0},
+ {0x11118d, 0x0},
+ {0x21118d, 0x0},
+ {0x0100c0, 0x0},
+ {0x1100c0, 0x0},
+ {0x2100c0, 0x0},
+ {0x0101c0, 0x0},
+ {0x1101c0, 0x0},
+ {0x2101c0, 0x0},
+ {0x0102c0, 0x0},
+ {0x1102c0, 0x0},
+ {0x2102c0, 0x0},
+ {0x0103c0, 0x0},
+ {0x1103c0, 0x0},
+ {0x2103c0, 0x0},
+ {0x0104c0, 0x0},
+ {0x1104c0, 0x0},
+ {0x2104c0, 0x0},
+ {0x0105c0, 0x0},
+ {0x1105c0, 0x0},
+ {0x2105c0, 0x0},
+ {0x0106c0, 0x0},
+ {0x1106c0, 0x0},
+ {0x2106c0, 0x0},
+ {0x0107c0, 0x0},
+ {0x1107c0, 0x0},
+ {0x2107c0, 0x0},
+ {0x0108c0, 0x0},
+ {0x1108c0, 0x0},
+ {0x2108c0, 0x0},
+ {0x0110c0, 0x0},
+ {0x1110c0, 0x0},
+ {0x2110c0, 0x0},
+ {0x0111c0, 0x0},
+ {0x1111c0, 0x0},
+ {0x2111c0, 0x0},
+ {0x0112c0, 0x0},
+ {0x1112c0, 0x0},
+ {0x2112c0, 0x0},
+ {0x0113c0, 0x0},
+ {0x1113c0, 0x0},
+ {0x2113c0, 0x0},
+ {0x0114c0, 0x0},
+ {0x1114c0, 0x0},
+ {0x2114c0, 0x0},
+ {0x0115c0, 0x0},
+ {0x1115c0, 0x0},
+ {0x2115c0, 0x0},
+ {0x0116c0, 0x0},
+ {0x1116c0, 0x0},
+ {0x2116c0, 0x0},
+ {0x0117c0, 0x0},
+ {0x1117c0, 0x0},
+ {0x2117c0, 0x0},
+ {0x0118c0, 0x0},
+ {0x1118c0, 0x0},
+ {0x2118c0, 0x0},
+ {0x0100c1, 0x0},
+ {0x1100c1, 0x0},
+ {0x2100c1, 0x0},
+ {0x0101c1, 0x0},
+ {0x1101c1, 0x0},
+ {0x2101c1, 0x0},
+ {0x0102c1, 0x0},
+ {0x1102c1, 0x0},
+ {0x2102c1, 0x0},
+ {0x0103c1, 0x0},
+ {0x1103c1, 0x0},
+ {0x2103c1, 0x0},
+ {0x0104c1, 0x0},
+ {0x1104c1, 0x0},
+ {0x2104c1, 0x0},
+ {0x0105c1, 0x0},
+ {0x1105c1, 0x0},
+ {0x2105c1, 0x0},
+ {0x0106c1, 0x0},
+ {0x1106c1, 0x0},
+ {0x2106c1, 0x0},
+ {0x0107c1, 0x0},
+ {0x1107c1, 0x0},
+ {0x2107c1, 0x0},
+ {0x0108c1, 0x0},
+ {0x1108c1, 0x0},
+ {0x2108c1, 0x0},
+ {0x0110c1, 0x0},
+ {0x1110c1, 0x0},
+ {0x2110c1, 0x0},
+ {0x0111c1, 0x0},
+ {0x1111c1, 0x0},
+ {0x2111c1, 0x0},
+ {0x0112c1, 0x0},
+ {0x1112c1, 0x0},
+ {0x2112c1, 0x0},
+ {0x0113c1, 0x0},
+ {0x1113c1, 0x0},
+ {0x2113c1, 0x0},
+ {0x0114c1, 0x0},
+ {0x1114c1, 0x0},
+ {0x2114c1, 0x0},
+ {0x0115c1, 0x0},
+ {0x1115c1, 0x0},
+ {0x2115c1, 0x0},
+ {0x0116c1, 0x0},
+ {0x1116c1, 0x0},
+ {0x2116c1, 0x0},
+ {0x0117c1, 0x0},
+ {0x1117c1, 0x0},
+ {0x2117c1, 0x0},
+ {0x0118c1, 0x0},
+ {0x1118c1, 0x0},
+ {0x2118c1, 0x0},
+ {0x010020, 0x0},
+ {0x110020, 0x0},
+ {0x210020, 0x0},
+ {0x011020, 0x0},
+ {0x111020, 0x0},
+ {0x211020, 0x0},
+ {0x020072, 0x0},
+ {0x020073, 0x0},
+ {0x020074, 0x0},
+ {0x0100aa, 0x0},
+ {0x0110aa, 0x0},
+ {0x020010, 0x0},
+ {0x120010, 0x0},
+ {0x220010, 0x0},
+ {0x020011, 0x0},
+ {0x120011, 0x0},
+ {0x220011, 0x0},
+ {0x0100ae, 0x0},
+ {0x1100ae, 0x0},
+ {0x2100ae, 0x0},
+ {0x0100af, 0x0},
+ {0x1100af, 0x0},
+ {0x2100af, 0x0},
+ {0x0110ae, 0x0},
+ {0x1110ae, 0x0},
+ {0x2110ae, 0x0},
+ {0x0110af, 0x0},
+ {0x1110af, 0x0},
+ {0x2110af, 0x0},
+ {0x020020, 0x0},
+ {0x120020, 0x0},
+ {0x220020, 0x0},
+ {0x0100a0, 0x0},
+ {0x0100a1, 0x0},
+ {0x0100a2, 0x0},
+ {0x0100a3, 0x0},
+ {0x0100a4, 0x0},
+ {0x0100a5, 0x0},
+ {0x0100a6, 0x0},
+ {0x0100a7, 0x0},
+ {0x0110a0, 0x0},
+ {0x0110a1, 0x0},
+ {0x0110a2, 0x0},
+ {0x0110a3, 0x0},
+ {0x0110a4, 0x0},
+ {0x0110a5, 0x0},
+ {0x0110a6, 0x0},
+ {0x0110a7, 0x0},
+ {0x02007c, 0x0},
+ {0x12007c, 0x0},
+ {0x22007c, 0x0},
+ {0x02007d, 0x0},
+ {0x12007d, 0x0},
+ {0x22007d, 0x0},
+ {0x0400fd, 0x0},
+ {0x0400c0, 0x0},
+ {0x090201, 0x0},
+ {0x190201, 0x0},
+ {0x290201, 0x0},
+ {0x090202, 0x0},
+ {0x190202, 0x0},
+ {0x290202, 0x0},
+ {0x090203, 0x0},
+ {0x190203, 0x0},
+ {0x290203, 0x0},
+ {0x090204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x090205, 0x0},
+ {0x190205, 0x0},
+ {0x290205, 0x0},
+ {0x090206, 0x0},
+ {0x190206, 0x0},
+ {0x290206, 0x0},
+ {0x090207, 0x0},
+ {0x190207, 0x0},
+ {0x290207, 0x0},
+ {0x090208, 0x0},
+ {0x190208, 0x0},
+ {0x290208, 0x0},
+ {0x010062, 0x0},
+ {0x010162, 0x0},
+ {0x010262, 0x0},
+ {0x010362, 0x0},
+ {0x010462, 0x0},
+ {0x010562, 0x0},
+ {0x010662, 0x0},
+ {0x010762, 0x0},
+ {0x010862, 0x0},
+ {0x011062, 0x0},
+ {0x011162, 0x0},
+ {0x011262, 0x0},
+ {0x011362, 0x0},
+ {0x011462, 0x0},
+ {0x011562, 0x0},
+ {0x011662, 0x0},
+ {0x011762, 0x0},
+ {0x011862, 0x0},
+ {0x020077, 0x0},
+ {0x010001, 0x0},
+ {0x011001, 0x0},
+ {0x010040, 0x0},
+ {0x010140, 0x0},
+ {0x010240, 0x0},
+ {0x010340, 0x0},
+ {0x010440, 0x0},
+ {0x010540, 0x0},
+ {0x010640, 0x0},
+ {0x010740, 0x0},
+ {0x010840, 0x0},
+ {0x010030, 0x0},
+ {0x010130, 0x0},
+ {0x010230, 0x0},
+ {0x010330, 0x0},
+ {0x010430, 0x0},
+ {0x010530, 0x0},
+ {0x010630, 0x0},
+ {0x010730, 0x0},
+ {0x010830, 0x0},
+ {0x011040, 0x0},
+ {0x011140, 0x0},
+ {0x011240, 0x0},
+ {0x011340, 0x0},
+ {0x011440, 0x0},
+ {0x011540, 0x0},
+ {0x011640, 0x0},
+ {0x011740, 0x0},
+ {0x011840, 0x0},
+ {0x011030, 0x0},
+ {0x011130, 0x0},
+ {0x011230, 0x0},
+ {0x011330, 0x0},
+ {0x011430, 0x0},
+ {0x011530, 0x0},
+ {0x011630, 0x0},
+ {0x011730, 0x0},
+ {0x011830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0x000d0000, 0x00000000},
+ {0x00054000, 0x00000000},
+ {0x00054001, 0x00000000},
+ {0x00054002, 0x00000000},
+ {0x00054003, 0x00000c80},
+ {0x00054004, 0x00000002},
+ {0x00054005, 0x00000000},
+ {0x00054006, 0x00000011},
+ {0x00054007, 0x00000000},
+ {0x00054008, 0x0000131f},
+ {0x00054009, 0x000000c8},
+ {0x0005400a, 0x00000000},
+ {0x0005400b, 0x00000002},
+ {0x0005400c, 0x00000000},
+ {0x0005400d, 0x00000000},
+ {0x0005400e, 0x00000000},
+ {0x0005400f, 0x00000100},
+ {0x00054010, 0x00000000},
+ {0x00054011, 0x00000000},
+ {0x00054012, 0x00000310},
+ {0x00054013, 0x00000000},
+ {0x00054014, 0x00000000},
+ {0x00054015, 0x00000000},
+ {0x00054016, 0x00000000},
+ {0x00054017, 0x00000000},
+ {0x00054018, 0x00000000},
+ {0x00054019, 0x00002dd4},
+ {0x0005401a, 0x00000031},
+ {0x0005401b, 0x00004d66},
+ {0x0005401c, 0x00004a00},
+ {0x0005401d, 0x00000000},
+ {0x0005401e, 0x00000016},
+ {0x0005401f, 0x00002dd4},
+ {0x00054020, 0x00000031},
+ {0x00054021, 0x00004d66},
+ {0x00054022, 0x00004a00},
+ {0x00054023, 0x00000000},
+ {0x00054024, 0x0000002e},
+ {0x00054025, 0x00000000},
+ {0x00054026, 0x00000000},
+ {0x00054027, 0x00000000},
+ {0x00054028, 0x00000000},
+ {0x00054029, 0x00000000},
+ {0x0005402a, 0x00000000},
+ {0x0005402b, 0x00000000},
+ {0x0005402c, 0x00000000},
+ {0x0005402d, 0x00000000},
+ {0x0005402e, 0x00000000},
+ {0x0005402f, 0x00000000},
+ {0x00054030, 0x00000000},
+ {0x00054031, 0x00000000},
+ {0x00054032, 0x0000d400},
+ {0x00054033, 0x0000312d},
+ {0x00054034, 0x00006600},
+ {0x00054035, 0x0000004d},
+ {0x00054036, 0x0000004a},
+ {0x00054037, 0x00001600},
+ {0x00054038, 0x0000d400},
+ {0x00054039, 0x0000312d},
+ {0x0005403a, 0x00006600},
+ {0x0005403b, 0x0000004d},
+ {0x0005403c, 0x0000004a},
+ {0x0005403d, 0x00002e00},
+ {0x0005403e, 0x00000000},
+ {0x0005403f, 0x00000000},
+ {0x00054040, 0x00000000},
+ {0x00054041, 0x00000000},
+ {0x00054042, 0x00000000},
+ {0x00054043, 0x00000000},
+ {0x00054044, 0x00000000},
+ {0x000d0000, 0x00000001},
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0x000d0000, 0x00000000},
+ {0x00054000, 0x00000000},
+ {0x00054001, 0x00000000},
+ {0x00054002, 0x00000101},
+ {0x00054003, 0x00000190},
+ {0x00054004, 0x00000002},
+ {0x00054005, 0x00000000},
+ {0x00054006, 0x00000011},
+ {0x00054007, 0x00000000},
+ {0x00054008, 0x0000121f},
+ {0x00054009, 0x000000c8},
+ {0x0005400a, 0x00000000},
+ {0x0005400b, 0x00000002},
+ {0x0005400c, 0x00000000},
+ {0x0005400d, 0x00000000},
+ {0x0005400e, 0x00000000},
+ {0x0005400f, 0x00000100},
+ {0x00054010, 0x00000000},
+ {0x00054011, 0x00000000},
+ {0x00054012, 0x00000310},
+ {0x00054013, 0x00000000},
+ {0x00054014, 0x00000000},
+ {0x00054015, 0x00000000},
+ {0x00054016, 0x00000000},
+ {0x00054017, 0x00000000},
+ {0x00054018, 0x00000000},
+ {0x00054019, 0x00000084},
+ {0x0005401a, 0x00000031},
+ {0x0005401b, 0x00004d66},
+ {0x0005401c, 0x00004a00},
+ {0x0005401d, 0x00000000},
+ {0x0005401e, 0x00000016},
+ {0x0005401f, 0x00000084},
+ {0x00054020, 0x00000031},
+ {0x00054021, 0x00004d66},
+ {0x00054022, 0x00004a00},
+ {0x00054023, 0x00000000},
+ {0x00054024, 0x0000002e},
+ {0x00054025, 0x00000000},
+ {0x00054026, 0x00000000},
+ {0x00054027, 0x00000000},
+ {0x00054028, 0x00000000},
+ {0x00054029, 0x00000000},
+ {0x0005402a, 0x00000000},
+ {0x0005402b, 0x00000000},
+ {0x0005402c, 0x00000000},
+ {0x0005402d, 0x00000000},
+ {0x0005402e, 0x00000000},
+ {0x0005402f, 0x00000000},
+ {0x00054030, 0x00000000},
+ {0x00054031, 0x00000000},
+ {0x00054032, 0x00008400},
+ {0x00054033, 0x00003100},
+ {0x00054034, 0x00006600},
+ {0x00054035, 0x0000004d},
+ {0x00054036, 0x0000004a},
+ {0x00054037, 0x00001600},
+ {0x00054038, 0x00008400},
+ {0x00054039, 0x00003100},
+ {0x0005403a, 0x00006600},
+ {0x0005403b, 0x0000004d},
+ {0x0005403c, 0x0000004a},
+ {0x0005403d, 0x00002e00},
+ {0x0005403e, 0x00000000},
+ {0x0005403f, 0x00000000},
+ {0x00054040, 0x00000000},
+ {0x00054041, 0x00000000},
+ {0x00054042, 0x00000000},
+ {0x00054043, 0x00000000},
+ {0x00054044, 0x00000000},
+ {0x000d0000, 0x00000001},
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0x000d0000, 0x00000000},
+ {0x00054000, 0x00000000},
+ {0x00054001, 0x00000000},
+ {0x00054002, 0x00000102},
+ {0x00054003, 0x00000064},
+ {0x00054004, 0x00000002},
+ {0x00054005, 0x00000000},
+ {0x00054006, 0x00000011},
+ {0x00054007, 0x00000000},
+ {0x00054008, 0x0000121f},
+ {0x00054009, 0x000000c8},
+ {0x0005400a, 0x00000000},
+ {0x0005400b, 0x00000002},
+ {0x0005400c, 0x00000000},
+ {0x0005400d, 0x00000000},
+ {0x0005400e, 0x00000000},
+ {0x0005400f, 0x00000100},
+ {0x00054010, 0x00000000},
+ {0x00054011, 0x00000000},
+ {0x00054012, 0x00000310},
+ {0x00054013, 0x00000000},
+ {0x00054014, 0x00000000},
+ {0x00054015, 0x00000000},
+ {0x00054016, 0x00000000},
+ {0x00054017, 0x00000000},
+ {0x00054018, 0x00000000},
+ {0x00054019, 0x00000084},
+ {0x0005401a, 0x00000031},
+ {0x0005401b, 0x00004d66},
+ {0x0005401c, 0x00004a00},
+ {0x0005401d, 0x00000000},
+ {0x0005401e, 0x00000016},
+ {0x0005401f, 0x00000084},
+ {0x00054020, 0x00000031},
+ {0x00054021, 0x00004d66},
+ {0x00054022, 0x00004a00},
+ {0x00054023, 0x00000000},
+ {0x00054024, 0x0000002e},
+ {0x00054025, 0x00000000},
+ {0x00054026, 0x00000000},
+ {0x00054027, 0x00000000},
+ {0x00054028, 0x00000000},
+ {0x00054029, 0x00000000},
+ {0x0005402a, 0x00000000},
+ {0x0005402b, 0x00000000},
+ {0x0005402c, 0x00000000},
+ {0x0005402d, 0x00000000},
+ {0x0005402e, 0x00000000},
+ {0x0005402f, 0x00000000},
+ {0x00054030, 0x00000000},
+ {0x00054031, 0x00000000},
+ {0x00054032, 0x00008400},
+ {0x00054033, 0x00003100},
+ {0x00054034, 0x00006600},
+ {0x00054035, 0x0000004d},
+ {0x00054036, 0x0000004a},
+ {0x00054037, 0x00001600},
+ {0x00054038, 0x00008400},
+ {0x00054039, 0x00003100},
+ {0x0005403a, 0x00006600},
+ {0x0005403b, 0x0000004d},
+ {0x0005403c, 0x0000004a},
+ {0x0005403d, 0x00002e00},
+ {0x0005403e, 0x00000000},
+ {0x0005403f, 0x00000000},
+ {0x00054040, 0x00000000},
+ {0x00054041, 0x00000000},
+ {0x00054042, 0x00000000},
+ {0x00054043, 0x00000000},
+ {0x00054044, 0x00000000},
+ {0x000d0000, 0x00000001},
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0x000d0000, 0x00000000},
+ {0x00054000, 0x00000000},
+ {0x00054001, 0x00000000},
+ {0x00054002, 0x00000000},
+ {0x00054003, 0x00000c80},
+ {0x00054004, 0x00000002},
+ {0x00054005, 0x00000000},
+ {0x00054006, 0x00000011},
+ {0x00054007, 0x00000000},
+ {0x00054008, 0x00000061},
+ {0x00054009, 0x000000c8},
+ {0x0005400a, 0x00000000},
+ {0x0005400b, 0x00000002},
+ {0x0005400c, 0x00000000},
+ {0x0005400d, 0x00000000},
+ {0x0005400e, 0x00000000},
+ {0x0005400f, 0x00000100},
+ {0x00054010, 0x00001f7f},
+ {0x00054011, 0x00000000},
+ {0x00054012, 0x00000310},
+ {0x00054013, 0x00000000},
+ {0x00054014, 0x00000000},
+ {0x00054015, 0x00000000},
+ {0x00054016, 0x00000000},
+ {0x00054017, 0x00000000},
+ {0x00054018, 0x00000000},
+ {0x00054019, 0x00002dd4},
+ {0x0005401a, 0x00000031},
+ {0x0005401b, 0x00004d66},
+ {0x0005401c, 0x00004a00},
+ {0x0005401d, 0x00000000},
+ {0x0005401e, 0x00000016},
+ {0x0005401f, 0x00002dd4},
+ {0x00054020, 0x00000031},
+ {0x00054021, 0x00004d66},
+ {0x00054022, 0x00004a00},
+ {0x00054023, 0x00000000},
+ {0x00054024, 0x0000002e},
+ {0x00054025, 0x00000000},
+ {0x00054026, 0x00000000},
+ {0x00054027, 0x00000000},
+ {0x00054028, 0x00000000},
+ {0x00054029, 0x00000000},
+ {0x0005402a, 0x00000000},
+ {0x0005402b, 0x00000000},
+ {0x0005402c, 0x00000000},
+ {0x0005402d, 0x00000000},
+ {0x0005402e, 0x00000000},
+ {0x0005402f, 0x00000000},
+ {0x00054030, 0x00000000},
+ {0x00054031, 0x00000000},
+ {0x00054032, 0x0000d400},
+ {0x00054033, 0x0000312d},
+ {0x00054034, 0x00006600},
+ {0x00054035, 0x0000004d},
+ {0x00054036, 0x0000004a},
+ {0x00054037, 0x00001600},
+ {0x00054038, 0x0000d400},
+ {0x00054039, 0x0000312d},
+ {0x0005403a, 0x00006600},
+ {0x0005403b, 0x0000004d},
+ {0x0005403c, 0x0000004a},
+ {0x0005403d, 0x00002e00},
+ {0x0005403e, 0x00000000},
+ {0x0005403f, 0x00000000},
+ {0x00054040, 0x00000000},
+ {0x00054041, 0x00000000},
+ {0x00054042, 0x00000000},
+ {0x00054043, 0x00000000},
+ {0x00054044, 0x00000000},
+ {0x000d0000, 0x00000001},
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x0},
+ {0x90033, 0xe8},
+ {0x90034, 0x109},
+ {0x90035, 0x2},
+ {0x90036, 0x10},
+ {0x90037, 0x139},
+ {0x90038, 0xb},
+ {0x90039, 0x7c0},
+ {0x9003a, 0x139},
+ {0x9003b, 0x44},
+ {0x9003c, 0x633},
+ {0x9003d, 0x159},
+ {0x9003e, 0x14f},
+ {0x9003f, 0x630},
+ {0x90040, 0x159},
+ {0x90041, 0x47},
+ {0x90042, 0x633},
+ {0x90043, 0x149},
+ {0x90044, 0x4f},
+ {0x90045, 0x633},
+ {0x90046, 0x179},
+ {0x90047, 0x8},
+ {0x90048, 0xe0},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x7c8},
+ {0x9004c, 0x109},
+ {0x9004d, 0x0},
+ {0x9004e, 0x1},
+ {0x9004f, 0x8},
+ {0x90050, 0x0},
+ {0x90051, 0x45a},
+ {0x90052, 0x9},
+ {0x90053, 0x0},
+ {0x90054, 0x448},
+ {0x90055, 0x109},
+ {0x90056, 0x40},
+ {0x90057, 0x633},
+ {0x90058, 0x179},
+ {0x90059, 0x1},
+ {0x9005a, 0x618},
+ {0x9005b, 0x109},
+ {0x9005c, 0x40c0},
+ {0x9005d, 0x633},
+ {0x9005e, 0x149},
+ {0x9005f, 0x8},
+ {0x90060, 0x4},
+ {0x90061, 0x48},
+ {0x90062, 0x4040},
+ {0x90063, 0x633},
+ {0x90064, 0x149},
+ {0x90065, 0x0},
+ {0x90066, 0x4},
+ {0x90067, 0x48},
+ {0x90068, 0x40},
+ {0x90069, 0x633},
+ {0x9006a, 0x149},
+ {0x9006b, 0x10},
+ {0x9006c, 0x4},
+ {0x9006d, 0x18},
+ {0x9006e, 0x0},
+ {0x9006f, 0x4},
+ {0x90070, 0x78},
+ {0x90071, 0x549},
+ {0x90072, 0x633},
+ {0x90073, 0x159},
+ {0x90074, 0xd49},
+ {0x90075, 0x633},
+ {0x90076, 0x159},
+ {0x90077, 0x94a},
+ {0x90078, 0x633},
+ {0x90079, 0x159},
+ {0x9007a, 0x441},
+ {0x9007b, 0x633},
+ {0x9007c, 0x149},
+ {0x9007d, 0x42},
+ {0x9007e, 0x633},
+ {0x9007f, 0x149},
+ {0x90080, 0x1},
+ {0x90081, 0x633},
+ {0x90082, 0x149},
+ {0x90083, 0x0},
+ {0x90084, 0xe0},
+ {0x90085, 0x109},
+ {0x90086, 0xa},
+ {0x90087, 0x10},
+ {0x90088, 0x109},
+ {0x90089, 0x9},
+ {0x9008a, 0x3c0},
+ {0x9008b, 0x149},
+ {0x9008c, 0x9},
+ {0x9008d, 0x3c0},
+ {0x9008e, 0x159},
+ {0x9008f, 0x18},
+ {0x90090, 0x10},
+ {0x90091, 0x109},
+ {0x90092, 0x0},
+ {0x90093, 0x3c0},
+ {0x90094, 0x109},
+ {0x90095, 0x18},
+ {0x90096, 0x4},
+ {0x90097, 0x48},
+ {0x90098, 0x18},
+ {0x90099, 0x4},
+ {0x9009a, 0x58},
+ {0x9009b, 0xb},
+ {0x9009c, 0x10},
+ {0x9009d, 0x109},
+ {0x9009e, 0x1},
+ {0x9009f, 0x10},
+ {0x900a0, 0x109},
+ {0x900a1, 0x5},
+ {0x900a2, 0x7c0},
+ {0x900a3, 0x109},
+ {0x40000, 0x811},
+ {0x40020, 0x880},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x4008},
+ {0x40021, 0x83},
+ {0x40041, 0x4f},
+ {0x40061, 0x0},
+ {0x40002, 0x4040},
+ {0x40022, 0x83},
+ {0x40042, 0x51},
+ {0x40062, 0x0},
+ {0x40003, 0x811},
+ {0x40023, 0x880},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x720},
+ {0x40024, 0xf},
+ {0x40044, 0x1740},
+ {0x40064, 0x0},
+ {0x40005, 0x16},
+ {0x40025, 0x83},
+ {0x40045, 0x4b},
+ {0x40065, 0x0},
+ {0x40006, 0x716},
+ {0x40026, 0xf},
+ {0x40046, 0x2001},
+ {0x40066, 0x0},
+ {0x40007, 0x716},
+ {0x40027, 0xf},
+ {0x40047, 0x2800},
+ {0x40067, 0x0},
+ {0x40008, 0x716},
+ {0x40028, 0xf},
+ {0x40048, 0xf00},
+ {0x40068, 0x0},
+ {0x40009, 0x720},
+ {0x40029, 0xf},
+ {0x40049, 0x1400},
+ {0x40069, 0x0},
+ {0x4000a, 0xe08},
+ {0x4002a, 0xc15},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x625},
+ {0x4002b, 0x15},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x4028},
+ {0x4002c, 0x80},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0xe08},
+ {0x4002d, 0xc1a},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x625},
+ {0x4002e, 0x1a},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x4040},
+ {0x4002f, 0x80},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x2604},
+ {0x40030, 0x15},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x708},
+ {0x40031, 0x5},
+ {0x40051, 0x0},
+ {0x40071, 0x2002},
+ {0x40012, 0x8},
+ {0x40032, 0x80},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x2604},
+ {0x40033, 0x1a},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x708},
+ {0x40034, 0xa},
+ {0x40054, 0x0},
+ {0x40074, 0x2002},
+ {0x40015, 0x4040},
+ {0x40035, 0x80},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x60a},
+ {0x40036, 0x15},
+ {0x40056, 0x1200},
+ {0x40076, 0x0},
+ {0x40017, 0x61a},
+ {0x40037, 0x15},
+ {0x40057, 0x1300},
+ {0x40077, 0x0},
+ {0x40018, 0x60a},
+ {0x40038, 0x1a},
+ {0x40058, 0x1200},
+ {0x40078, 0x0},
+ {0x40019, 0x642},
+ {0x40039, 0x1a},
+ {0x40059, 0x1300},
+ {0x40079, 0x0},
+ {0x4001a, 0x4808},
+ {0x4003a, 0x880},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900a4, 0x0},
+ {0x900a5, 0x790},
+ {0x900a6, 0x11a},
+ {0x900a7, 0x8},
+ {0x900a8, 0x7aa},
+ {0x900a9, 0x2a},
+ {0x900aa, 0x10},
+ {0x900ab, 0x7b2},
+ {0x900ac, 0x2a},
+ {0x900ad, 0x0},
+ {0x900ae, 0x7c8},
+ {0x900af, 0x109},
+ {0x900b0, 0x10},
+ {0x900b1, 0x10},
+ {0x900b2, 0x109},
+ {0x900b3, 0x10},
+ {0x900b4, 0x2a8},
+ {0x900b5, 0x129},
+ {0x900b6, 0x8},
+ {0x900b7, 0x370},
+ {0x900b8, 0x129},
+ {0x900b9, 0xa},
+ {0x900ba, 0x3c8},
+ {0x900bb, 0x1a9},
+ {0x900bc, 0xc},
+ {0x900bd, 0x408},
+ {0x900be, 0x199},
+ {0x900bf, 0x14},
+ {0x900c0, 0x790},
+ {0x900c1, 0x11a},
+ {0x900c2, 0x8},
+ {0x900c3, 0x4},
+ {0x900c4, 0x18},
+ {0x900c5, 0xe},
+ {0x900c6, 0x408},
+ {0x900c7, 0x199},
+ {0x900c8, 0x8},
+ {0x900c9, 0x8568},
+ {0x900ca, 0x108},
+ {0x900cb, 0x18},
+ {0x900cc, 0x790},
+ {0x900cd, 0x16a},
+ {0x900ce, 0x8},
+ {0x900cf, 0x1d8},
+ {0x900d0, 0x169},
+ {0x900d1, 0x10},
+ {0x900d2, 0x8558},
+ {0x900d3, 0x168},
+ {0x900d4, 0x70},
+ {0x900d5, 0x788},
+ {0x900d6, 0x16a},
+ {0x900d7, 0x1ff8},
+ {0x900d8, 0x85a8},
+ {0x900d9, 0x1e8},
+ {0x900da, 0x50},
+ {0x900db, 0x798},
+ {0x900dc, 0x16a},
+ {0x900dd, 0x60},
+ {0x900de, 0x7a0},
+ {0x900df, 0x16a},
+ {0x900e0, 0x8},
+ {0x900e1, 0x8310},
+ {0x900e2, 0x168},
+ {0x900e3, 0x8},
+ {0x900e4, 0xa310},
+ {0x900e5, 0x168},
+ {0x900e6, 0xa},
+ {0x900e7, 0x408},
+ {0x900e8, 0x169},
+ {0x900e9, 0x6e},
+ {0x900ea, 0x0},
+ {0x900eb, 0x68},
+ {0x900ec, 0x0},
+ {0x900ed, 0x408},
+ {0x900ee, 0x169},
+ {0x900ef, 0x0},
+ {0x900f0, 0x8310},
+ {0x900f1, 0x168},
+ {0x900f2, 0x0},
+ {0x900f3, 0xa310},
+ {0x900f4, 0x168},
+ {0x900f5, 0x1ff8},
+ {0x900f6, 0x85a8},
+ {0x900f7, 0x1e8},
+ {0x900f8, 0x68},
+ {0x900f9, 0x798},
+ {0x900fa, 0x16a},
+ {0x900fb, 0x78},
+ {0x900fc, 0x7a0},
+ {0x900fd, 0x16a},
+ {0x900fe, 0x68},
+ {0x900ff, 0x790},
+ {0x90100, 0x16a},
+ {0x90101, 0x8},
+ {0x90102, 0x8b10},
+ {0x90103, 0x168},
+ {0x90104, 0x8},
+ {0x90105, 0xab10},
+ {0x90106, 0x168},
+ {0x90107, 0xa},
+ {0x90108, 0x408},
+ {0x90109, 0x169},
+ {0x9010a, 0x58},
+ {0x9010b, 0x0},
+ {0x9010c, 0x68},
+ {0x9010d, 0x0},
+ {0x9010e, 0x408},
+ {0x9010f, 0x169},
+ {0x90110, 0x0},
+ {0x90111, 0x8b10},
+ {0x90112, 0x168},
+ {0x90113, 0x1},
+ {0x90114, 0xab10},
+ {0x90115, 0x168},
+ {0x90116, 0x0},
+ {0x90117, 0x1d8},
+ {0x90118, 0x169},
+ {0x90119, 0x80},
+ {0x9011a, 0x790},
+ {0x9011b, 0x16a},
+ {0x9011c, 0x18},
+ {0x9011d, 0x7aa},
+ {0x9011e, 0x6a},
+ {0x9011f, 0xa},
+ {0x90120, 0x0},
+ {0x90121, 0x1e9},
+ {0x90122, 0x8},
+ {0x90123, 0x8080},
+ {0x90124, 0x108},
+ {0x90125, 0xf},
+ {0x90126, 0x408},
+ {0x90127, 0x169},
+ {0x90128, 0xc},
+ {0x90129, 0x0},
+ {0x9012a, 0x68},
+ {0x9012b, 0x9},
+ {0x9012c, 0x0},
+ {0x9012d, 0x1a9},
+ {0x9012e, 0x0},
+ {0x9012f, 0x408},
+ {0x90130, 0x169},
+ {0x90131, 0x0},
+ {0x90132, 0x8080},
+ {0x90133, 0x108},
+ {0x90134, 0x8},
+ {0x90135, 0x7aa},
+ {0x90136, 0x6a},
+ {0x90137, 0x0},
+ {0x90138, 0x8568},
+ {0x90139, 0x108},
+ {0x9013a, 0xb7},
+ {0x9013b, 0x790},
+ {0x9013c, 0x16a},
+ {0x9013d, 0x1f},
+ {0x9013e, 0x0},
+ {0x9013f, 0x68},
+ {0x90140, 0x8},
+ {0x90141, 0x8558},
+ {0x90142, 0x168},
+ {0x90143, 0xf},
+ {0x90144, 0x408},
+ {0x90145, 0x169},
+ {0x90146, 0xd},
+ {0x90147, 0x0},
+ {0x90148, 0x68},
+ {0x90149, 0x0},
+ {0x9014a, 0x408},
+ {0x9014b, 0x169},
+ {0x9014c, 0x0},
+ {0x9014d, 0x8558},
+ {0x9014e, 0x168},
+ {0x9014f, 0x8},
+ {0x90150, 0x3c8},
+ {0x90151, 0x1a9},
+ {0x90152, 0x3},
+ {0x90153, 0x370},
+ {0x90154, 0x129},
+ {0x90155, 0x20},
+ {0x90156, 0x2aa},
+ {0x90157, 0x9},
+ {0x90158, 0x0},
+ {0x90159, 0x400},
+ {0x9015a, 0x10e},
+ {0x9015b, 0x8},
+ {0x9015c, 0xe8},
+ {0x9015d, 0x109},
+ {0x9015e, 0x0},
+ {0x9015f, 0x8140},
+ {0x90160, 0x10c},
+ {0x90161, 0x10},
+ {0x90162, 0x8138},
+ {0x90163, 0x10c},
+ {0x90164, 0x8},
+ {0x90165, 0x7c8},
+ {0x90166, 0x101},
+ {0x90167, 0x8},
+ {0x90168, 0x448},
+ {0x90169, 0x109},
+ {0x9016a, 0xf},
+ {0x9016b, 0x7c0},
+ {0x9016c, 0x109},
+ {0x9016d, 0x0},
+ {0x9016e, 0xe8},
+ {0x9016f, 0x109},
+ {0x90170, 0x47},
+ {0x90171, 0x630},
+ {0x90172, 0x109},
+ {0x90173, 0x8},
+ {0x90174, 0x618},
+ {0x90175, 0x109},
+ {0x90176, 0x8},
+ {0x90177, 0xe0},
+ {0x90178, 0x109},
+ {0x90179, 0x0},
+ {0x9017a, 0x7c8},
+ {0x9017b, 0x109},
+ {0x9017c, 0x8},
+ {0x9017d, 0x8140},
+ {0x9017e, 0x10c},
+ {0x9017f, 0x0},
+ {0x90180, 0x1},
+ {0x90181, 0x8},
+ {0x90182, 0x8},
+ {0x90183, 0x4},
+ {0x90184, 0x8},
+ {0x90185, 0x8},
+ {0x90186, 0x7c8},
+ {0x90187, 0x101},
+ {0x90006, 0x0},
+ {0x90007, 0x0},
+ {0x90008, 0x8},
+ {0x90009, 0x0},
+ {0x9000a, 0x0},
+ {0x9000b, 0x0},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x9001f, 0x29},
+ {0x90026, 0x6a},
+ {0x400d0, 0x0},
+ {0x400d1, 0x101},
+ {0x400d2, 0x105},
+ {0x400d3, 0x107},
+ {0x400d4, 0x10f},
+ {0x400d5, 0x202},
+ {0x400d6, 0x20a},
+ {0x400d7, 0x20b},
+ {0x2003a, 0x2},
+ {0x2000b, 0x64},
+ {0x2000c, 0xc8},
+ {0x2000d, 0x7d0},
+ {0x2000e, 0x2c},
+ {0x12000b, 0xc},
+ {0x12000c, 0x19},
+ {0x12000d, 0xfa},
+ {0x12000e, 0x10},
+ {0x22000b, 0x3},
+ {0x22000c, 0x6},
+ {0x22000d, 0x3e},
+ {0x22000e, 0x10},
+ {0x9000c, 0x0},
+ {0x9000d, 0x173},
+ {0x9000e, 0x60},
+ {0x9000f, 0x6110},
+ {0x90010, 0x2152},
+ {0x90011, 0xdfbd},
+ {0x90012, 0x2060},
+ {0x90013, 0x6152},
+ {0x20010, 0x5a},
+ {0x20011, 0x3},
+ {0x40080, 0xe0},
+ {0x40081, 0x12},
+ {0x40082, 0xe0},
+ {0x40083, 0x12},
+ {0x40084, 0xe0},
+ {0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
+ {0x400fd, 0xf},
+ {0x10011, 0x1},
+ {0x10012, 0x1},
+ {0x10013, 0x180},
+ {0x10018, 0x1},
+ {0x10002, 0x6209},
+ {0x100b2, 0x1},
+ {0x101b4, 0x1},
+ {0x102b4, 0x1},
+ {0x103b4, 0x1},
+ {0x104b4, 0x1},
+ {0x105b4, 0x1},
+ {0x106b4, 0x1},
+ {0x107b4, 0x1},
+ {0x108b4, 0x1},
+ {0x11011, 0x1},
+ {0x11012, 0x1},
+ {0x11013, 0x180},
+ {0x11018, 0x1},
+ {0x11002, 0x6209},
+ {0x110b2, 0x1},
+ {0x111b4, 0x1},
+ {0x112b4, 0x1},
+ {0x113b4, 0x1},
+ {0x114b4, 0x1},
+ {0x115b4, 0x1},
+ {0x116b4, 0x1},
+ {0x117b4, 0x1},
+ {0x118b4, 0x1},
+ {0x20089, 0x1},
+ {0x20088, 0x19},
+ {0xc0080, 0x2},
+ {0xd0000, 0x1},
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3200mts 1D */
+ .drate = 3200,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3200mts 2D */
+ .drate = 3200,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3200, 400, 100, },
+};
diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c
index 80f79ce888..5d4c2ac4c9 100644
--- a/board/freescale/imx8mn_evk/spl.c
+++ b/board/freescale/imx8mn_evk/spl.c
@@ -25,6 +25,12 @@
#include <dm/device.h>
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
+#include <power/pmic.h>
+#include <power/pca9450.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -52,6 +58,43 @@ void spl_board_init(void)
printf("Failed to find clock node. Check device tree\n");
}
+#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
+int power_init_board(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = pmic_get("pca9450 at 25", &dev);
+ if (ret == -ENODEV) {
+ puts("No pca9450 at 25\n");
+ return 0;
+ }
+ if (ret != 0)
+ return ret;
+
+ /* BUCKxOUT_DVS0/1 control BUCK123 output */
+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+ /* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */
+ /* Set DVS1 to 0.85v for suspend */
+ /* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
+ pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+ /* set VDD_SNVS_0V8 from default 0.85V */
+ pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
+
+ /* enable LDO4 to 1.2v */
+ pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x44);
+
+ /* set WDOG_B_CFG to cold reset */
+ pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig
new file mode 100644
index 0000000000..c53dc968c8
--- /dev/null
+++ b/configs/imx8mn_evk_defconfig
@@ -0,0 +1,93 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_TARGET_IMX8MN_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk"
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_WATCHDOG=y
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 17/26] imx8mn: Add low drive mode support for DDR4/LPDDR4 EVK
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (15 preceding siblings ...)
2021-03-19 7:57 ` [PATCH 16/26] imx8mn: Add LPDDR4 EVK board support Peng Fan
@ 2021-03-19 7:57 ` Peng Fan
2021-03-19 7:57 ` [PATCH 18/26] imx: logos: use NXP logo Peng Fan
` (8 subsequent siblings)
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:57 UTC (permalink / raw)
To: u-boot
From: Ye Li <ye.li@nxp.com>
Add dedicated defconfigs for iMX8MN low drive mode which set the VDD_SOC
and VDD_DRAM to 0.8v, DDR at 1600MTS (800Mhz clock) and GPU at 200Mhz.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/imx8m/soc.c | 45 +
board/freescale/imx8mn_evk/Kconfig | 4 +
board/freescale/imx8mn_evk/Makefile | 5 +
board/freescale/imx8mn_evk/ddr4_timing_ld.c | 1057 ++++++++++++
board/freescale/imx8mn_evk/lpddr4_timing_ld.c | 1441 +++++++++++++++++
board/freescale/imx8mn_evk/spl.c | 7 +-
6 files changed, 2558 insertions(+), 1 deletion(-)
create mode 100644 board/freescale/imx8mn_evk/ddr4_timing_ld.c
create mode 100644 board/freescale/imx8mn_evk/lpddr4_timing_ld.c
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 5f37282ff1..884ba76acd 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -726,6 +726,41 @@ int disable_vpu_nodes(void *blob)
return -EPERM;
}
+#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
+static int low_drive_gpu_freq(void *blob)
+{
+ static const char *nodes_path_8mn[] = {
+ "/gpu at 38000000",
+ "/soc at 0/gpu at 38000000"
+ };
+
+ int nodeoff, cnt, i;
+ u32 assignedclks[7];
+
+ nodeoff = fdt_path_offset(blob, nodes_path_8mn[0]);
+ if (nodeoff < 0)
+ return nodeoff;
+
+ cnt = fdtdec_get_int_array_count(blob, nodeoff, "assigned-clock-rates", assignedclks, 7);
+ if (cnt < 0)
+ return cnt;
+
+ if (cnt != 7)
+ printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt);
+
+ assignedclks[cnt - 1] = 200000000;
+ assignedclks[cnt - 2] = 200000000;
+
+ for (i = 0; i < cnt; i++) {
+ debug("<%u>, ", assignedclks[i]);
+ assignedclks[i] = cpu_to_fdt32(assignedclks[i]);
+ }
+ debug("\n");
+
+ return fdt_setprop(blob, nodeoff, "assigned-clock-rates", &assignedclks, sizeof(assignedclks));
+}
+#endif
+
int disable_gpu_nodes(void *blob)
{
static const char * const nodes_path_8mn[] = {
@@ -895,6 +930,16 @@ usb_modify_speed:
#elif defined(CONFIG_IMX8MN)
if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl())
disable_gpu_nodes(blob);
+#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
+ else {
+ int ldm_gpu = low_drive_gpu_freq(blob);
+
+ if (ldm_gpu < 0)
+ printf("Update GPU node assigned-clock-rates failed\n");
+ else
+ printf("Update GPU node assigned-clock-rates ok\n");
+ }
+#endif
if (is_imx8mnd() || is_imx8mndl())
disable_cpu_nodes(blob, 2);
diff --git a/board/freescale/imx8mn_evk/Kconfig b/board/freescale/imx8mn_evk/Kconfig
index ace6fc1e39..478f4ed66e 100644
--- a/board/freescale/imx8mn_evk/Kconfig
+++ b/board/freescale/imx8mn_evk/Kconfig
@@ -9,6 +9,10 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "imx8mn_evk"
+config IMX8MN_LOW_DRIVE_MODE
+ bool "Enable the low drive mode of iMX8MN on EVK board"
+ default n
+
source "board/freescale/common/Kconfig"
endif
diff --git a/board/freescale/imx8mn_evk/Makefile b/board/freescale/imx8mn_evk/Makefile
index 5d7dbe6628..42d1179724 100644
--- a/board/freescale/imx8mn_evk/Makefile
+++ b/board/freescale/imx8mn_evk/Makefile
@@ -8,6 +8,11 @@ obj-y += imx8mn_evk.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
+ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_ld.o
+obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing_ld.o
+else
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
endif
+endif
diff --git a/board/freescale/imx8mn_evk/ddr4_timing_ld.c b/board/freescale/imx8mn_evk/ddr4_timing_ld.c
new file mode 100644
index 0000000000..983fc7d99f
--- /dev/null
+++ b/board/freescale/imx8mn_evk/ddr4_timing_ld.c
@@ -0,0 +1,1057 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400000, 0x81040010 },
+ { 0x3d400030, 0x20 },
+ { 0x3d400034, 0x221306 },
+ { 0x3d400050, 0x210070 },
+ { 0x3d400054, 0x10008 },
+ { 0x3d400060, 0x0 },
+ { 0x3d400064, 0x6100dc },
+ { 0x3d4000c0, 0x0 },
+ { 0x3d4000c4, 0x1000 },
+ { 0x3d4000d0, 0xc00200c5 },
+ { 0x3d4000d4, 0x500000 },
+ { 0x3d4000dc, 0x2340105 },
+ { 0x3d4000e0, 0x0 },
+ { 0x3d4000e4, 0x110000 },
+ { 0x3d4000e8, 0x2000600 },
+ { 0x3d4000ec, 0x410 },
+ { 0x3d4000f0, 0x20 },
+ { 0x3d4000f4, 0xec7 },
+ { 0x3d400100, 0xd0c1b0d },
+ { 0x3d400104, 0x30313 },
+ { 0x3d400108, 0x508060a },
+ { 0x3d40010c, 0x400c },
+ { 0x3d400110, 0x6030306 },
+ { 0x3d400114, 0x4040302 },
+ { 0x3d40011c, 0x404 },
+ { 0x3d400120, 0x5050d08 },
+ { 0x3d400124, 0x20308 },
+ { 0x3d40012c, 0x1406010e },
+ { 0x3d400130, 0x8 },
+ { 0x3d40013c, 0x0 },
+ { 0x3d400180, 0x1000040 },
+ { 0x3d400184, 0x30d4 },
+ { 0x3d400190, 0x38b8204 },
+ { 0x3d400194, 0x2020303 },
+ { 0x3d400198, 0x7f04011 },
+ { 0x3d40019c, 0xb0 },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0x48005a },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x1 },
+ { 0x3d4001b4, 0xb04 },
+ { 0x3d4001b8, 0x4 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x0 },
+ { 0x3d400200, 0x3f1f },
+ { 0x3d400204, 0x3f0909 },
+ { 0x3d400208, 0x700 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf07 },
+ { 0x3d400220, 0x3f01 },
+ { 0x3d400240, 0x600061c },
+ { 0x3d400244, 0x1323 },
+ { 0x3d400400, 0x100 },
+ { 0x3d400250, 0x317d1a07 },
+ { 0x3d400254, 0xf },
+ { 0x3d40025c, 0x2a001b76 },
+ { 0x3d400264, 0x7300b473 },
+ { 0x3d40026c, 0x30000e06 },
+ { 0x3d400300, 0x14 },
+ { 0x3d40036c, 0x10 },
+ { 0x3d400404, 0x13193 },
+ { 0x3d400408, 0x6096 },
+ { 0x3d400490, 0x1 },
+ { 0x3d400494, 0x2000c00 },
+ { 0x3d400498, 0x3c00db },
+ { 0x3d40049c, 0x100009 },
+ { 0x3d4004a0, 0x2 },
+ { 0x3d402050, 0x210070 },
+ { 0x3d402064, 0x400093 },
+ { 0x3d4020dc, 0x40105 },
+ { 0x3d4020e0, 0x0 },
+ { 0x3d4020e8, 0x2000600 },
+ { 0x3d4020ec, 0x10 },
+ { 0x3d402100, 0xb081209 },
+ { 0x3d402104, 0x2020d },
+ { 0x3d402108, 0x5050309 },
+ { 0x3d40210c, 0x400c },
+ { 0x3d402110, 0x5030206 },
+ { 0x3d402114, 0x3030202 },
+ { 0x3d40211c, 0x303 },
+ { 0x3d402120, 0x4040d06 },
+ { 0x3d402124, 0x20208 },
+ { 0x3d40212c, 0x1205010e },
+ { 0x3d402130, 0x8 },
+ { 0x3d40213c, 0x0 },
+ { 0x3d402180, 0x1000040 },
+ { 0x3d402190, 0x3858204 },
+ { 0x3d402194, 0x2020303 },
+ { 0x3d4021b4, 0x504 },
+ { 0x3d4021b8, 0x4 },
+ { 0x3d402240, 0x6000604 },
+ { 0x3d4020f4, 0xec7 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x1005f, 0x2fd },
+ { 0x1015f, 0x2fd },
+ { 0x1105f, 0x2fd },
+ { 0x1115f, 0x2fd },
+ { 0x11005f, 0x2fd },
+ { 0x11015f, 0x2fd },
+ { 0x11105f, 0x2fd },
+ { 0x11115f, 0x2fd },
+ { 0x55, 0x355 },
+ { 0x1055, 0x355 },
+ { 0x2055, 0x355 },
+ { 0x3055, 0x355 },
+ { 0x4055, 0x55 },
+ { 0x5055, 0x55 },
+ { 0x6055, 0x355 },
+ { 0x7055, 0x355 },
+ { 0x8055, 0x355 },
+ { 0x9055, 0x355 },
+ { 0x200c5, 0xb },
+ { 0x1200c5, 0x6 },
+ { 0x2002e, 0x1 },
+ { 0x12002e, 0x1 },
+ { 0x20024, 0x8 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x8 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0xa },
+ { 0x120056, 0xa },
+ { 0x1004d, 0x1a },
+ { 0x1014d, 0x1a },
+ { 0x1104d, 0x1a },
+ { 0x1114d, 0x1a },
+ { 0x11004d, 0x1a },
+ { 0x11014d, 0x1a },
+ { 0x11104d, 0x1a },
+ { 0x11114d, 0x1a },
+ { 0x10049, 0xe38 },
+ { 0x10149, 0xe38 },
+ { 0x11049, 0xe38 },
+ { 0x11149, 0xe38 },
+ { 0x110049, 0xe38 },
+ { 0x110149, 0xe38 },
+ { 0x111049, 0xe38 },
+ { 0x111149, 0xe38 },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x1 },
+ { 0x20075, 0x2 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x190 },
+ { 0x120008, 0x10a },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x268 },
+ { 0x10043, 0x5b1 },
+ { 0x10143, 0x5b1 },
+ { 0x11043, 0x5b1 },
+ { 0x11143, 0x5b1 },
+ { 0x1200b2, 0x268 },
+ { 0x110043, 0x5b1 },
+ { 0x110143, 0x5b1 },
+ { 0x111043, 0x5b1 },
+ { 0x111143, 0x5b1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x20019, 0x5 },
+ { 0x120019, 0x5 },
+ { 0x200f0, 0x5555 },
+ { 0x200f1, 0x5555 },
+ { 0x200f2, 0x5555 },
+ { 0x200f3, 0x5555 },
+ { 0x200f4, 0x5555 },
+ { 0x200f5, 0x5555 },
+ { 0x200f6, 0x5555 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x2005b, 0x7529 },
+ { 0x2005c, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x200cc, 0x1f7 },
+ { 0x1200c7, 0x21 },
+ { 0x1200ca, 0x24 },
+ { 0x1200cc, 0x1f7 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x0200b2, 0x0},
+ {0x1200b2, 0x0},
+ {0x2200b2, 0x0},
+ {0x0200cb, 0x0},
+ {0x010043, 0x0},
+ {0x110043, 0x0},
+ {0x210043, 0x0},
+ {0x010143, 0x0},
+ {0x110143, 0x0},
+ {0x210143, 0x0},
+ {0x011043, 0x0},
+ {0x111043, 0x0},
+ {0x211043, 0x0},
+ {0x011143, 0x0},
+ {0x111143, 0x0},
+ {0x211143, 0x0},
+ {0x000080, 0x0},
+ {0x100080, 0x0},
+ {0x200080, 0x0},
+ {0x001080, 0x0},
+ {0x101080, 0x0},
+ {0x201080, 0x0},
+ {0x002080, 0x0},
+ {0x102080, 0x0},
+ {0x202080, 0x0},
+ {0x003080, 0x0},
+ {0x103080, 0x0},
+ {0x203080, 0x0},
+ {0x004080, 0x0},
+ {0x104080, 0x0},
+ {0x204080, 0x0},
+ {0x005080, 0x0},
+ {0x105080, 0x0},
+ {0x205080, 0x0},
+ {0x006080, 0x0},
+ {0x106080, 0x0},
+ {0x206080, 0x0},
+ {0x007080, 0x0},
+ {0x107080, 0x0},
+ {0x207080, 0x0},
+ {0x008080, 0x0},
+ {0x108080, 0x0},
+ {0x208080, 0x0},
+ {0x009080, 0x0},
+ {0x109080, 0x0},
+ {0x209080, 0x0},
+ {0x010080, 0x0},
+ {0x110080, 0x0},
+ {0x210080, 0x0},
+ {0x010180, 0x0},
+ {0x110180, 0x0},
+ {0x210180, 0x0},
+ {0x010081, 0x0},
+ {0x110081, 0x0},
+ {0x210081, 0x0},
+ {0x010181, 0x0},
+ {0x110181, 0x0},
+ {0x210181, 0x0},
+ {0x010082, 0x0},
+ {0x110082, 0x0},
+ {0x210082, 0x0},
+ {0x010182, 0x0},
+ {0x110182, 0x0},
+ {0x210182, 0x0},
+ {0x010083, 0x0},
+ {0x110083, 0x0},
+ {0x210083, 0x0},
+ {0x010183, 0x0},
+ {0x110183, 0x0},
+ {0x210183, 0x0},
+ {0x011080, 0x0},
+ {0x111080, 0x0},
+ {0x211080, 0x0},
+ {0x011180, 0x0},
+ {0x111180, 0x0},
+ {0x211180, 0x0},
+ {0x011081, 0x0},
+ {0x111081, 0x0},
+ {0x211081, 0x0},
+ {0x011181, 0x0},
+ {0x111181, 0x0},
+ {0x211181, 0x0},
+ {0x011082, 0x0},
+ {0x111082, 0x0},
+ {0x211082, 0x0},
+ {0x011182, 0x0},
+ {0x111182, 0x0},
+ {0x211182, 0x0},
+ {0x011083, 0x0},
+ {0x111083, 0x0},
+ {0x211083, 0x0},
+ {0x011183, 0x0},
+ {0x111183, 0x0},
+ {0x211183, 0x0},
+ {0x0100d0, 0x0},
+ {0x1100d0, 0x0},
+ {0x2100d0, 0x0},
+ {0x0101d0, 0x0},
+ {0x1101d0, 0x0},
+ {0x2101d0, 0x0},
+ {0x0100d1, 0x0},
+ {0x1100d1, 0x0},
+ {0x2100d1, 0x0},
+ {0x0101d1, 0x0},
+ {0x1101d1, 0x0},
+ {0x2101d1, 0x0},
+ {0x0100d2, 0x0},
+ {0x1100d2, 0x0},
+ {0x2100d2, 0x0},
+ {0x0101d2, 0x0},
+ {0x1101d2, 0x0},
+ {0x2101d2, 0x0},
+ {0x0100d3, 0x0},
+ {0x1100d3, 0x0},
+ {0x2100d3, 0x0},
+ {0x0101d3, 0x0},
+ {0x1101d3, 0x0},
+ {0x2101d3, 0x0},
+ {0x0110d0, 0x0},
+ {0x1110d0, 0x0},
+ {0x2110d0, 0x0},
+ {0x0111d0, 0x0},
+ {0x1111d0, 0x0},
+ {0x2111d0, 0x0},
+ {0x0110d1, 0x0},
+ {0x1110d1, 0x0},
+ {0x2110d1, 0x0},
+ {0x0111d1, 0x0},
+ {0x1111d1, 0x0},
+ {0x2111d1, 0x0},
+ {0x0110d2, 0x0},
+ {0x1110d2, 0x0},
+ {0x2110d2, 0x0},
+ {0x0111d2, 0x0},
+ {0x1111d2, 0x0},
+ {0x2111d2, 0x0},
+ {0x0110d3, 0x0},
+ {0x1110d3, 0x0},
+ {0x2110d3, 0x0},
+ {0x0111d3, 0x0},
+ {0x1111d3, 0x0},
+ {0x2111d3, 0x0},
+ {0x010068, 0x0},
+ {0x010168, 0x0},
+ {0x010268, 0x0},
+ {0x010368, 0x0},
+ {0x010468, 0x0},
+ {0x010568, 0x0},
+ {0x010668, 0x0},
+ {0x010768, 0x0},
+ {0x010868, 0x0},
+ {0x010069, 0x0},
+ {0x010169, 0x0},
+ {0x010269, 0x0},
+ {0x010369, 0x0},
+ {0x010469, 0x0},
+ {0x010569, 0x0},
+ {0x010669, 0x0},
+ {0x010769, 0x0},
+ {0x010869, 0x0},
+ {0x01006a, 0x0},
+ {0x01016a, 0x0},
+ {0x01026a, 0x0},
+ {0x01036a, 0x0},
+ {0x01046a, 0x0},
+ {0x01056a, 0x0},
+ {0x01066a, 0x0},
+ {0x01076a, 0x0},
+ {0x01086a, 0x0},
+ {0x01006b, 0x0},
+ {0x01016b, 0x0},
+ {0x01026b, 0x0},
+ {0x01036b, 0x0},
+ {0x01046b, 0x0},
+ {0x01056b, 0x0},
+ {0x01066b, 0x0},
+ {0x01076b, 0x0},
+ {0x01086b, 0x0},
+ {0x011068, 0x0},
+ {0x011168, 0x0},
+ {0x011268, 0x0},
+ {0x011368, 0x0},
+ {0x011468, 0x0},
+ {0x011568, 0x0},
+ {0x011668, 0x0},
+ {0x011768, 0x0},
+ {0x011868, 0x0},
+ {0x011069, 0x0},
+ {0x011169, 0x0},
+ {0x011269, 0x0},
+ {0x011369, 0x0},
+ {0x011469, 0x0},
+ {0x011569, 0x0},
+ {0x011669, 0x0},
+ {0x011769, 0x0},
+ {0x011869, 0x0},
+ {0x01106a, 0x0},
+ {0x01116a, 0x0},
+ {0x01126a, 0x0},
+ {0x01136a, 0x0},
+ {0x01146a, 0x0},
+ {0x01156a, 0x0},
+ {0x01166a, 0x0},
+ {0x01176a, 0x0},
+ {0x01186a, 0x0},
+ {0x01106b, 0x0},
+ {0x01116b, 0x0},
+ {0x01126b, 0x0},
+ {0x01136b, 0x0},
+ {0x01146b, 0x0},
+ {0x01156b, 0x0},
+ {0x01166b, 0x0},
+ {0x01176b, 0x0},
+ {0x01186b, 0x0},
+ {0x01008c, 0x0},
+ {0x11008c, 0x0},
+ {0x21008c, 0x0},
+ {0x01018c, 0x0},
+ {0x11018c, 0x0},
+ {0x21018c, 0x0},
+ {0x01008d, 0x0},
+ {0x11008d, 0x0},
+ {0x21008d, 0x0},
+ {0x01018d, 0x0},
+ {0x11018d, 0x0},
+ {0x21018d, 0x0},
+ {0x01008e, 0x0},
+ {0x11008e, 0x0},
+ {0x21008e, 0x0},
+ {0x01018e, 0x0},
+ {0x11018e, 0x0},
+ {0x21018e, 0x0},
+ {0x01008f, 0x0},
+ {0x11008f, 0x0},
+ {0x21008f, 0x0},
+ {0x01018f, 0x0},
+ {0x11018f, 0x0},
+ {0x21018f, 0x0},
+ {0x01108c, 0x0},
+ {0x11108c, 0x0},
+ {0x21108c, 0x0},
+ {0x01118c, 0x0},
+ {0x11118c, 0x0},
+ {0x21118c, 0x0},
+ {0x01108d, 0x0},
+ {0x11108d, 0x0},
+ {0x21108d, 0x0},
+ {0x01118d, 0x0},
+ {0x11118d, 0x0},
+ {0x21118d, 0x0},
+ {0x01108e, 0x0},
+ {0x11108e, 0x0},
+ {0x21108e, 0x0},
+ {0x01118e, 0x0},
+ {0x11118e, 0x0},
+ {0x21118e, 0x0},
+ {0x01108f, 0x0},
+ {0x11108f, 0x0},
+ {0x21108f, 0x0},
+ {0x01118f, 0x0},
+ {0x11118f, 0x0},
+ {0x21118f, 0x0},
+ {0x0100c0, 0x0},
+ {0x1100c0, 0x0},
+ {0x2100c0, 0x0},
+ {0x0101c0, 0x0},
+ {0x1101c0, 0x0},
+ {0x2101c0, 0x0},
+ {0x0102c0, 0x0},
+ {0x1102c0, 0x0},
+ {0x2102c0, 0x0},
+ {0x0103c0, 0x0},
+ {0x1103c0, 0x0},
+ {0x2103c0, 0x0},
+ {0x0104c0, 0x0},
+ {0x1104c0, 0x0},
+ {0x2104c0, 0x0},
+ {0x0105c0, 0x0},
+ {0x1105c0, 0x0},
+ {0x2105c0, 0x0},
+ {0x0106c0, 0x0},
+ {0x1106c0, 0x0},
+ {0x2106c0, 0x0},
+ {0x0107c0, 0x0},
+ {0x1107c0, 0x0},
+ {0x2107c0, 0x0},
+ {0x0108c0, 0x0},
+ {0x1108c0, 0x0},
+ {0x2108c0, 0x0},
+ {0x0100c1, 0x0},
+ {0x1100c1, 0x0},
+ {0x2100c1, 0x0},
+ {0x0101c1, 0x0},
+ {0x1101c1, 0x0},
+ {0x2101c1, 0x0},
+ {0x0102c1, 0x0},
+ {0x1102c1, 0x0},
+ {0x2102c1, 0x0},
+ {0x0103c1, 0x0},
+ {0x1103c1, 0x0},
+ {0x2103c1, 0x0},
+ {0x0104c1, 0x0},
+ {0x1104c1, 0x0},
+ {0x2104c1, 0x0},
+ {0x0105c1, 0x0},
+ {0x1105c1, 0x0},
+ {0x2105c1, 0x0},
+ {0x0106c1, 0x0},
+ {0x1106c1, 0x0},
+ {0x2106c1, 0x0},
+ {0x0107c1, 0x0},
+ {0x1107c1, 0x0},
+ {0x2107c1, 0x0},
+ {0x0108c1, 0x0},
+ {0x1108c1, 0x0},
+ {0x2108c1, 0x0},
+ {0x0100c2, 0x0},
+ {0x1100c2, 0x0},
+ {0x2100c2, 0x0},
+ {0x0101c2, 0x0},
+ {0x1101c2, 0x0},
+ {0x2101c2, 0x0},
+ {0x0102c2, 0x0},
+ {0x1102c2, 0x0},
+ {0x2102c2, 0x0},
+ {0x0103c2, 0x0},
+ {0x1103c2, 0x0},
+ {0x2103c2, 0x0},
+ {0x0104c2, 0x0},
+ {0x1104c2, 0x0},
+ {0x2104c2, 0x0},
+ {0x0105c2, 0x0},
+ {0x1105c2, 0x0},
+ {0x2105c2, 0x0},
+ {0x0106c2, 0x0},
+ {0x1106c2, 0x0},
+ {0x2106c2, 0x0},
+ {0x0107c2, 0x0},
+ {0x1107c2, 0x0},
+ {0x2107c2, 0x0},
+ {0x0108c2, 0x0},
+ {0x1108c2, 0x0},
+ {0x2108c2, 0x0},
+ {0x0100c3, 0x0},
+ {0x1100c3, 0x0},
+ {0x2100c3, 0x0},
+ {0x0101c3, 0x0},
+ {0x1101c3, 0x0},
+ {0x2101c3, 0x0},
+ {0x0102c3, 0x0},
+ {0x1102c3, 0x0},
+ {0x2102c3, 0x0},
+ {0x0103c3, 0x0},
+ {0x1103c3, 0x0},
+ {0x2103c3, 0x0},
+ {0x0104c3, 0x0},
+ {0x1104c3, 0x0},
+ {0x2104c3, 0x0},
+ {0x0105c3, 0x0},
+ {0x1105c3, 0x0},
+ {0x2105c3, 0x0},
+ {0x0106c3, 0x0},
+ {0x1106c3, 0x0},
+ {0x2106c3, 0x0},
+ {0x0107c3, 0x0},
+ {0x1107c3, 0x0},
+ {0x2107c3, 0x0},
+ {0x0108c3, 0x0},
+ {0x1108c3, 0x0},
+ {0x2108c3, 0x0},
+ {0x0110c0, 0x0},
+ {0x1110c0, 0x0},
+ {0x2110c0, 0x0},
+ {0x0111c0, 0x0},
+ {0x1111c0, 0x0},
+ {0x2111c0, 0x0},
+ {0x0112c0, 0x0},
+ {0x1112c0, 0x0},
+ {0x2112c0, 0x0},
+ {0x0113c0, 0x0},
+ {0x1113c0, 0x0},
+ {0x2113c0, 0x0},
+ {0x0114c0, 0x0},
+ {0x1114c0, 0x0},
+ {0x2114c0, 0x0},
+ {0x0115c0, 0x0},
+ {0x1115c0, 0x0},
+ {0x2115c0, 0x0},
+ {0x0116c0, 0x0},
+ {0x1116c0, 0x0},
+ {0x2116c0, 0x0},
+ {0x0117c0, 0x0},
+ {0x1117c0, 0x0},
+ {0x2117c0, 0x0},
+ {0x0118c0, 0x0},
+ {0x1118c0, 0x0},
+ {0x2118c0, 0x0},
+ {0x0110c1, 0x0},
+ {0x1110c1, 0x0},
+ {0x2110c1, 0x0},
+ {0x0111c1, 0x0},
+ {0x1111c1, 0x0},
+ {0x2111c1, 0x0},
+ {0x0112c1, 0x0},
+ {0x1112c1, 0x0},
+ {0x2112c1, 0x0},
+ {0x0113c1, 0x0},
+ {0x1113c1, 0x0},
+ {0x2113c1, 0x0},
+ {0x0114c1, 0x0},
+ {0x1114c1, 0x0},
+ {0x2114c1, 0x0},
+ {0x0115c1, 0x0},
+ {0x1115c1, 0x0},
+ {0x2115c1, 0x0},
+ {0x0116c1, 0x0},
+ {0x1116c1, 0x0},
+ {0x2116c1, 0x0},
+ {0x0117c1, 0x0},
+ {0x1117c1, 0x0},
+ {0x2117c1, 0x0},
+ {0x0118c1, 0x0},
+ {0x1118c1, 0x0},
+ {0x2118c1, 0x0},
+ {0x0110c2, 0x0},
+ {0x1110c2, 0x0},
+ {0x2110c2, 0x0},
+ {0x0111c2, 0x0},
+ {0x1111c2, 0x0},
+ {0x2111c2, 0x0},
+ {0x0112c2, 0x0},
+ {0x1112c2, 0x0},
+ {0x2112c2, 0x0},
+ {0x0113c2, 0x0},
+ {0x1113c2, 0x0},
+ {0x2113c2, 0x0},
+ {0x0114c2, 0x0},
+ {0x1114c2, 0x0},
+ {0x2114c2, 0x0},
+ {0x0115c2, 0x0},
+ {0x1115c2, 0x0},
+ {0x2115c2, 0x0},
+ {0x0116c2, 0x0},
+ {0x1116c2, 0x0},
+ {0x2116c2, 0x0},
+ {0x0117c2, 0x0},
+ {0x1117c2, 0x0},
+ {0x2117c2, 0x0},
+ {0x0118c2, 0x0},
+ {0x1118c2, 0x0},
+ {0x2118c2, 0x0},
+ {0x0110c3, 0x0},
+ {0x1110c3, 0x0},
+ {0x2110c3, 0x0},
+ {0x0111c3, 0x0},
+ {0x1111c3, 0x0},
+ {0x2111c3, 0x0},
+ {0x0112c3, 0x0},
+ {0x1112c3, 0x0},
+ {0x2112c3, 0x0},
+ {0x0113c3, 0x0},
+ {0x1113c3, 0x0},
+ {0x2113c3, 0x0},
+ {0x0114c3, 0x0},
+ {0x1114c3, 0x0},
+ {0x2114c3, 0x0},
+ {0x0115c3, 0x0},
+ {0x1115c3, 0x0},
+ {0x2115c3, 0x0},
+ {0x0116c3, 0x0},
+ {0x1116c3, 0x0},
+ {0x2116c3, 0x0},
+ {0x0117c3, 0x0},
+ {0x1117c3, 0x0},
+ {0x2117c3, 0x0},
+ {0x0118c3, 0x0},
+ {0x1118c3, 0x0},
+ {0x2118c3, 0x0},
+ {0x010020, 0x0},
+ {0x110020, 0x0},
+ {0x210020, 0x0},
+ {0x011020, 0x0},
+ {0x111020, 0x0},
+ {0x211020, 0x0},
+ {0x02007d, 0x0},
+ {0x12007d, 0x0},
+ {0x22007d, 0x0},
+ {0x010040, 0x0},
+ {0x010140, 0x0},
+ {0x010240, 0x0},
+ {0x010340, 0x0},
+ {0x010440, 0x0},
+ {0x010540, 0x0},
+ {0x010640, 0x0},
+ {0x010740, 0x0},
+ {0x010840, 0x0},
+ {0x010030, 0x0},
+ {0x010130, 0x0},
+ {0x010230, 0x0},
+ {0x010330, 0x0},
+ {0x010430, 0x0},
+ {0x010530, 0x0},
+ {0x010630, 0x0},
+ {0x010730, 0x0},
+ {0x010830, 0x0},
+ {0x011040, 0x0},
+ {0x011140, 0x0},
+ {0x011240, 0x0},
+ {0x011340, 0x0},
+ {0x011440, 0x0},
+ {0x011540, 0x0},
+ {0x011640, 0x0},
+ {0x011740, 0x0},
+ {0x011840, 0x0},
+ {0x011030, 0x0},
+ {0x011130, 0x0},
+ {0x011230, 0x0},
+ {0x011330, 0x0},
+ {0x011430, 0x0},
+ {0x011530, 0x0},
+ {0x011630, 0x0},
+ {0x011730, 0x0},
+ {0x011830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0x640 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2830 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x31f },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x100 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x234 },
+ { 0x54030, 0x105 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x600 },
+ { 0x54035, 0x410 },
+ { 0x54036, 0x101 },
+ { 0x5403f, 0x1221 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x1 },
+ { 0x54003, 0x42a },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2830 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x21f },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x100 },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x4 },
+ { 0x54030, 0x105 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x600 },
+ { 0x54035, 0x10 },
+ { 0x54036, 0x101 },
+ { 0x5403f, 0x1221 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0x640 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2830 },
+ { 0x54006, 0x25e },
+ { 0x54007, 0x1000 },
+ { 0x54008, 0x101 },
+ { 0x5400b, 0x61 },
+ { 0x5400c, 0xc8 },
+ { 0x5400d, 0x100 },
+ { 0x5400e, 0x1f7f },
+ { 0x54012, 0x1 },
+ { 0x5402f, 0x234 },
+ { 0x54030, 0x105 },
+ { 0x54033, 0x200 },
+ { 0x54034, 0x600 },
+ { 0x54035, 0x410 },
+ { 0x54036, 0x101 },
+ { 0x5403f, 0x1221 },
+ { 0x541fc, 0x100 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x2 },
+ { 0x90033, 0x10 },
+ { 0x90034, 0x139 },
+ { 0x90035, 0xb },
+ { 0x90036, 0x7c0 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0x44 },
+ { 0x90039, 0x633 },
+ { 0x9003a, 0x159 },
+ { 0x9003b, 0x14f },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x47 },
+ { 0x9003f, 0x633 },
+ { 0x90040, 0x149 },
+ { 0x90041, 0x4f },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x179 },
+ { 0x90044, 0x8 },
+ { 0x90045, 0xe0 },
+ { 0x90046, 0x109 },
+ { 0x90047, 0x0 },
+ { 0x90048, 0x7c8 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x1 },
+ { 0x9004c, 0x8 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x45a },
+ { 0x9004f, 0x9 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x448 },
+ { 0x90052, 0x109 },
+ { 0x90053, 0x40 },
+ { 0x90054, 0x633 },
+ { 0x90055, 0x179 },
+ { 0x90056, 0x1 },
+ { 0x90057, 0x618 },
+ { 0x90058, 0x109 },
+ { 0x90059, 0x40c0 },
+ { 0x9005a, 0x633 },
+ { 0x9005b, 0x149 },
+ { 0x9005c, 0x8 },
+ { 0x9005d, 0x4 },
+ { 0x9005e, 0x48 },
+ { 0x9005f, 0x4040 },
+ { 0x90060, 0x633 },
+ { 0x90061, 0x149 },
+ { 0x90062, 0x0 },
+ { 0x90063, 0x4 },
+ { 0x90064, 0x48 },
+ { 0x90065, 0x40 },
+ { 0x90066, 0x633 },
+ { 0x90067, 0x149 },
+ { 0x90068, 0x10 },
+ { 0x90069, 0x4 },
+ { 0x9006a, 0x18 },
+ { 0x9006b, 0x0 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x78 },
+ { 0x9006e, 0x549 },
+ { 0x9006f, 0x633 },
+ { 0x90070, 0x159 },
+ { 0x90071, 0xd49 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0x94a },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x441 },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x149 },
+ { 0x9007a, 0x42 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x1 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x0 },
+ { 0x90081, 0xe0 },
+ { 0x90082, 0x109 },
+ { 0x90083, 0xa },
+ { 0x90084, 0x10 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0x9 },
+ { 0x90087, 0x3c0 },
+ { 0x90088, 0x149 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x159 },
+ { 0x9008c, 0x18 },
+ { 0x9008d, 0x10 },
+ { 0x9008e, 0x109 },
+ { 0x9008f, 0x0 },
+ { 0x90090, 0x3c0 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x18 },
+ { 0x90093, 0x4 },
+ { 0x90094, 0x48 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x58 },
+ { 0x90098, 0xb },
+ { 0x90099, 0x10 },
+ { 0x9009a, 0x109 },
+ { 0x9009b, 0x1 },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x5 },
+ { 0x9009f, 0x7c0 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x0 },
+ { 0x900a2, 0x8140 },
+ { 0x900a3, 0x10c },
+ { 0x900a4, 0x10 },
+ { 0x900a5, 0x8138 },
+ { 0x900a6, 0x10c },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7c8 },
+ { 0x900a9, 0x101 },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x448 },
+ { 0x900ac, 0x109 },
+ { 0x900ad, 0xf },
+ { 0x900ae, 0x7c0 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x47 },
+ { 0x900b1, 0x630 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x8 },
+ { 0x900b4, 0x618 },
+ { 0x900b5, 0x109 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0xe0 },
+ { 0x900b8, 0x109 },
+ { 0x900b9, 0x0 },
+ { 0x900ba, 0x7c8 },
+ { 0x900bb, 0x109 },
+ { 0x900bc, 0x8 },
+ { 0x900bd, 0x8140 },
+ { 0x900be, 0x10c },
+ { 0x900bf, 0x0 },
+ { 0x900c0, 0x1 },
+ { 0x900c1, 0x8 },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x8 },
+ { 0x900c5, 0x8 },
+ { 0x900c6, 0x7c8 },
+ { 0x900c7, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x90026, 0x2b },
+ { 0x2000b, 0x32 },
+ { 0x2000c, 0x64 },
+ { 0x2000d, 0x3e8 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0x21 },
+ { 0x12000c, 0x42 },
+ { 0x12000d, 0x29a },
+ { 0x12000e, 0x21 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0xffff },
+ { 0x90013, 0x6152 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x0 },
+ { 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 1600mts 1D */
+ .drate = 1600,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 1066mts 1D */
+ .drate = 1066,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P0 1600mts 2D */
+ .drate = 1600,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 1600, 1066, },
+};
+
diff --git a/board/freescale/imx8mn_evk/lpddr4_timing_ld.c b/board/freescale/imx8mn_evk/lpddr4_timing_ld.c
new file mode 100644
index 0000000000..5faa0021a7
--- /dev/null
+++ b/board/freescale/imx8mn_evk/lpddr4_timing_ld.c
@@ -0,0 +1,1441 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa3080020 },
+ { 0x3d400020, 0x111 },
+ { 0x3d400024, 0x1f400 },
+ { 0x3d400064, 0x300070 },
+ { 0x3d4000d0, 0xc002030f },
+ { 0x3d4000d4, 0x500000 },
+ { 0x3d4000dc, 0xa40012 },
+ { 0x3d4000e0, 0x310000 },
+ { 0x3d4000e8, 0x66004d },
+ { 0x3d4000ec, 0x16004d },
+ { 0x3d400100, 0x10100d11 },
+ { 0x3d400104, 0x3041a },
+ { 0x3d40010c, 0x606000 },
+ { 0x3d400110, 0x8040408 },
+ { 0x3d400114, 0x2030606 },
+ { 0x3d400118, 0x1010004 },
+ { 0x3d40011c, 0x301 },
+ { 0x3d400130, 0x20300 },
+ { 0x3d400134, 0xa100002 },
+ { 0x3d400138, 0x73 },
+ { 0x3d400144, 0x500028 },
+ { 0x3d400180, 0x190000c },
+ { 0x3d400184, 0x14030d4 },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x4898204 },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x904 },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x4070f0f },
+ { 0x3d400200, 0x17 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d400250, 0x29001701 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x11 },
+ { 0x3d402024, 0x7d00 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0xc001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004d },
+ { 0x3d4020ec, 0x16004d },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x11 },
+ { 0x3d403024, 0x1f40 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x310000 },
+ { 0x3d4030e8, 0x66004d },
+ { 0x3d4030ec, 0x16004d },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0xb },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x1 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x220024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x1 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x190 },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xdc },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x2005b, 0x7529 },
+ { 0x2005c, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x200cc, 0x1f7 },
+ { 0x1200c7, 0x21 },
+ { 0x1200ca, 0x24 },
+ { 0x1200cc, 0x1f7 },
+ { 0x2200c7, 0x21 },
+ { 0x2200ca, 0x24 },
+ { 0x2200cc, 0x1f7 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x22007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x22007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x0200b2, 0x0},
+ {0x1200b2, 0x0},
+ {0x2200b2, 0x0},
+ {0x0200cb, 0x0},
+ {0x010043, 0x0},
+ {0x110043, 0x0},
+ {0x210043, 0x0},
+ {0x010143, 0x0},
+ {0x110143, 0x0},
+ {0x210143, 0x0},
+ {0x011043, 0x0},
+ {0x111043, 0x0},
+ {0x211043, 0x0},
+ {0x011143, 0x0},
+ {0x111143, 0x0},
+ {0x211143, 0x0},
+ {0x000080, 0x0},
+ {0x100080, 0x0},
+ {0x200080, 0x0},
+ {0x001080, 0x0},
+ {0x101080, 0x0},
+ {0x201080, 0x0},
+ {0x002080, 0x0},
+ {0x102080, 0x0},
+ {0x202080, 0x0},
+ {0x003080, 0x0},
+ {0x103080, 0x0},
+ {0x203080, 0x0},
+ {0x004080, 0x0},
+ {0x104080, 0x0},
+ {0x204080, 0x0},
+ {0x005080, 0x0},
+ {0x105080, 0x0},
+ {0x205080, 0x0},
+ {0x006080, 0x0},
+ {0x106080, 0x0},
+ {0x206080, 0x0},
+ {0x007080, 0x0},
+ {0x107080, 0x0},
+ {0x207080, 0x0},
+ {0x008080, 0x0},
+ {0x108080, 0x0},
+ {0x208080, 0x0},
+ {0x009080, 0x0},
+ {0x109080, 0x0},
+ {0x209080, 0x0},
+ {0x010080, 0x0},
+ {0x110080, 0x0},
+ {0x210080, 0x0},
+ {0x010180, 0x0},
+ {0x110180, 0x0},
+ {0x210180, 0x0},
+ {0x011080, 0x0},
+ {0x111080, 0x0},
+ {0x211080, 0x0},
+ {0x011180, 0x0},
+ {0x111180, 0x0},
+ {0x211180, 0x0},
+ {0x010081, 0x0},
+ {0x110081, 0x0},
+ {0x210081, 0x0},
+ {0x010181, 0x0},
+ {0x110181, 0x0},
+ {0x210181, 0x0},
+ {0x011081, 0x0},
+ {0x111081, 0x0},
+ {0x211081, 0x0},
+ {0x011181, 0x0},
+ {0x111181, 0x0},
+ {0x211181, 0x0},
+ {0x0100d0, 0x0},
+ {0x1100d0, 0x0},
+ {0x2100d0, 0x0},
+ {0x0101d0, 0x0},
+ {0x1101d0, 0x0},
+ {0x2101d0, 0x0},
+ {0x0110d0, 0x0},
+ {0x1110d0, 0x0},
+ {0x2110d0, 0x0},
+ {0x0111d0, 0x0},
+ {0x1111d0, 0x0},
+ {0x2111d0, 0x0},
+ {0x0100d1, 0x0},
+ {0x1100d1, 0x0},
+ {0x2100d1, 0x0},
+ {0x0101d1, 0x0},
+ {0x1101d1, 0x0},
+ {0x2101d1, 0x0},
+ {0x0110d1, 0x0},
+ {0x1110d1, 0x0},
+ {0x2110d1, 0x0},
+ {0x0111d1, 0x0},
+ {0x1111d1, 0x0},
+ {0x2111d1, 0x0},
+ {0x010068, 0x0},
+ {0x010168, 0x0},
+ {0x010268, 0x0},
+ {0x010368, 0x0},
+ {0x010468, 0x0},
+ {0x010568, 0x0},
+ {0x010668, 0x0},
+ {0x010768, 0x0},
+ {0x010868, 0x0},
+ {0x011068, 0x0},
+ {0x011168, 0x0},
+ {0x011268, 0x0},
+ {0x011368, 0x0},
+ {0x011468, 0x0},
+ {0x011568, 0x0},
+ {0x011668, 0x0},
+ {0x011768, 0x0},
+ {0x011868, 0x0},
+ {0x010069, 0x0},
+ {0x010169, 0x0},
+ {0x010269, 0x0},
+ {0x010369, 0x0},
+ {0x010469, 0x0},
+ {0x010569, 0x0},
+ {0x010669, 0x0},
+ {0x010769, 0x0},
+ {0x010869, 0x0},
+ {0x011069, 0x0},
+ {0x011169, 0x0},
+ {0x011269, 0x0},
+ {0x011369, 0x0},
+ {0x011469, 0x0},
+ {0x011569, 0x0},
+ {0x011669, 0x0},
+ {0x011769, 0x0},
+ {0x011869, 0x0},
+ {0x01008c, 0x0},
+ {0x11008c, 0x0},
+ {0x21008c, 0x0},
+ {0x01018c, 0x0},
+ {0x11018c, 0x0},
+ {0x21018c, 0x0},
+ {0x01108c, 0x0},
+ {0x11108c, 0x0},
+ {0x21108c, 0x0},
+ {0x01118c, 0x0},
+ {0x11118c, 0x0},
+ {0x21118c, 0x0},
+ {0x01008d, 0x0},
+ {0x11008d, 0x0},
+ {0x21008d, 0x0},
+ {0x01018d, 0x0},
+ {0x11018d, 0x0},
+ {0x21018d, 0x0},
+ {0x01108d, 0x0},
+ {0x11108d, 0x0},
+ {0x21108d, 0x0},
+ {0x01118d, 0x0},
+ {0x11118d, 0x0},
+ {0x21118d, 0x0},
+ {0x0100c0, 0x0},
+ {0x1100c0, 0x0},
+ {0x2100c0, 0x0},
+ {0x0101c0, 0x0},
+ {0x1101c0, 0x0},
+ {0x2101c0, 0x0},
+ {0x0102c0, 0x0},
+ {0x1102c0, 0x0},
+ {0x2102c0, 0x0},
+ {0x0103c0, 0x0},
+ {0x1103c0, 0x0},
+ {0x2103c0, 0x0},
+ {0x0104c0, 0x0},
+ {0x1104c0, 0x0},
+ {0x2104c0, 0x0},
+ {0x0105c0, 0x0},
+ {0x1105c0, 0x0},
+ {0x2105c0, 0x0},
+ {0x0106c0, 0x0},
+ {0x1106c0, 0x0},
+ {0x2106c0, 0x0},
+ {0x0107c0, 0x0},
+ {0x1107c0, 0x0},
+ {0x2107c0, 0x0},
+ {0x0108c0, 0x0},
+ {0x1108c0, 0x0},
+ {0x2108c0, 0x0},
+ {0x0110c0, 0x0},
+ {0x1110c0, 0x0},
+ {0x2110c0, 0x0},
+ {0x0111c0, 0x0},
+ {0x1111c0, 0x0},
+ {0x2111c0, 0x0},
+ {0x0112c0, 0x0},
+ {0x1112c0, 0x0},
+ {0x2112c0, 0x0},
+ {0x0113c0, 0x0},
+ {0x1113c0, 0x0},
+ {0x2113c0, 0x0},
+ {0x0114c0, 0x0},
+ {0x1114c0, 0x0},
+ {0x2114c0, 0x0},
+ {0x0115c0, 0x0},
+ {0x1115c0, 0x0},
+ {0x2115c0, 0x0},
+ {0x0116c0, 0x0},
+ {0x1116c0, 0x0},
+ {0x2116c0, 0x0},
+ {0x0117c0, 0x0},
+ {0x1117c0, 0x0},
+ {0x2117c0, 0x0},
+ {0x0118c0, 0x0},
+ {0x1118c0, 0x0},
+ {0x2118c0, 0x0},
+ {0x0100c1, 0x0},
+ {0x1100c1, 0x0},
+ {0x2100c1, 0x0},
+ {0x0101c1, 0x0},
+ {0x1101c1, 0x0},
+ {0x2101c1, 0x0},
+ {0x0102c1, 0x0},
+ {0x1102c1, 0x0},
+ {0x2102c1, 0x0},
+ {0x0103c1, 0x0},
+ {0x1103c1, 0x0},
+ {0x2103c1, 0x0},
+ {0x0104c1, 0x0},
+ {0x1104c1, 0x0},
+ {0x2104c1, 0x0},
+ {0x0105c1, 0x0},
+ {0x1105c1, 0x0},
+ {0x2105c1, 0x0},
+ {0x0106c1, 0x0},
+ {0x1106c1, 0x0},
+ {0x2106c1, 0x0},
+ {0x0107c1, 0x0},
+ {0x1107c1, 0x0},
+ {0x2107c1, 0x0},
+ {0x0108c1, 0x0},
+ {0x1108c1, 0x0},
+ {0x2108c1, 0x0},
+ {0x0110c1, 0x0},
+ {0x1110c1, 0x0},
+ {0x2110c1, 0x0},
+ {0x0111c1, 0x0},
+ {0x1111c1, 0x0},
+ {0x2111c1, 0x0},
+ {0x0112c1, 0x0},
+ {0x1112c1, 0x0},
+ {0x2112c1, 0x0},
+ {0x0113c1, 0x0},
+ {0x1113c1, 0x0},
+ {0x2113c1, 0x0},
+ {0x0114c1, 0x0},
+ {0x1114c1, 0x0},
+ {0x2114c1, 0x0},
+ {0x0115c1, 0x0},
+ {0x1115c1, 0x0},
+ {0x2115c1, 0x0},
+ {0x0116c1, 0x0},
+ {0x1116c1, 0x0},
+ {0x2116c1, 0x0},
+ {0x0117c1, 0x0},
+ {0x1117c1, 0x0},
+ {0x2117c1, 0x0},
+ {0x0118c1, 0x0},
+ {0x1118c1, 0x0},
+ {0x2118c1, 0x0},
+ {0x010020, 0x0},
+ {0x110020, 0x0},
+ {0x210020, 0x0},
+ {0x011020, 0x0},
+ {0x111020, 0x0},
+ {0x211020, 0x0},
+ {0x020072, 0x0},
+ {0x020073, 0x0},
+ {0x020074, 0x0},
+ {0x0100aa, 0x0},
+ {0x0110aa, 0x0},
+ {0x020010, 0x0},
+ {0x120010, 0x0},
+ {0x220010, 0x0},
+ {0x020011, 0x0},
+ {0x120011, 0x0},
+ {0x220011, 0x0},
+ {0x0100ae, 0x0},
+ {0x1100ae, 0x0},
+ {0x2100ae, 0x0},
+ {0x0100af, 0x0},
+ {0x1100af, 0x0},
+ {0x2100af, 0x0},
+ {0x0110ae, 0x0},
+ {0x1110ae, 0x0},
+ {0x2110ae, 0x0},
+ {0x0110af, 0x0},
+ {0x1110af, 0x0},
+ {0x2110af, 0x0},
+ {0x020020, 0x0},
+ {0x120020, 0x0},
+ {0x220020, 0x0},
+ {0x0100a0, 0x0},
+ {0x0100a1, 0x0},
+ {0x0100a2, 0x0},
+ {0x0100a3, 0x0},
+ {0x0100a4, 0x0},
+ {0x0100a5, 0x0},
+ {0x0100a6, 0x0},
+ {0x0100a7, 0x0},
+ {0x0110a0, 0x0},
+ {0x0110a1, 0x0},
+ {0x0110a2, 0x0},
+ {0x0110a3, 0x0},
+ {0x0110a4, 0x0},
+ {0x0110a5, 0x0},
+ {0x0110a6, 0x0},
+ {0x0110a7, 0x0},
+ {0x02007c, 0x0},
+ {0x12007c, 0x0},
+ {0x22007c, 0x0},
+ {0x02007d, 0x0},
+ {0x12007d, 0x0},
+ {0x22007d, 0x0},
+ {0x0400fd, 0x0},
+ {0x0400c0, 0x0},
+ {0x090201, 0x0},
+ {0x190201, 0x0},
+ {0x290201, 0x0},
+ {0x090202, 0x0},
+ {0x190202, 0x0},
+ {0x290202, 0x0},
+ {0x090203, 0x0},
+ {0x190203, 0x0},
+ {0x290203, 0x0},
+ {0x090204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x090205, 0x0},
+ {0x190205, 0x0},
+ {0x290205, 0x0},
+ {0x090206, 0x0},
+ {0x190206, 0x0},
+ {0x290206, 0x0},
+ {0x090207, 0x0},
+ {0x190207, 0x0},
+ {0x290207, 0x0},
+ {0x090208, 0x0},
+ {0x190208, 0x0},
+ {0x290208, 0x0},
+ {0x010062, 0x0},
+ {0x010162, 0x0},
+ {0x010262, 0x0},
+ {0x010362, 0x0},
+ {0x010462, 0x0},
+ {0x010562, 0x0},
+ {0x010662, 0x0},
+ {0x010762, 0x0},
+ {0x010862, 0x0},
+ {0x011062, 0x0},
+ {0x011162, 0x0},
+ {0x011262, 0x0},
+ {0x011362, 0x0},
+ {0x011462, 0x0},
+ {0x011562, 0x0},
+ {0x011662, 0x0},
+ {0x011762, 0x0},
+ {0x011862, 0x0},
+ {0x020077, 0x0},
+ {0x010001, 0x0},
+ {0x011001, 0x0},
+ {0x010040, 0x0},
+ {0x010140, 0x0},
+ {0x010240, 0x0},
+ {0x010340, 0x0},
+ {0x010440, 0x0},
+ {0x010540, 0x0},
+ {0x010640, 0x0},
+ {0x010740, 0x0},
+ {0x010840, 0x0},
+ {0x010030, 0x0},
+ {0x010130, 0x0},
+ {0x010230, 0x0},
+ {0x010330, 0x0},
+ {0x010430, 0x0},
+ {0x010530, 0x0},
+ {0x010630, 0x0},
+ {0x010730, 0x0},
+ {0x010830, 0x0},
+ {0x011040, 0x0},
+ {0x011140, 0x0},
+ {0x011240, 0x0},
+ {0x011340, 0x0},
+ {0x011440, 0x0},
+ {0x011540, 0x0},
+ {0x011640, 0x0},
+ {0x011740, 0x0},
+ {0x011840, 0x0},
+ {0x011030, 0x0},
+ {0x011130, 0x0},
+ {0x011230, 0x0},
+ {0x011330, 0x0},
+ {0x011430, 0x0},
+ {0x011530, 0x0},
+ {0x011630, 0x0},
+ {0x011730, 0x0},
+ {0x011830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0x640 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x12a4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x12a4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x54032, 0xa400 },
+ { 0x54033, 0x3112 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xa400 },
+ { 0x54039, 0x3112 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0x640 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400d, 0x100 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x12a4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x12a4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x54032, 0xa400 },
+ { 0x54033, 0x3112 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xa400 },
+ { 0x54039, 0x3112 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xb },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x633 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x633 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x633 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x633 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x633 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x633 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x633 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xb },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x1 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x625 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
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+ { 0x4000e, 0x625 },
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+ { 0x4000f, 0x4040 },
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+ { 0x40010, 0x2604 },
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+ { 0x40050, 0x0 },
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+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
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+ { 0x40033, 0x1a },
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+ { 0x40034, 0xa },
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+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a4, 0x0 },
+ { 0x900a5, 0x790 },
+ { 0x900a6, 0x11a },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7aa },
+ { 0x900a9, 0x2a },
+ { 0x900aa, 0x10 },
+ { 0x900ab, 0x7b2 },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x0 },
+ { 0x900ae, 0x7c8 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x10 },
+ { 0x900b1, 0x10 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x0 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xd },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x0 },
+ { 0x90159, 0x400 },
+ { 0x9015a, 0x10e },
+ { 0x9015b, 0x8 },
+ { 0x9015c, 0xe8 },
+ { 0x9015d, 0x109 },
+ { 0x9015e, 0x0 },
+ { 0x9015f, 0x8140 },
+ { 0x90160, 0x10c },
+ { 0x90161, 0x10 },
+ { 0x90162, 0x8138 },
+ { 0x90163, 0x10c },
+ { 0x90164, 0x8 },
+ { 0x90165, 0x7c8 },
+ { 0x90166, 0x101 },
+ { 0x90167, 0x8 },
+ { 0x90168, 0x448 },
+ { 0x90169, 0x109 },
+ { 0x9016a, 0xf },
+ { 0x9016b, 0x7c0 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0x0 },
+ { 0x9016e, 0xe8 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x47 },
+ { 0x90171, 0x630 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x8 },
+ { 0x90174, 0x618 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0xe0 },
+ { 0x90178, 0x109 },
+ { 0x90179, 0x0 },
+ { 0x9017a, 0x7c8 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x8 },
+ { 0x9017d, 0x8140 },
+ { 0x9017e, 0x10c },
+ { 0x9017f, 0x0 },
+ { 0x90180, 0x1 },
+ { 0x90181, 0x8 },
+ { 0x90182, 0x8 },
+ { 0x90183, 0x4 },
+ { 0x90184, 0x8 },
+ { 0x90185, 0x8 },
+ { 0x90186, 0x7c8 },
+ { 0x90187, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x29 },
+ { 0x90026, 0x6a },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x2000b, 0x32 },
+ { 0x2000c, 0x64 },
+ { 0x2000d, 0x3e8 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0xc },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x3 },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x2060 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x120010, 0x5a },
+ { 0x120011, 0x3 },
+ { 0x220010, 0x5a },
+ { 0x220011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 1600mts 1D */
+ .drate = 1600,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 1600mts 2D */
+ .drate = 1600,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 1600, 400, 100, },
+};
diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c
index 5d4c2ac4c9..03f2a56e80 100644
--- a/board/freescale/imx8mn_evk/spl.c
+++ b/board/freescale/imx8mn_evk/spl.c
@@ -75,10 +75,15 @@ int power_init_board(void)
/* BUCKxOUT_DVS0/1 control BUCK123 output */
pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
+ /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10);
+#else
/* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
+#endif
/* Set DVS1 to 0.85v for suspend */
/* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */
- pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 18/26] imx: logos: use NXP logo
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (16 preceding siblings ...)
2021-03-19 7:57 ` [PATCH 17/26] imx8mn: Add low drive mode support for DDR4/LPDDR4 EVK Peng Fan
@ 2021-03-19 7:57 ` Peng Fan
2021-03-19 7:57 ` [PATCH 19/26] imx8mn: Add support for 11x11 UltraLite part number Peng Fan
` (7 subsequent siblings)
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:57 UTC (permalink / raw)
To: u-boot
From: Peng Fan <peng.fan@nxp.com>
Use NXP logo. The vendor and board dir not changed,
only replace the content of freescale.bmp.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
tools/logos/freescale.bmp | Bin 46738 -> 47670 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/tools/logos/freescale.bmp b/tools/logos/freescale.bmp
index 1589e8073d133b61d5dedb99ff393ef9aa68a07f..43e0591c8ead8641e0fa8de3f13fcca5f55b3a69 100644
GIT binary patch
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--
2.30.0
^ permalink raw reply [flat|nested] 42+ messages in thread* [PATCH 19/26] imx8mn: Add support for 11x11 UltraLite part number
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (17 preceding siblings ...)
2021-03-19 7:57 ` [PATCH 18/26] imx: logos: use NXP logo Peng Fan
@ 2021-03-19 7:57 ` Peng Fan
2021-03-19 7:57 ` [PATCH 20/26] imx8m: Update thermal and PMU kernel nodes for dual/single cores Peng Fan
` (6 subsequent siblings)
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:57 UTC (permalink / raw)
To: u-boot
From: Ye Li <ye.li@nxp.com>
There are 3 part numbers for 11x11 i.MX8MNano with different core number
configuration: UltraLite Quad/Dual/Solo
Comparing with i.MX8MN Lite parts, they have MIPI DSI disabled. So
checking the MIPI DSI disable fuse to recognize these parts.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx/cpu.h | 11 ++++---
arch/arm/include/asm/mach-imx/sys_proto.h | 6 +++-
arch/arm/mach-imx/cpu.c | 8 ++++-
arch/arm/mach-imx/imx8m/soc.c | 36 +++++++++++++++--------
4 files changed, 43 insertions(+), 18 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index f37fe21446..28244d7671 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -40,10 +40,13 @@
#define MXC_CPU_IMX8MNL 0x8e /* dummy ID */
#define MXC_CPU_IMX8MNDL 0x8f /* dummy ID */
#define MXC_CPU_IMX8MNSL 0x181 /* dummy ID */
-#define MXC_CPU_IMX8MP 0x182/* dummy ID */
-#define MXC_CPU_IMX8MP6 0x184 /* dummy ID */
-#define MXC_CPU_IMX8MPL 0x186 /* dummy ID */
-#define MXC_CPU_IMX8MPD 0x187 /* dummy ID */
+#define MXC_CPU_IMX8MNUQ 0x182 /* dummy ID */
+#define MXC_CPU_IMX8MNUD 0x183 /* dummy ID */
+#define MXC_CPU_IMX8MNUS 0x184 /* dummy ID */
+#define MXC_CPU_IMX8MP 0x185/* dummy ID */
+#define MXC_CPU_IMX8MP6 0x186 /* dummy ID */
+#define MXC_CPU_IMX8MPL 0x187 /* dummy ID */
+#define MXC_CPU_IMX8MPD 0x188 /* dummy ID */
#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
#define MXC_CPU_IMX8QM 0x91 /* dummy ID */
#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 43eae6d796..c7668ffc4d 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -60,12 +60,16 @@ struct bd_info;
#define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL))
#define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \
is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \
- is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL))
+ is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL) || \
+ is_cpu_type(MXC_CPU_IMX8MNUD) || is_cpu_type(MXC_CPU_IMX8MNUS) || is_cpu_type(MXC_CPU_IMX8MNUQ))
#define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND))
#define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS))
#define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL))
#define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL))
#define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL))
+#define is_imx8mnuq() (is_cpu_type(MXC_CPU_IMX8MNUQ))
+#define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD))
+#define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS))
#define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \
is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6))
#define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD))
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 38b87ed5c3..423b715352 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -117,7 +117,13 @@ const char *get_imx_type(u32 imxtype)
case MXC_CPU_IMX8MNDL:
return "8MNano DualLite"; /* Dual-core Lite version */
case MXC_CPU_IMX8MNSL:
- return "8MNano SoloLite"; /* Single-core Lite version */
+ return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */
+ case MXC_CPU_IMX8MNUQ:
+ return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */
+ case MXC_CPU_IMX8MNUD:
+ return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */
+ case MXC_CPU_IMX8MNUS:
+ return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */
case MXC_CPU_IMX8MM:
return "8MMQ"; /* Quad-core version of the imx8mm */
case MXC_CPU_IMX8MML:
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 884ba76acd..a9b6ac962d 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -324,18 +324,30 @@ static u32 get_cpu_variant_type(u32 type)
} else if (type == MXC_CPU_IMX8MN) {
switch (value & 0x3) {
case 2:
- if (value & 0x1000000)
- return MXC_CPU_IMX8MNDL;
- else
+ if (value & 0x1000000) {
+ if (value & 0x10000000) /* MIPI DSI */
+ return MXC_CPU_IMX8MNUD;
+ else
+ return MXC_CPU_IMX8MNDL;
+ } else {
return MXC_CPU_IMX8MND;
+ }
case 3:
- if (value & 0x1000000)
- return MXC_CPU_IMX8MNSL;
- else
+ if (value & 0x1000000) {
+ if (value & 0x10000000) /* MIPI DSI */
+ return MXC_CPU_IMX8MNUS;
+ else
+ return MXC_CPU_IMX8MNSL;
+ } else {
return MXC_CPU_IMX8MNS;
+ }
default:
- if (value & 0x1000000)
- return MXC_CPU_IMX8MNL;
+ if (value & 0x1000000) {
+ if (value & 0x10000000) /* MIPI DSI */
+ return MXC_CPU_IMX8MNUQ;
+ else
+ return MXC_CPU_IMX8MNL;
+ }
break;
}
} else if (type == MXC_CPU_IMX8MP) {
@@ -468,7 +480,7 @@ int arch_cpu_init(void)
if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() ||
is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() ||
- is_imx8mnsl() || is_imx8mpd()) {
+ is_imx8mnsl() || is_imx8mpd() || is_imx8mnud() || is_imx8mnus()) {
/* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */
struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840);
struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880);
@@ -477,7 +489,7 @@ int arch_cpu_init(void)
writel(0x1, &pgc_core2->pgcr);
writel(0x1, &pgc_core3->pgcr);
- if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl()) {
+ if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) {
writel(0x1, &pgc_core1->pgcr);
writel(0xE, &gpc->cpu_pgc_dn_trg);
} else {
@@ -941,9 +953,9 @@ usb_modify_speed:
}
#endif
- if (is_imx8mnd() || is_imx8mndl())
+ if (is_imx8mnd() || is_imx8mndl() || is_imx8mnud())
disable_cpu_nodes(blob, 2);
- else if (is_imx8mns() || is_imx8mnsl())
+ else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus())
disable_cpu_nodes(blob, 3);
#elif defined(CONFIG_IMX8MP)
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 20/26] imx8m: Update thermal and PMU kernel nodes for dual/single cores
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (18 preceding siblings ...)
2021-03-19 7:57 ` [PATCH 19/26] imx8mn: Add support for 11x11 UltraLite part number Peng Fan
@ 2021-03-19 7:57 ` Peng Fan
2021-03-19 7:57 ` [PATCH 21/26] imx8m: soc: update fuse path Peng Fan
` (5 subsequent siblings)
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:57 UTC (permalink / raw)
To: u-boot
From: Ye Li <ye.li@nxp.com>
For dual core and single core iMX8M parts, the thermal node and PMU node
in kernel DTB also needs update to remove the refers to deleted core nodes.
Otherwise both driver will fail to work.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/imx8m/soc.c | 76 +++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index a9b6ac962d..6f7f093e87 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -810,6 +810,79 @@ int disable_dsp_nodes(void *blob)
return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
}
+static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores)
+{
+ static const char * const thermal_path[] = {
+ "/thermal-zones/cpu-thermal/cooling-maps/map0"
+ };
+
+ int nodeoff, cnt, i, ret, j;
+ u32 cooling_dev[12];
+
+ for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
+ nodeoff = fdt_path_offset(blob, thermal_path[i]);
+ if (nodeoff < 0)
+ continue; /* Not found, skip it */
+
+ cnt = fdtdec_get_int_array_count(blob, nodeoff, "cooling-device", cooling_dev, 12);
+ if (cnt < 0)
+ continue;
+
+ if (cnt != 12)
+ printf("Warning: %s, cooling-device count %d\n", thermal_path[i], cnt);
+
+ for (j = 0; j < cnt; j++)
+ cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]);
+
+ ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev,
+ sizeof(u32) * (12 - disabled_cores * 3));
+ if (ret < 0) {
+ printf("Warning: %s, cooling-device setprop failed %d\n",
+ thermal_path[i], ret);
+ continue;
+ }
+
+ printf("Update node %s, cooling-device prop\n", thermal_path[i]);
+ }
+}
+
+static void disable_pmu_cpu_nodes(void *blob, u32 disabled_cores)
+{
+ static const char * const pmu_path[] = {
+ "/pmu"
+ };
+
+ int nodeoff, cnt, i, ret, j;
+ u32 irq_affinity[4];
+
+ for (i = 0; i < ARRAY_SIZE(pmu_path); i++) {
+ nodeoff = fdt_path_offset(blob, pmu_path[i]);
+ if (nodeoff < 0)
+ continue; /* Not found, skip it */
+
+ cnt = fdtdec_get_int_array_count(blob, nodeoff, "interrupt-affinity",
+ irq_affinity, 4);
+ if (cnt < 0)
+ continue;
+
+ if (cnt != 4)
+ printf("Warning: %s, interrupt-affinity count %d\n", pmu_path[i], cnt);
+
+ for (j = 0; j < cnt; j++)
+ irq_affinity[j] = cpu_to_fdt32(irq_affinity[j]);
+
+ ret = fdt_setprop(blob, nodeoff, "interrupt-affinity", &irq_affinity,
+ sizeof(u32) * (4 - disabled_cores));
+ if (ret < 0) {
+ printf("Warning: %s, interrupt-affinity setprop failed %d\n",
+ pmu_path[i], ret);
+ continue;
+ }
+
+ printf("Update node %s, interrupt-affinity prop\n", pmu_path[i]);
+ }
+}
+
static int disable_cpu_nodes(void *blob, u32 disabled_cores)
{
static const char * const nodes_path[] = {
@@ -842,6 +915,9 @@ static int disable_cpu_nodes(void *blob, u32 disabled_cores)
}
}
+ disable_thermal_cpu_nodes(blob, disabled_cores);
+ disable_pmu_cpu_nodes(blob, disabled_cores);
+
return 0;
}
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 21/26] imx8m: soc: update fuse path
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (19 preceding siblings ...)
2021-03-19 7:57 ` [PATCH 20/26] imx8m: Update thermal and PMU kernel nodes for dual/single cores Peng Fan
@ 2021-03-19 7:57 ` Peng Fan
2021-03-19 7:57 ` [PATCH 22/26] imx8m: ddr: Disable CA VREF Training for LPDDR4 Peng Fan
` (4 subsequent siblings)
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:57 UTC (permalink / raw)
To: u-boot
From: Peng Fan <peng.fan@nxp.com>
Update fuse path to disable modules correctly.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/imx8m/soc.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 6f7f093e87..c447ea2ab9 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -628,7 +628,8 @@ static int disable_mipi_dsi_nodes(void *blob)
"/mipi_dsi_bridge at 30A00000",
"/dsi_phy at 30A00300",
"/soc at 0/bus at 30800000/mipi_dsi at 30a00000",
- "/soc at 0/bus at 30800000/dphy at 30a00300"
+ "/soc at 0/bus at 30800000/dphy at 30a00300",
+ "/soc at 0/bus at 30800000/mipi-dsi at 30a00000",
};
return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
@@ -656,7 +657,8 @@ static int check_mipi_dsi_nodes(void *blob)
{
static const char * const lcdif_path[] = {
"/lcdif at 30320000",
- "/soc at 0/bus at 30000000/lcdif at 30320000"
+ "/soc at 0/bus at 30000000/lcdif at 30320000",
+ "/soc at 0/bus at 30000000/lcd-controller at 30320000"
};
static const char * const mipi_dsi_path[] = {
"/mipi_dsi at 30A00000",
@@ -664,11 +666,13 @@ static int check_mipi_dsi_nodes(void *blob)
};
static const char * const lcdif_ep_path[] = {
"/lcdif at 30320000/port at 0/mipi-dsi-endpoint",
- "/soc at 0/bus at 30000000/lcdif at 30320000/port at 0/endpoint"
+ "/soc at 0/bus at 30000000/lcdif at 30320000/port at 0/endpoint",
+ "/soc at 0/bus at 30000000/lcd-controller at 30320000/port at 0/endpoint"
};
static const char * const mipi_dsi_ep_path[] = {
"/mipi_dsi at 30A00000/port at 1/endpoint",
- "/soc at 0/bus at 30800000/mipi_dsi at 30a00000/ports/port at 0/endpoint"
+ "/soc at 0/bus at 30800000/mipi_dsi at 30a00000/ports/port at 0/endpoint",
+ "/soc at 0/bus at 30800000/mipi-dsi at 30a00000/ports/port at 0/endpoint at 0"
};
int lookup_node;
@@ -776,7 +780,8 @@ static int low_drive_gpu_freq(void *blob)
int disable_gpu_nodes(void *blob)
{
static const char * const nodes_path_8mn[] = {
- "/gpu at 38000000"
+ "/gpu at 38000000",
+ "/soc@/gpu at 38000000"
};
return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 22/26] imx8m: ddr: Disable CA VREF Training for LPDDR4
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (20 preceding siblings ...)
2021-03-19 7:57 ` [PATCH 21/26] imx8m: soc: update fuse path Peng Fan
@ 2021-03-19 7:57 ` Peng Fan
2021-03-24 21:25 ` Tim Harvey
2021-03-19 7:57 ` [PATCH 23/26] arch: mach-imx: imx8m: fix unique_id read error for imx8mp Peng Fan
` (3 subsequent siblings)
25 siblings, 1 reply; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:57 UTC (permalink / raw)
To: u-boot
From: Ye Li <ye.li@nxp.com>
Users reported LPDDR4 MR12 value is set to 0 during PHY training,
not the value from FSP timing structure, which cause compliance test failed.
The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing
but not set in 1D. According to PHY training application node,
to enable the feature both 1D and 2D need set this field to 1,
otherwise the training result will be incorrect.
The PHY training doc also recommends to set CATrainOpt[0] to 0 to use
MR12 value from message block (FSP structure). So update the LPDDR4
scripts of all mscale to clear CATrainOpt[0].
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
board/freescale/imx8mn_evk/lpddr4_timing_ld.c | 1 -
board/freescale/imx8mp_evk/lpddr4_timing.c | 2 --
2 files changed, 3 deletions(-)
diff --git a/board/freescale/imx8mn_evk/lpddr4_timing_ld.c b/board/freescale/imx8mn_evk/lpddr4_timing_ld.c
index 5faa0021a7..aa23c35094 100644
--- a/board/freescale/imx8mn_evk/lpddr4_timing_ld.c
+++ b/board/freescale/imx8mn_evk/lpddr4_timing_ld.c
@@ -799,7 +799,6 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0x54008, 0x61 },
{ 0x54009, 0xc8 },
{ 0x5400b, 0x2 },
- { 0x5400d, 0x100 },
{ 0x5400f, 0x100 },
{ 0x54010, 0x1f7f },
{ 0x54012, 0x310 },
diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c
index 9d069fc27a..8c5306d5d2 100755
--- a/board/freescale/imx8mp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mp_evk/lpddr4_timing.c
@@ -1298,7 +1298,6 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0x54008, 0x61 },
{ 0x54009, 0xc8 },
{ 0x5400b, 0x2 },
- { 0x5400d, 0x100 },
{ 0x5400f, 0x100 },
{ 0x54010, 0x1f7f },
{ 0x54012, 0x310 },
@@ -1330,7 +1329,6 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0x54008, 0x61 },
{ 0x54009, 0xc8 },
{ 0x5400b, 0x2 },
- { 0x5400d, 0x100 },
{ 0x5400f, 0x100 },
{ 0x54010, 0x1f7f },
{ 0x54012, 0x310 },
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 22/26] imx8m: ddr: Disable CA VREF Training for LPDDR4
2021-03-19 7:57 ` [PATCH 22/26] imx8m: ddr: Disable CA VREF Training for LPDDR4 Peng Fan
@ 2021-03-24 21:25 ` Tim Harvey
2021-03-25 8:14 ` Stefano Babic
0 siblings, 1 reply; 42+ messages in thread
From: Tim Harvey @ 2021-03-24 21:25 UTC (permalink / raw)
To: u-boot
On Fri, Mar 19, 2021 at 12:31 AM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>
> From: Ye Li <ye.li@nxp.com>
>
> Users reported LPDDR4 MR12 value is set to 0 during PHY training,
> not the value from FSP timing structure, which cause compliance test failed.
> The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing
> but not set in 1D. According to PHY training application node,
> to enable the feature both 1D and 2D need set this field to 1,
> otherwise the training result will be incorrect.
> The PHY training doc also recommends to set CATrainOpt[0] to 0 to use
> MR12 value from message block (FSP structure). So update the LPDDR4
> scripts of all mscale to clear CATrainOpt[0].
Peng,
Is this issue being addressed by an update of the NXP i.MX 8M Family
DDR Tools app that generates this code? Is there a reference to this
issue online anywhere?
A bit unrelated but I would love to see NXP step up and replace the
silly NXP i.MX 8M Family DDR Tools windows app with code that could be
enabled in the SPL to do the same thing. Personally it's a bit of a
joke to require having a Windows PC around to bring up an ARM
processor board and I would hope there are folks at NXP that are
utterly ashamed at this as well. One could easily use the opensource
imx-usb-loader to load an SPL that performed this calibration and
training code.
Tim
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 22/26] imx8m: ddr: Disable CA VREF Training for LPDDR4
2021-03-24 21:25 ` Tim Harvey
@ 2021-03-25 8:14 ` Stefano Babic
2021-03-25 8:35 ` Peng Fan
0 siblings, 1 reply; 42+ messages in thread
From: Stefano Babic @ 2021-03-25 8:14 UTC (permalink / raw)
To: u-boot
Hi Tim,
On 24.03.21 22:25, Tim Harvey wrote:
> On Fri, Mar 19, 2021 at 12:31 AM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>>
>> From: Ye Li <ye.li@nxp.com>
>>
>> Users reported LPDDR4 MR12 value is set to 0 during PHY training,
>> not the value from FSP timing structure, which cause compliance test failed.
>> The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing
>> but not set in 1D. According to PHY training application node,
>> to enable the feature both 1D and 2D need set this field to 1,
>> otherwise the training result will be incorrect.
>> The PHY training doc also recommends to set CATrainOpt[0] to 0 to use
>> MR12 value from message block (FSP structure). So update the LPDDR4
>> scripts of all mscale to clear CATrainOpt[0].
>
> Peng,
>
> Is this issue being addressed by an update of the NXP i.MX 8M Family
> DDR Tools app that generates this code? Is there a reference to this
> issue online anywhere?
>
> A bit unrelated but I would love to see NXP step up and replace the
> silly NXP i.MX 8M Family DDR Tools windows app with code that could be
> enabled in the SPL to do the same thing. Personally it's a bit of a
> joke to require having a Windows PC around to bring up an ARM
> processor board and I would hope there are folks at NXP that are
> utterly ashamed at this as well. One could easily use the opensource
> imx-usb-loader to load an SPL that performed this calibration and
> training code.
You find a lot of friends here....most of us will frankly be glad if
there will be such as tool, or at least if some code is published to
help to port to Linux. NXP story did not show a big interest in the past
with the Windows-based MFGTools, but I hoped this was changed with
"uuu". Such as tool will really help to improve i.MX support and enlarge
NXP community (just a couple of notes: I do not expect Peng can decide
this, but he can report our thought internally to NXP).
Best regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 22/26] imx8m: ddr: Disable CA VREF Training for LPDDR4
2021-03-25 8:14 ` Stefano Babic
@ 2021-03-25 8:35 ` Peng Fan
0 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-25 8:35 UTC (permalink / raw)
To: u-boot
On 2021/3/25 16:14, Stefano Babic wrote:
> Hi Tim,
>
> On 24.03.21 22:25, Tim Harvey wrote:
>> On Fri, Mar 19, 2021 at 12:31 AM Peng Fan (OSS) <peng.fan@oss.nxp.com>
>> wrote:
>>>
>>> From: Ye Li <ye.li@nxp.com>
>>>
>>> Users reported LPDDR4 MR12 value is set to 0 during PHY training,
>>> not the value from FSP timing structure, which cause compliance test
>>> failed.
>>> The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing
>>> but not set in 1D.? According to PHY training application node,
>>> to enable the feature both 1D and 2D need set this field to 1,
>>> otherwise the training result will be incorrect.
>>> The PHY training doc also recommends to set CATrainOpt[0] to 0 to use
>>> MR12 value from message block (FSP structure). So update the LPDDR4
>>> scripts of all mscale to clear CATrainOpt[0].
>>
>> Peng,
>>
>> Is this issue being addressed by an update of the NXP i.MX 8M Family
>> DDR Tools app that generates this code? Is there a reference to this
>> issue online anywhere?
>>
>> A bit unrelated but I would love to see NXP step up and replace the
>> silly NXP i.MX 8M Family DDR Tools windows app with code that could be
>> enabled in the SPL to do the same thing. Personally it's a bit of a
>> joke to require having a Windows PC around to bring up an ARM
>> processor board and I would hope there are folks at NXP that are
>> utterly ashamed at this as well. One could easily use the opensource
>> imx-usb-loader to load an SPL that performed this calibration and
>> training code.
>
> You find a lot of friends here....most of us will frankly be glad if
> there will be such as tool, or at least if some code is published to
> help to port to Linux. NXP story did not show a big interest in the past
> with the Windows-based MFGTools, but I hoped this was changed with
> "uuu". Such as tool will really help to improve i.MX support and enlarge
> NXP community (just a couple of notes: I do not expect Peng can decide
> this, but he can report our thought internally to NXP).
I have forwarded Tim's to NXP internal. And will also add yours'
comments about this DDR tool.
I am not the DDR guy, it is out of my power to do the convert, but I'll
try to sell your ideas.
Thanks,
Peng.
>
> Best regards,
> Stefano
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 23/26] arch: mach-imx: imx8m: fix unique_id read error for imx8mp
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (21 preceding siblings ...)
2021-03-19 7:57 ` [PATCH 22/26] imx8m: ddr: Disable CA VREF Training for LPDDR4 Peng Fan
@ 2021-03-19 7:57 ` Peng Fan
2021-03-19 7:57 ` [PATCH 24/26] iMX8MQ: Recognize the B2 revision Peng Fan
` (2 subsequent siblings)
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:57 UTC (permalink / raw)
To: u-boot
From: Peng Fan <peng.fan@nxp.com>
The value of Unique ID in uboot and kernel is different for iMX8MP:
serial#=02e1444a0002aaff
root at imx8mpevk:/sys/devices/soc0# cat soc_uid
D699300002E1444A
The reason is that Fuse Addresses of Unique ID of iMX8MP are 0x420 and
0x430.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 3f50014618..49bac8c1fa 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -120,6 +120,16 @@ struct ocotp_regs {
} bank[0];
};
+#ifdef CONFIG_IMX8MP
+struct fuse_bank0_regs {
+ u32 lock;
+ u32 rsvd0[7];
+ u32 uid_low;
+ u32 rsvd1[3];
+ u32 uid_high;
+ u32 rsvd2[3];
+};
+#else
struct fuse_bank0_regs {
u32 lock;
u32 rsvd0[3];
@@ -128,6 +138,7 @@ struct fuse_bank0_regs {
u32 uid_high;
u32 rsvd2[7];
};
+#endif
struct fuse_bank1_regs {
u32 tester3;
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 24/26] iMX8MQ: Recognize the B2 revision
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (22 preceding siblings ...)
2021-03-19 7:57 ` [PATCH 23/26] arch: mach-imx: imx8m: fix unique_id read error for imx8mp Peng Fan
@ 2021-03-19 7:57 ` Peng Fan
2021-03-19 7:57 ` [PATCH 25/26] misc: ocotp: Update OCOTP driver for iMX8MQ B2 Peng Fan
2021-03-19 7:57 ` [PATCH 26/26] imx8mq_evk: Applying default LPDDR4 script for B2 Peng Fan
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:57 UTC (permalink / raw)
To: u-boot
From: Ye Li <ye.li@nxp.com>
i.MX8MQ B2 is using same value in OCOTP_READ_FUSE_DATA like B1, so
we have to check the ROM verision to distinguish the revision.
As we have checked the B1 rev for sticky bits work around in
secure boot. So it won't apply on B2.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx/cpu.h | 1 +
arch/arm/mach-imx/imx8m/soc.c | 11 ++++++++++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 28244d7671..ef090eb2f2 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -65,6 +65,7 @@
#define CHIP_REV_1_5 0x15
#define CHIP_REV_2_0 0x20
#define CHIP_REV_2_1 0x21
+#define CHIP_REV_2_2 0x22
#define CHIP_REV_2_5 0x25
#define CHIP_REV_3_0 0x30
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index c447ea2ab9..573cacb10d 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -410,7 +410,16 @@ u32 get_cpu_rev(void)
* 0xff0055aa is magic number for B1.
*/
if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
- reg = CHIP_REV_2_1;
+ /*
+ * B2 uses same DIGPROG and OCOTP_READ_FUSE_DATA value with B1,
+ * so have to check ROM to distinguish them
+ */
+ rom_version = readl((void __iomem *)ROM_VERSION_B0);
+ rom_version &= 0xff;
+ if (rom_version == CHIP_REV_2_2)
+ reg = CHIP_REV_2_2;
+ else
+ reg = CHIP_REV_2_1;
} else {
rom_version =
readl((void __iomem *)ROM_VERSION_A0);
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 25/26] misc: ocotp: Update OCOTP driver for iMX8MQ B2
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (23 preceding siblings ...)
2021-03-19 7:57 ` [PATCH 24/26] iMX8MQ: Recognize the B2 revision Peng Fan
@ 2021-03-19 7:57 ` Peng Fan
2021-03-19 7:57 ` [PATCH 26/26] imx8mq_evk: Applying default LPDDR4 script for B2 Peng Fan
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:57 UTC (permalink / raw)
To: u-boot
From: Ye Li <ye.li@nxp.com>
i.MX8MQ B2 also has fixed value in OCOTP_READ_FUSE_DATA register,
so it does not support "fuse sense" command like B1.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/misc/mxc_ocotp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 926c62c8a1..b1893a5c7e 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -335,7 +335,7 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
struct ocotp_regs *regs;
int ret;
- if (is_imx8mq() && is_soc_rev(CHIP_REV_2_1)) {
+ if (is_imx8mq() && (soc_rev() >= CHIP_REV_2_1)) {
printf("mxc_ocotp %s(): fuse sense is disabled\n", __func__);
return -EPERM;
}
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 26/26] imx8mq_evk: Applying default LPDDR4 script for B2
2021-03-19 7:56 [PATCH 00/26] imx: update for i.MX8M Peng Fan
` (24 preceding siblings ...)
2021-03-19 7:57 ` [PATCH 25/26] misc: ocotp: Update OCOTP driver for iMX8MQ B2 Peng Fan
@ 2021-03-19 7:57 ` Peng Fan
25 siblings, 0 replies; 42+ messages in thread
From: Peng Fan @ 2021-03-19 7:57 UTC (permalink / raw)
To: u-boot
From: Ye Li <ye.li@nxp.com>
Both i.MX8MQ B1 and B2 should use default LPDDR4 script, while B0
has another dedicated script.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
board/freescale/imx8mq_evk/spl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c
index 82753585f2..e8e0efe485 100644
--- a/board/freescale/imx8mq_evk/spl.c
+++ b/board/freescale/imx8mq_evk/spl.c
@@ -36,7 +36,7 @@ extern struct dram_timing_info dram_timing_b0;
static void spl_dram_init(void)
{
/* ddr init */
- if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
+ if (soc_rev() >= CHIP_REV_2_1)
ddr_init(&dram_timing);
else
ddr_init(&dram_timing_b0);
--
2.30.0
^ permalink raw reply related [flat|nested] 42+ messages in thread