[PATCH v2 0/4] add devicetree for Forlinx FETA40i-C & OKA40i-C

[PATCH v2 0/4] add devicetree for Forlinx FETA40i-C & OKA40i-C

[Ivan Uvarov]

This patch series adds devicetree support for the Forlinx FETA40i-C SoM
and OKA40i-C carrier board/devboard.

The FETA40i-C is an "industrial/automotive" SoM by Forlinx.

SoM specs:
- SoC: R40 or A40i
- PMIC: AXP221S
- RAM: 1GiB/2GiB DDR3 (dual-rank)
- eMMC: 8GB,
- Mates with carrier board via four 80-pin connectors (AXK6F80337YG).

OKA40i-C is a carrier board by the same manufacturer for this SoM,
whose main purpose is as a development board with a variety of
peripherals:

- Power: DC5V barrel or USB OTG or 4.2V Lipo battery
- Video out: HDMI, TV out, LVDS
- WiFi+Bluetooth: RL-UM02WBS-8723BU-V1.2 (802.11 b/g/n, BT V2.1/3.0/4.0)
- Ethernet: 10/100Mbps
- Storage: µSD, fullsize SD, eMMC (on SoM), SATA
- USB: 3 x USB2.0 Host (2 via hub, 1 native), 1 x USB2.0 OTG (micro-B)
- UART: RS232, RS485, 4 3.3v uarts (of which 2 have RTS/CTS)
- Other I/O: SPI x2, TWI, SDIO header, GPIO header, JTAG header
- Mini PCIe slot with sim holder for WLAN modem
- Smart card holder
- RTC (RX8010SJ)
- Two user LEDs
- Three user buttons (via KeyADC).

Of the board features listed above, support for the following has *NOT*
been tested:
- TV out & LVDS
- SATA
- Smart cards
- KeyADC buttons (no support)

The series consists of four patches, the first three of which are mutually
independent (although patch 2 may not apply without patch 1).
The last patch depends on patches 2 and 3.

Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com>
---

Changelog:

v1 -> v2:

* split patch into series
  * edits to sun8i-r40.dtsi are now in separate patch
* add dt bindings for compatible strings (in separate patch)
* add /omit-if-no-ref/ to the new uart pin nodes
  * preliminary patch adds the keyword to existing nodes for UART0 & UART3
* whitespace fixes as suggested by checkpatch.pl


draft2 -> v1: 

* fix indentation from spaces to tabs;
* remove commented properties and other extraneous comments;
* enable uarts 2,4,5&7 and alias uart3;
* update the user-LED bindings;
* remove mmc1 & add mmc3 binding;
* bring together the max/min microvolts on three regulators;
    * The reported 2.5v value in ALDO2 comes from U-Boot, where apparently
      this is the KConfig default for this regulator. The correct voltage
      is 1.8v.
* remove extraneous `always-on`s from regulators dldo1 and eldo2/3;
* remove reg_dldo3 node entirely.



Ivan Uvarov (4):
  ARM: dts: sun8i: r40: add /omit-if-no-ref/ to pinmux nodes for UARTs 0&3
  ARM: dts: sun8i: r40: add pinmux settings for MMC3 and UARTs 2,4,5&7
  dt-bindings: arm: add compatible strings for Forlinx OKA40i-C
  ARM: dts: sun8i: r40: add devicetree for Forlinx FETA40i-C & OKA40i-C

 .../devicetree/bindings/arm/sunxi.yaml        |   5 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 arch/arm/boot/dts/Makefile                    |   1 +
 arch/arm/boot/dts/sun8i-r40-feta40i.dtsi      |  66 +++++
 arch/arm/boot/dts/sun8i-r40-oka40i-c.dts      | 243 ++++++++++++++++++
 arch/arm/boot/dts/sun8i-r40.dtsi              |  43 ++++
 6 files changed, 360 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-r40-feta40i.dtsi
 create mode 100644 arch/arm/boot/dts/sun8i-r40-oka40i-c.dts

-- 
2.25.1

[PATCH v2 0/4] add devicetree for Forlinx FETA40i-C & OKA40i-C

[Ivan Uvarov]

This patch series adds devicetree support for the Forlinx FETA40i-C SoM
and OKA40i-C carrier board/devboard.

The FETA40i-C is an "industrial/automotive" SoM by Forlinx.

SoM specs:
- SoC: R40 or A40i
- PMIC: AXP221S
- RAM: 1GiB/2GiB DDR3 (dual-rank)
- eMMC: 8GB,
- Mates with carrier board via four 80-pin connectors (AXK6F80337YG).

OKA40i-C is a carrier board by the same manufacturer for this SoM,
whose main purpose is as a development board with a variety of
peripherals:

- Power: DC5V barrel or USB OTG or 4.2V Lipo battery
- Video out: HDMI, TV out, LVDS
- WiFi+Bluetooth: RL-UM02WBS-8723BU-V1.2 (802.11 b/g/n, BT V2.1/3.0/4.0)
- Ethernet: 10/100Mbps
- Storage: µSD, fullsize SD, eMMC (on SoM), SATA
- USB: 3 x USB2.0 Host (2 via hub, 1 native), 1 x USB2.0 OTG (micro-B)
- UART: RS232, RS485, 4 3.3v uarts (of which 2 have RTS/CTS)
- Other I/O: SPI x2, TWI, SDIO header, GPIO header, JTAG header
- Mini PCIe slot with sim holder for WLAN modem
- Smart card holder
- RTC (RX8010SJ)
- Two user LEDs
- Three user buttons (via KeyADC).

Of the board features listed above, support for the following has *NOT*
been tested:
- TV out & LVDS
- SATA
- Smart cards
- KeyADC buttons (no support)

The series consists of four patches, the first three of which are mutually
independent (although patch 2 may not apply without patch 1).
The last patch depends on patches 2 and 3.

Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com>
---

Changelog:

v1 -> v2:

* split patch into series
  * edits to sun8i-r40.dtsi are now in separate patch
* add dt bindings for compatible strings (in separate patch)
* add /omit-if-no-ref/ to the new uart pin nodes
  * preliminary patch adds the keyword to existing nodes for UART0 & UART3
* whitespace fixes as suggested by checkpatch.pl


draft2 -> v1: 

* fix indentation from spaces to tabs;
* remove commented properties and other extraneous comments;
* enable uarts 2,4,5&7 and alias uart3;
* update the user-LED bindings;
* remove mmc1 & add mmc3 binding;
* bring together the max/min microvolts on three regulators;
    * The reported 2.5v value in ALDO2 comes from U-Boot, where apparently
      this is the KConfig default for this regulator. The correct voltage
      is 1.8v.
* remove extraneous `always-on`s from regulators dldo1 and eldo2/3;
* remove reg_dldo3 node entirely.



Ivan Uvarov (4):
  ARM: dts: sun8i: r40: add /omit-if-no-ref/ to pinmux nodes for UARTs 0&3
  ARM: dts: sun8i: r40: add pinmux settings for MMC3 and UARTs 2,4,5&7
  dt-bindings: arm: add compatible strings for Forlinx OKA40i-C
  ARM: dts: sun8i: r40: add devicetree for Forlinx FETA40i-C & OKA40i-C

 .../devicetree/bindings/arm/sunxi.yaml        |   5 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 arch/arm/boot/dts/Makefile                    |   1 +
 arch/arm/boot/dts/sun8i-r40-feta40i.dtsi      |  66 +++++
 arch/arm/boot/dts/sun8i-r40-oka40i-c.dts      | 243 ++++++++++++++++++
 arch/arm/boot/dts/sun8i-r40.dtsi              |  43 ++++
 6 files changed, 360 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-r40-feta40i.dtsi
 create mode 100644 arch/arm/boot/dts/sun8i-r40-oka40i-c.dts

-- 
2.25.1


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[PATCH v2 1/4] ARM: dts: sun8i: r40: add /omit-if-no-ref/ to pinmux nodes for UARTs 0&3

[Ivan Uvarov]

This patch adds the /omit-if-no-ref/ keyword to the pio nodes for
UART0 and UART3 pins of the R40 SoC, which would reduce the fdt size on
boards which do not use these UARTs.

Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com>

 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index d5ad3b9efd..0b257a0779 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -631,16 +631,19 @@ spi1_cs1_pi_pin: spi1-cs1-pi-pin {
 				function = "spi1";
 			};
 
+			/omit-if-no-ref/
 			uart0_pb_pins: uart0-pb-pins {
 				pins = "PB22", "PB23";
 				function = "uart0";
 			};
 
+			/omit-if-no-ref/
 			uart3_pg_pins: uart3-pg-pins {
 				pins = "PG6", "PG7";
 				function = "uart3";
 			};
 
+			/omit-if-no-ref/
 			uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
 				pins = "PG8", "PG9";
 				function = "uart3";
-- 
2.25.1

[PATCH v2 1/4] ARM: dts: sun8i: r40: add /omit-if-no-ref/ to pinmux nodes for UARTs 0&3

[Ivan Uvarov]

This patch adds the /omit-if-no-ref/ keyword to the pio nodes for
UART0 and UART3 pins of the R40 SoC, which would reduce the fdt size on
boards which do not use these UARTs.

Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com>

 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index d5ad3b9efd..0b257a0779 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -631,16 +631,19 @@ spi1_cs1_pi_pin: spi1-cs1-pi-pin {
 				function = "spi1";
 			};
 
+			/omit-if-no-ref/
 			uart0_pb_pins: uart0-pb-pins {
 				pins = "PB22", "PB23";
 				function = "uart0";
 			};
 
+			/omit-if-no-ref/
 			uart3_pg_pins: uart3-pg-pins {
 				pins = "PG6", "PG7";
 				function = "uart3";
 			};
 
+			/omit-if-no-ref/
 			uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
 				pins = "PG8", "PG9";
 				function = "uart3";
-- 
2.25.1


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[PATCH v2 2/4] ARM: dts: sun8i: r40: add pinmux settings for MMC3 and UARTs 2,4,5&7

[Ivan Uvarov]

The Forlinx OKA40i-C devboard makes use of UARTs 0,2,3,4,5 and 7 of the R40
SoC, of which UART 0 is connected to an RS232 converter, UART 5 routed to
an RS485 converter, and the rest broken out directly via labeled headers.
The board also contains a micro-SD slot connected to SDC3.

This patch adds settings to R40's pinmux node for those UARTs that were not
already mapped, which would allow us to make use of all available UARTs and
the micro-SD slot on this board in a further patch.

Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com>

 1 file changed, 40 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 0b257a0779..51031a0e59 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -357,6 +357,8 @@ mmc3: mmc@1c12000 {
 			clock-names = "ahb", "mmc";
 			resets = <&ccu RST_BUS_MMC3>;
 			reset-names = "ahb";
+			pinctrl-0 = <&mmc3_pins>;
+			pinctrl-names = "default";
 			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 			#address-cells = <1>;
@@ -601,6 +603,14 @@ mmc2_pins: mmc2-pins {
 				bias-pull-up;
 			};
 
+			mmc3_pins: mmc3-pins {
+				pins = "PI4", "PI5", "PI6",
+				       "PI7", "PI8", "PI9";
+				function = "mmc3";
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
 			/omit-if-no-ref/
 			spi0_pc_pins: spi0-pc-pins {
 				pins = "PC0", "PC1", "PC2";
@@ -637,6 +647,18 @@ uart0_pb_pins: uart0-pb-pins {
 				function = "uart0";
 			};
 
+			/omit-if-no-ref/
+			uart2_pi_pins: uart2-pi-pins {
+				pins = "PI18", "PI19";
+				function = "uart2";
+			};
+
+			/omit-if-no-ref/
+			uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{
+				pins = "PI16", "PI17";
+				function = "uart2";
+			};
+
 			/omit-if-no-ref/
 			uart3_pg_pins: uart3-pg-pins {
 				pins = "PG6", "PG7";
@@ -648,6 +670,24 @@ uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
 				pins = "PG8", "PG9";
 				function = "uart3";
 			};
+
+			/omit-if-no-ref/
+			uart4_pg_pins: uart4-pg-pins {
+				pins = "PG10", "PG11";
+				function = "uart4";
+			};
+
+			/omit-if-no-ref/
+			uart5_ph_pins: uart5-ph-pins {
+				pins = "PH6", "PH7";
+				function = "uart5";
+			};
+
+			/omit-if-no-ref/
+			uart7_pi_pins: uart7-pi-pins {
+				pins = "PI20", "PI21";
+				function = "uart7";
+			};
 		};
 
 		wdt: watchdog@1c20c90 {
-- 
2.25.1

[PATCH v2 2/4] ARM: dts: sun8i: r40: add pinmux settings for MMC3 and UARTs 2, 4, 5&7

[Ivan Uvarov]

The Forlinx OKA40i-C devboard makes use of UARTs 0,2,3,4,5 and 7 of the R40
SoC, of which UART 0 is connected to an RS232 converter, UART 5 routed to
an RS485 converter, and the rest broken out directly via labeled headers.
The board also contains a micro-SD slot connected to SDC3.

This patch adds settings to R40's pinmux node for those UARTs that were not
already mapped, which would allow us to make use of all available UARTs and
the micro-SD slot on this board in a further patch.

Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com>

 1 file changed, 40 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 0b257a0779..51031a0e59 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -357,6 +357,8 @@ mmc3: mmc@1c12000 {
 			clock-names = "ahb", "mmc";
 			resets = <&ccu RST_BUS_MMC3>;
 			reset-names = "ahb";
+			pinctrl-0 = <&mmc3_pins>;
+			pinctrl-names = "default";
 			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 			#address-cells = <1>;
@@ -601,6 +603,14 @@ mmc2_pins: mmc2-pins {
 				bias-pull-up;
 			};
 
+			mmc3_pins: mmc3-pins {
+				pins = "PI4", "PI5", "PI6",
+				       "PI7", "PI8", "PI9";
+				function = "mmc3";
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
 			/omit-if-no-ref/
 			spi0_pc_pins: spi0-pc-pins {
 				pins = "PC0", "PC1", "PC2";
@@ -637,6 +647,18 @@ uart0_pb_pins: uart0-pb-pins {
 				function = "uart0";
 			};
 
+			/omit-if-no-ref/
+			uart2_pi_pins: uart2-pi-pins {
+				pins = "PI18", "PI19";
+				function = "uart2";
+			};
+
+			/omit-if-no-ref/
+			uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{
+				pins = "PI16", "PI17";
+				function = "uart2";
+			};
+
 			/omit-if-no-ref/
 			uart3_pg_pins: uart3-pg-pins {
 				pins = "PG6", "PG7";
@@ -648,6 +670,24 @@ uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
 				pins = "PG8", "PG9";
 				function = "uart3";
 			};
+
+			/omit-if-no-ref/
+			uart4_pg_pins: uart4-pg-pins {
+				pins = "PG10", "PG11";
+				function = "uart4";
+			};
+
+			/omit-if-no-ref/
+			uart5_ph_pins: uart5-ph-pins {
+				pins = "PH6", "PH7";
+				function = "uart5";
+			};
+
+			/omit-if-no-ref/
+			uart7_pi_pins: uart7-pi-pins {
+				pins = "PI20", "PI21";
+				function = "uart7";
+			};
 		};
 
 		wdt: watchdog@1c20c90 {
-- 
2.25.1


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[PATCH v2 3/4] dt-bindings: arm: add compatible strings for Forlinx OKA40i-C

[Ivan Uvarov]

The OKA40i-C is a carrier/development board for the Forlinx FETA40i-C SoM
based on the Allwinner R40/A40i SoC.

This patch adds the relevant dt-binding documentation in preparation for
the next patch, which adds a devicetree for the SoM and board.

Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com>

 2 files changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
index 08607c7ec1..096405aedc 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.yaml
+++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
@@ -224,6 +224,11 @@ properties:
           - const: empire-electronix,m712
           - const: allwinner,sun5i-a13
 
+      - description: Forlinx OKA40i-C Development board
+        items:
+          - const: forlinx,oka40i-c
+          - const: allwinner,sun8i-r40
+
       - description: FriendlyARM NanoPi A64
         items:
           - const: friendlyarm,nanopi-a64
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index f6064d84a4..e2ea1a731e 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -403,6 +403,8 @@ patternProperties:
     description: Firefly
   "^focaltech,.*":
     description: FocalTech Systems Co.,Ltd
+  "^forlinx,.*":
+    description: Baoding Forlinx Embedded Technology Co., Ltd.
   "^frida,.*":
     description: Shenzhen Frida LCD Co., Ltd.
   "^friendlyarm,.*":
-- 
2.25.1

[PATCH v2 3/4] dt-bindings: arm: add compatible strings for Forlinx OKA40i-C

[Ivan Uvarov]

The OKA40i-C is a carrier/development board for the Forlinx FETA40i-C SoM
based on the Allwinner R40/A40i SoC.

This patch adds the relevant dt-binding documentation in preparation for
the next patch, which adds a devicetree for the SoM and board.

Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com>

 2 files changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
index 08607c7ec1..096405aedc 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.yaml
+++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
@@ -224,6 +224,11 @@ properties:
           - const: empire-electronix,m712
           - const: allwinner,sun5i-a13
 
+      - description: Forlinx OKA40i-C Development board
+        items:
+          - const: forlinx,oka40i-c
+          - const: allwinner,sun8i-r40
+
       - description: FriendlyARM NanoPi A64
         items:
           - const: friendlyarm,nanopi-a64
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index f6064d84a4..e2ea1a731e 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -403,6 +403,8 @@ patternProperties:
     description: Firefly
   "^focaltech,.*":
     description: FocalTech Systems Co.,Ltd
+  "^forlinx,.*":
+    description: Baoding Forlinx Embedded Technology Co., Ltd.
   "^frida,.*":
     description: Shenzhen Frida LCD Co., Ltd.
   "^friendlyarm,.*":
-- 
2.25.1


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[PATCH v2 4/4] ARM: dts: sun8i: r40: add devicetree for Forlinx FETA40i-C & OKA40i-C

[Ivan Uvarov]

The FETA40i-C is a SoM by Forlinx based on the Allwinner R40/A40i.

SoM specifications:

- SoC: R40 or A40i
- PMIC: AXP221S
- RAM: 1GiB/2GiB DDR3 (dual-rank)
- eMMC: 8GB,
- Mates with carrier board via four 80-pin connectors (AXK6F80337YG).

OKA40i-C is a carrier board by the same manufacturer for this SoM,
whose main purpose is as a development board with a wide variety of
peripherals:

- Power: DC5V barrel or USB OTG or 4.2V Lipo battery
- Video out: HDMI, TV out, LVDS
- WiFi+Bluetooth: RL-UM02WBS-8723BU-V1.2 (802.11 b/g/n, BT V2.1/3.0/4.0)
- Ethernet: 10/100Mbps
- Storage: µSD, fullsize SD, eMMC (on SoM), SATA
- USB: 3 x USB2.0 Host (2 via hub, 1 native), 1 x USB2.0 OTG (micro-B)
- UART: RS232, RS485, 4 3.3v uarts (of which 2 have RTS/CTS)
- Other I/O: SPI x2, TWI, SDIO header, GPIO header, JTAG header
- Mini PCIe slot with sim holder for WLAN modem
- Smart card holder
- RTC (RX8010SJ)
- Two user LEDs
- Three user buttons (via KeyADC).

This patch adds a devicetree for the aforementioned SoM and devboard.
In order to reflect the modularity of this devboard and simplify adding
support for future hardware based on the same SoM, the devicetree is split:
Everything pertaining to the SoM itself is described in a separate .dtsi
file, which is included by the devboard's .dts.

Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com>

 3 files changed, 310 insertions(+)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8e5d4ab4e7..88aae9de95 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1222,6 +1222,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
 	sun8i-r16-nintendo-super-nes-classic.dtb \
 	sun8i-r16-parrot.dtb \
 	sun8i-r40-bananapi-m2-ultra.dtb \
+	sun8i-r40-oka40i-c.dtb \
 	sun8i-s3-elimo-initium.dtb \
 	sun8i-s3-lichee-zero-plus.dtb \
 	sun8i-s3-pinecube.dtb \
diff --git a/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi
new file mode 100644
index 0000000000..d3cc6f974f
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com>
+// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is:
+//  Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+//  Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+
+#include "sun8i-r40.dtsi"
+
+&i2c0 {
+	status = "okay";
+
+	axp22x: pmic@34 {
+		compatible = "x-powers,axp221";
+		reg = <0x34>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+#include "axp22x.dtsi"
+
+&mmc2 {
+	vmmc-supply = <&reg_dcdc1>;
+	vqmmc-supply = <&reg_aldo2>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&pio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&clk_out_a_pin>;
+	vcc-pa-supply = <&reg_dcdc1>;
+	vcc-pc-supply = <&reg_aldo2>;
+	vcc-pd-supply = <&reg_dcdc1>;
+	vcc-pf-supply = <&reg_dldo4>;
+	vcc-pg-supply = <&reg_dldo1>;
+};
+
+&reg_aldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-name = "vcc-pa";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-3v3";
+};
+
+&reg_dldo1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi-io";
+};
+
+&reg_dldo4 {
+	regulator-always-on;
+	regulator-min-microvolt = <2500000>;
+	regulator-max-microvolt = <2500000>;
+	regulator-name = "vdd2v5-sata";
+};
diff --git a/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts b/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts
new file mode 100644
index 0000000000..133991d7b3
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts
@@ -0,0 +1,243 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com>
+// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is:
+//	Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+//	Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+
+/dts-v1/;
+#include "sun8i-r40-feta40i.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "Forlinx OKA40i-C";
+	compatible = "forlinx,oka40i-c", "allwinner,sun8i-r40";
+
+	aliases {
+		ethernet0 = &gmac;
+		serial0 = &uart0;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5; /* RS485 */
+		serial7 = &uart7;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-5 {
+			gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_STATUS;
+		};
+
+		led-6 {
+			gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_STATUS;
+		};
+	};
+
+	reg_vcc5v0: vcc5v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	wifi_pwrseq: wifi_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; // PB10 WIFI_EN
+		clocks = <&ccu CLK_OUTA>;
+		clock-names = "ext_clock";
+	};
+};
+
+&ahci {
+	ahci-supply = <&reg_dldo4>;
+	phy-supply = <&reg_eldo2>;
+	status = "okay";
+};
+
+&de {
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&ehci2 {
+	status = "okay";
+};
+
+&gmac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac_rgmii_pins>;
+	phy-handle = <&phy1>;
+	phy-mode = "rgmii-id";
+	phy-supply = <&reg_dcdc1>;
+	status = "okay";
+};
+
+&gmac_mdio {
+	phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+	};
+};
+
+&hdmi {
+	status = "okay";
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&mmc0 {
+	vmmc-supply = <&reg_dcdc1>;
+	vqmmc-supply = <&reg_dcdc1>;
+	bus-width = <4>;
+	cd-gpios = <&pio 8 11 GPIO_ACTIVE_LOW>; // PI11
+	status = "okay";
+};
+
+&mmc3 {
+	vmmc-supply = <&reg_dcdc1>;
+	vqmmc-supply = <&reg_dcdc1>;
+	bus-width = <4>;
+	cd-gpios = <&pio 8 10 GPIO_ACTIVE_LOW>; // PI10
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&ohci2 {
+	status = "okay";
+};
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "avcc";
+};
+
+&reg_dc1sw {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-lcd";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1100000>;
+	regulator-max-microvolt = <1100000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <1100000>;
+	regulator-max-microvolt = <1100000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1500000>;
+	regulator-max-microvolt = <1500000>;
+	regulator-name = "vcc-dram";
+};
+
+&reg_dldo2 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi";
+};
+
+&reg_eldo2 {
+	regulator-min-microvolt = <1200000>;
+	regulator-max-microvolt = <1200000>;
+	regulator-name = "vdd1v2-sata";
+};
+
+&reg_eldo3 {
+	regulator-min-microvolt = <2800000>;
+	regulator-max-microvolt = <2800000>;
+	regulator-name = "vcc-pe";
+};
+
+&tcon_tv0 {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pb_pins>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pi_pins>, <&uart2_rts_cts_pi_pins>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart4_pg_pins>;
+	status = "okay";
+};
+
+&uart5 { /* RS485 */
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart5_ph_pins>;
+	status = "okay";
+};
+
+&uart7 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart7_pi_pins>;
+	status = "okay";
+};
+
+&usbphy {
+	usb1_vbus-supply = <&reg_vcc5v0>;
+	usb2_vbus-supply = <&reg_vcc5v0>;
+	status = "okay";
+};
-- 
2.25.1

[PATCH v2 4/4] ARM: dts: sun8i: r40: add devicetree for Forlinx FETA40i-C & OKA40i-C

[Ivan Uvarov]

The FETA40i-C is a SoM by Forlinx based on the Allwinner R40/A40i.

SoM specifications:

- SoC: R40 or A40i
- PMIC: AXP221S
- RAM: 1GiB/2GiB DDR3 (dual-rank)
- eMMC: 8GB,
- Mates with carrier board via four 80-pin connectors (AXK6F80337YG).

OKA40i-C is a carrier board by the same manufacturer for this SoM,
whose main purpose is as a development board with a wide variety of
peripherals:

- Power: DC5V barrel or USB OTG or 4.2V Lipo battery
- Video out: HDMI, TV out, LVDS
- WiFi+Bluetooth: RL-UM02WBS-8723BU-V1.2 (802.11 b/g/n, BT V2.1/3.0/4.0)
- Ethernet: 10/100Mbps
- Storage: µSD, fullsize SD, eMMC (on SoM), SATA
- USB: 3 x USB2.0 Host (2 via hub, 1 native), 1 x USB2.0 OTG (micro-B)
- UART: RS232, RS485, 4 3.3v uarts (of which 2 have RTS/CTS)
- Other I/O: SPI x2, TWI, SDIO header, GPIO header, JTAG header
- Mini PCIe slot with sim holder for WLAN modem
- Smart card holder
- RTC (RX8010SJ)
- Two user LEDs
- Three user buttons (via KeyADC).

This patch adds a devicetree for the aforementioned SoM and devboard.
In order to reflect the modularity of this devboard and simplify adding
support for future hardware based on the same SoM, the devicetree is split:
Everything pertaining to the SoM itself is described in a separate .dtsi
file, which is included by the devboard's .dts.

Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com>

 3 files changed, 310 insertions(+)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8e5d4ab4e7..88aae9de95 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1222,6 +1222,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
 	sun8i-r16-nintendo-super-nes-classic.dtb \
 	sun8i-r16-parrot.dtb \
 	sun8i-r40-bananapi-m2-ultra.dtb \
+	sun8i-r40-oka40i-c.dtb \
 	sun8i-s3-elimo-initium.dtb \
 	sun8i-s3-lichee-zero-plus.dtb \
 	sun8i-s3-pinecube.dtb \
diff --git a/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi
new file mode 100644
index 0000000000..d3cc6f974f
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com>
+// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is:
+//  Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+//  Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+
+#include "sun8i-r40.dtsi"
+
+&i2c0 {
+	status = "okay";
+
+	axp22x: pmic@34 {
+		compatible = "x-powers,axp221";
+		reg = <0x34>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+#include "axp22x.dtsi"
+
+&mmc2 {
+	vmmc-supply = <&reg_dcdc1>;
+	vqmmc-supply = <&reg_aldo2>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&pio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&clk_out_a_pin>;
+	vcc-pa-supply = <&reg_dcdc1>;
+	vcc-pc-supply = <&reg_aldo2>;
+	vcc-pd-supply = <&reg_dcdc1>;
+	vcc-pf-supply = <&reg_dldo4>;
+	vcc-pg-supply = <&reg_dldo1>;
+};
+
+&reg_aldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-name = "vcc-pa";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-3v3";
+};
+
+&reg_dldo1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi-io";
+};
+
+&reg_dldo4 {
+	regulator-always-on;
+	regulator-min-microvolt = <2500000>;
+	regulator-max-microvolt = <2500000>;
+	regulator-name = "vdd2v5-sata";
+};
diff --git a/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts b/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts
new file mode 100644
index 0000000000..133991d7b3
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts
@@ -0,0 +1,243 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com>
+// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is:
+//	Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+//	Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+
+/dts-v1/;
+#include "sun8i-r40-feta40i.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "Forlinx OKA40i-C";
+	compatible = "forlinx,oka40i-c", "allwinner,sun8i-r40";
+
+	aliases {
+		ethernet0 = &gmac;
+		serial0 = &uart0;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5; /* RS485 */
+		serial7 = &uart7;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-5 {
+			gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_STATUS;
+		};
+
+		led-6 {
+			gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_STATUS;
+		};
+	};
+
+	reg_vcc5v0: vcc5v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	wifi_pwrseq: wifi_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; // PB10 WIFI_EN
+		clocks = <&ccu CLK_OUTA>;
+		clock-names = "ext_clock";
+	};
+};
+
+&ahci {
+	ahci-supply = <&reg_dldo4>;
+	phy-supply = <&reg_eldo2>;
+	status = "okay";
+};
+
+&de {
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&ehci2 {
+	status = "okay";
+};
+
+&gmac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac_rgmii_pins>;
+	phy-handle = <&phy1>;
+	phy-mode = "rgmii-id";
+	phy-supply = <&reg_dcdc1>;
+	status = "okay";
+};
+
+&gmac_mdio {
+	phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+	};
+};
+
+&hdmi {
+	status = "okay";
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&mmc0 {
+	vmmc-supply = <&reg_dcdc1>;
+	vqmmc-supply = <&reg_dcdc1>;
+	bus-width = <4>;
+	cd-gpios = <&pio 8 11 GPIO_ACTIVE_LOW>; // PI11
+	status = "okay";
+};
+
+&mmc3 {
+	vmmc-supply = <&reg_dcdc1>;
+	vqmmc-supply = <&reg_dcdc1>;
+	bus-width = <4>;
+	cd-gpios = <&pio 8 10 GPIO_ACTIVE_LOW>; // PI10
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&ohci2 {
+	status = "okay";
+};
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "avcc";
+};
+
+&reg_dc1sw {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-lcd";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1100000>;
+	regulator-max-microvolt = <1100000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <1100000>;
+	regulator-max-microvolt = <1100000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1500000>;
+	regulator-max-microvolt = <1500000>;
+	regulator-name = "vcc-dram";
+};
+
+&reg_dldo2 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi";
+};
+
+&reg_eldo2 {
+	regulator-min-microvolt = <1200000>;
+	regulator-max-microvolt = <1200000>;
+	regulator-name = "vdd1v2-sata";
+};
+
+&reg_eldo3 {
+	regulator-min-microvolt = <2800000>;
+	regulator-max-microvolt = <2800000>;
+	regulator-name = "vcc-pe";
+};
+
+&tcon_tv0 {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pb_pins>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pi_pins>, <&uart2_rts_cts_pi_pins>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart4_pg_pins>;
+	status = "okay";
+};
+
+&uart5 { /* RS485 */
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart5_ph_pins>;
+	status = "okay";
+};
+
+&uart7 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart7_pi_pins>;
+	status = "okay";
+};
+
+&usbphy {
+	usb1_vbus-supply = <&reg_vcc5v0>;
+	usb2_vbus-supply = <&reg_vcc5v0>;
+	status = "okay";
+};
-- 
2.25.1


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Re: [PATCH v2 1/4] ARM: dts: sun8i: r40: add /omit-if-no-ref/ to pinmux nodes for UARTs 0&3

[Andre Przywara]

On Mon, 22 Mar 2021 13:55:35 +0300
Ivan Uvarov <i.uvarov@cognitivepilot.com> wrote:

Hi,

> This patch adds the /omit-if-no-ref/ keyword to the pio nodes for
> UART0 and UART3 pins of the R40 SoC, which would reduce the fdt size on
> boards which do not use these UARTs.

But what boards are those? It seems like all boards use uart3-pg and
the two existing boards use UART0.

I think the idea is to use omit-if-no-ref on some rarely used nodes, so
if there is only a single user, for instance. Your next patch is a good
example.

So I don't think this patch here is needed at all.

Cheers,
Andre

> 
> Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com>
> 
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
> index d5ad3b9efd..0b257a0779 100644
> --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -631,16 +631,19 @@ spi1_cs1_pi_pin: spi1-cs1-pi-pin {
>  				function = "spi1";
>  			};
>  
> +			/omit-if-no-ref/
>  			uart0_pb_pins: uart0-pb-pins {
>  				pins = "PB22", "PB23";
>  				function = "uart0";
>  			};
>  
> +			/omit-if-no-ref/
>  			uart3_pg_pins: uart3-pg-pins {
>  				pins = "PG6", "PG7";
>  				function = "uart3";
>  			};
>  
> +			/omit-if-no-ref/
>  			uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
>  				pins = "PG8", "PG9";
>  				function = "uart3";

Re: [PATCH v2 1/4] ARM: dts: sun8i: r40: add /omit-if-no-ref/ to pinmux nodes for UARTs 0&3

[Andre Przywara]

On Mon, 22 Mar 2021 13:55:35 +0300
Ivan Uvarov <i.uvarov@cognitivepilot.com> wrote:

Hi,

> This patch adds the /omit-if-no-ref/ keyword to the pio nodes for
> UART0 and UART3 pins of the R40 SoC, which would reduce the fdt size on
> boards which do not use these UARTs.

But what boards are those? It seems like all boards use uart3-pg and
the two existing boards use UART0.

I think the idea is to use omit-if-no-ref on some rarely used nodes, so
if there is only a single user, for instance. Your next patch is a good
example.

So I don't think this patch here is needed at all.

Cheers,
Andre

> 
> Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com>
> 
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
> index d5ad3b9efd..0b257a0779 100644
> --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -631,16 +631,19 @@ spi1_cs1_pi_pin: spi1-cs1-pi-pin {
>  				function = "spi1";
>  			};
>  
> +			/omit-if-no-ref/
>  			uart0_pb_pins: uart0-pb-pins {
>  				pins = "PB22", "PB23";
>  				function = "uart0";
>  			};
>  
> +			/omit-if-no-ref/
>  			uart3_pg_pins: uart3-pg-pins {
>  				pins = "PG6", "PG7";
>  				function = "uart3";
>  			};
>  
> +			/omit-if-no-ref/
>  			uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
>  				pins = "PG8", "PG9";
>  				function = "uart3";


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Re: [PATCH v2 2/4] ARM: dts: sun8i: r40: add pinmux settings for MMC3 and UARTs 2,4,5&7

[Andre Przywara]

On Mon, 22 Mar 2021 13:55:36 +0300
Ivan Uvarov <i.uvarov@cognitivepilot.com> wrote:

Hi,

> The Forlinx OKA40i-C devboard makes use of UARTs 0,2,3,4,5 and 7 of the R40
> SoC, of which UART 0 is connected to an RS232 converter, UART 5 routed to
> an RS485 converter, and the rest broken out directly via labeled headers.
> The board also contains a micro-SD slot connected to SDC3.
> 
> This patch adds settings to R40's pinmux node for those UARTs that were not
> already mapped, which would allow us to make use of all available UARTs and
> the micro-SD slot on this board in a further patch.
> 
> Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com>

Looks alright, compared against the R40 manual.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> 
>  1 file changed, 40 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
> index 0b257a0779..51031a0e59 100644
> --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -357,6 +357,8 @@ mmc3: mmc@1c12000 {
>  			clock-names = "ahb", "mmc";
>  			resets = <&ccu RST_BUS_MMC3>;
>  			reset-names = "ahb";
> +			pinctrl-0 = <&mmc3_pins>;
> +			pinctrl-names = "default";
>  			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
>  			status = "disabled";
>  			#address-cells = <1>;
> @@ -601,6 +603,14 @@ mmc2_pins: mmc2-pins {
>  				bias-pull-up;
>  			};
>  
> +			mmc3_pins: mmc3-pins {
> +				pins = "PI4", "PI5", "PI6",
> +				       "PI7", "PI8", "PI9";
> +				function = "mmc3";
> +				drive-strength = <30>;
> +				bias-pull-up;
> +			};
> +
>  			/omit-if-no-ref/
>  			spi0_pc_pins: spi0-pc-pins {
>  				pins = "PC0", "PC1", "PC2";
> @@ -637,6 +647,18 @@ uart0_pb_pins: uart0-pb-pins {
>  				function = "uart0";
>  			};
>  
> +			/omit-if-no-ref/
> +			uart2_pi_pins: uart2-pi-pins {
> +				pins = "PI18", "PI19";
> +				function = "uart2";
> +			};
> +
> +			/omit-if-no-ref/
> +			uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{
> +				pins = "PI16", "PI17";
> +				function = "uart2";
> +			};
> +
>  			/omit-if-no-ref/
>  			uart3_pg_pins: uart3-pg-pins {
>  				pins = "PG6", "PG7";
> @@ -648,6 +670,24 @@ uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
>  				pins = "PG8", "PG9";
>  				function = "uart3";
>  			};
> +
> +			/omit-if-no-ref/
> +			uart4_pg_pins: uart4-pg-pins {
> +				pins = "PG10", "PG11";
> +				function = "uart4";
> +			};
> +
> +			/omit-if-no-ref/
> +			uart5_ph_pins: uart5-ph-pins {
> +				pins = "PH6", "PH7";
> +				function = "uart5";
> +			};
> +
> +			/omit-if-no-ref/
> +			uart7_pi_pins: uart7-pi-pins {
> +				pins = "PI20", "PI21";
> +				function = "uart7";
> +			};
>  		};
>  
>  		wdt: watchdog@1c20c90 {

Re: [PATCH v2 2/4] ARM: dts: sun8i: r40: add pinmux settings for MMC3 and UARTs 2,4,5&7

[Andre Przywara]

On Mon, 22 Mar 2021 13:55:36 +0300
Ivan Uvarov <i.uvarov@cognitivepilot.com> wrote:

Hi,

> The Forlinx OKA40i-C devboard makes use of UARTs 0,2,3,4,5 and 7 of the R40
> SoC, of which UART 0 is connected to an RS232 converter, UART 5 routed to
> an RS485 converter, and the rest broken out directly via labeled headers.
> The board also contains a micro-SD slot connected to SDC3.
> 
> This patch adds settings to R40's pinmux node for those UARTs that were not
> already mapped, which would allow us to make use of all available UARTs and
> the micro-SD slot on this board in a further patch.
> 
> Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com>

Looks alright, compared against the R40 manual.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> 
>  1 file changed, 40 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
> index 0b257a0779..51031a0e59 100644
> --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -357,6 +357,8 @@ mmc3: mmc@1c12000 {
>  			clock-names = "ahb", "mmc";
>  			resets = <&ccu RST_BUS_MMC3>;
>  			reset-names = "ahb";
> +			pinctrl-0 = <&mmc3_pins>;
> +			pinctrl-names = "default";
>  			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
>  			status = "disabled";
>  			#address-cells = <1>;
> @@ -601,6 +603,14 @@ mmc2_pins: mmc2-pins {
>  				bias-pull-up;
>  			};
>  
> +			mmc3_pins: mmc3-pins {
> +				pins = "PI4", "PI5", "PI6",
> +				       "PI7", "PI8", "PI9";
> +				function = "mmc3";
> +				drive-strength = <30>;
> +				bias-pull-up;
> +			};
> +
>  			/omit-if-no-ref/
>  			spi0_pc_pins: spi0-pc-pins {
>  				pins = "PC0", "PC1", "PC2";
> @@ -637,6 +647,18 @@ uart0_pb_pins: uart0-pb-pins {
>  				function = "uart0";
>  			};
>  
> +			/omit-if-no-ref/
> +			uart2_pi_pins: uart2-pi-pins {
> +				pins = "PI18", "PI19";
> +				function = "uart2";
> +			};
> +
> +			/omit-if-no-ref/
> +			uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{
> +				pins = "PI16", "PI17";
> +				function = "uart2";
> +			};
> +
>  			/omit-if-no-ref/
>  			uart3_pg_pins: uart3-pg-pins {
>  				pins = "PG6", "PG7";
> @@ -648,6 +670,24 @@ uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
>  				pins = "PG8", "PG9";
>  				function = "uart3";
>  			};
> +
> +			/omit-if-no-ref/
> +			uart4_pg_pins: uart4-pg-pins {
> +				pins = "PG10", "PG11";
> +				function = "uart4";
> +			};
> +
> +			/omit-if-no-ref/
> +			uart5_ph_pins: uart5-ph-pins {
> +				pins = "PH6", "PH7";
> +				function = "uart5";
> +			};
> +
> +			/omit-if-no-ref/
> +			uart7_pi_pins: uart7-pi-pins {
> +				pins = "PI20", "PI21";
> +				function = "uart7";
> +			};
>  		};
>  
>  		wdt: watchdog@1c20c90 {


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Re: [PATCH v2 3/4] dt-bindings: arm: add compatible strings for Forlinx OKA40i-C

[Andre Przywara]

On Mon, 22 Mar 2021 13:55:37 +0300
Ivan Uvarov <i.uvarov@cognitivepilot.com> wrote:

Hi,

> The OKA40i-C is a carrier/development board for the Forlinx FETA40i-C SoM
> based on the Allwinner R40/A40i SoC.
> 
> This patch adds the relevant dt-binding documentation in preparation for
> the next patch, which adds a devicetree for the SoM and board.
> 
> Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com>
> 
>  2 files changed, 7 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
> index 08607c7ec1..096405aedc 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.yaml
> +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
> @@ -224,6 +224,11 @@ properties:
>            - const: empire-electronix,m712
>            - const: allwinner,sun5i-a13
>  
> +      - description: Forlinx OKA40i-C Development board
> +        items:
> +          - const: forlinx,oka40i-c

I think you should add the SoM name in here, compare:
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts

Cheers,
Andre


> +          - const: allwinner,sun8i-r40
> +
>        - description: FriendlyARM NanoPi A64
>          items:
>            - const: friendlyarm,nanopi-a64
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index f6064d84a4..e2ea1a731e 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -403,6 +403,8 @@ patternProperties:
>      description: Firefly
>    "^focaltech,.*":
>      description: FocalTech Systems Co.,Ltd
> +  "^forlinx,.*":
> +    description: Baoding Forlinx Embedded Technology Co., Ltd.
>    "^frida,.*":
>      description: Shenzhen Frida LCD Co., Ltd.
>    "^friendlyarm,.*":

Re: [PATCH v2 3/4] dt-bindings: arm: add compatible strings for Forlinx OKA40i-C

[Andre Przywara]

On Mon, 22 Mar 2021 13:55:37 +0300
Ivan Uvarov <i.uvarov@cognitivepilot.com> wrote:

Hi,

> The OKA40i-C is a carrier/development board for the Forlinx FETA40i-C SoM
> based on the Allwinner R40/A40i SoC.
> 
> This patch adds the relevant dt-binding documentation in preparation for
> the next patch, which adds a devicetree for the SoM and board.
> 
> Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com>
> 
>  2 files changed, 7 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
> index 08607c7ec1..096405aedc 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.yaml
> +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
> @@ -224,6 +224,11 @@ properties:
>            - const: empire-electronix,m712
>            - const: allwinner,sun5i-a13
>  
> +      - description: Forlinx OKA40i-C Development board
> +        items:
> +          - const: forlinx,oka40i-c

I think you should add the SoM name in here, compare:
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts

Cheers,
Andre


> +          - const: allwinner,sun8i-r40
> +
>        - description: FriendlyARM NanoPi A64
>          items:
>            - const: friendlyarm,nanopi-a64
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index f6064d84a4..e2ea1a731e 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -403,6 +403,8 @@ patternProperties:
>      description: Firefly
>    "^focaltech,.*":
>      description: FocalTech Systems Co.,Ltd
> +  "^forlinx,.*":
> +    description: Baoding Forlinx Embedded Technology Co., Ltd.
>    "^frida,.*":
>      description: Shenzhen Frida LCD Co., Ltd.
>    "^friendlyarm,.*":


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Re: [PATCH v2 4/4] ARM: dts: sun8i: r40: add devicetree for Forlinx FETA40i-C & OKA40i-C

[Andre Przywara]

On Mon, 22 Mar 2021 13:55:38 +0300
Ivan Uvarov <i.uvarov@cognitivepilot.com> wrote:

Hi,

> The FETA40i-C is a SoM by Forlinx based on the Allwinner R40/A40i.
> 
> SoM specifications:
> 
> - SoC: R40 or A40i
> - PMIC: AXP221S
> - RAM: 1GiB/2GiB DDR3 (dual-rank)
> - eMMC: 8GB,
> - Mates with carrier board via four 80-pin connectors (AXK6F80337YG).
> 
> OKA40i-C is a carrier board by the same manufacturer for this SoM,
> whose main purpose is as a development board with a wide variety of
> peripherals:
> 
> - Power: DC5V barrel or USB OTG or 4.2V Lipo battery
> - Video out: HDMI, TV out, LVDS
> - WiFi+Bluetooth: RL-UM02WBS-8723BU-V1.2 (802.11 b/g/n, BT V2.1/3.0/4.0)
> - Ethernet: 10/100Mbps
> - Storage: µSD, fullsize SD, eMMC (on SoM), SATA
> - USB: 3 x USB2.0 Host (2 via hub, 1 native), 1 x USB2.0 OTG (micro-B)
> - UART: RS232, RS485, 4 3.3v uarts (of which 2 have RTS/CTS)
> - Other I/O: SPI x2, TWI, SDIO header, GPIO header, JTAG header
> - Mini PCIe slot with sim holder for WLAN modem
> - Smart card holder
> - RTC (RX8010SJ)
> - Two user LEDs
> - Three user buttons (via KeyADC).
> 
> This patch adds a devicetree for the aforementioned SoM and devboard.
> In order to reflect the modularity of this devboard and simplify adding
> support for future hardware based on the same SoM, the devicetree is split:
> Everything pertaining to the SoM itself is described in a separate .dtsi
> file, which is included by the devboard's .dts.
> 
> Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com>
> 
>  3 files changed, 310 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 8e5d4ab4e7..88aae9de95 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1222,6 +1222,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
>  	sun8i-r16-nintendo-super-nes-classic.dtb \
>  	sun8i-r16-parrot.dtb \
>  	sun8i-r40-bananapi-m2-ultra.dtb \
> +	sun8i-r40-oka40i-c.dtb \
>  	sun8i-s3-elimo-initium.dtb \
>  	sun8i-s3-lichee-zero-plus.dtb \
>  	sun8i-s3-pinecube.dtb \
> diff --git a/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi
> new file mode 100644
> index 0000000000..d3cc6f974f
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi
> @@ -0,0 +1,66 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> +// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com>
> +// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is:
> +//  Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
> +//  Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
> +
> +#include "sun8i-r40.dtsi"
> +
> +&i2c0 {
> +	status = "okay";
> +
> +	axp22x: pmic@34 {
> +		compatible = "x-powers,axp221";
> +		reg = <0x34>;
> +		interrupt-parent = <&nmi_intc>;
> +		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +};
> +
> +#include "axp22x.dtsi"
> +
> +&mmc2 {
> +	vmmc-supply = <&reg_dcdc1>;
> +	vqmmc-supply = <&reg_aldo2>;
> +	bus-width = <8>;
> +	non-removable;
> +	status = "okay";
> +};
> +
> +&pio {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&clk_out_a_pin>;
> +	vcc-pa-supply = <&reg_dcdc1>;
uar> +	vcc-pc-supply = <&reg_aldo2>;
> +	vcc-pd-supply = <&reg_dcdc1>;
> +	vcc-pf-supply = <&reg_dldo4>;
> +	vcc-pg-supply = <&reg_dldo1>;
> +};
> +
> +&reg_aldo2 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <1800000>;
> +	regulator-max-microvolt = <1800000>;
> +	regulator-name = "vcc-pa";
> +};
> +
> +&reg_dcdc1 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <3300000>;
> +	regulator-max-microvolt = <3300000>;
> +	regulator-name = "vcc-3v3";
> +};
> +
> +&reg_dldo1 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <3300000>;
> +	regulator-max-microvolt = <3300000>;
> +	regulator-name = "vcc-wifi-io";
> +};
> +
> +&reg_dldo4 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <2500000>;
> +	regulator-max-microvolt = <2500000>;
> +	regulator-name = "vdd2v5-sata";
> +};
> diff --git a/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts b/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts
> new file mode 100644
> index 0000000000..133991d7b3
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts
> @@ -0,0 +1,243 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> +// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com>
> +// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is:
> +//	Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
> +//	Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
> +
> +/dts-v1/;
> +#include "sun8i-r40-feta40i.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +
> +/ {
> +	model = "Forlinx OKA40i-C";
> +	compatible = "forlinx,oka40i-c", "allwinner,sun8i-r40";

As mentioned in the other patch, this should contain the SoM compatible
string in-between the two.

> +
> +	aliases {
> +		ethernet0 = &gmac;
> +		serial0 = &uart0;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +		serial5 = &uart5; /* RS485 */
> +		serial7 = &uart7;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	connector {
> +		compatible = "hdmi-connector";
> +		type = "a";
> +
> +		port {
> +			hdmi_con_in: endpoint {
> +				remote-endpoint = <&hdmi_out_con>;
> +			};
> +		};
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +
> +		led-5 {
> +			gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */
> +			color = <LED_COLOR_ID_GREEN>;
> +			function = LED_FUNCTION_STATUS;
> +		};
> +
> +		led-6 {
> +			gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */
> +			color = <LED_COLOR_ID_BLUE>;
> +			function = LED_FUNCTION_STATUS;
> +		};
> +	};
> +
> +	reg_vcc5v0: vcc5v0 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vcc5v0";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +	};
> +
> +	wifi_pwrseq: wifi_pwrseq {
> +		compatible = "mmc-pwrseq-simple";
> +		reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; // PB10 WIFI_EN
> +		clocks = <&ccu CLK_OUTA>;
> +		clock-names = "ext_clock";
> +	};
> +};
> +
> +&ahci {
> +	ahci-supply = <&reg_dldo4>;
> +	phy-supply = <&reg_eldo2>;
> +	status = "okay";
> +};
> +
> +&de {
> +	status = "okay";
> +};
> +
> +&ehci1 {
> +	status = "okay";
> +};
> +
> +&ehci2 {
> +	status = "okay";
> +};
> +
> +&gmac {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&gmac_rgmii_pins>;
> +	phy-handle = <&phy1>;
> +	phy-mode = "rgmii-id";
> +	phy-supply = <&reg_dcdc1>;
> +	status = "okay";
> +};
> +
> +&gmac_mdio {
> +	phy1: ethernet-phy@1 {
> +		compatible = "ethernet-phy-ieee802.3-c22";
> +		reg = <1>;
> +	};
> +};
> +
> +&hdmi {
> +	status = "okay";
> +};
> +
> +&hdmi_out {
> +	hdmi_out_con: endpoint {
> +		remote-endpoint = <&hdmi_con_in>;
> +	};
> +};
> +
> +&i2c2 {
> +	status = "okay";
> +};
> +
> +&mmc0 {
> +	vmmc-supply = <&reg_dcdc1>;
> +	vqmmc-supply = <&reg_dcdc1>;
> +	bus-width = <4>;
> +	cd-gpios = <&pio 8 11 GPIO_ACTIVE_LOW>; // PI11
> +	status = "okay";
> +};
> +
> +&mmc3 {
> +	vmmc-supply = <&reg_dcdc1>;
> +	vqmmc-supply = <&reg_dcdc1>;
> +	bus-width = <4>;
> +	cd-gpios = <&pio 8 10 GPIO_ACTIVE_LOW>; // PI10
> +	status = "okay";
> +};
> +
> +&ohci1 {
> +	status = "okay";
> +};
> +
> +&ohci2 {
> +	status = "okay";
> +};
> +
> +&reg_aldo3 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <3000000>;
> +	regulator-max-microvolt = <3000000>;
> +	regulator-name = "avcc";
> +};

I believe this regulator should be in the SoM .dtsi. If I get this
correctly, this regulator is somewhat essential, also the connection is
entirely on the SoM (as both the AXP and the SoC are).
I don't know for sure if you can actually disable this if you don't
need any "analogue" functionality, but then any board .dts could still
put a: status = "disabled"; property in its .dts.

> +
> +&reg_dc1sw {
> +	regulator-min-microvolt = <3300000>;
> +	regulator-max-microvolt = <3300000>;
> +	regulator-name = "vcc-lcd";
> +};
> +
> +&reg_dcdc2 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <1100000>;
> +	regulator-max-microvolt = <1100000>;
> +	regulator-name = "vdd-cpu";
> +};
> +
> +&reg_dcdc3 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <1100000>;
> +	regulator-max-microvolt = <1100000>;
> +	regulator-name = "vdd-sys";
> +};
> +
> +&reg_dcdc5 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <1500000>;
> +	regulator-max-microvolt = <1500000>;
> +	regulator-name = "vcc-dram";
> +};

Those three (cpu, sys, dram) definitely belong into the SoM .dtsi.

> +
> +&reg_dldo2 {
> +	regulator-min-microvolt = <3300000>;
> +	regulator-max-microvolt = <3300000>;
> +	regulator-name = "vcc-wifi";
> +};
> +
> +&reg_eldo2 {
> +	regulator-min-microvolt = <1200000>;
> +	regulator-max-microvolt = <1200000>;
> +	regulator-name = "vdd1v2-sata";
> +};

Since this is not always-on, but is hardwired on the SoM, it should
probably just live in the SoM .dtsi as well.

> +
> +&reg_eldo3 {
> +	regulator-min-microvolt = <2800000>;
> +	regulator-max-microvolt = <2800000>;
> +	regulator-name = "vcc-pe";
> +};

I guess the same rationale applies to PE: the line is on the SoM, and
any board users could just reference it from there to make use of it.

The rest looks alright.

Cheers,
Andre

> +
> +&tcon_tv0 {
> +	status = "okay";
> +};
> +
> +&uart0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart0_pb_pins>;
> +	status = "okay";
> +};
> +
> +&uart2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart2_pi_pins>, <&uart2_rts_cts_pi_pins>;
> +	uart-has-rtscts;
> +	status = "okay";
> +};
> +
> +&uart3 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>;
> +	uart-has-rtscts;
> +	status = "okay";
> +};
> +
> +&uart4 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart4_pg_pins>;
> +	status = "okay";
> +};
> +
> +&uart5 { /* RS485 */
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart5_ph_pins>;
> +	status = "okay";
> +};
> +
> +&uart7 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart7_pi_pins>;
> +	status = "okay";
> +};
> +
> +&usbphy {
> +	usb1_vbus-supply = <&reg_vcc5v0>;
> +	usb2_vbus-supply = <&reg_vcc5v0>;
> +	status = "okay";
> +};

Re: [PATCH v2 4/4] ARM: dts: sun8i: r40: add devicetree for Forlinx FETA40i-C & OKA40i-C

[Andre Przywara]

On Mon, 22 Mar 2021 13:55:38 +0300
Ivan Uvarov <i.uvarov@cognitivepilot.com> wrote:

Hi,

> The FETA40i-C is a SoM by Forlinx based on the Allwinner R40/A40i.
> 
> SoM specifications:
> 
> - SoC: R40 or A40i
> - PMIC: AXP221S
> - RAM: 1GiB/2GiB DDR3 (dual-rank)
> - eMMC: 8GB,
> - Mates with carrier board via four 80-pin connectors (AXK6F80337YG).
> 
> OKA40i-C is a carrier board by the same manufacturer for this SoM,
> whose main purpose is as a development board with a wide variety of
> peripherals:
> 
> - Power: DC5V barrel or USB OTG or 4.2V Lipo battery
> - Video out: HDMI, TV out, LVDS
> - WiFi+Bluetooth: RL-UM02WBS-8723BU-V1.2 (802.11 b/g/n, BT V2.1/3.0/4.0)
> - Ethernet: 10/100Mbps
> - Storage: µSD, fullsize SD, eMMC (on SoM), SATA
> - USB: 3 x USB2.0 Host (2 via hub, 1 native), 1 x USB2.0 OTG (micro-B)
> - UART: RS232, RS485, 4 3.3v uarts (of which 2 have RTS/CTS)
> - Other I/O: SPI x2, TWI, SDIO header, GPIO header, JTAG header
> - Mini PCIe slot with sim holder for WLAN modem
> - Smart card holder
> - RTC (RX8010SJ)
> - Two user LEDs
> - Three user buttons (via KeyADC).
> 
> This patch adds a devicetree for the aforementioned SoM and devboard.
> In order to reflect the modularity of this devboard and simplify adding
> support for future hardware based on the same SoM, the devicetree is split:
> Everything pertaining to the SoM itself is described in a separate .dtsi
> file, which is included by the devboard's .dts.
> 
> Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com>
> 
>  3 files changed, 310 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 8e5d4ab4e7..88aae9de95 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1222,6 +1222,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
>  	sun8i-r16-nintendo-super-nes-classic.dtb \
>  	sun8i-r16-parrot.dtb \
>  	sun8i-r40-bananapi-m2-ultra.dtb \
> +	sun8i-r40-oka40i-c.dtb \
>  	sun8i-s3-elimo-initium.dtb \
>  	sun8i-s3-lichee-zero-plus.dtb \
>  	sun8i-s3-pinecube.dtb \
> diff --git a/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi
> new file mode 100644
> index 0000000000..d3cc6f974f
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi
> @@ -0,0 +1,66 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> +// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com>
> +// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is:
> +//  Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
> +//  Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
> +
> +#include "sun8i-r40.dtsi"
> +
> +&i2c0 {
> +	status = "okay";
> +
> +	axp22x: pmic@34 {
> +		compatible = "x-powers,axp221";
> +		reg = <0x34>;
> +		interrupt-parent = <&nmi_intc>;
> +		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +};
> +
> +#include "axp22x.dtsi"
> +
> +&mmc2 {
> +	vmmc-supply = <&reg_dcdc1>;
> +	vqmmc-supply = <&reg_aldo2>;
> +	bus-width = <8>;
> +	non-removable;
> +	status = "okay";
> +};
> +
> +&pio {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&clk_out_a_pin>;
> +	vcc-pa-supply = <&reg_dcdc1>;
uar> +	vcc-pc-supply = <&reg_aldo2>;
> +	vcc-pd-supply = <&reg_dcdc1>;
> +	vcc-pf-supply = <&reg_dldo4>;
> +	vcc-pg-supply = <&reg_dldo1>;
> +};
> +
> +&reg_aldo2 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <1800000>;
> +	regulator-max-microvolt = <1800000>;
> +	regulator-name = "vcc-pa";
> +};
> +
> +&reg_dcdc1 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <3300000>;
> +	regulator-max-microvolt = <3300000>;
> +	regulator-name = "vcc-3v3";
> +};
> +
> +&reg_dldo1 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <3300000>;
> +	regulator-max-microvolt = <3300000>;
> +	regulator-name = "vcc-wifi-io";
> +};
> +
> +&reg_dldo4 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <2500000>;
> +	regulator-max-microvolt = <2500000>;
> +	regulator-name = "vdd2v5-sata";
> +};
> diff --git a/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts b/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts
> new file mode 100644
> index 0000000000..133991d7b3
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts
> @@ -0,0 +1,243 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> +// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com>
> +// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is:
> +//	Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
> +//	Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
> +
> +/dts-v1/;
> +#include "sun8i-r40-feta40i.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +
> +/ {
> +	model = "Forlinx OKA40i-C";
> +	compatible = "forlinx,oka40i-c", "allwinner,sun8i-r40";

As mentioned in the other patch, this should contain the SoM compatible
string in-between the two.

> +
> +	aliases {
> +		ethernet0 = &gmac;
> +		serial0 = &uart0;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +		serial5 = &uart5; /* RS485 */
> +		serial7 = &uart7;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	connector {
> +		compatible = "hdmi-connector";
> +		type = "a";
> +
> +		port {
> +			hdmi_con_in: endpoint {
> +				remote-endpoint = <&hdmi_out_con>;
> +			};
> +		};
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +
> +		led-5 {
> +			gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */
> +			color = <LED_COLOR_ID_GREEN>;
> +			function = LED_FUNCTION_STATUS;
> +		};
> +
> +		led-6 {
> +			gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */
> +			color = <LED_COLOR_ID_BLUE>;
> +			function = LED_FUNCTION_STATUS;
> +		};
> +	};
> +
> +	reg_vcc5v0: vcc5v0 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vcc5v0";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +	};
> +
> +	wifi_pwrseq: wifi_pwrseq {
> +		compatible = "mmc-pwrseq-simple";
> +		reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; // PB10 WIFI_EN
> +		clocks = <&ccu CLK_OUTA>;
> +		clock-names = "ext_clock";
> +	};
> +};
> +
> +&ahci {
> +	ahci-supply = <&reg_dldo4>;
> +	phy-supply = <&reg_eldo2>;
> +	status = "okay";
> +};
> +
> +&de {
> +	status = "okay";
> +};
> +
> +&ehci1 {
> +	status = "okay";
> +};
> +
> +&ehci2 {
> +	status = "okay";
> +};
> +
> +&gmac {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&gmac_rgmii_pins>;
> +	phy-handle = <&phy1>;
> +	phy-mode = "rgmii-id";
> +	phy-supply = <&reg_dcdc1>;
> +	status = "okay";
> +};
> +
> +&gmac_mdio {
> +	phy1: ethernet-phy@1 {
> +		compatible = "ethernet-phy-ieee802.3-c22";
> +		reg = <1>;
> +	};
> +};
> +
> +&hdmi {
> +	status = "okay";
> +};
> +
> +&hdmi_out {
> +	hdmi_out_con: endpoint {
> +		remote-endpoint = <&hdmi_con_in>;
> +	};
> +};
> +
> +&i2c2 {
> +	status = "okay";
> +};
> +
> +&mmc0 {
> +	vmmc-supply = <&reg_dcdc1>;
> +	vqmmc-supply = <&reg_dcdc1>;
> +	bus-width = <4>;
> +	cd-gpios = <&pio 8 11 GPIO_ACTIVE_LOW>; // PI11
> +	status = "okay";
> +};
> +
> +&mmc3 {
> +	vmmc-supply = <&reg_dcdc1>;
> +	vqmmc-supply = <&reg_dcdc1>;
> +	bus-width = <4>;
> +	cd-gpios = <&pio 8 10 GPIO_ACTIVE_LOW>; // PI10
> +	status = "okay";
> +};
> +
> +&ohci1 {
> +	status = "okay";
> +};
> +
> +&ohci2 {
> +	status = "okay";
> +};
> +
> +&reg_aldo3 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <3000000>;
> +	regulator-max-microvolt = <3000000>;
> +	regulator-name = "avcc";
> +};

I believe this regulator should be in the SoM .dtsi. If I get this
correctly, this regulator is somewhat essential, also the connection is
entirely on the SoM (as both the AXP and the SoC are).
I don't know for sure if you can actually disable this if you don't
need any "analogue" functionality, but then any board .dts could still
put a: status = "disabled"; property in its .dts.

> +
> +&reg_dc1sw {
> +	regulator-min-microvolt = <3300000>;
> +	regulator-max-microvolt = <3300000>;
> +	regulator-name = "vcc-lcd";
> +};
> +
> +&reg_dcdc2 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <1100000>;
> +	regulator-max-microvolt = <1100000>;
> +	regulator-name = "vdd-cpu";
> +};
> +
> +&reg_dcdc3 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <1100000>;
> +	regulator-max-microvolt = <1100000>;
> +	regulator-name = "vdd-sys";
> +};
> +
> +&reg_dcdc5 {
> +	regulator-always-on;
> +	regulator-min-microvolt = <1500000>;
> +	regulator-max-microvolt = <1500000>;
> +	regulator-name = "vcc-dram";
> +};

Those three (cpu, sys, dram) definitely belong into the SoM .dtsi.

> +
> +&reg_dldo2 {
> +	regulator-min-microvolt = <3300000>;
> +	regulator-max-microvolt = <3300000>;
> +	regulator-name = "vcc-wifi";
> +};
> +
> +&reg_eldo2 {
> +	regulator-min-microvolt = <1200000>;
> +	regulator-max-microvolt = <1200000>;
> +	regulator-name = "vdd1v2-sata";
> +};

Since this is not always-on, but is hardwired on the SoM, it should
probably just live in the SoM .dtsi as well.

> +
> +&reg_eldo3 {
> +	regulator-min-microvolt = <2800000>;
> +	regulator-max-microvolt = <2800000>;
> +	regulator-name = "vcc-pe";
> +};

I guess the same rationale applies to PE: the line is on the SoM, and
any board users could just reference it from there to make use of it.

The rest looks alright.

Cheers,
Andre

> +
> +&tcon_tv0 {
> +	status = "okay";
> +};
> +
> +&uart0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart0_pb_pins>;
> +	status = "okay";
> +};
> +
> +&uart2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart2_pi_pins>, <&uart2_rts_cts_pi_pins>;
> +	uart-has-rtscts;
> +	status = "okay";
> +};
> +
> +&uart3 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>;
> +	uart-has-rtscts;
> +	status = "okay";
> +};
> +
> +&uart4 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart4_pg_pins>;
> +	status = "okay";
> +};
> +
> +&uart5 { /* RS485 */
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart5_ph_pins>;
> +	status = "okay";
> +};
> +
> +&uart7 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart7_pi_pins>;
> +	status = "okay";
> +};
> +
> +&usbphy {
> +	usb1_vbus-supply = <&reg_vcc5v0>;
> +	usb2_vbus-supply = <&reg_vcc5v0>;
> +	status = "okay";
> +};


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Re: [PATCH v2 1/4] ARM: dts: sun8i: r40: add /omit-if-no-ref/ to pinmux nodes for UARTs 0&3

[Ivan Uvarov]

On Mon, 22 Mar 2021 16:18:04 +0000
Andre Przywara <andre.przywara@arm.com> wrote:

> On Mon, 22 Mar 2021 13:55:35 +0300
> Ivan Uvarov <i.uvarov@cognitivepilot.com> wrote:
> 
> Hi,
>   
> > This patch adds the /omit-if-no-ref/ keyword to the pio nodes for
> > UART0 and UART3 pins of the R40 SoC, which would reduce the fdt
> > size on boards which do not use these UARTs.    
> 
> But what boards are those? It seems like all boards use uart3-pg and
> the two existing boards use UART0.
> 
> I think the idea is to use omit-if-no-ref on some rarely used nodes,
> so if there is only a single user, for instance. Your next patch is a
> good example.
> 
> So I don't think this patch here is needed at all.
> 
> Cheers,
> Andre
>   

This is a valid complaint, and the patch indeed is not strictly
necessary. At the same time, the keyword certainly doesn't hurt, and
it would be a good base for future R40 boards. 

As to what boards I'm referring to, there's at least the carrier board
for the FETA40i which our company is privately developing, the support
for which we probably won't upstream as it's highly unlikely it'll ever
get into the hands of anyone who would appreciate such support.

I must also mention that I only added this patch to the series due to
explicit encouragement from Maxime in his last response to v1 of the patch:

On Fri, 19 Mar 2021 14:24:48 +0100 
Maxime Ripard <maxime@cerno.tech> wrote:
> On Tue, Mar 16, 2021 at 06:48:58PM +0300, Ivan Uvarov wrote:  
> > Also, would it be a good idea to add /omit-if-no-ref/ to the uart3
> > pins as well while I'm here?   
>
> To all the nodes honestly. If you want to make a preliminary patch doing
> this, go ahead :)  

Since there's two differing viewpoints on the subject, this definitely
deserves more discussion.

--
Regards,
Ivan Uvarov

Re: [PATCH v2 1/4] ARM: dts: sun8i: r40: add /omit-if-no-ref/ to pinmux nodes for UARTs 0&3

[Ivan Uvarov]

On Mon, 22 Mar 2021 16:18:04 +0000
Andre Przywara <andre.przywara@arm.com> wrote:

> On Mon, 22 Mar 2021 13:55:35 +0300
> Ivan Uvarov <i.uvarov@cognitivepilot.com> wrote:
> 
> Hi,
>   
> > This patch adds the /omit-if-no-ref/ keyword to the pio nodes for
> > UART0 and UART3 pins of the R40 SoC, which would reduce the fdt
> > size on boards which do not use these UARTs.    
> 
> But what boards are those? It seems like all boards use uart3-pg and
> the two existing boards use UART0.
> 
> I think the idea is to use omit-if-no-ref on some rarely used nodes,
> so if there is only a single user, for instance. Your next patch is a
> good example.
> 
> So I don't think this patch here is needed at all.
> 
> Cheers,
> Andre
>   

This is a valid complaint, and the patch indeed is not strictly
necessary. At the same time, the keyword certainly doesn't hurt, and
it would be a good base for future R40 boards. 

As to what boards I'm referring to, there's at least the carrier board
for the FETA40i which our company is privately developing, the support
for which we probably won't upstream as it's highly unlikely it'll ever
get into the hands of anyone who would appreciate such support.

I must also mention that I only added this patch to the series due to
explicit encouragement from Maxime in his last response to v1 of the patch:

On Fri, 19 Mar 2021 14:24:48 +0100 
Maxime Ripard <maxime@cerno.tech> wrote:
> On Tue, Mar 16, 2021 at 06:48:58PM +0300, Ivan Uvarov wrote:  
> > Also, would it be a good idea to add /omit-if-no-ref/ to the uart3
> > pins as well while I'm here?   
>
> To all the nodes honestly. If you want to make a preliminary patch doing
> this, go ahead :)  

Since there's two differing viewpoints on the subject, this definitely
deserves more discussion.

--
Regards,
Ivan Uvarov

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Re: [PATCH v2 1/4] ARM: dts: sun8i: r40: add /omit-if-no-ref/ to pinmux nodes for UARTs 0&3

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 807 bytes --]

On Mon, Mar 22, 2021 at 04:18:04PM +0000, Andre Przywara wrote:
> On Mon, 22 Mar 2021 13:55:35 +0300
> Ivan Uvarov <i.uvarov@cognitivepilot.com> wrote:
> 
> Hi,
> 
> > This patch adds the /omit-if-no-ref/ keyword to the pio nodes for
> > UART0 and UART3 pins of the R40 SoC, which would reduce the fdt size on
> > boards which do not use these UARTs.
> 
> But what boards are those? It seems like all boards use uart3-pg and
> the two existing boards use UART0.
> 
> I think the idea is to use omit-if-no-ref on some rarely used nodes, so
> if there is only a single user, for instance. Your next patch is a good
> example.

There's no real cost associated to it though, so it's just easier to
flag all the nodes and let the compiler figure out if it should evict
them or not.

Maxime

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Re: [PATCH v2 1/4] ARM: dts: sun8i: r40: add /omit-if-no-ref/ to pinmux nodes for UARTs 0&3

[Maxime Ripard]

[-- Attachment #1.1: Type: text/plain, Size: 807 bytes --]

On Mon, Mar 22, 2021 at 04:18:04PM +0000, Andre Przywara wrote:
> On Mon, 22 Mar 2021 13:55:35 +0300
> Ivan Uvarov <i.uvarov@cognitivepilot.com> wrote:
> 
> Hi,
> 
> > This patch adds the /omit-if-no-ref/ keyword to the pio nodes for
> > UART0 and UART3 pins of the R40 SoC, which would reduce the fdt size on
> > boards which do not use these UARTs.
> 
> But what boards are those? It seems like all boards use uart3-pg and
> the two existing boards use UART0.
> 
> I think the idea is to use omit-if-no-ref on some rarely used nodes, so
> if there is only a single user, for instance. Your next patch is a good
> example.

There's no real cost associated to it though, so it's just easier to
flag all the nodes and let the compiler figure out if it should evict
them or not.

Maxime

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