From: Eric Anholt <eric@anholt.net>
To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
freedreno@lists.freedesktop.org, Rob Clark <robdclark@gmail.com>,
Sean Paul <sean@poorly.run>,
Jordan Crouse <jcrouse@codeaurora.org>,
Robin Murphy <robin.murphy@arm.com>,
Will Deacon <will@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Joerg Roedel <joro@8bytes.org>,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, Eric Anholt <eric@anholt.net>
Subject: [PATCH 2/2] arm64: dts: msm8996: Mark the GPU's SMMU as an adreno one.
Date: Fri, 26 Mar 2021 16:13:03 -0700 [thread overview]
Message-ID: <20210326231303.3071950-2-eric@anholt.net> (raw)
In-Reply-To: <20210326231303.3071950-1-eric@anholt.net>
This enables the adreno-specific SMMU path that sets HUPCF so
(user-managed) page faults don't wedge the GPU.
Signed-off-by: Eric Anholt <eric@anholt.net>
---
We've been seeing a flaky test per day or so in Mesa CI where the
kernel gets wedged after an iommu fault turns into CP errors. With
this patch, the CI isn't throwing the string of CP errors on the
faults in any of the ~10 jobs I've run so far.
arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 6de136e3add9..432b87ec9c5e 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1127,7 +1127,7 @@ cci_i2c1: i2c-bus@1 {
};
adreno_smmu: iommu@b40000 {
- compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+ compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
reg = <0x00b40000 0x10000>;
#global-interrupts = <1>;
--
2.31.0
WARNING: multiple messages have this Message-ID (diff)
From: Eric Anholt <eric@anholt.net>
To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
freedreno@lists.freedesktop.org, Rob Clark <robdclark@gmail.com>,
Sean Paul <sean@poorly.run>,
Jordan Crouse <jcrouse@codeaurora.org>,
Robin Murphy <robin.murphy@arm.com>,
Will Deacon <will@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Joerg Roedel <joro@8bytes.org>,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, Eric Anholt <eric@anholt.net>
Subject: [PATCH 2/2] arm64: dts: msm8996: Mark the GPU's SMMU as an adreno one.
Date: Fri, 26 Mar 2021 16:13:03 -0700 [thread overview]
Message-ID: <20210326231303.3071950-2-eric@anholt.net> (raw)
In-Reply-To: <20210326231303.3071950-1-eric@anholt.net>
This enables the adreno-specific SMMU path that sets HUPCF so
(user-managed) page faults don't wedge the GPU.
Signed-off-by: Eric Anholt <eric@anholt.net>
---
We've been seeing a flaky test per day or so in Mesa CI where the
kernel gets wedged after an iommu fault turns into CP errors. With
this patch, the CI isn't throwing the string of CP errors on the
faults in any of the ~10 jobs I've run so far.
arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 6de136e3add9..432b87ec9c5e 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1127,7 +1127,7 @@ cci_i2c1: i2c-bus@1 {
};
adreno_smmu: iommu@b40000 {
- compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+ compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
reg = <0x00b40000 0x10000>;
#global-interrupts = <1>;
--
2.31.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Eric Anholt <eric@anholt.net>
To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
freedreno@lists.freedesktop.org, Rob Clark <robdclark@gmail.com>,
Sean Paul <sean@poorly.run>,
Jordan Crouse <jcrouse@codeaurora.org>,
Robin Murphy <robin.murphy@arm.com>,
Will Deacon <will@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Joerg Roedel <joro@8bytes.org>,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Subject: [PATCH 2/2] arm64: dts: msm8996: Mark the GPU's SMMU as an adreno one.
Date: Fri, 26 Mar 2021 16:13:03 -0700 [thread overview]
Message-ID: <20210326231303.3071950-2-eric@anholt.net> (raw)
In-Reply-To: <20210326231303.3071950-1-eric@anholt.net>
This enables the adreno-specific SMMU path that sets HUPCF so
(user-managed) page faults don't wedge the GPU.
Signed-off-by: Eric Anholt <eric@anholt.net>
---
We've been seeing a flaky test per day or so in Mesa CI where the
kernel gets wedged after an iommu fault turns into CP errors. With
this patch, the CI isn't throwing the string of CP errors on the
faults in any of the ~10 jobs I've run so far.
arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 6de136e3add9..432b87ec9c5e 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1127,7 +1127,7 @@ cci_i2c1: i2c-bus@1 {
};
adreno_smmu: iommu@b40000 {
- compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+ compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
reg = <0x00b40000 0x10000>;
#global-interrupts = <1>;
--
2.31.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2021-03-26 23:14 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-26 23:13 [PATCH 1/2] iommu/arm-smmu-qcom: Skip the TTBR1 quirk for db820c Eric Anholt
2021-03-26 23:13 ` Eric Anholt
2021-03-26 23:13 ` Eric Anholt
2021-03-26 23:13 ` Eric Anholt [this message]
2021-03-26 23:13 ` [PATCH 2/2] arm64: dts: msm8996: Mark the GPU's SMMU as an adreno one Eric Anholt
2021-03-26 23:13 ` Eric Anholt
2021-03-30 3:23 ` Bjorn Andersson
2021-03-30 3:23 ` Bjorn Andersson
2021-03-30 3:23 ` Bjorn Andersson
2021-03-29 14:47 ` [PATCH 1/2] iommu/arm-smmu-qcom: Skip the TTBR1 quirk for db820c Will Deacon
2021-03-29 14:47 ` Will Deacon
2021-03-29 14:47 ` Will Deacon
2021-03-29 17:55 ` Eric Anholt
2021-03-29 17:55 ` Eric Anholt
2021-03-29 17:55 ` Eric Anholt
2021-03-30 4:02 ` Rob Clark
2021-03-30 4:02 ` Rob Clark
2021-03-30 4:02 ` Rob Clark
2021-03-30 9:34 ` Will Deacon
2021-03-30 9:34 ` Will Deacon
2021-03-30 9:34 ` Will Deacon
2021-03-30 15:03 ` Rob Clark
2021-03-30 15:03 ` Rob Clark
2021-03-30 15:03 ` Rob Clark
2021-03-30 15:31 ` Will Deacon
2021-03-30 15:31 ` Will Deacon
2021-03-30 15:31 ` Will Deacon
2021-03-30 16:07 ` Rob Clark
2021-03-30 16:07 ` Rob Clark
2021-03-30 16:07 ` Rob Clark
2021-05-25 17:14 ` Bjorn Andersson
2021-05-25 17:14 ` Bjorn Andersson
2021-05-25 17:14 ` Bjorn Andersson
2021-03-30 3:22 ` Bjorn Andersson
2021-03-30 3:22 ` Bjorn Andersson
2021-03-30 3:22 ` Bjorn Andersson
2021-06-08 11:42 ` Will Deacon
2021-06-08 11:42 ` Will Deacon
2021-06-08 11:42 ` Will Deacon
2021-07-20 2:30 ` patchwork-bot+linux-arm-msm
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