From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Eric Anholt <eric@anholt.net>
Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
freedreno@lists.freedesktop.org, Rob Clark <robdclark@gmail.com>,
Sean Paul <sean@poorly.run>,
Jordan Crouse <jcrouse@codeaurora.org>,
Robin Murphy <robin.murphy@arm.com>,
Will Deacon <will@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Joerg Roedel <joro@8bytes.org>,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] arm64: dts: msm8996: Mark the GPU's SMMU as an adreno one.
Date: Mon, 29 Mar 2021 22:23:53 -0500 [thread overview]
Message-ID: <YGKZybLYu5xQW9Yn@builder.lan> (raw)
In-Reply-To: <20210326231303.3071950-2-eric@anholt.net>
On Fri 26 Mar 18:13 CDT 2021, Eric Anholt wrote:
> This enables the adreno-specific SMMU path that sets HUPCF so
> (user-managed) page faults don't wedge the GPU.
>
> Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
@Will, can you pick this together with the driver patch? (So that they
land in order)
Regards,
Bjorn
> ---
>
> We've been seeing a flaky test per day or so in Mesa CI where the
> kernel gets wedged after an iommu fault turns into CP errors. With
> this patch, the CI isn't throwing the string of CP errors on the
> faults in any of the ~10 jobs I've run so far.
>
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index 6de136e3add9..432b87ec9c5e 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -1127,7 +1127,7 @@ cci_i2c1: i2c-bus@1 {
> };
>
> adreno_smmu: iommu@b40000 {
> - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
> + compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
> reg = <0x00b40000 0x10000>;
>
> #global-interrupts = <1>;
> --
> 2.31.0
>
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Eric Anholt <eric@anholt.net>
Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
freedreno@lists.freedesktop.org, Rob Clark <robdclark@gmail.com>,
Sean Paul <sean@poorly.run>,
Jordan Crouse <jcrouse@codeaurora.org>,
Robin Murphy <robin.murphy@arm.com>,
Will Deacon <will@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Joerg Roedel <joro@8bytes.org>,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] arm64: dts: msm8996: Mark the GPU's SMMU as an adreno one.
Date: Mon, 29 Mar 2021 22:23:53 -0500 [thread overview]
Message-ID: <YGKZybLYu5xQW9Yn@builder.lan> (raw)
In-Reply-To: <20210326231303.3071950-2-eric@anholt.net>
On Fri 26 Mar 18:13 CDT 2021, Eric Anholt wrote:
> This enables the adreno-specific SMMU path that sets HUPCF so
> (user-managed) page faults don't wedge the GPU.
>
> Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
@Will, can you pick this together with the driver patch? (So that they
land in order)
Regards,
Bjorn
> ---
>
> We've been seeing a flaky test per day or so in Mesa CI where the
> kernel gets wedged after an iommu fault turns into CP errors. With
> this patch, the CI isn't throwing the string of CP errors on the
> faults in any of the ~10 jobs I've run so far.
>
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index 6de136e3add9..432b87ec9c5e 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -1127,7 +1127,7 @@ cci_i2c1: i2c-bus@1 {
> };
>
> adreno_smmu: iommu@b40000 {
> - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
> + compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
> reg = <0x00b40000 0x10000>;
>
> #global-interrupts = <1>;
> --
> 2.31.0
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Eric Anholt <eric@anholt.net>
Cc: freedreno@lists.freedesktop.org, Will Deacon <will@kernel.org>,
devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
Joerg Roedel <joro@8bytes.org>,
Jordan Crouse <jcrouse@codeaurora.org>,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Rob Herring <robh+dt@kernel.org>, Sean Paul <sean@poorly.run>,
linux-arm-kernel@lists.infradead.org,
Robin Murphy <robin.murphy@arm.com>
Subject: Re: [PATCH 2/2] arm64: dts: msm8996: Mark the GPU's SMMU as an adreno one.
Date: Mon, 29 Mar 2021 22:23:53 -0500 [thread overview]
Message-ID: <YGKZybLYu5xQW9Yn@builder.lan> (raw)
In-Reply-To: <20210326231303.3071950-2-eric@anholt.net>
On Fri 26 Mar 18:13 CDT 2021, Eric Anholt wrote:
> This enables the adreno-specific SMMU path that sets HUPCF so
> (user-managed) page faults don't wedge the GPU.
>
> Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
@Will, can you pick this together with the driver patch? (So that they
land in order)
Regards,
Bjorn
> ---
>
> We've been seeing a flaky test per day or so in Mesa CI where the
> kernel gets wedged after an iommu fault turns into CP errors. With
> this patch, the CI isn't throwing the string of CP errors on the
> faults in any of the ~10 jobs I've run so far.
>
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index 6de136e3add9..432b87ec9c5e 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -1127,7 +1127,7 @@ cci_i2c1: i2c-bus@1 {
> };
>
> adreno_smmu: iommu@b40000 {
> - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
> + compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
> reg = <0x00b40000 0x10000>;
>
> #global-interrupts = <1>;
> --
> 2.31.0
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2021-03-30 3:24 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-26 23:13 [PATCH 1/2] iommu/arm-smmu-qcom: Skip the TTBR1 quirk for db820c Eric Anholt
2021-03-26 23:13 ` Eric Anholt
2021-03-26 23:13 ` Eric Anholt
2021-03-26 23:13 ` [PATCH 2/2] arm64: dts: msm8996: Mark the GPU's SMMU as an adreno one Eric Anholt
2021-03-26 23:13 ` Eric Anholt
2021-03-26 23:13 ` Eric Anholt
2021-03-30 3:23 ` Bjorn Andersson [this message]
2021-03-30 3:23 ` Bjorn Andersson
2021-03-30 3:23 ` Bjorn Andersson
2021-03-29 14:47 ` [PATCH 1/2] iommu/arm-smmu-qcom: Skip the TTBR1 quirk for db820c Will Deacon
2021-03-29 14:47 ` Will Deacon
2021-03-29 14:47 ` Will Deacon
2021-03-29 17:55 ` Eric Anholt
2021-03-29 17:55 ` Eric Anholt
2021-03-29 17:55 ` Eric Anholt
2021-03-30 4:02 ` Rob Clark
2021-03-30 4:02 ` Rob Clark
2021-03-30 4:02 ` Rob Clark
2021-03-30 9:34 ` Will Deacon
2021-03-30 9:34 ` Will Deacon
2021-03-30 9:34 ` Will Deacon
2021-03-30 15:03 ` Rob Clark
2021-03-30 15:03 ` Rob Clark
2021-03-30 15:03 ` Rob Clark
2021-03-30 15:31 ` Will Deacon
2021-03-30 15:31 ` Will Deacon
2021-03-30 15:31 ` Will Deacon
2021-03-30 16:07 ` Rob Clark
2021-03-30 16:07 ` Rob Clark
2021-03-30 16:07 ` Rob Clark
2021-05-25 17:14 ` Bjorn Andersson
2021-05-25 17:14 ` Bjorn Andersson
2021-05-25 17:14 ` Bjorn Andersson
2021-03-30 3:22 ` Bjorn Andersson
2021-03-30 3:22 ` Bjorn Andersson
2021-03-30 3:22 ` Bjorn Andersson
2021-06-08 11:42 ` Will Deacon
2021-06-08 11:42 ` Will Deacon
2021-06-08 11:42 ` Will Deacon
2021-07-20 2:30 ` patchwork-bot+linux-arm-msm
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=YGKZybLYu5xQW9Yn@builder.lan \
--to=bjorn.andersson@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=eric@anholt.net \
--cc=freedreno@lists.freedesktop.org \
--cc=jcrouse@codeaurora.org \
--cc=joro@8bytes.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=robdclark@gmail.com \
--cc=robh+dt@kernel.org \
--cc=robin.murphy@arm.com \
--cc=sean@poorly.run \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.