* [PATCH 1/3] clk: mediatek: Add MT8175 clock driver
@ 2021-03-30 14:30 Fabien Parent
2021-03-30 14:30 ` [PATCH 2/3] ARM: mediatek: Add MT8175 support Fabien Parent
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Fabien Parent @ 2021-03-30 14:30 UTC (permalink / raw)
To: u-boot
Add the topckgen, apmixedsys and infracfg clock driver for the MT8175
SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8175.c | 785 +++++++++++++++++++++++++
include/dt-bindings/clock/mt8175-clk.h | 392 ++++++++++++
3 files changed, 1178 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8175.c
create mode 100644 include/dt-bindings/clock/mt8175-clk.h
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 522e72422144..0f3135eca39c 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_MT8512) += clk-mt8512.o
obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
+obj-$(CONFIG_TARGET_MT8175) += clk-mt8175.o
obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
diff --git a/drivers/clk/mediatek/clk-mt8175.c b/drivers/clk/mediatek/clk-mt8175.c
new file mode 100644
index 000000000000..cb5841181d2d
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8175.c
@@ -0,0 +1,785 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8175 SoC
+ *
+ * Copyright (C) 2021 BayLibre, SAS
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Fabien Parent <fparent@baylibre.com>
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt8175-clk.h>
+
+#include "clk-mtk.h"
+
+#define MT8175_PLL_FMAX (3800UL * MHZ)
+#define MT8175_PLL_FMIN (1500UL * MHZ)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .rst_bar_mask = BIT(23), \
+ .fmax = MT8175_PLL_FMAX, \
+ .flags = _flags, \
+ .pcwbits = _pcwbits, \
+ .pcwibits = 8, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001, 0, 22, 0x0310, 24,
+ 0x0310, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0xFF000001, HAVE_RST_BAR, 22,
+ 0x022C, 24, 0x022C, 0),
+ PLL(CLK_APMIXED_UNIVPLL, 0x0208, 0x0214, 0xFF000001, HAVE_RST_BAR, 22,
+ 0x020C, 24, 0x020C, 0),
+ PLL(CLK_APMIXED_MFGPLL, 0x0218, 0x0224, 0x00000001, 0, 22, 0x021C, 24,
+ 0x021C, 0),
+ PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001, 0, 22, 0x0354, 24,
+ 0x0354, 0),
+ PLL(CLK_APMIXED_MMPLL, 0x0330, 0x033C, 0x00000001, 0, 22, 0x0334, 24,
+ 0x0334, 0),
+ PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001, 0, 32, 0x0320, 24,
+ 0x0324, 0),
+ PLL(CLK_APMIXED_APLL2, 0x0360, 0x0370, 0x00000001, 0, 32, 0x0364, 24,
+ 0x0368, 0),
+ PLL(CLK_APMIXED_LVDSPLL, 0x0374, 0x0380, 0x00000001, 0, 22, 0x0378, 24,
+ 0x0378, 0),
+ PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x00000001, 0, 22, 0x0394, 24,
+ 0x0394, 0),
+ PLL(CLK_APMIXED_APUPLL, 0x03A0, 0x03AC, 0x00000001, 0, 22, 0x03A4, 24,
+ 0x03A4, 0),
+};
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 0),
+ FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, CLK_TOP_CLK26M, 75000000),
+ FIXED_CLK(CLK_TOP_VPLL_DPIX, CLK_TOP_CLK26M, 75000000),
+ FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, CLK_TOP_CLK26M, 52500000),
+ FIXED_CLK(CLK_TOP_CLK26M, CLK_XTAL, 26000000),
+ FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+ FACTOR(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL, 1, 2, CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12,
+ CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24,
+ CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_UNIVPLL2_D32, CLK_TOP_UNIVPLL, 1, 96,
+ CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10,
+ CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20,
+ CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_MMPLL, CLK_APMIXED_MMPLL, 1, 1,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_MFGPLL, CLK_APMIXED_MFGPLL, 1, 1,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_LVDSPLL_D2, CLK_APMIXED_LVDSPLL, 1, 2,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_LVDSPLL_D4, CLK_APMIXED_LVDSPLL, 1, 4,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_LVDSPLL_D8, CLK_APMIXED_LVDSPLL, 1, 8,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_LVDSPLL_D16, CLK_APMIXED_LVDSPLL, 1, 16,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_USB20_192M, CLK_TOP_UNIVPLL, 1, 1, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_USB20_192M_D4, CLK_TOP_USB20_192M, 1, 4,
+ CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_USB20_192M_D8, CLK_TOP_USB20_192M, 1, 8,
+ CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_USB20_192M_D16, CLK_TOP_USB20_192M, 1, 16,
+ CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_USB20_192M_D32, CLK_TOP_USB20_192M, 1, 32,
+ CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1, CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_APLL1_D2, CLK_TOP_APLL1, 1, 2, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 4, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_APLL1_D8, CLK_TOP_APLL1, 1, 8, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1, CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_APLL2_D4, CLK_TOP_APLL2, 1, 4, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_APLL2_D8, CLK_TOP_APLL2, 1, 8, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1, CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_DSPPLL, CLK_APMIXED_DSPPLL, 1, 1, CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_DSPPLL_D2, CLK_APMIXED_DSPPLL, 1, 2, CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_DSPPLL_D4, CLK_APMIXED_DSPPLL, 1, 4, CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_DSPPLL_D8, CLK_APMIXED_DSPPLL, 1, 8, CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_APUPLL, CLK_APMIXED_APUPLL, 1, 1, CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_CLK26M_D52, CLK_TOP_CLK26M, 1, 52, CLK_PARENT_TOPCKGEN),
+};
+
+static const int axi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL_D7,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYSPLL3_D2
+};
+
+static const int mem_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MMPLL,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_SYSPLL1_D2
+};
+
+static const int mm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MMPLL,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_SYSPLL_D5,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_UNIVPLL_D5,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_MMPLL_D2,
+};
+
+static const int scp_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL4_D2,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_UNIVPLL_D3
+};
+
+static const int mfg_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MFGPLL,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_UNIVPLL_D3
+};
+
+static const int atb_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYSPLL1_D2
+};
+
+static const int camtg_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_USB20_192M_D8,
+ CLK_TOP_UNIVPLL2_D8,
+ CLK_TOP_USB20_192M_D4,
+ CLK_TOP_UNIVPLL2_D32,
+ CLK_TOP_USB20_192M_D16,
+ CLK_TOP_USB20_192M_D32,
+};
+
+static const int uart_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const int spi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const int msdc50_0_hc_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_SYSPLL2_D2
+};
+
+static const int msdc50_0_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MSDCPLL,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL_D5,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_SYSPLL4_D2
+};
+
+static const int msdc50_2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MSDCPLL,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4
+};
+
+static const int msdc30_1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MSDCPLL_D2,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYSPLL2_D4,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const int audio_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL3_D4,
+ CLK_TOP_SYSPLL4_D4,
+ CLK_TOP_SYSPLL1_D16
+};
+
+static const int aud_intbus_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYSPLL4_D2
+};
+
+static const int aud_1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL1
+};
+
+static const int aud_2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL2
+};
+
+static const int aud_engen1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL1_D2,
+ CLK_TOP_APLL1_D4,
+ CLK_TOP_APLL1_D8
+};
+
+static const int aud_engen2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL2_D2,
+ CLK_TOP_APLL2_D4,
+ CLK_TOP_APLL2_D8,
+};
+
+static const int aud_spdif_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D2
+};
+
+static const int disp_pwm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D4
+};
+
+static const int dxcc_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYSPLL1_D8
+};
+
+static const int ssusb_sys_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_UNIVPLL3_D2
+};
+
+static const int spm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D8
+};
+
+static const int i2c_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_UNIVPLL3_D2,
+ CLK_TOP_SYSPLL1_D8,
+ CLK_TOP_SYSPLL2_D8
+};
+
+static const int pwm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_SYSPLL1_D8
+};
+
+static const int senif_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_UNIVPLL2_D2
+};
+
+static const int aes_fde_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MSDCPLL,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D2
+};
+
+static const int dpi0_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_LVDSPLL_D2,
+ CLK_TOP_LVDSPLL_D4,
+ CLK_TOP_LVDSPLL_D8,
+ CLK_TOP_LVDSPLL_D16
+};
+
+static const int dsp_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYS_26M_D2,
+ CLK_TOP_DSPPLL,
+ CLK_TOP_DSPPLL_D2,
+ CLK_TOP_DSPPLL_D4,
+ CLK_TOP_DSPPLL_D8
+};
+
+static const int nfi2x_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_SYSPLL_D7,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_SYSPLL2_D4,
+ CLK_TOP_MSDCPLL_D2,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_UNIVPLL_D5
+};
+
+static const int nfiecc_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL4_D2,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_SYSPLL_D7,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL_D5
+};
+
+static const int ecc_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_SYSPLL_D2
+};
+
+static const int eth_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D8,
+ CLK_TOP_SYSPLL4_D4,
+ CLK_TOP_SYSPLL1_D8,
+ CLK_TOP_SYSPLL4_D2
+};
+
+static const int gcpu_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_SYSPLL2_D2
+};
+
+static const int gcpu_cpm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL2_D2
+};
+
+static const int apu_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D2,
+ CLK_APMIXED_APUPLL,
+ CLK_TOP_MMPLL,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_SYSPLL1_D4
+};
+
+static const struct mtk_composite top_muxes[] = {
+ /* CLK_CFG_0 */
+ MUX(CLK_TOP_AXI_SEL, axi_parents, 0x040, 0, 2),
+ MUX(CLK_TOP_MEM_SEL, mem_parents, 0x040, 8, 2),
+ MUX(CLK_TOP_MM_SEL, mm_parents, 0x040, 16, 3),
+ MUX(CLK_TOP_SCP_SEL, scp_parents, 0x040, 24, 3),
+ /* CLK_CFG_1 */
+ MUX(CLK_TOP_MFG_SEL, mfg_parents, 0x050, 0, 2),
+ MUX(CLK_TOP_ATB_SEL, atb_parents, 0x050, 8, 2),
+ MUX(CLK_TOP_CAMTG_SEL, camtg_parents, 0x050, 16, 3),
+ MUX(CLK_TOP_CAMTG1_SEL, camtg_parents, 0x050, 24, 3),
+ /* CLK_CFG_2 */
+ MUX(CLK_TOP_UART_SEL, uart_parents, 0x060, 0, 1),
+ MUX(CLK_TOP_SPI_SEL, spi_parents, 0x060, 8, 2),
+ MUX(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents, 0x060, 16, 2),
+ MUX(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents, 0x060, 24, 2),
+ /* CLK_CFG_3 */
+ MUX(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, 0x070, 0, 3),
+ MUX(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents, 0x070, 8, 3),
+ MUX(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x070, 16, 3),
+ MUX(CLK_TOP_AUDIO_SEL, audio_parents, 0x070, 24, 2),
+ /* CLK_CFG_4 */
+ MUX(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x080, 0, 2),
+ MUX(CLK_TOP_AUD_1_SEL, aud_1_parents, 0x080, 8, 1),
+ MUX(CLK_TOP_AUD_2_SEL, aud_2_parents, 0x080, 16, 1),
+ MUX(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x080, 24, 2),
+ /* CLK_CFG_5 */
+ MUX(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x090, 0, 2),
+ MUX(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents, 0x090, 8, 1),
+ MUX(CLK_TOP_DISP_PWM_SEL, disp_pwm_parents, 0x090, 16, 2),
+ /* CLK_CFG_6 */
+ MUX(CLK_TOP_DXCC_SEL, dxcc_parents, 0x0a0, 0, 2),
+ MUX(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents, 0x0a0, 8, 2),
+ MUX(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents, 0x0a0, 16, 2),
+ MUX(CLK_TOP_SPM_SEL, spm_parents, 0x0a0, 24, 1),
+ /* CLK_CFG_7 */
+ MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x0b0, 0, 3),
+ MUX(CLK_TOP_PWM_SEL, pwm_parents, 0x0b0, 8, 2),
+ MUX(CLK_TOP_SENIF_SEL, senif_parents, 0x0b0, 16, 2),
+ MUX(CLK_TOP_AES_FDE_SEL, aes_fde_parents, 0x0b0, 24, 3),
+ /* CLK_CFG_8 */
+ MUX(CLK_TOP_CAMTM_SEL, senif_parents, 0x0c0, 0, 2),
+ MUX(CLK_TOP_DPI0_SEL, dpi0_parents, 0x0c0, 8, 3),
+ MUX(CLK_TOP_DPI1_SEL, dpi0_parents, 0x0c0, 16, 3),
+ MUX(CLK_TOP_DSP_SEL, dsp_parents, 0x0c0, 24, 3),
+ /* CLK_CFG_9 */
+ MUX(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x0d0, 0, 3),
+ MUX(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x0d0, 8, 3),
+ MUX(CLK_TOP_ECC_SEL, ecc_parents, 0x0d0, 16, 3),
+ MUX(CLK_TOP_ETH_SEL, eth_parents, 0x0d0, 24, 3),
+ /* CLK_CFG_10 */
+ MUX(CLK_TOP_GCPU_SEL, gcpu_parents, 0x0e0, 0, 3),
+ MUX(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents, 0x0e0, 8, 2),
+ MUX(CLK_TOP_APU_SEL, apu_parents, 0x0e0, 16, 3),
+ MUX(CLK_TOP_APU_IF_SEL, apu_parents, 0x0e0, 24, 3),
+};
+
+static const struct mtk_clk_tree mt8175_clk_tree = {
+ .xtal_rate = 26 * MHZ,
+ .xtal2_rate = 26 * MHZ,
+ .fdivs_offs = CLK_TOP_SYSPLL_D2,
+ .muxes_offs = CLK_TOP_AXI_SEL,
+ .plls = apmixed_plls,
+ .fclks = top_fixed_clks,
+ .fdivs = top_fixed_divs,
+ .muxes = top_muxes,
+};
+
+static const struct mtk_gate_regs infra2_cg_regs = {
+ .set_ofs = 0x80,
+ .clr_ofs = 0x84,
+ .sta_ofs = 0x90,
+};
+
+static const struct mtk_gate_regs infra3_cg_regs = {
+ .set_ofs = 0x88,
+ .clr_ofs = 0x8c,
+ .sta_ofs = 0x94,
+};
+
+static const struct mtk_gate_regs infra4_cg_regs = {
+ .set_ofs = 0xa4,
+ .clr_ofs = 0xa8,
+ .sta_ofs = 0xac,
+};
+
+static const struct mtk_gate_regs infra5_cg_regs = {
+ .set_ofs = 0xc0,
+ .clr_ofs = 0xc4,
+ .sta_ofs = 0xc8,
+};
+
+static const struct mtk_gate_regs infra6_cg_regs = {
+ .set_ofs = 0xd0,
+ .clr_ofs = 0xd4,
+ .sta_ofs = 0xd8,
+};
+
+#define GATE_INFRA2(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_INFRA3(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra3_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_INFRA4(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra4_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_INFRA5(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra5_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_INFRA6(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra6_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate infra_clks[] = {
+ /* IFR2 */
+ GATE_INFRA2(CLK_IFR_PMIC_TMR, CLK_TOP_CLK26M, 0),
+ GATE_INFRA2(CLK_IFR_PMIC_AP, CLK_TOP_CLK26M, 1),
+ GATE_INFRA2(CLK_IFR_PMIC_MD, CLK_TOP_CLK26M, 2),
+ GATE_INFRA2(CLK_IFR_PMIC_CONN, CLK_TOP_CLK26M, 3),
+ GATE_INFRA2(CLK_IFR_ICUSB, CLK_TOP_AXI_SEL, 8),
+ GATE_INFRA2(CLK_IFR_GCE, CLK_TOP_AXI_SEL, 9),
+ GATE_INFRA2(CLK_IFR_THERM, CLK_TOP_AXI_SEL, 10),
+ GATE_INFRA2(CLK_IFR_PWM_HCLK, CLK_TOP_AXI_SEL, 15),
+ GATE_INFRA2(CLK_IFR_PWM1, CLK_TOP_PWM_SEL, 16),
+ GATE_INFRA2(CLK_IFR_PWM2, CLK_TOP_PWM_SEL, 17),
+ GATE_INFRA2(CLK_IFR_PWM3, CLK_TOP_PWM_SEL, 18),
+ GATE_INFRA2(CLK_IFR_PWM4, CLK_TOP_PWM_SEL, 19),
+ GATE_INFRA2(CLK_IFR_PWM5, CLK_TOP_PWM_SEL, 20),
+ GATE_INFRA2(CLK_IFR_PWM, CLK_TOP_PWM_SEL, 21),
+ GATE_INFRA2(CLK_IFR_UART0, CLK_TOP_UART_SEL, 22),
+ GATE_INFRA2(CLK_IFR_UART1, CLK_TOP_UART_SEL, 23),
+ GATE_INFRA2(CLK_IFR_UART2, CLK_TOP_UART_SEL, 24),
+ GATE_INFRA2(CLK_IFR_DSP_UART, CLK_TOP_UART_SEL, 26),
+ GATE_INFRA2(CLK_IFR_GCE_26M, CLK_TOP_CLK26M, 27),
+ GATE_INFRA2(CLK_IFR_CQ_DMA_FPC, CLK_TOP_AXI_SEL, 28),
+ GATE_INFRA2(CLK_IFR_BTIF, CLK_TOP_AXI_SEL, 31),
+ /* IFR3 */
+ GATE_INFRA3(CLK_IFR_SPI0, CLK_TOP_SPI_SEL, 1),
+ GATE_INFRA3(CLK_IFR_MSDC0_HCLK, CLK_TOP_MSDC50_0_HC_SEL, 2),
+ GATE_INFRA3(CLK_IFR_MSDC2_HCLK, CLK_TOP_MSDC2_2_HC_SEL, 3),
+ GATE_INFRA3(CLK_IFR_MSDC1_HCLK, CLK_TOP_AXI_SEL, 4),
+ GATE_INFRA3(CLK_IFR_DVFSRC, CLK_TOP_CLK26M, 7),
+ GATE_INFRA3(CLK_IFR_GCPU, CLK_TOP_AXI_SEL, 8),
+ GATE_INFRA3(CLK_IFR_TRNG, CLK_TOP_AXI_SEL, 9),
+ GATE_INFRA3(CLK_IFR_AUXADC, CLK_TOP_CLK26M, 10),
+ GATE_INFRA3(CLK_IFR_AUXADC_MD, CLK_TOP_CLK26M, 14),
+ GATE_INFRA3(CLK_IFR_AP_DMA, CLK_TOP_AXI_SEL, 18),
+ GATE_INFRA3(CLK_IFR_DEBUGSYS, CLK_TOP_AXI_SEL, 24),
+ GATE_INFRA3(CLK_IFR_AUDIO, CLK_TOP_AXI_SEL, 25),
+ /* IFR4 */
+ GATE_INFRA4(CLK_IFR_PWM_FBCLK6, CLK_TOP_PWM_SEL, 0),
+ GATE_INFRA4(CLK_IFR_DISP_PWM, CLK_TOP_DISP_PWM_SEL, 2),
+ GATE_INFRA4(CLK_IFR_AUD_26M_BK, CLK_TOP_CLK26M, 4),
+ GATE_INFRA4(CLK_IFR_CQ_DMA, CLK_TOP_AXI_SEL, 27),
+ /* IFR5 */
+ GATE_INFRA5(CLK_IFR_MSDC0_SF, CLK_TOP_MSDC50_0_SEL, 0),
+ GATE_INFRA5(CLK_IFR_MSDC1_SF, CLK_TOP_MSDC50_0_SEL, 1),
+ GATE_INFRA5(CLK_IFR_MSDC2_SF, CLK_TOP_MSDC50_0_SEL, 2),
+ GATE_INFRA5(CLK_IFR_AP_MSDC0, CLK_TOP_MSDC50_0_SEL, 7),
+ GATE_INFRA5(CLK_IFR_MD_MSDC0, CLK_TOP_MSDC50_0_SEL, 8),
+ GATE_INFRA5(CLK_IFR_MSDC0_SRC, CLK_TOP_MSDC50_0_SEL, 9),
+ GATE_INFRA5(CLK_IFR_MSDC1_SRC, CLK_TOP_MSDC30_1_SEL, 10),
+ GATE_INFRA5(CLK_IFR_MSDC2_SRC, CLK_TOP_MSDC50_2_SEL, 11),
+ GATE_INFRA5(CLK_IFR_PWRAP_TMR, CLK_TOP_CLK26M, 12),
+ GATE_INFRA5(CLK_IFR_PWRAP_SPI, CLK_TOP_CLK26M, 13),
+ GATE_INFRA5(CLK_IFR_PWRAP_SYS, CLK_TOP_CLK26M, 14),
+ GATE_INFRA5(CLK_IFR_IRRX_26M, CLK_TOP_CLK26M, 22),
+ GATE_INFRA5(CLK_IFR_IRRX_32K, CLK_TOP_CLK32K, 23),
+ GATE_INFRA5(CLK_IFR_I2C0_AXI, CLK_TOP_I2C_SEL, 24),
+ GATE_INFRA5(CLK_IFR_I2C1_AXI, CLK_TOP_I2C_SEL, 25),
+ GATE_INFRA5(CLK_IFR_I2C2_AXI, CLK_TOP_I2C_SEL, 26),
+ GATE_INFRA5(CLK_IFR_I2C3_AXI, CLK_TOP_I2C_SEL, 27),
+ GATE_INFRA5(CLK_IFR_NIC_AXI, CLK_TOP_AXI_SEL, 28),
+ GATE_INFRA5(CLK_IFR_NIC_SLV_AXI, CLK_TOP_AXI_SEL, 29),
+ GATE_INFRA5(CLK_IFR_APU_AXI, CLK_TOP_AXI_SEL, 30),
+ /* IFR6 */
+ GATE_INFRA6(CLK_IFR_NFIECC, CLK_TOP_NFIECC_SEL, 0),
+ GATE_INFRA6(CLK_IFR_NFI1X_BK, CLK_TOP_NFI2X_SEL, 1),
+ GATE_INFRA6(CLK_IFR_NFIECC_BK, CLK_TOP_NFI2X_SEL, 2),
+ GATE_INFRA6(CLK_IFR_NFI_BK, CLK_TOP_AXI_SEL, 3),
+ GATE_INFRA6(CLK_IFR_MSDC2_AP_BK, CLK_TOP_AXI_SEL, 4),
+ GATE_INFRA6(CLK_IFR_MSDC2_MD_BK, CLK_TOP_AXI_SEL, 5),
+ GATE_INFRA6(CLK_IFR_MSDC2_BK, CLK_TOP_AXI_SEL, 6),
+ GATE_INFRA6(CLK_IFR_SUSB_133_BK, CLK_TOP_AXI_SEL, 7),
+ GATE_INFRA6(CLK_IFR_SUSB_66_BK, CLK_TOP_AXI_SEL, 8),
+ GATE_INFRA6(CLK_IFR_SSUSB_SYS, CLK_TOP_SSUSB_SYS_SEL, 9),
+ GATE_INFRA6(CLK_IFR_SSUSB_REF, CLK_TOP_SSUSB_SYS_SEL, 10),
+ GATE_INFRA6(CLK_IFR_SSUSB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11),
+};
+
+static const struct mtk_gate_regs top0_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x0,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x104,
+ .sta_ofs = 0x104,
+};
+
+#define GATE_TOP0(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP1_I(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate top_clks[] = {
+ /* TOP0 */
+ GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10),
+ GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11),
+ GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16),
+ GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17),
+ /* TOP1 */
+ GATE_TOP1_I(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4, 8),
+ GATE_TOP1_I(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4, 9),
+ GATE_TOP1_I(CLK_TOP_LVDSTX_CLKDIG_EN, CLK_TOP_LVDSTX_CLKDIG_CTS, 20),
+ GATE_TOP1_I(CLK_TOP_VPLL_DPIX_EN, CLK_TOP_VPLL_DPIX, 21),
+ GATE_TOP1_I(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22),
+ GATE_TOP1_I(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23),
+};
+
+static int mt8175_apmixedsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8175_clk_tree);
+}
+
+static int mt8175_topckgen_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8175_clk_tree);
+}
+
+static int mt8175_topckgen_cg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt8175_clk_tree, top_clks);
+}
+
+static int mt8175_infracfg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt8175_clk_tree, infra_clks);
+}
+
+static const struct udevice_id mt8175_apmixed_compat[] = {
+ { .compatible = "mediatek,mt8175-apmixedsys", },
+ { }
+};
+
+static const struct udevice_id mt8175_topckgen_compat[] = {
+ { .compatible = "mediatek,mt8175-topckgen", },
+ { }
+};
+
+static const struct udevice_id mt8175_topckgen_cg_compat[] = {
+ { .compatible = "mediatek,mt8175-topckgen-cg", },
+ { }
+};
+
+static const struct udevice_id mt8175_infracfg_compat[] = {
+ { .compatible = "mediatek,mt8175-infracfg", },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+ .name = "mt8175-apmixedsys",
+ .id = UCLASS_CLK,
+ .of_match = mt8175_apmixed_compat,
+ .probe = mt8175_apmixedsys_probe,
+ .priv_auto = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_apmixedsys_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+ .name = "mt8175-topckgen",
+ .id = UCLASS_CLK,
+ .of_match = mt8175_topckgen_compat,
+ .probe = mt8175_topckgen_probe,
+ .priv_auto = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_topckgen_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
+ .name = "mt8175-topckgen-cg",
+ .id = UCLASS_CLK,
+ .of_match = mt8175_topckgen_cg_compat,
+ .probe = mt8175_topckgen_cg_probe,
+ .priv_auto = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_infracfg) = {
+ .name = "mt8175-infracfg",
+ .id = UCLASS_CLK,
+ .of_match = mt8175_infracfg_compat,
+ .probe = mt8175_infracfg_probe,
+ .priv_auto = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/include/dt-bindings/clock/mt8175-clk.h b/include/dt-bindings/clock/mt8175-clk.h
new file mode 100644
index 000000000000..4f5992db3ec9
--- /dev/null
+++ b/include/dt-bindings/clock/mt8175-clk.h
@@ -0,0 +1,392 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8175_H
+#define _DT_BINDINGS_CLK_MT8175_H
+
+/* TOPCKGEN */
+
+#define CLK_TOP_CLK_NULL 0
+#define CLK_TOP_DSI0_LNTC_DSICK 1
+#define CLK_TOP_VPLL_DPIX 2
+#define CLK_TOP_LVDSTX_CLKDIG_CTS 3
+#define CLK_TOP_CLK26M 4
+#define CLK_TOP_CLK32K 5
+#define CLK_TOP_I2S0_BCK 6
+#define CLK_TOP_SYS_26M_D2 7
+#define CLK_TOP_SYSPLL_D2 8
+#define CLK_TOP_SYSPLL1_D2 9
+#define CLK_TOP_SYSPLL1_D4 10
+#define CLK_TOP_SYSPLL1_D8 11
+#define CLK_TOP_SYSPLL1_D16 12
+#define CLK_TOP_SYSPLL_D3 13
+#define CLK_TOP_SYSPLL2_D2 14
+#define CLK_TOP_SYSPLL2_D4 15
+#define CLK_TOP_SYSPLL2_D8 16
+#define CLK_TOP_SYSPLL_D5 17
+#define CLK_TOP_SYSPLL3_D2 18
+#define CLK_TOP_SYSPLL3_D4 19
+#define CLK_TOP_SYSPLL_D7 20
+#define CLK_TOP_SYSPLL4_D2 21
+#define CLK_TOP_SYSPLL4_D4 22
+#define CLK_TOP_UNIVPLL 23
+#define CLK_TOP_UNIVPLL_D2 24
+#define CLK_TOP_UNIVPLL1_D2 25
+#define CLK_TOP_UNIVPLL1_D4 26
+#define CLK_TOP_UNIVPLL_D3 27
+#define CLK_TOP_UNIVPLL2_D2 28
+#define CLK_TOP_UNIVPLL2_D4 29
+#define CLK_TOP_UNIVPLL2_D8 30
+#define CLK_TOP_UNIVPLL2_D32 31
+#define CLK_TOP_UNIVPLL_D5 32
+#define CLK_TOP_UNIVPLL3_D2 33
+#define CLK_TOP_UNIVPLL3_D4 34
+#define CLK_TOP_MMPLL 35
+#define CLK_TOP_MMPLL_D2 36
+#define CLK_TOP_MFGPLL 37
+#define CLK_TOP_LVDSPLL_D2 38
+#define CLK_TOP_LVDSPLL_D4 39
+#define CLK_TOP_LVDSPLL_D8 40
+#define CLK_TOP_LVDSPLL_D16 41
+#define CLK_TOP_USB20_192M 42
+#define CLK_TOP_USB20_192M_D4 43
+#define CLK_TOP_USB20_192M_D8 44
+#define CLK_TOP_USB20_192M_D16 45
+#define CLK_TOP_USB20_192M_D32 46
+#define CLK_TOP_APLL1 47
+#define CLK_TOP_APLL1_D2 48
+#define CLK_TOP_APLL1_D4 49
+#define CLK_TOP_APLL1_D8 50
+#define CLK_TOP_APLL2 51
+#define CLK_TOP_APLL2_D2 52
+#define CLK_TOP_APLL2_D4 53
+#define CLK_TOP_APLL2_D8 54
+#define CLK_TOP_MSDCPLL 55
+#define CLK_TOP_MSDCPLL_D2 56
+#define CLK_TOP_DSPPLL 57
+#define CLK_TOP_DSPPLL_D2 58
+#define CLK_TOP_DSPPLL_D4 59
+#define CLK_TOP_DSPPLL_D8 60
+#define CLK_TOP_APUPLL 61
+#define CLK_TOP_CLK26M_D52 62
+#define CLK_TOP_AXI_SEL 63
+#define CLK_TOP_MEM_SEL 64
+#define CLK_TOP_MM_SEL 65
+#define CLK_TOP_SCP_SEL 66
+#define CLK_TOP_MFG_SEL 67
+#define CLK_TOP_ATB_SEL 68
+#define CLK_TOP_CAMTG_SEL 69
+#define CLK_TOP_CAMTG1_SEL 70
+#define CLK_TOP_UART_SEL 71
+#define CLK_TOP_SPI_SEL 72
+#define CLK_TOP_MSDC50_0_HC_SEL 73
+#define CLK_TOP_MSDC2_2_HC_SEL 74
+#define CLK_TOP_MSDC50_0_SEL 75
+#define CLK_TOP_MSDC50_2_SEL 76
+#define CLK_TOP_MSDC30_1_SEL 77
+#define CLK_TOP_AUDIO_SEL 78
+#define CLK_TOP_AUD_INTBUS_SEL 79
+#define CLK_TOP_AUD_1_SEL 80
+#define CLK_TOP_AUD_2_SEL 81
+#define CLK_TOP_AUD_ENGEN1_SEL 82
+#define CLK_TOP_AUD_ENGEN2_SEL 83
+#define CLK_TOP_AUD_SPDIF_SEL 84
+#define CLK_TOP_DISP_PWM_SEL 85
+#define CLK_TOP_DXCC_SEL 86
+#define CLK_TOP_SSUSB_SYS_SEL 87
+#define CLK_TOP_SSUSB_XHCI_SEL 88
+#define CLK_TOP_SPM_SEL 89
+#define CLK_TOP_I2C_SEL 90
+#define CLK_TOP_PWM_SEL 91
+#define CLK_TOP_SENIF_SEL 92
+#define CLK_TOP_AES_FDE_SEL 93
+#define CLK_TOP_CAMTM_SEL 94
+#define CLK_TOP_DPI0_SEL 95
+#define CLK_TOP_DPI1_SEL 96
+#define CLK_TOP_DSP_SEL 97
+#define CLK_TOP_NFI2X_SEL 98
+#define CLK_TOP_NFIECC_SEL 99
+#define CLK_TOP_ECC_SEL 100
+#define CLK_TOP_ETH_SEL 101
+#define CLK_TOP_GCPU_SEL 102
+#define CLK_TOP_GCPU_CPM_SEL 103
+#define CLK_TOP_APU_SEL 104
+#define CLK_TOP_APU_IF_SEL 105
+#define CLK_TOP_MBIST_DIAG_SEL 106
+#define CLK_TOP_APLL_I2S0_SEL 107
+#define CLK_TOP_APLL_I2S1_SEL 108
+#define CLK_TOP_APLL_I2S2_SEL 109
+#define CLK_TOP_APLL_I2S3_SEL 110
+#define CLK_TOP_APLL_TDMOUT_SEL 111
+#define CLK_TOP_APLL_TDMIN_SEL 112
+#define CLK_TOP_APLL_SPDIF_SEL 113
+#define CLK_TOP_APLL12_CK_DIV0 114
+#define CLK_TOP_APLL12_CK_DIV1 115
+#define CLK_TOP_APLL12_CK_DIV2 116
+#define CLK_TOP_APLL12_CK_DIV3 117
+#define CLK_TOP_APLL12_CK_DIV4 118
+#define CLK_TOP_APLL12_CK_DIV4B 119
+#define CLK_TOP_APLL12_CK_DIV5 120
+#define CLK_TOP_APLL12_CK_DIV5B 121
+#define CLK_TOP_APLL12_CK_DIV6 122
+#define CLK_TOP_NR_CLK 123
+
+/* TOPCKGEN Gates */
+#define CLK_TOP_CONN_32K 0
+#define CLK_TOP_CONN_26M 1
+#define CLK_TOP_DSP_32K 2
+#define CLK_TOP_DSP_26M 3
+#define CLK_TOP_USB20_48M_EN 4
+#define CLK_TOP_UNIVPLL_48M_EN 5
+#define CLK_TOP_LVDSTX_CLKDIG_EN 6
+#define CLK_TOP_VPLL_DPIX_EN 7
+#define CLK_TOP_SSUSB_TOP_CK_EN 8
+#define CLK_TOP_SSUSB_PHY_CK_EN 9
+#define CLK_TOP_AUD_I2S0_M 10
+#define CLK_TOP_AUD_I2S1_M 11
+#define CLK_TOP_AUD_I2S2_M 12
+#define CLK_TOP_AUD_I2S3_M 13
+#define CLK_TOP_AUD_TDMOUT_M 14
+#define CLK_TOP_AUD_TDMOUT_B 15
+#define CLK_TOP_AUD_TDMIN_M 16
+#define CLK_TOP_AUD_TDMIN_B 17
+#define CLK_TOP_AUD_SPDIF_M 18
+
+/* INFRACFG */
+
+#define CLK_IFR_PMIC_TMR 0
+#define CLK_IFR_PMIC_AP 1
+#define CLK_IFR_PMIC_MD 2
+#define CLK_IFR_PMIC_CONN 3
+#define CLK_IFR_ICUSB 4
+#define CLK_IFR_GCE 5
+#define CLK_IFR_THERM 6
+#define CLK_IFR_PWM_HCLK 7
+#define CLK_IFR_PWM1 8
+#define CLK_IFR_PWM2 9
+#define CLK_IFR_PWM3 10
+#define CLK_IFR_PWM4 11
+#define CLK_IFR_PWM5 12
+#define CLK_IFR_PWM 13
+#define CLK_IFR_UART0 14
+#define CLK_IFR_UART1 15
+#define CLK_IFR_UART2 16
+#define CLK_IFR_DSP_UART 17
+#define CLK_IFR_GCE_26M 18
+#define CLK_IFR_CQ_DMA_FPC 19
+#define CLK_IFR_BTIF 20
+#define CLK_IFR_SPI0 21
+#define CLK_IFR_MSDC0_HCLK 22
+#define CLK_IFR_MSDC2_HCLK 23
+#define CLK_IFR_MSDC1_HCLK 24
+#define CLK_IFR_DVFSRC 25
+#define CLK_IFR_GCPU 26
+#define CLK_IFR_TRNG 27
+#define CLK_IFR_AUXADC 28
+#define CLK_IFR_AUXADC_MD 29
+#define CLK_IFR_AP_DMA 30
+#define CLK_IFR_DEBUGSYS 31
+#define CLK_IFR_AUDIO 32
+#define CLK_IFR_PWM_FBCLK6 33
+#define CLK_IFR_DISP_PWM 34
+#define CLK_IFR_AUD_26M_BK 35
+#define CLK_IFR_CQ_DMA 36
+#define CLK_IFR_MSDC0_SF 37
+#define CLK_IFR_MSDC1_SF 38
+#define CLK_IFR_MSDC2_SF 39
+#define CLK_IFR_AP_MSDC0 40
+#define CLK_IFR_MD_MSDC0 41
+#define CLK_IFR_MSDC0_SRC 42
+#define CLK_IFR_MSDC1_SRC 43
+#define CLK_IFR_MSDC2_SRC 44
+#define CLK_IFR_PWRAP_TMR 45
+#define CLK_IFR_PWRAP_SPI 46
+#define CLK_IFR_PWRAP_SYS 47
+#define CLK_IFR_IRRX_26M 48
+#define CLK_IFR_IRRX_32K 49
+#define CLK_IFR_I2C0_AXI 50
+#define CLK_IFR_I2C1_AXI 51
+#define CLK_IFR_I2C2_AXI 52
+#define CLK_IFR_I2C3_AXI 53
+#define CLK_IFR_NIC_AXI 54
+#define CLK_IFR_NIC_SLV_AXI 55
+#define CLK_IFR_APU_AXI 56
+#define CLK_IFR_NFIECC 57
+#define CLK_IFR_NFI1X_BK 58
+#define CLK_IFR_NFIECC_BK 59
+#define CLK_IFR_NFI_BK 60
+#define CLK_IFR_MSDC2_AP_BK 61
+#define CLK_IFR_MSDC2_MD_BK 62
+#define CLK_IFR_MSDC2_BK 63
+#define CLK_IFR_SUSB_133_BK 64
+#define CLK_IFR_SUSB_66_BK 65
+#define CLK_IFR_SSUSB_SYS 66
+#define CLK_IFR_SSUSB_REF 67
+#define CLK_IFR_SSUSB_XHCI 68
+#define CLK_IFR_NR_CLK 69
+
+/* PERICFG */
+
+#define CLK_PERIAXI 0
+#define CLK_PERI_NR_CLK 1
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL 0
+#define CLK_APMIXED_MAINPLL 1
+#define CLK_APMIXED_UNIVPLL 2
+#define CLK_APMIXED_MFGPLL 3
+#define CLK_APMIXED_MSDCPLL 4
+#define CLK_APMIXED_MMPLL 5
+#define CLK_APMIXED_APLL1 6
+#define CLK_APMIXED_APLL2 7
+#define CLK_APMIXED_LVDSPLL 8
+#define CLK_APMIXED_DSPPLL 9
+#define CLK_APMIXED_APUPLL 10
+#define CLK_APMIXED_NR_CLK 11
+
+/* GCE */
+
+#define CLK_GCE_FAXI 0
+#define CLK_GCE_NR_CLK 1
+
+/* AUDIOTOP */
+
+#define CLK_AUD_AFE 0
+#define CLK_AUD_I2S 1
+#define CLK_AUD_22M 2
+#define CLK_AUD_24M 3
+#define CLK_AUD_INTDIR 4
+#define CLK_AUD_APLL2_TUNER 5
+#define CLK_AUD_APLL_TUNER 6
+#define CLK_AUD_SPDF 7
+#define CLK_AUD_HDMI 8
+#define CLK_AUD_HDMI_IN 9
+#define CLK_AUD_ADC 10
+#define CLK_AUD_DAC 11
+#define CLK_AUD_DAC_PREDIS 12
+#define CLK_AUD_TML 13
+#define CLK_AUD_I2S1_BK 14
+#define CLK_AUD_I2S2_BK 15
+#define CLK_AUD_I2S3_BK 16
+#define CLK_AUD_I2S4_BK 17
+#define CLK_AUD_NR_CLK 18
+
+/* MIPI_CSI0A */
+
+#define CLK_MIPI0A_CSR_CSI_EN_0A 0
+#define CLK_MIPI_RX_ANA_CSI0A_NR_CLK 1
+
+/* MIPI_CSI0B */
+
+#define CLK_MIPI0B_CSR_CSI_EN_0B 0
+#define CLK_MIPI_RX_ANA_CSI0B_NR_CLK 1
+
+/* MIPI_CSI1A */
+
+#define CLK_MIPI1A_CSR_CSI_EN_1A 0
+#define CLK_MIPI_RX_ANA_CSI1A_NR_CLK 1
+
+/* MIPI_CSI1B */
+
+#define CLK_MIPI1B_CSR_CSI_EN_1B 0
+#define CLK_MIPI_RX_ANA_CSI1B_NR_CLK 1
+
+/* MIPI_CSI2A */
+
+#define CLK_MIPI2A_CSR_CSI_EN_2A 0
+#define CLK_MIPI_RX_ANA_CSI2A_NR_CLK 1
+
+/* MIPI_CSI2B */
+
+#define CLK_MIPI2B_CSR_CSI_EN_2B 0
+#define CLK_MIPI_RX_ANA_CSI2B_NR_CLK 1
+
+/* MCUCFG */
+
+#define CLK_MCU_BUS_SEL 0
+#define CLK_MCU_NR_CLK 1
+
+/* MFGCFG */
+
+#define CLK_MFG_BG3D 0
+#define CLK_MFG_MBIST_DIAG 1
+#define CLK_MFG_NR_CLK 2
+
+/* MMSYS */
+
+#define CLK_MM_MM_MDP_RDMA0 0
+#define CLK_MM_MM_MDP_CCORR0 1
+#define CLK_MM_MM_MDP_RSZ0 2
+#define CLK_MM_MM_MDP_RSZ1 3
+#define CLK_MM_MM_MDP_TDSHP0 4
+#define CLK_MM_MM_MDP_WROT0 5
+#define CLK_MM_MM_MDP_WDMA0 6
+#define CLK_MM_MM_DISP_OVL0 7
+#define CLK_MM_MM_DISP_OVL0_21 8
+#define CLK_MM_MM_DISP_RSZ0 9
+#define CLK_MM_MM_DISP_RDMA0 10
+#define CLK_MM_MM_DISP_WDMA0 11
+#define CLK_MM_MM_DISP_COLOR0 12
+#define CLK_MM_MM_DISP_CCORR0 13
+#define CLK_MM_MM_DISP_AAL0 14
+#define CLK_MM_MM_DISP_GAMMA0 15
+#define CLK_MM_MM_DISP_DITHER0 16
+#define CLK_MM_MM_DSI0 17
+#define CLK_MM_MM_DISP_RDMA1 18
+#define CLK_MM_MM_MDP_RDMA1 19
+#define CLK_MM_DPI0_DPI0 20
+#define CLK_MM_MM_FAKE 21
+#define CLK_MM_MM_SMI_COMMON 22
+#define CLK_MM_MM_SMI_LARB0 23
+#define CLK_MM_MM_SMI_COMM0 24
+#define CLK_MM_MM_SMI_COMM1 25
+#define CLK_MM_MM_CAM_MDP 26
+#define CLK_MM_MM_SMI_IMG 27
+#define CLK_MM_MM_SMI_CAM 28
+#define CLK_MM_IMG_IMG_DL_RELAY 29
+#define CLK_MM_IMG_IMG_DL_ASYNC_TOP 30
+#define CLK_MM_DSI0_DIG_DSI 31
+#define CLK_MM_26M_HRTWT 32
+#define CLK_MM_MM_DPI0 33
+#define CLK_MM_LVDSTX_PXL 34
+#define CLK_MM_LVDSTX_CTS 35
+#define CLK_MM_NR_CLK 36
+
+/* IMGSYS */
+
+#define CLK_CAM_LARB2 0
+#define CLK_CAM 1
+#define CLK_CAMTG 2
+#define CLK_CAM_SENIF 3
+#define CLK_CAMSV0 4
+#define CLK_CAMSV1 5
+#define CLK_CAM_FDVT 6
+#define CLK_CAM_WPE 7
+#define CLK_CAM_NR_CLK 8
+
+/* VDECSYS */
+
+#define CLK_VDEC_VDEC 0
+#define CLK_VDEC_LARB1 1
+#define CLK_VDEC_NR_CLK 2
+
+/* VENCSYS */
+
+#define CLK_VENC 0
+#define CLK_VENC_JPGENC 1
+#define CLK_VENC_NR_CLK 2
+
+/* APUSYS */
+
+#define CLK_APU_IPU_CK 0
+#define CLK_APU_AXI 1
+#define CLK_APU_JTAG 2
+#define CLK_APU_IF_CK 3
+#define CLK_APU_EDMA 4
+#define CLK_APU_AHB 5
+#define CLK_APU_NR_CLK 6
+
+#endif /* _DT_BINDINGS_CLK_MT8175_H */
--
2.31.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/3] ARM: mediatek: Add MT8175 support
2021-03-30 14:30 [PATCH 1/3] clk: mediatek: Add MT8175 clock driver Fabien Parent
@ 2021-03-30 14:30 ` Fabien Parent
2021-04-01 1:42 ` Chunfeng Yun
2021-03-30 14:30 ` [PATCH 3/3] board: Add MT8175 pumpkin board support Fabien Parent
2021-04-19 15:48 ` [PATCH 1/3] clk: mediatek: Add MT8175 clock driver Fabien Parent
2 siblings, 1 reply; 6+ messages in thread
From: Fabien Parent @ 2021-03-30 14:30 UTC (permalink / raw)
To: u-boot
Add MT8175 SoC support.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
v2:
* Removed 'usb_host' node
* Removed some unneeded "mac" reg and interrupts definitio
in the 'usb' node
* Modify the u3phy and its subnode to encode the ranges property as
<prop-encoded-array>.
arch/arm/dts/mt8175.dtsi | 229 +++++++++++++++++++++++++
arch/arm/mach-mediatek/Kconfig | 9 +
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt8175/Makefile | 3 +
arch/arm/mach-mediatek/mt8175/init.c | 75 ++++++++
5 files changed, 317 insertions(+)
create mode 100644 arch/arm/dts/mt8175.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8175/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8175/init.c
diff --git a/arch/arm/dts/mt8175.dtsi b/arch/arm/dts/mt8175.dtsi
new file mode 100644
index 000000000000..bfb02741eef4
--- /dev/null
+++ b/arch/arm/dts/mt8175.dtsi
@@ -0,0 +1,229 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Copyright (C) 2021 BayLibre, SAS
+ * Author: Ben Ho <ben.ho@mediatek.com>
+ * Erin Lo <erin.lo@mediatek.com>
+ * Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/mt8175-clk.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ compatible = "mediatek,mt8175";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x002>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x003>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ watchdog: watchdog at 10007000 {
+ compatible = "mediatek,mt8175-rgu",
+ "mediatek,wdt";
+ reg = <0 0x10007000 0 0x100>;
+ #reset-cells = <1>;
+ };
+
+ gic: interrupt-controller at c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0xc000000 0 0x80000>,
+ <0 0xc080000 0 0x80000>;
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ sysirq: intpol-controller at 10200a80 {
+ compatible = "mediatek,mt8175-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200a80 0 0x20>;
+ };
+
+ topckgen: topckgen at 10000000 {
+ compatible = "mediatek,mt8175-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ topckgen_cg: topckgen-cg at 10000000 {
+ compatible = "mediatek,mt8175-topckgen-cg", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: infracfg at 10001000 {
+ compatible = "mediatek,mt8175-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apmixedsys: syscon at 1000c000 {
+ compatible = "mediatek,mt8175-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ uart0: uart0 at 11002000 {
+ compatible = "mediatek,mt8175-uart",
+ "mediatek,hsuart";
+ reg = <0 0x11002000 0 0x1000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
+ clock-frequency = <26000000>;
+ clocks = <&topckgen CLK_TOP_CLK26M>, <&infracfg CLK_IFR_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: uart1 at 11003000 {
+ compatible = "mediatek,mt8175-uart",
+ "mediatek,hsuart";
+ reg = <0 0x11003000 0 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_CLK26M>, <&infracfg CLK_IFR_UART1>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: uart2 at 11004000 {
+ compatible = "mediatek,mt8175-uart",
+ "mediatek,hsuart";
+ reg = <0 0x11004000 0 0x1000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_CLK26M>, <&infracfg CLK_IFR_UART2>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ mmc0: mmc at 11230000 {
+ compatible = "mediatek,mt8175-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x1000>,
+ <0 0x11cd0000 0 0x1000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+ <&infracfg CLK_IFR_MSDC0_HCLK>,
+ <&infracfg CLK_IFR_MSDC0_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ u3phy: usb-phy at 11cc0000 {
+ compatible = "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11cc0000 0x2000>;
+ status = "okay";
+
+ u2port0: usb-phy at 0 {
+ reg = <0 0x400>;
+ clocks = <&topckgen_cg CLK_TOP_SSUSB_PHY_CK_EN>,
+ <&topckgen_cg CLK_TOP_USB20_48M_EN>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u2port1: usb-phy at 1000 {
+ reg = <0x1000 0x400>;
+ clocks = <&topckgen_cg CLK_TOP_SSUSB_PHY_CK_EN>,
+ <&topckgen_cg CLK_TOP_USB20_48M_EN>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+ usb: usb at 11201000 {
+ compatible ="mediatek,mt8175-mtu3", "mediatek,mtu3";
+ reg = <0 0x11203e00 0 0x0100>;
+ reg-names = "ippc";
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u2port1 PHY_TYPE_USB2>;
+ clocks = <&topckgen_cg CLK_TOP_SSUSB_TOP_CK_EN>,
+ <&infracfg CLK_IFR_SSUSB_REF>,
+ <&infracfg CLK_IFR_SSUSB_SYS>,
+ <&infracfg CLK_IFR_ICUSB>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck",
+ "dma_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ ssusb: ssusb at 11200000 {
+ compatible = "mediatek,ssusb";
+ reg = <0 0x11200000 0 0x3e00>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index e067604d9b39..4a91fb764175 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -41,6 +41,14 @@ config TARGET_MT7629
including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
+config TARGET_MT8175
+ bool "MediaTek MT8175 SoC"
+ select ARM64
+ help
+ The MediaTek MT8175 is a ARM64-based SoC with a quad-core Cortex-A53.
+ It is including UART, SPI, USB2.0 dual role, SD and MMC cards, NAND, PWM,
+ I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options.
+
config TARGET_MT8183
bool "MediaTek MT8183 SoC"
select ARM64
@@ -83,6 +91,7 @@ endchoice
source "board/mediatek/mt7622/Kconfig"
source "board/mediatek/mt7623/Kconfig"
source "board/mediatek/mt7629/Kconfig"
+source "board/mediatek/mt8175/Kconfig"
source "board/mediatek/mt8183/Kconfig"
source "board/mediatek/mt8512/Kconfig"
source "board/mediatek/mt8516/Kconfig"
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index 0f5b0c16d2cb..ba030fb0b373 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_MT8512) += mt8512/
obj-$(CONFIG_TARGET_MT7622) += mt7622/
obj-$(CONFIG_TARGET_MT7623) += mt7623/
obj-$(CONFIG_TARGET_MT7629) += mt7629/
+obj-$(CONFIG_TARGET_MT8175) += mt8175/
obj-$(CONFIG_TARGET_MT8183) += mt8183/
obj-$(CONFIG_TARGET_MT8516) += mt8516/
obj-$(CONFIG_TARGET_MT8518) += mt8518/
diff --git a/arch/arm/mach-mediatek/mt8175/Makefile b/arch/arm/mach-mediatek/mt8175/Makefile
new file mode 100644
index 000000000000..886ab7e4eb9f
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8175/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
diff --git a/arch/arm/mach-mediatek/mt8175/init.c b/arch/arm/mach-mediatek/mt8175/init.c
new file mode 100644
index 000000000000..5161c1ce78d5
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8175/init.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Copyright (C) 2021 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
+#include <asm/system.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = gd->ram_base;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
+
+int mtk_pll_early_init(void)
+{
+ return 0;
+}
+
+int mtk_soc_early_init(void)
+{
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: MediaTek MT8175\n");
+ return 0;
+}
+
+static struct mm_region mt8175_mem_map[] = {
+ {
+ /* DDR */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+ }, {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ 0,
+ }
+};
+
+struct mm_region *mem_map = mt8175_mem_map;
--
2.31.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/3] board: Add MT8175 pumpkin board support
2021-03-30 14:30 [PATCH 1/3] clk: mediatek: Add MT8175 clock driver Fabien Parent
2021-03-30 14:30 ` [PATCH 2/3] ARM: mediatek: Add MT8175 support Fabien Parent
@ 2021-03-30 14:30 ` Fabien Parent
2021-04-19 15:48 ` [PATCH 1/3] clk: mediatek: Add MT8175 clock driver Fabien Parent
2 siblings, 0 replies; 6+ messages in thread
From: Fabien Parent @ 2021-03-30 14:30 UTC (permalink / raw)
To: u-boot
Add the MT8175 pumpkin board support.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/mt8175-pumpkin.dts | 95 ++++++++++++++++++++++++++
board/mediatek/mt8175/Kconfig | 13 ++++
board/mediatek/mt8175/MAINTAINERS | 6 ++
board/mediatek/mt8175/Makefile | 3 +
board/mediatek/mt8175/mt8175_pumpkin.c | 28 ++++++++
configs/mt8175_pumpkin_defconfig | 81 ++++++++++++++++++++++
include/configs/mt8175.h | 41 +++++++++++
8 files changed, 268 insertions(+)
create mode 100644 arch/arm/dts/mt8175-pumpkin.dts
create mode 100644 board/mediatek/mt8175/Kconfig
create mode 100644 board/mediatek/mt8175/MAINTAINERS
create mode 100644 board/mediatek/mt8175/Makefile
create mode 100644 board/mediatek/mt8175/mt8175_pumpkin.c
create mode 100644 configs/mt8175_pumpkin_defconfig
create mode 100644 include/configs/mt8175.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9a8de46272a2..18f6763d569a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1013,6 +1013,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-bananapi-bpi-r64.dtb \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
+ mt8175-pumpkin.dtb \
mt8183-pumpkin.dtb \
mt8512-bm1-emmc.dtb \
mt8516-pumpkin.dtb \
diff --git a/arch/arm/dts/mt8175-pumpkin.dts b/arch/arm/dts/mt8175-pumpkin.dts
new file mode 100644
index 000000000000..9c5bc845a781
--- /dev/null
+++ b/arch/arm/dts/mt8175-pumpkin.dts
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2021 BayLibre SAS.
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include <config.h>
+#include "mt8175.dtsi"
+
+/ {
+ model = "MT8175 pumpkin board";
+ compatible = "mediatek,mt8175-pumpkin", "mediatek,mt8175";
+
+ memory at 40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon at 43000000 {
+ no-map;
+ reg = <0 0x43000000 0 0x30000>;
+ };
+
+ /* 12 MiB reserved for OP-TEE (BL32)
+ * +-----------------------+ 0x43e0_0000
+ * | SHMEM 2MiB |
+ * +-----------------------+ 0x43c0_0000
+ * | | TA_RAM 8MiB |
+ * + TZDRAM +--------------+ 0x4340_0000
+ * | | TEE_RAM 2MiB |
+ * +-----------------------+ 0x4320_0000
+ */
+ optee_reserved: optee at 43200000 {
+ no-map;
+ reg = <0 0x43200000 0 0x00c00000>;
+ };
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <4>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&ssusb {
+ mediatek,force-vbus;
+ maximum-speed = "high-speed";
+ dr_mode = "peripheral";
+ status = "okay";
+};
diff --git a/board/mediatek/mt8175/Kconfig b/board/mediatek/mt8175/Kconfig
new file mode 100644
index 000000000000..00fd6c9c7f6e
--- /dev/null
+++ b/board/mediatek/mt8175/Kconfig
@@ -0,0 +1,13 @@
+if TARGET_MT8175
+
+config SYS_BOARD
+ default "mt8175"
+
+config SYS_CONFIG_NAME
+ default "mt8175"
+
+config MTK_BROM_HEADER_INFO
+ string
+ default "media=emmc"
+
+endif
diff --git a/board/mediatek/mt8175/MAINTAINERS b/board/mediatek/mt8175/MAINTAINERS
new file mode 100644
index 000000000000..1d2c966a8b44
--- /dev/null
+++ b/board/mediatek/mt8175/MAINTAINERS
@@ -0,0 +1,6 @@
+MT8175 Pumpkin
+M: Fabien Parent <fparent@baylibre.com>
+S: Maintained
+F: board/mediatek/mt8175
+F: include/configs/mt8175.h
+F: configs/mt8175_pumpkin_defconfig
diff --git a/board/mediatek/mt8175/Makefile b/board/mediatek/mt8175/Makefile
new file mode 100644
index 000000000000..65fb3a6cb42c
--- /dev/null
+++ b/board/mediatek/mt8175/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += mt8175_pumpkin.o
diff --git a/board/mediatek/mt8175/mt8175_pumpkin.c b/board/mediatek/mt8175/mt8175_pumpkin.c
new file mode 100644
index 000000000000..f071089cd44a
--- /dev/null
+++ b/board/mediatek/mt8175/mt8175_pumpkin.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 BayLibre SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <net.h>
+
+int board_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (CONFIG_IS_ENABLED(USB_GADGET)) {
+ ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
+ if (ret) {
+ pr_err("%s: Cannot find USB device\n", __func__);
+ return ret;
+ }
+ }
+
+ if (CONFIG_IS_ENABLED(USB_ETHER))
+ usb_ether_init();
+
+ return 0;
+}
diff --git a/configs/mt8175_pumpkin_defconfig b/configs/mt8175_pumpkin_defconfig
new file mode 100644
index 000000000000..9d17659c9691
--- /dev/null
+++ b/configs/mt8175_pumpkin_defconfig
@@ -0,0 +1,81 @@
+CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_SYS_TEXT_BASE=0x4c000000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x0
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MT8175=y
+CONFIG_DEBUG_UART_BASE=0x11002000
+CONFIG_DEBUG_UART_CLOCK=26000000
+# CONFIG_PSCI_RESET is not set
+CONFIG_DEFAULT_DEVICE_TREE="mt8175-pumpkin"
+CONFIG_DEBUG_UART=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_DEFAULT_FDT_FILE="mt8175-pumpkin"
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_MEMORY is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_BLOCK_CACHE is not set
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DEVRES=y
+CONFIG_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x4d000000
+CONFIG_FASTBOOT_BUF_SIZE=0x8000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+# CONFIG_INPUT is not set
+CONFIG_DM_MMC=y
+# CONFIG_MMC_QUIRKS is not set
+CONFIG_MMC_MTK=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
+CONFIG_BAUDRATE=921600
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_MTK_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_MTU3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x0e8d
+CONFIG_USB_GADGET_PRODUCT_NUM=0x201c
+CONFIG_USB_ETHER=y
+CONFIG_WDT=y
+CONFIG_WDT_MTK=y
+# CONFIG_REGEX is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/mt8175.h b/include/configs/mt8175.h
new file mode 100644
index 000000000000..1f7a8032a65f
--- /dev/null
+++ b/include/configs/mt8175.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for MT8175 based boards
+ *
+ * Copyright (C) 2021 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com
+ */
+
+#ifndef __MT8175_H
+#define __MT8175_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MALLOC_LEN SZ_4M
+
+#define CONFIG_CPU_ARMV8
+#define COUNTER_FREQUENCY 13000000
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_COM1 0x11005200
+#define CONFIG_SYS_NS16550_CLK 26000000
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+
+/* Environment settings */
+#include <config_distro_bootcmd.h>
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "scriptaddr=0x40000000\0" \
+ BOOTENV
+
+#endif
--
2.31.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/3] ARM: mediatek: Add MT8175 support
2021-03-30 14:30 ` [PATCH 2/3] ARM: mediatek: Add MT8175 support Fabien Parent
@ 2021-04-01 1:42 ` Chunfeng Yun
0 siblings, 0 replies; 6+ messages in thread
From: Chunfeng Yun @ 2021-04-01 1:42 UTC (permalink / raw)
To: u-boot
On Tue, 2021-03-30 at 16:30 +0200, Fabien Parent wrote:
> Add MT8175 SoC support.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>
> v2:
nit: add v2 also in title
> * Removed 'usb_host' node
> * Removed some unneeded "mac" reg and interrupts definitio
> in the 'usb' node
> * Modify the u3phy and its subnode to encode the ranges property as
> <prop-encoded-array>.
>
> arch/arm/dts/mt8175.dtsi | 229 +++++++++++++++++++++++++
> arch/arm/mach-mediatek/Kconfig | 9 +
> arch/arm/mach-mediatek/Makefile | 1 +
> arch/arm/mach-mediatek/mt8175/Makefile | 3 +
> arch/arm/mach-mediatek/mt8175/init.c | 75 ++++++++
> 5 files changed, 317 insertions(+)
> create mode 100644 arch/arm/dts/mt8175.dtsi
> create mode 100644 arch/arm/mach-mediatek/mt8175/Makefile
> create mode 100644 arch/arm/mach-mediatek/mt8175/init.c
>
> diff --git a/arch/arm/dts/mt8175.dtsi b/arch/arm/dts/mt8175.dtsi
> new file mode 100644
> index 000000000000..bfb02741eef4
> --- /dev/null
> +++ b/arch/arm/dts/mt8175.dtsi
> @@ -0,0 +1,229 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2021 MediaTek Inc.
> + * Copyright (C) 2021 BayLibre, SAS
> + * Author: Ben Ho <ben.ho@mediatek.com>
> + * Erin Lo <erin.lo@mediatek.com>
> + * Fabien Parent <fparent@baylibre.com>
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/clock/mt8175-clk.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/phy/phy.h>
> +
> +/ {
> + compatible = "mediatek,mt8175";
> + interrupt-parent = <&sysirq>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + };
> + };
> +
> + cpu0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x000>;
> + enable-method = "psci";
> + };
> +
> + cpu1: cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x001>;
> + enable-method = "psci";
> + };
> +
> + cpu2: cpu at 2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x002>;
> + enable-method = "psci";
> + };
> +
> + cpu3: cpu at 3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x003>;
> + enable-method = "psci";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + watchdog: watchdog at 10007000 {
> + compatible = "mediatek,mt8175-rgu",
> + "mediatek,wdt";
> + reg = <0 0x10007000 0 0x100>;
> + #reset-cells = <1>;
> + };
> +
> + gic: interrupt-controller at c000000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <4>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0xc000000 0 0x80000>,
> + <0 0xc080000 0 0x80000>;
> +
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> + };
> +
> + sysirq: intpol-controller at 10200a80 {
> + compatible = "mediatek,mt8175-sysirq",
> + "mediatek,mt6577-sysirq";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + reg = <0 0x10200a80 0 0x20>;
> + };
> +
> + topckgen: topckgen at 10000000 {
> + compatible = "mediatek,mt8175-topckgen", "syscon";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + topckgen_cg: topckgen-cg at 10000000 {
> + compatible = "mediatek,mt8175-topckgen-cg", "syscon";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + infracfg: infracfg at 10001000 {
> + compatible = "mediatek,mt8175-infracfg", "syscon";
> + reg = <0 0x10001000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + apmixedsys: syscon at 1000c000 {
> + compatible = "mediatek,mt8175-apmixedsys", "syscon";
> + reg = <0 0x1000c000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + uart0: uart0 at 11002000 {
> + compatible = "mediatek,mt8175-uart",
> + "mediatek,hsuart";
> + reg = <0 0x11002000 0 0x1000>;
> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
> + clock-frequency = <26000000>;
> + clocks = <&topckgen CLK_TOP_CLK26M>, <&infracfg CLK_IFR_UART0>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + uart1: uart1 at 11003000 {
> + compatible = "mediatek,mt8175-uart",
> + "mediatek,hsuart";
> + reg = <0 0x11003000 0 0x1000>;
> + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_CLK26M>, <&infracfg CLK_IFR_UART1>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + uart2: uart2 at 11004000 {
> + compatible = "mediatek,mt8175-uart",
> + "mediatek,hsuart";
> + reg = <0 0x11004000 0 0x1000>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_CLK26M>, <&infracfg CLK_IFR_UART2>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + mmc0: mmc at 11230000 {
Nit: Usually sort nodes according to address
> + compatible = "mediatek,mt8175-mmc", "mediatek,mt8183-mmc";
> + reg = <0 0x11230000 0 0x1000>,
> + <0 0x11cd0000 0 0x1000>;
> + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> + <&infracfg CLK_IFR_MSDC0_HCLK>,
> + <&infracfg CLK_IFR_MSDC0_SRC>;
> + clock-names = "source", "hclk", "source_cg";
> + status = "disabled";
> + };
> +
> + u3phy: usb-phy at 11cc0000 {
> + compatible = "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x11cc0000 0x2000>;
> + status = "okay";
> +
> + u2port0: usb-phy at 0 {
> + reg = <0 0x400>;
> + clocks = <&topckgen_cg CLK_TOP_SSUSB_PHY_CK_EN>,
> + <&topckgen_cg CLK_TOP_USB20_48M_EN>;
> + clock-names = "ref", "da_ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> +
> + u2port1: usb-phy at 1000 {
> + reg = <0x1000 0x400>;
> + clocks = <&topckgen_cg CLK_TOP_SSUSB_PHY_CK_EN>,
> + <&topckgen_cg CLK_TOP_USB20_48M_EN>;
> + clock-names = "ref", "da_ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> + };
> +
> + usb: usb at 11201000 {
> + compatible ="mediatek,mt8175-mtu3", "mediatek,mtu3";
> + reg = <0 0x11203e00 0 0x0100>;
> + reg-names = "ippc";
> + phys = <&u2port0 PHY_TYPE_USB2>,
> + <&u2port1 PHY_TYPE_USB2>;
> + clocks = <&topckgen_cg CLK_TOP_SSUSB_TOP_CK_EN>,
> + <&infracfg CLK_IFR_SSUSB_REF>,
> + <&infracfg CLK_IFR_SSUSB_SYS>,
> + <&infracfg CLK_IFR_ICUSB>;
> + clock-names = "sys_ck", "ref_ck", "mcu_ck",
> + "dma_ck";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + ssusb: ssusb at 11200000 {
> + compatible = "mediatek,ssusb";
> + reg = <0 0x11200000 0 0x3e00>;
> + reg-names = "mac";
> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
> + status = "disabled";
> + };
> + };
> + };
> +};
For usb / phy nodes:
Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Thanks a lot
> diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
> index e067604d9b39..4a91fb764175 100644
> --- a/arch/arm/mach-mediatek/Kconfig
> +++ b/arch/arm/mach-mediatek/Kconfig
> @@ -41,6 +41,14 @@ config TARGET_MT7629
> including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
> switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
>
> +config TARGET_MT8175
> + bool "MediaTek MT8175 SoC"
> + select ARM64
> + help
> + The MediaTek MT8175 is a ARM64-based SoC with a quad-core Cortex-A53.
> + It is including UART, SPI, USB2.0 dual role, SD and MMC cards, NAND, PWM,
> + I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options.
> +
> config TARGET_MT8183
> bool "MediaTek MT8183 SoC"
> select ARM64
> @@ -83,6 +91,7 @@ endchoice
> source "board/mediatek/mt7622/Kconfig"
> source "board/mediatek/mt7623/Kconfig"
> source "board/mediatek/mt7629/Kconfig"
> +source "board/mediatek/mt8175/Kconfig"
> source "board/mediatek/mt8183/Kconfig"
> source "board/mediatek/mt8512/Kconfig"
> source "board/mediatek/mt8516/Kconfig"
> diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
> index 0f5b0c16d2cb..ba030fb0b373 100644
> --- a/arch/arm/mach-mediatek/Makefile
> +++ b/arch/arm/mach-mediatek/Makefile
> @@ -7,6 +7,7 @@ obj-$(CONFIG_MT8512) += mt8512/
> obj-$(CONFIG_TARGET_MT7622) += mt7622/
> obj-$(CONFIG_TARGET_MT7623) += mt7623/
> obj-$(CONFIG_TARGET_MT7629) += mt7629/
> +obj-$(CONFIG_TARGET_MT8175) += mt8175/
> obj-$(CONFIG_TARGET_MT8183) += mt8183/
> obj-$(CONFIG_TARGET_MT8516) += mt8516/
> obj-$(CONFIG_TARGET_MT8518) += mt8518/
> diff --git a/arch/arm/mach-mediatek/mt8175/Makefile b/arch/arm/mach-mediatek/mt8175/Makefile
> new file mode 100644
> index 000000000000..886ab7e4eb9f
> --- /dev/null
> +++ b/arch/arm/mach-mediatek/mt8175/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +obj-y += init.o
> diff --git a/arch/arm/mach-mediatek/mt8175/init.c b/arch/arm/mach-mediatek/mt8175/init.c
> new file mode 100644
> index 000000000000..5161c1ce78d5
> --- /dev/null
> +++ b/arch/arm/mach-mediatek/mt8175/init.c
> @@ -0,0 +1,75 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2021 MediaTek Inc.
> + * Copyright (C) 2021 BayLibre, SAS
> + * Author: Fabien Parent <fparent@baylibre.com>
> + */
> +
> +#include <common.h>
> +#include <fdtdec.h>
> +#include <asm/armv8/mmu.h>
> +#include <asm/global_data.h>
> +#include <asm/system.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> + int ret;
> +
> + ret = fdtdec_setup_memory_banksize();
> + if (ret)
> + return ret;
> +
> + return fdtdec_setup_mem_size_base();
> +}
> +
> +int dram_init_banksize(void)
> +{
> + gd->bd->bi_dram[0].start = gd->ram_base;
> + gd->bd->bi_dram[0].size = gd->ram_size;
> +
> + return 0;
> +}
> +
> +int mtk_pll_early_init(void)
> +{
> + return 0;
> +}
> +
> +int mtk_soc_early_init(void)
> +{
> + return 0;
> +}
> +
> +void reset_cpu(ulong addr)
> +{
> + psci_system_reset();
> +}
> +
> +int print_cpuinfo(void)
> +{
> + printf("CPU: MediaTek MT8175\n");
> + return 0;
> +}
> +
> +static struct mm_region mt8175_mem_map[] = {
> + {
> + /* DDR */
> + .virt = 0x40000000UL,
> + .phys = 0x40000000UL,
> + .size = 0x40000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
> + }, {
> + .virt = 0x00000000UL,
> + .phys = 0x00000000UL,
> + .size = 0x20000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + 0,
> + }
> +};
> +
> +struct mm_region *mem_map = mt8175_mem_map;
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/3] clk: mediatek: Add MT8175 clock driver
2021-03-30 14:30 [PATCH 1/3] clk: mediatek: Add MT8175 clock driver Fabien Parent
2021-03-30 14:30 ` [PATCH 2/3] ARM: mediatek: Add MT8175 support Fabien Parent
2021-03-30 14:30 ` [PATCH 3/3] board: Add MT8175 pumpkin board support Fabien Parent
@ 2021-04-19 15:48 ` Fabien Parent
2 siblings, 0 replies; 6+ messages in thread
From: Fabien Parent @ 2021-04-19 15:48 UTC (permalink / raw)
To: u-boot
Please do NOT merge this patch series. MTK asked me to resend this
patch series with a different SoC Part-Number.
On Tue, Mar 30, 2021 at 4:31 PM Fabien Parent <fparent@baylibre.com> wrote:
>
> Add the topckgen, apmixedsys and infracfg clock driver for the MT8175
> SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
> drivers/clk/mediatek/Makefile | 1 +
> drivers/clk/mediatek/clk-mt8175.c | 785 +++++++++++++++++++++++++
> include/dt-bindings/clock/mt8175-clk.h | 392 ++++++++++++
> 3 files changed, 1178 insertions(+)
> create mode 100644 drivers/clk/mediatek/clk-mt8175.c
> create mode 100644 include/dt-bindings/clock/mt8175-clk.h
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 522e72422144..0f3135eca39c 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -7,6 +7,7 @@ obj-$(CONFIG_MT8512) += clk-mt8512.o
> obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
> obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o
> obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
> +obj-$(CONFIG_TARGET_MT8175) += clk-mt8175.o
> obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
> obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
> obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
> diff --git a/drivers/clk/mediatek/clk-mt8175.c b/drivers/clk/mediatek/clk-mt8175.c
> new file mode 100644
> index 000000000000..cb5841181d2d
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8175.c
> @@ -0,0 +1,785 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * MediaTek clock driver for MT8175 SoC
> + *
> + * Copyright (C) 2021 BayLibre, SAS
> + * Copyright (c) 2021 MediaTek Inc.
> + * Author: Fabien Parent <fparent@baylibre.com>
> + * Author: Weiyi Lu <weiyi.lu@mediatek.com>
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <asm/io.h>
> +#include <dt-bindings/clock/mt8175-clk.h>
> +
> +#include "clk-mtk.h"
> +
> +#define MT8175_PLL_FMAX (3800UL * MHZ)
> +#define MT8175_PLL_FMIN (1500UL * MHZ)
> +
> +/* apmixedsys */
> +#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
> + _pd_shift, _pcw_reg, _pcw_shift) { \
> + .id = _id, \
> + .reg = _reg, \
> + .pwr_reg = _pwr_reg, \
> + .en_mask = _en_mask, \
> + .rst_bar_mask = BIT(23), \
> + .fmax = MT8175_PLL_FMAX, \
> + .flags = _flags, \
> + .pcwbits = _pcwbits, \
> + .pcwibits = 8, \
> + .pd_reg = _pd_reg, \
> + .pd_shift = _pd_shift, \
> + .pcw_reg = _pcw_reg, \
> + .pcw_shift = _pcw_shift, \
> + }
> +
> +static const struct mtk_pll_data apmixed_plls[] = {
> + PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001, 0, 22, 0x0310, 24,
> + 0x0310, 0),
> + PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0xFF000001, HAVE_RST_BAR, 22,
> + 0x022C, 24, 0x022C, 0),
> + PLL(CLK_APMIXED_UNIVPLL, 0x0208, 0x0214, 0xFF000001, HAVE_RST_BAR, 22,
> + 0x020C, 24, 0x020C, 0),
> + PLL(CLK_APMIXED_MFGPLL, 0x0218, 0x0224, 0x00000001, 0, 22, 0x021C, 24,
> + 0x021C, 0),
> + PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001, 0, 22, 0x0354, 24,
> + 0x0354, 0),
> + PLL(CLK_APMIXED_MMPLL, 0x0330, 0x033C, 0x00000001, 0, 22, 0x0334, 24,
> + 0x0334, 0),
> + PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001, 0, 32, 0x0320, 24,
> + 0x0324, 0),
> + PLL(CLK_APMIXED_APLL2, 0x0360, 0x0370, 0x00000001, 0, 32, 0x0364, 24,
> + 0x0368, 0),
> + PLL(CLK_APMIXED_LVDSPLL, 0x0374, 0x0380, 0x00000001, 0, 22, 0x0378, 24,
> + 0x0378, 0),
> + PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x00000001, 0, 22, 0x0394, 24,
> + 0x0394, 0),
> + PLL(CLK_APMIXED_APUPLL, 0x03A0, 0x03AC, 0x00000001, 0, 22, 0x03A4, 24,
> + 0x03A4, 0),
> +};
> +
> +static const struct mtk_fixed_clk top_fixed_clks[] = {
> + FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 0),
> + FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, CLK_TOP_CLK26M, 75000000),
> + FIXED_CLK(CLK_TOP_VPLL_DPIX, CLK_TOP_CLK26M, 75000000),
> + FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, CLK_TOP_CLK26M, 52500000),
> + FIXED_CLK(CLK_TOP_CLK26M, CLK_XTAL, 26000000),
> + FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
> +};
> +
> +static const struct mtk_fixed_factor top_fixed_divs[] = {
> + FACTOR(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL, 1, 2, CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2, CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4, CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8, CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3, CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6, CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12,
> + CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24,
> + CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_UNIVPLL2_D32, CLK_TOP_UNIVPLL, 1, 96,
> + CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5, CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10,
> + CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20,
> + CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_MMPLL, CLK_APMIXED_MMPLL, 1, 1,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_MFGPLL, CLK_APMIXED_MFGPLL, 1, 1,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_LVDSPLL_D2, CLK_APMIXED_LVDSPLL, 1, 2,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_LVDSPLL_D4, CLK_APMIXED_LVDSPLL, 1, 4,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_LVDSPLL_D8, CLK_APMIXED_LVDSPLL, 1, 8,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_LVDSPLL_D16, CLK_APMIXED_LVDSPLL, 1, 16,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_USB20_192M, CLK_TOP_UNIVPLL, 1, 1, CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_USB20_192M_D4, CLK_TOP_USB20_192M, 1, 4,
> + CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_USB20_192M_D8, CLK_TOP_USB20_192M, 1, 8,
> + CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_USB20_192M_D16, CLK_TOP_USB20_192M, 1, 16,
> + CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_USB20_192M_D32, CLK_TOP_USB20_192M, 1, 32,
> + CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1, CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_APLL1_D2, CLK_TOP_APLL1, 1, 2, CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 4, CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_APLL1_D8, CLK_TOP_APLL1, 1, 8, CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1, CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2, CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_APLL2_D4, CLK_TOP_APLL2, 1, 4, CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_APLL2_D8, CLK_TOP_APLL2, 1, 8, CLK_PARENT_TOPCKGEN),
> + FACTOR(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1, CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2,
> + CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_DSPPLL, CLK_APMIXED_DSPPLL, 1, 1, CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_DSPPLL_D2, CLK_APMIXED_DSPPLL, 1, 2, CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_DSPPLL_D4, CLK_APMIXED_DSPPLL, 1, 4, CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_DSPPLL_D8, CLK_APMIXED_DSPPLL, 1, 8, CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_APUPLL, CLK_APMIXED_APUPLL, 1, 1, CLK_PARENT_APMIXED),
> + FACTOR(CLK_TOP_CLK26M_D52, CLK_TOP_CLK26M, 1, 52, CLK_PARENT_TOPCKGEN),
> +};
> +
> +static const int axi_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_SYSPLL_D7,
> + CLK_TOP_SYSPLL1_D4,
> + CLK_TOP_SYSPLL3_D2
> +};
> +
> +static const int mem_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_MMPLL,
> + CLK_TOP_SYSPLL_D3,
> + CLK_TOP_SYSPLL1_D2
> +};
> +
> +static const int mm_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_MMPLL,
> + CLK_TOP_SYSPLL1_D2,
> + CLK_TOP_SYSPLL_D5,
> + CLK_TOP_SYSPLL1_D4,
> + CLK_TOP_UNIVPLL_D5,
> + CLK_TOP_UNIVPLL1_D2,
> + CLK_TOP_MMPLL_D2,
> +};
> +
> +static const int scp_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_SYSPLL4_D2,
> + CLK_TOP_UNIVPLL2_D2,
> + CLK_TOP_SYSPLL1_D2,
> + CLK_TOP_UNIVPLL1_D2,
> + CLK_TOP_SYSPLL_D3,
> + CLK_TOP_UNIVPLL_D3
> +};
> +
> +static const int mfg_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_MFGPLL,
> + CLK_TOP_SYSPLL_D3,
> + CLK_TOP_UNIVPLL_D3
> +};
> +
> +static const int atb_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_SYSPLL1_D4,
> + CLK_TOP_SYSPLL1_D2
> +};
> +
> +static const int camtg_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_USB20_192M_D8,
> + CLK_TOP_UNIVPLL2_D8,
> + CLK_TOP_USB20_192M_D4,
> + CLK_TOP_UNIVPLL2_D32,
> + CLK_TOP_USB20_192M_D16,
> + CLK_TOP_USB20_192M_D32,
> +};
> +
> +static const int uart_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_UNIVPLL2_D8
> +};
> +
> +static const int spi_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_UNIVPLL2_D2,
> + CLK_TOP_UNIVPLL2_D4,
> + CLK_TOP_UNIVPLL2_D8
> +};
> +
> +static const int msdc50_0_hc_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_SYSPLL1_D2,
> + CLK_TOP_UNIVPLL1_D4,
> + CLK_TOP_SYSPLL2_D2
> +};
> +
> +static const int msdc50_0_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_MSDCPLL,
> + CLK_TOP_UNIVPLL1_D2,
> + CLK_TOP_SYSPLL1_D2,
> + CLK_TOP_UNIVPLL_D5,
> + CLK_TOP_SYSPLL2_D2,
> + CLK_TOP_UNIVPLL1_D4,
> + CLK_TOP_SYSPLL4_D2
> +};
> +
> +static const int msdc50_2_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_MSDCPLL,
> + CLK_TOP_UNIVPLL_D3,
> + CLK_TOP_UNIVPLL1_D2,
> + CLK_TOP_SYSPLL1_D2,
> + CLK_TOP_UNIVPLL2_D2,
> + CLK_TOP_SYSPLL2_D2,
> + CLK_TOP_UNIVPLL1_D4
> +};
> +
> +static const int msdc30_1_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_MSDCPLL_D2,
> + CLK_TOP_UNIVPLL2_D2,
> + CLK_TOP_SYSPLL2_D2,
> + CLK_TOP_UNIVPLL1_D4,
> + CLK_TOP_SYSPLL1_D4,
> + CLK_TOP_SYSPLL2_D4,
> + CLK_TOP_UNIVPLL2_D8
> +};
> +
> +static const int audio_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_SYSPLL3_D4,
> + CLK_TOP_SYSPLL4_D4,
> + CLK_TOP_SYSPLL1_D16
> +};
> +
> +static const int aud_intbus_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_SYSPLL1_D4,
> + CLK_TOP_SYSPLL4_D2
> +};
> +
> +static const int aud_1_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_APLL1
> +};
> +
> +static const int aud_2_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_APLL2
> +};
> +
> +static const int aud_engen1_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_APLL1_D2,
> + CLK_TOP_APLL1_D4,
> + CLK_TOP_APLL1_D8
> +};
> +
> +static const int aud_engen2_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_APLL2_D2,
> + CLK_TOP_APLL2_D4,
> + CLK_TOP_APLL2_D8,
> +};
> +
> +static const int aud_spdif_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_UNIVPLL_D2
> +};
> +
> +static const int disp_pwm_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_UNIVPLL2_D4
> +};
> +
> +static const int dxcc_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_SYSPLL1_D2,
> + CLK_TOP_SYSPLL1_D4,
> + CLK_TOP_SYSPLL1_D8
> +};
> +
> +static const int ssusb_sys_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_UNIVPLL3_D4,
> + CLK_TOP_UNIVPLL2_D4,
> + CLK_TOP_UNIVPLL3_D2
> +};
> +
> +static const int spm_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_SYSPLL1_D8
> +};
> +
> +static const int i2c_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_UNIVPLL3_D4,
> + CLK_TOP_UNIVPLL3_D2,
> + CLK_TOP_SYSPLL1_D8,
> + CLK_TOP_SYSPLL2_D8
> +};
> +
> +static const int pwm_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_UNIVPLL3_D4,
> + CLK_TOP_SYSPLL1_D8
> +};
> +
> +static const int senif_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_UNIVPLL1_D4,
> + CLK_TOP_UNIVPLL1_D2,
> + CLK_TOP_UNIVPLL2_D2
> +};
> +
> +static const int aes_fde_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_MSDCPLL,
> + CLK_TOP_UNIVPLL_D3,
> + CLK_TOP_UNIVPLL2_D2,
> + CLK_TOP_UNIVPLL1_D2,
> + CLK_TOP_SYSPLL1_D2
> +};
> +
> +static const int dpi0_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_LVDSPLL_D2,
> + CLK_TOP_LVDSPLL_D4,
> + CLK_TOP_LVDSPLL_D8,
> + CLK_TOP_LVDSPLL_D16
> +};
> +
> +static const int dsp_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_SYS_26M_D2,
> + CLK_TOP_DSPPLL,
> + CLK_TOP_DSPPLL_D2,
> + CLK_TOP_DSPPLL_D4,
> + CLK_TOP_DSPPLL_D8
> +};
> +
> +static const int nfi2x_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_SYSPLL2_D2,
> + CLK_TOP_SYSPLL_D7,
> + CLK_TOP_SYSPLL_D3,
> + CLK_TOP_SYSPLL2_D4,
> + CLK_TOP_MSDCPLL_D2,
> + CLK_TOP_UNIVPLL1_D2,
> + CLK_TOP_UNIVPLL_D5
> +};
> +
> +static const int nfiecc_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_SYSPLL4_D2,
> + CLK_TOP_UNIVPLL2_D4,
> + CLK_TOP_SYSPLL_D7,
> + CLK_TOP_UNIVPLL1_D2,
> + CLK_TOP_SYSPLL1_D2,
> + CLK_TOP_UNIVPLL2_D2,
> + CLK_TOP_SYSPLL_D5
> +};
> +
> +static const int ecc_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_UNIVPLL2_D2,
> + CLK_TOP_UNIVPLL1_D2,
> + CLK_TOP_UNIVPLL_D3,
> + CLK_TOP_SYSPLL_D2
> +};
> +
> +static const int eth_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_UNIVPLL2_D8,
> + CLK_TOP_SYSPLL4_D4,
> + CLK_TOP_SYSPLL1_D8,
> + CLK_TOP_SYSPLL4_D2
> +};
> +
> +static const int gcpu_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_UNIVPLL_D3,
> + CLK_TOP_UNIVPLL2_D2,
> + CLK_TOP_SYSPLL_D3,
> + CLK_TOP_SYSPLL2_D2
> +};
> +
> +static const int gcpu_cpm_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_UNIVPLL2_D2,
> + CLK_TOP_SYSPLL2_D2
> +};
> +
> +static const int apu_parents[] = {
> + CLK_TOP_CLK26M,
> + CLK_TOP_UNIVPLL_D2,
> + CLK_APMIXED_APUPLL,
> + CLK_TOP_MMPLL,
> + CLK_TOP_SYSPLL_D3,
> + CLK_TOP_UNIVPLL1_D2,
> + CLK_TOP_SYSPLL1_D2,
> + CLK_TOP_SYSPLL1_D4
> +};
> +
> +static const struct mtk_composite top_muxes[] = {
> + /* CLK_CFG_0 */
> + MUX(CLK_TOP_AXI_SEL, axi_parents, 0x040, 0, 2),
> + MUX(CLK_TOP_MEM_SEL, mem_parents, 0x040, 8, 2),
> + MUX(CLK_TOP_MM_SEL, mm_parents, 0x040, 16, 3),
> + MUX(CLK_TOP_SCP_SEL, scp_parents, 0x040, 24, 3),
> + /* CLK_CFG_1 */
> + MUX(CLK_TOP_MFG_SEL, mfg_parents, 0x050, 0, 2),
> + MUX(CLK_TOP_ATB_SEL, atb_parents, 0x050, 8, 2),
> + MUX(CLK_TOP_CAMTG_SEL, camtg_parents, 0x050, 16, 3),
> + MUX(CLK_TOP_CAMTG1_SEL, camtg_parents, 0x050, 24, 3),
> + /* CLK_CFG_2 */
> + MUX(CLK_TOP_UART_SEL, uart_parents, 0x060, 0, 1),
> + MUX(CLK_TOP_SPI_SEL, spi_parents, 0x060, 8, 2),
> + MUX(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents, 0x060, 16, 2),
> + MUX(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents, 0x060, 24, 2),
> + /* CLK_CFG_3 */
> + MUX(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, 0x070, 0, 3),
> + MUX(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents, 0x070, 8, 3),
> + MUX(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x070, 16, 3),
> + MUX(CLK_TOP_AUDIO_SEL, audio_parents, 0x070, 24, 2),
> + /* CLK_CFG_4 */
> + MUX(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x080, 0, 2),
> + MUX(CLK_TOP_AUD_1_SEL, aud_1_parents, 0x080, 8, 1),
> + MUX(CLK_TOP_AUD_2_SEL, aud_2_parents, 0x080, 16, 1),
> + MUX(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x080, 24, 2),
> + /* CLK_CFG_5 */
> + MUX(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x090, 0, 2),
> + MUX(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents, 0x090, 8, 1),
> + MUX(CLK_TOP_DISP_PWM_SEL, disp_pwm_parents, 0x090, 16, 2),
> + /* CLK_CFG_6 */
> + MUX(CLK_TOP_DXCC_SEL, dxcc_parents, 0x0a0, 0, 2),
> + MUX(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents, 0x0a0, 8, 2),
> + MUX(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents, 0x0a0, 16, 2),
> + MUX(CLK_TOP_SPM_SEL, spm_parents, 0x0a0, 24, 1),
> + /* CLK_CFG_7 */
> + MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x0b0, 0, 3),
> + MUX(CLK_TOP_PWM_SEL, pwm_parents, 0x0b0, 8, 2),
> + MUX(CLK_TOP_SENIF_SEL, senif_parents, 0x0b0, 16, 2),
> + MUX(CLK_TOP_AES_FDE_SEL, aes_fde_parents, 0x0b0, 24, 3),
> + /* CLK_CFG_8 */
> + MUX(CLK_TOP_CAMTM_SEL, senif_parents, 0x0c0, 0, 2),
> + MUX(CLK_TOP_DPI0_SEL, dpi0_parents, 0x0c0, 8, 3),
> + MUX(CLK_TOP_DPI1_SEL, dpi0_parents, 0x0c0, 16, 3),
> + MUX(CLK_TOP_DSP_SEL, dsp_parents, 0x0c0, 24, 3),
> + /* CLK_CFG_9 */
> + MUX(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x0d0, 0, 3),
> + MUX(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x0d0, 8, 3),
> + MUX(CLK_TOP_ECC_SEL, ecc_parents, 0x0d0, 16, 3),
> + MUX(CLK_TOP_ETH_SEL, eth_parents, 0x0d0, 24, 3),
> + /* CLK_CFG_10 */
> + MUX(CLK_TOP_GCPU_SEL, gcpu_parents, 0x0e0, 0, 3),
> + MUX(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents, 0x0e0, 8, 2),
> + MUX(CLK_TOP_APU_SEL, apu_parents, 0x0e0, 16, 3),
> + MUX(CLK_TOP_APU_IF_SEL, apu_parents, 0x0e0, 24, 3),
> +};
> +
> +static const struct mtk_clk_tree mt8175_clk_tree = {
> + .xtal_rate = 26 * MHZ,
> + .xtal2_rate = 26 * MHZ,
> + .fdivs_offs = CLK_TOP_SYSPLL_D2,
> + .muxes_offs = CLK_TOP_AXI_SEL,
> + .plls = apmixed_plls,
> + .fclks = top_fixed_clks,
> + .fdivs = top_fixed_divs,
> + .muxes = top_muxes,
> +};
> +
> +static const struct mtk_gate_regs infra2_cg_regs = {
> + .set_ofs = 0x80,
> + .clr_ofs = 0x84,
> + .sta_ofs = 0x90,
> +};
> +
> +static const struct mtk_gate_regs infra3_cg_regs = {
> + .set_ofs = 0x88,
> + .clr_ofs = 0x8c,
> + .sta_ofs = 0x94,
> +};
> +
> +static const struct mtk_gate_regs infra4_cg_regs = {
> + .set_ofs = 0xa4,
> + .clr_ofs = 0xa8,
> + .sta_ofs = 0xac,
> +};
> +
> +static const struct mtk_gate_regs infra5_cg_regs = {
> + .set_ofs = 0xc0,
> + .clr_ofs = 0xc4,
> + .sta_ofs = 0xc8,
> +};
> +
> +static const struct mtk_gate_regs infra6_cg_regs = {
> + .set_ofs = 0xd0,
> + .clr_ofs = 0xd4,
> + .sta_ofs = 0xd8,
> +};
> +
> +#define GATE_INFRA2(_id, _parent, _shift) { \
> + .id = _id, \
> + .parent = _parent, \
> + .regs = &infra2_cg_regs, \
> + .shift = _shift, \
> + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
> + }
> +
> +#define GATE_INFRA3(_id, _parent, _shift) { \
> + .id = _id, \
> + .parent = _parent, \
> + .regs = &infra3_cg_regs, \
> + .shift = _shift, \
> + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
> + }
> +
> +#define GATE_INFRA4(_id, _parent, _shift) { \
> + .id = _id, \
> + .parent = _parent, \
> + .regs = &infra4_cg_regs, \
> + .shift = _shift, \
> + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
> + }
> +
> +#define GATE_INFRA5(_id, _parent, _shift) { \
> + .id = _id, \
> + .parent = _parent, \
> + .regs = &infra5_cg_regs, \
> + .shift = _shift, \
> + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
> + }
> +
> +#define GATE_INFRA6(_id, _parent, _shift) { \
> + .id = _id, \
> + .parent = _parent, \
> + .regs = &infra6_cg_regs, \
> + .shift = _shift, \
> + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
> + }
> +
> +static const struct mtk_gate infra_clks[] = {
> + /* IFR2 */
> + GATE_INFRA2(CLK_IFR_PMIC_TMR, CLK_TOP_CLK26M, 0),
> + GATE_INFRA2(CLK_IFR_PMIC_AP, CLK_TOP_CLK26M, 1),
> + GATE_INFRA2(CLK_IFR_PMIC_MD, CLK_TOP_CLK26M, 2),
> + GATE_INFRA2(CLK_IFR_PMIC_CONN, CLK_TOP_CLK26M, 3),
> + GATE_INFRA2(CLK_IFR_ICUSB, CLK_TOP_AXI_SEL, 8),
> + GATE_INFRA2(CLK_IFR_GCE, CLK_TOP_AXI_SEL, 9),
> + GATE_INFRA2(CLK_IFR_THERM, CLK_TOP_AXI_SEL, 10),
> + GATE_INFRA2(CLK_IFR_PWM_HCLK, CLK_TOP_AXI_SEL, 15),
> + GATE_INFRA2(CLK_IFR_PWM1, CLK_TOP_PWM_SEL, 16),
> + GATE_INFRA2(CLK_IFR_PWM2, CLK_TOP_PWM_SEL, 17),
> + GATE_INFRA2(CLK_IFR_PWM3, CLK_TOP_PWM_SEL, 18),
> + GATE_INFRA2(CLK_IFR_PWM4, CLK_TOP_PWM_SEL, 19),
> + GATE_INFRA2(CLK_IFR_PWM5, CLK_TOP_PWM_SEL, 20),
> + GATE_INFRA2(CLK_IFR_PWM, CLK_TOP_PWM_SEL, 21),
> + GATE_INFRA2(CLK_IFR_UART0, CLK_TOP_UART_SEL, 22),
> + GATE_INFRA2(CLK_IFR_UART1, CLK_TOP_UART_SEL, 23),
> + GATE_INFRA2(CLK_IFR_UART2, CLK_TOP_UART_SEL, 24),
> + GATE_INFRA2(CLK_IFR_DSP_UART, CLK_TOP_UART_SEL, 26),
> + GATE_INFRA2(CLK_IFR_GCE_26M, CLK_TOP_CLK26M, 27),
> + GATE_INFRA2(CLK_IFR_CQ_DMA_FPC, CLK_TOP_AXI_SEL, 28),
> + GATE_INFRA2(CLK_IFR_BTIF, CLK_TOP_AXI_SEL, 31),
> + /* IFR3 */
> + GATE_INFRA3(CLK_IFR_SPI0, CLK_TOP_SPI_SEL, 1),
> + GATE_INFRA3(CLK_IFR_MSDC0_HCLK, CLK_TOP_MSDC50_0_HC_SEL, 2),
> + GATE_INFRA3(CLK_IFR_MSDC2_HCLK, CLK_TOP_MSDC2_2_HC_SEL, 3),
> + GATE_INFRA3(CLK_IFR_MSDC1_HCLK, CLK_TOP_AXI_SEL, 4),
> + GATE_INFRA3(CLK_IFR_DVFSRC, CLK_TOP_CLK26M, 7),
> + GATE_INFRA3(CLK_IFR_GCPU, CLK_TOP_AXI_SEL, 8),
> + GATE_INFRA3(CLK_IFR_TRNG, CLK_TOP_AXI_SEL, 9),
> + GATE_INFRA3(CLK_IFR_AUXADC, CLK_TOP_CLK26M, 10),
> + GATE_INFRA3(CLK_IFR_AUXADC_MD, CLK_TOP_CLK26M, 14),
> + GATE_INFRA3(CLK_IFR_AP_DMA, CLK_TOP_AXI_SEL, 18),
> + GATE_INFRA3(CLK_IFR_DEBUGSYS, CLK_TOP_AXI_SEL, 24),
> + GATE_INFRA3(CLK_IFR_AUDIO, CLK_TOP_AXI_SEL, 25),
> + /* IFR4 */
> + GATE_INFRA4(CLK_IFR_PWM_FBCLK6, CLK_TOP_PWM_SEL, 0),
> + GATE_INFRA4(CLK_IFR_DISP_PWM, CLK_TOP_DISP_PWM_SEL, 2),
> + GATE_INFRA4(CLK_IFR_AUD_26M_BK, CLK_TOP_CLK26M, 4),
> + GATE_INFRA4(CLK_IFR_CQ_DMA, CLK_TOP_AXI_SEL, 27),
> + /* IFR5 */
> + GATE_INFRA5(CLK_IFR_MSDC0_SF, CLK_TOP_MSDC50_0_SEL, 0),
> + GATE_INFRA5(CLK_IFR_MSDC1_SF, CLK_TOP_MSDC50_0_SEL, 1),
> + GATE_INFRA5(CLK_IFR_MSDC2_SF, CLK_TOP_MSDC50_0_SEL, 2),
> + GATE_INFRA5(CLK_IFR_AP_MSDC0, CLK_TOP_MSDC50_0_SEL, 7),
> + GATE_INFRA5(CLK_IFR_MD_MSDC0, CLK_TOP_MSDC50_0_SEL, 8),
> + GATE_INFRA5(CLK_IFR_MSDC0_SRC, CLK_TOP_MSDC50_0_SEL, 9),
> + GATE_INFRA5(CLK_IFR_MSDC1_SRC, CLK_TOP_MSDC30_1_SEL, 10),
> + GATE_INFRA5(CLK_IFR_MSDC2_SRC, CLK_TOP_MSDC50_2_SEL, 11),
> + GATE_INFRA5(CLK_IFR_PWRAP_TMR, CLK_TOP_CLK26M, 12),
> + GATE_INFRA5(CLK_IFR_PWRAP_SPI, CLK_TOP_CLK26M, 13),
> + GATE_INFRA5(CLK_IFR_PWRAP_SYS, CLK_TOP_CLK26M, 14),
> + GATE_INFRA5(CLK_IFR_IRRX_26M, CLK_TOP_CLK26M, 22),
> + GATE_INFRA5(CLK_IFR_IRRX_32K, CLK_TOP_CLK32K, 23),
> + GATE_INFRA5(CLK_IFR_I2C0_AXI, CLK_TOP_I2C_SEL, 24),
> + GATE_INFRA5(CLK_IFR_I2C1_AXI, CLK_TOP_I2C_SEL, 25),
> + GATE_INFRA5(CLK_IFR_I2C2_AXI, CLK_TOP_I2C_SEL, 26),
> + GATE_INFRA5(CLK_IFR_I2C3_AXI, CLK_TOP_I2C_SEL, 27),
> + GATE_INFRA5(CLK_IFR_NIC_AXI, CLK_TOP_AXI_SEL, 28),
> + GATE_INFRA5(CLK_IFR_NIC_SLV_AXI, CLK_TOP_AXI_SEL, 29),
> + GATE_INFRA5(CLK_IFR_APU_AXI, CLK_TOP_AXI_SEL, 30),
> + /* IFR6 */
> + GATE_INFRA6(CLK_IFR_NFIECC, CLK_TOP_NFIECC_SEL, 0),
> + GATE_INFRA6(CLK_IFR_NFI1X_BK, CLK_TOP_NFI2X_SEL, 1),
> + GATE_INFRA6(CLK_IFR_NFIECC_BK, CLK_TOP_NFI2X_SEL, 2),
> + GATE_INFRA6(CLK_IFR_NFI_BK, CLK_TOP_AXI_SEL, 3),
> + GATE_INFRA6(CLK_IFR_MSDC2_AP_BK, CLK_TOP_AXI_SEL, 4),
> + GATE_INFRA6(CLK_IFR_MSDC2_MD_BK, CLK_TOP_AXI_SEL, 5),
> + GATE_INFRA6(CLK_IFR_MSDC2_BK, CLK_TOP_AXI_SEL, 6),
> + GATE_INFRA6(CLK_IFR_SUSB_133_BK, CLK_TOP_AXI_SEL, 7),
> + GATE_INFRA6(CLK_IFR_SUSB_66_BK, CLK_TOP_AXI_SEL, 8),
> + GATE_INFRA6(CLK_IFR_SSUSB_SYS, CLK_TOP_SSUSB_SYS_SEL, 9),
> + GATE_INFRA6(CLK_IFR_SSUSB_REF, CLK_TOP_SSUSB_SYS_SEL, 10),
> + GATE_INFRA6(CLK_IFR_SSUSB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11),
> +};
> +
> +static const struct mtk_gate_regs top0_cg_regs = {
> + .set_ofs = 0x0,
> + .clr_ofs = 0x0,
> + .sta_ofs = 0x0,
> +};
> +
> +static const struct mtk_gate_regs top1_cg_regs = {
> + .set_ofs = 0x104,
> + .clr_ofs = 0x104,
> + .sta_ofs = 0x104,
> +};
> +
> +#define GATE_TOP0(_id, _parent, _shift) { \
> + .id = _id, \
> + .parent = _parent, \
> + .regs = &top0_cg_regs, \
> + .shift = _shift, \
> + .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
> + }
> +
> +#define GATE_TOP1_I(_id, _parent, _shift) { \
> + .id = _id, \
> + .parent = _parent, \
> + .regs = &top1_cg_regs, \
> + .shift = _shift, \
> + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
> + }
> +
> +static const struct mtk_gate top_clks[] = {
> + /* TOP0 */
> + GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10),
> + GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11),
> + GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16),
> + GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17),
> + /* TOP1 */
> + GATE_TOP1_I(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4, 8),
> + GATE_TOP1_I(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4, 9),
> + GATE_TOP1_I(CLK_TOP_LVDSTX_CLKDIG_EN, CLK_TOP_LVDSTX_CLKDIG_CTS, 20),
> + GATE_TOP1_I(CLK_TOP_VPLL_DPIX_EN, CLK_TOP_VPLL_DPIX, 21),
> + GATE_TOP1_I(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22),
> + GATE_TOP1_I(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23),
> +};
> +
> +static int mt8175_apmixedsys_probe(struct udevice *dev)
> +{
> + return mtk_common_clk_init(dev, &mt8175_clk_tree);
> +}
> +
> +static int mt8175_topckgen_probe(struct udevice *dev)
> +{
> + return mtk_common_clk_init(dev, &mt8175_clk_tree);
> +}
> +
> +static int mt8175_topckgen_cg_probe(struct udevice *dev)
> +{
> + return mtk_common_clk_gate_init(dev, &mt8175_clk_tree, top_clks);
> +}
> +
> +static int mt8175_infracfg_probe(struct udevice *dev)
> +{
> + return mtk_common_clk_gate_init(dev, &mt8175_clk_tree, infra_clks);
> +}
> +
> +static const struct udevice_id mt8175_apmixed_compat[] = {
> + { .compatible = "mediatek,mt8175-apmixedsys", },
> + { }
> +};
> +
> +static const struct udevice_id mt8175_topckgen_compat[] = {
> + { .compatible = "mediatek,mt8175-topckgen", },
> + { }
> +};
> +
> +static const struct udevice_id mt8175_topckgen_cg_compat[] = {
> + { .compatible = "mediatek,mt8175-topckgen-cg", },
> + { }
> +};
> +
> +static const struct udevice_id mt8175_infracfg_compat[] = {
> + { .compatible = "mediatek,mt8175-infracfg", },
> + { }
> +};
> +
> +U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
> + .name = "mt8175-apmixedsys",
> + .id = UCLASS_CLK,
> + .of_match = mt8175_apmixed_compat,
> + .probe = mt8175_apmixedsys_probe,
> + .priv_auto = sizeof(struct mtk_clk_priv),
> + .ops = &mtk_clk_apmixedsys_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
> +
> +U_BOOT_DRIVER(mtk_clk_topckgen) = {
> + .name = "mt8175-topckgen",
> + .id = UCLASS_CLK,
> + .of_match = mt8175_topckgen_compat,
> + .probe = mt8175_topckgen_probe,
> + .priv_auto = sizeof(struct mtk_clk_priv),
> + .ops = &mtk_clk_topckgen_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
> +
> +U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
> + .name = "mt8175-topckgen-cg",
> + .id = UCLASS_CLK,
> + .of_match = mt8175_topckgen_cg_compat,
> + .probe = mt8175_topckgen_cg_probe,
> + .priv_auto = sizeof(struct mtk_clk_priv),
> + .ops = &mtk_clk_gate_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
> +
> +U_BOOT_DRIVER(mtk_clk_infracfg) = {
> + .name = "mt8175-infracfg",
> + .id = UCLASS_CLK,
> + .of_match = mt8175_infracfg_compat,
> + .probe = mt8175_infracfg_probe,
> + .priv_auto = sizeof(struct mtk_clk_priv),
> + .ops = &mtk_clk_gate_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
> diff --git a/include/dt-bindings/clock/mt8175-clk.h b/include/dt-bindings/clock/mt8175-clk.h
> new file mode 100644
> index 000000000000..4f5992db3ec9
> --- /dev/null
> +++ b/include/dt-bindings/clock/mt8175-clk.h
> @@ -0,0 +1,392 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_MT8175_H
> +#define _DT_BINDINGS_CLK_MT8175_H
> +
> +/* TOPCKGEN */
> +
> +#define CLK_TOP_CLK_NULL 0
> +#define CLK_TOP_DSI0_LNTC_DSICK 1
> +#define CLK_TOP_VPLL_DPIX 2
> +#define CLK_TOP_LVDSTX_CLKDIG_CTS 3
> +#define CLK_TOP_CLK26M 4
> +#define CLK_TOP_CLK32K 5
> +#define CLK_TOP_I2S0_BCK 6
> +#define CLK_TOP_SYS_26M_D2 7
> +#define CLK_TOP_SYSPLL_D2 8
> +#define CLK_TOP_SYSPLL1_D2 9
> +#define CLK_TOP_SYSPLL1_D4 10
> +#define CLK_TOP_SYSPLL1_D8 11
> +#define CLK_TOP_SYSPLL1_D16 12
> +#define CLK_TOP_SYSPLL_D3 13
> +#define CLK_TOP_SYSPLL2_D2 14
> +#define CLK_TOP_SYSPLL2_D4 15
> +#define CLK_TOP_SYSPLL2_D8 16
> +#define CLK_TOP_SYSPLL_D5 17
> +#define CLK_TOP_SYSPLL3_D2 18
> +#define CLK_TOP_SYSPLL3_D4 19
> +#define CLK_TOP_SYSPLL_D7 20
> +#define CLK_TOP_SYSPLL4_D2 21
> +#define CLK_TOP_SYSPLL4_D4 22
> +#define CLK_TOP_UNIVPLL 23
> +#define CLK_TOP_UNIVPLL_D2 24
> +#define CLK_TOP_UNIVPLL1_D2 25
> +#define CLK_TOP_UNIVPLL1_D4 26
> +#define CLK_TOP_UNIVPLL_D3 27
> +#define CLK_TOP_UNIVPLL2_D2 28
> +#define CLK_TOP_UNIVPLL2_D4 29
> +#define CLK_TOP_UNIVPLL2_D8 30
> +#define CLK_TOP_UNIVPLL2_D32 31
> +#define CLK_TOP_UNIVPLL_D5 32
> +#define CLK_TOP_UNIVPLL3_D2 33
> +#define CLK_TOP_UNIVPLL3_D4 34
> +#define CLK_TOP_MMPLL 35
> +#define CLK_TOP_MMPLL_D2 36
> +#define CLK_TOP_MFGPLL 37
> +#define CLK_TOP_LVDSPLL_D2 38
> +#define CLK_TOP_LVDSPLL_D4 39
> +#define CLK_TOP_LVDSPLL_D8 40
> +#define CLK_TOP_LVDSPLL_D16 41
> +#define CLK_TOP_USB20_192M 42
> +#define CLK_TOP_USB20_192M_D4 43
> +#define CLK_TOP_USB20_192M_D8 44
> +#define CLK_TOP_USB20_192M_D16 45
> +#define CLK_TOP_USB20_192M_D32 46
> +#define CLK_TOP_APLL1 47
> +#define CLK_TOP_APLL1_D2 48
> +#define CLK_TOP_APLL1_D4 49
> +#define CLK_TOP_APLL1_D8 50
> +#define CLK_TOP_APLL2 51
> +#define CLK_TOP_APLL2_D2 52
> +#define CLK_TOP_APLL2_D4 53
> +#define CLK_TOP_APLL2_D8 54
> +#define CLK_TOP_MSDCPLL 55
> +#define CLK_TOP_MSDCPLL_D2 56
> +#define CLK_TOP_DSPPLL 57
> +#define CLK_TOP_DSPPLL_D2 58
> +#define CLK_TOP_DSPPLL_D4 59
> +#define CLK_TOP_DSPPLL_D8 60
> +#define CLK_TOP_APUPLL 61
> +#define CLK_TOP_CLK26M_D52 62
> +#define CLK_TOP_AXI_SEL 63
> +#define CLK_TOP_MEM_SEL 64
> +#define CLK_TOP_MM_SEL 65
> +#define CLK_TOP_SCP_SEL 66
> +#define CLK_TOP_MFG_SEL 67
> +#define CLK_TOP_ATB_SEL 68
> +#define CLK_TOP_CAMTG_SEL 69
> +#define CLK_TOP_CAMTG1_SEL 70
> +#define CLK_TOP_UART_SEL 71
> +#define CLK_TOP_SPI_SEL 72
> +#define CLK_TOP_MSDC50_0_HC_SEL 73
> +#define CLK_TOP_MSDC2_2_HC_SEL 74
> +#define CLK_TOP_MSDC50_0_SEL 75
> +#define CLK_TOP_MSDC50_2_SEL 76
> +#define CLK_TOP_MSDC30_1_SEL 77
> +#define CLK_TOP_AUDIO_SEL 78
> +#define CLK_TOP_AUD_INTBUS_SEL 79
> +#define CLK_TOP_AUD_1_SEL 80
> +#define CLK_TOP_AUD_2_SEL 81
> +#define CLK_TOP_AUD_ENGEN1_SEL 82
> +#define CLK_TOP_AUD_ENGEN2_SEL 83
> +#define CLK_TOP_AUD_SPDIF_SEL 84
> +#define CLK_TOP_DISP_PWM_SEL 85
> +#define CLK_TOP_DXCC_SEL 86
> +#define CLK_TOP_SSUSB_SYS_SEL 87
> +#define CLK_TOP_SSUSB_XHCI_SEL 88
> +#define CLK_TOP_SPM_SEL 89
> +#define CLK_TOP_I2C_SEL 90
> +#define CLK_TOP_PWM_SEL 91
> +#define CLK_TOP_SENIF_SEL 92
> +#define CLK_TOP_AES_FDE_SEL 93
> +#define CLK_TOP_CAMTM_SEL 94
> +#define CLK_TOP_DPI0_SEL 95
> +#define CLK_TOP_DPI1_SEL 96
> +#define CLK_TOP_DSP_SEL 97
> +#define CLK_TOP_NFI2X_SEL 98
> +#define CLK_TOP_NFIECC_SEL 99
> +#define CLK_TOP_ECC_SEL 100
> +#define CLK_TOP_ETH_SEL 101
> +#define CLK_TOP_GCPU_SEL 102
> +#define CLK_TOP_GCPU_CPM_SEL 103
> +#define CLK_TOP_APU_SEL 104
> +#define CLK_TOP_APU_IF_SEL 105
> +#define CLK_TOP_MBIST_DIAG_SEL 106
> +#define CLK_TOP_APLL_I2S0_SEL 107
> +#define CLK_TOP_APLL_I2S1_SEL 108
> +#define CLK_TOP_APLL_I2S2_SEL 109
> +#define CLK_TOP_APLL_I2S3_SEL 110
> +#define CLK_TOP_APLL_TDMOUT_SEL 111
> +#define CLK_TOP_APLL_TDMIN_SEL 112
> +#define CLK_TOP_APLL_SPDIF_SEL 113
> +#define CLK_TOP_APLL12_CK_DIV0 114
> +#define CLK_TOP_APLL12_CK_DIV1 115
> +#define CLK_TOP_APLL12_CK_DIV2 116
> +#define CLK_TOP_APLL12_CK_DIV3 117
> +#define CLK_TOP_APLL12_CK_DIV4 118
> +#define CLK_TOP_APLL12_CK_DIV4B 119
> +#define CLK_TOP_APLL12_CK_DIV5 120
> +#define CLK_TOP_APLL12_CK_DIV5B 121
> +#define CLK_TOP_APLL12_CK_DIV6 122
> +#define CLK_TOP_NR_CLK 123
> +
> +/* TOPCKGEN Gates */
> +#define CLK_TOP_CONN_32K 0
> +#define CLK_TOP_CONN_26M 1
> +#define CLK_TOP_DSP_32K 2
> +#define CLK_TOP_DSP_26M 3
> +#define CLK_TOP_USB20_48M_EN 4
> +#define CLK_TOP_UNIVPLL_48M_EN 5
> +#define CLK_TOP_LVDSTX_CLKDIG_EN 6
> +#define CLK_TOP_VPLL_DPIX_EN 7
> +#define CLK_TOP_SSUSB_TOP_CK_EN 8
> +#define CLK_TOP_SSUSB_PHY_CK_EN 9
> +#define CLK_TOP_AUD_I2S0_M 10
> +#define CLK_TOP_AUD_I2S1_M 11
> +#define CLK_TOP_AUD_I2S2_M 12
> +#define CLK_TOP_AUD_I2S3_M 13
> +#define CLK_TOP_AUD_TDMOUT_M 14
> +#define CLK_TOP_AUD_TDMOUT_B 15
> +#define CLK_TOP_AUD_TDMIN_M 16
> +#define CLK_TOP_AUD_TDMIN_B 17
> +#define CLK_TOP_AUD_SPDIF_M 18
> +
> +/* INFRACFG */
> +
> +#define CLK_IFR_PMIC_TMR 0
> +#define CLK_IFR_PMIC_AP 1
> +#define CLK_IFR_PMIC_MD 2
> +#define CLK_IFR_PMIC_CONN 3
> +#define CLK_IFR_ICUSB 4
> +#define CLK_IFR_GCE 5
> +#define CLK_IFR_THERM 6
> +#define CLK_IFR_PWM_HCLK 7
> +#define CLK_IFR_PWM1 8
> +#define CLK_IFR_PWM2 9
> +#define CLK_IFR_PWM3 10
> +#define CLK_IFR_PWM4 11
> +#define CLK_IFR_PWM5 12
> +#define CLK_IFR_PWM 13
> +#define CLK_IFR_UART0 14
> +#define CLK_IFR_UART1 15
> +#define CLK_IFR_UART2 16
> +#define CLK_IFR_DSP_UART 17
> +#define CLK_IFR_GCE_26M 18
> +#define CLK_IFR_CQ_DMA_FPC 19
> +#define CLK_IFR_BTIF 20
> +#define CLK_IFR_SPI0 21
> +#define CLK_IFR_MSDC0_HCLK 22
> +#define CLK_IFR_MSDC2_HCLK 23
> +#define CLK_IFR_MSDC1_HCLK 24
> +#define CLK_IFR_DVFSRC 25
> +#define CLK_IFR_GCPU 26
> +#define CLK_IFR_TRNG 27
> +#define CLK_IFR_AUXADC 28
> +#define CLK_IFR_AUXADC_MD 29
> +#define CLK_IFR_AP_DMA 30
> +#define CLK_IFR_DEBUGSYS 31
> +#define CLK_IFR_AUDIO 32
> +#define CLK_IFR_PWM_FBCLK6 33
> +#define CLK_IFR_DISP_PWM 34
> +#define CLK_IFR_AUD_26M_BK 35
> +#define CLK_IFR_CQ_DMA 36
> +#define CLK_IFR_MSDC0_SF 37
> +#define CLK_IFR_MSDC1_SF 38
> +#define CLK_IFR_MSDC2_SF 39
> +#define CLK_IFR_AP_MSDC0 40
> +#define CLK_IFR_MD_MSDC0 41
> +#define CLK_IFR_MSDC0_SRC 42
> +#define CLK_IFR_MSDC1_SRC 43
> +#define CLK_IFR_MSDC2_SRC 44
> +#define CLK_IFR_PWRAP_TMR 45
> +#define CLK_IFR_PWRAP_SPI 46
> +#define CLK_IFR_PWRAP_SYS 47
> +#define CLK_IFR_IRRX_26M 48
> +#define CLK_IFR_IRRX_32K 49
> +#define CLK_IFR_I2C0_AXI 50
> +#define CLK_IFR_I2C1_AXI 51
> +#define CLK_IFR_I2C2_AXI 52
> +#define CLK_IFR_I2C3_AXI 53
> +#define CLK_IFR_NIC_AXI 54
> +#define CLK_IFR_NIC_SLV_AXI 55
> +#define CLK_IFR_APU_AXI 56
> +#define CLK_IFR_NFIECC 57
> +#define CLK_IFR_NFI1X_BK 58
> +#define CLK_IFR_NFIECC_BK 59
> +#define CLK_IFR_NFI_BK 60
> +#define CLK_IFR_MSDC2_AP_BK 61
> +#define CLK_IFR_MSDC2_MD_BK 62
> +#define CLK_IFR_MSDC2_BK 63
> +#define CLK_IFR_SUSB_133_BK 64
> +#define CLK_IFR_SUSB_66_BK 65
> +#define CLK_IFR_SSUSB_SYS 66
> +#define CLK_IFR_SSUSB_REF 67
> +#define CLK_IFR_SSUSB_XHCI 68
> +#define CLK_IFR_NR_CLK 69
> +
> +/* PERICFG */
> +
> +#define CLK_PERIAXI 0
> +#define CLK_PERI_NR_CLK 1
> +
> +/* APMIXEDSYS */
> +
> +#define CLK_APMIXED_ARMPLL 0
> +#define CLK_APMIXED_MAINPLL 1
> +#define CLK_APMIXED_UNIVPLL 2
> +#define CLK_APMIXED_MFGPLL 3
> +#define CLK_APMIXED_MSDCPLL 4
> +#define CLK_APMIXED_MMPLL 5
> +#define CLK_APMIXED_APLL1 6
> +#define CLK_APMIXED_APLL2 7
> +#define CLK_APMIXED_LVDSPLL 8
> +#define CLK_APMIXED_DSPPLL 9
> +#define CLK_APMIXED_APUPLL 10
> +#define CLK_APMIXED_NR_CLK 11
> +
> +/* GCE */
> +
> +#define CLK_GCE_FAXI 0
> +#define CLK_GCE_NR_CLK 1
> +
> +/* AUDIOTOP */
> +
> +#define CLK_AUD_AFE 0
> +#define CLK_AUD_I2S 1
> +#define CLK_AUD_22M 2
> +#define CLK_AUD_24M 3
> +#define CLK_AUD_INTDIR 4
> +#define CLK_AUD_APLL2_TUNER 5
> +#define CLK_AUD_APLL_TUNER 6
> +#define CLK_AUD_SPDF 7
> +#define CLK_AUD_HDMI 8
> +#define CLK_AUD_HDMI_IN 9
> +#define CLK_AUD_ADC 10
> +#define CLK_AUD_DAC 11
> +#define CLK_AUD_DAC_PREDIS 12
> +#define CLK_AUD_TML 13
> +#define CLK_AUD_I2S1_BK 14
> +#define CLK_AUD_I2S2_BK 15
> +#define CLK_AUD_I2S3_BK 16
> +#define CLK_AUD_I2S4_BK 17
> +#define CLK_AUD_NR_CLK 18
> +
> +/* MIPI_CSI0A */
> +
> +#define CLK_MIPI0A_CSR_CSI_EN_0A 0
> +#define CLK_MIPI_RX_ANA_CSI0A_NR_CLK 1
> +
> +/* MIPI_CSI0B */
> +
> +#define CLK_MIPI0B_CSR_CSI_EN_0B 0
> +#define CLK_MIPI_RX_ANA_CSI0B_NR_CLK 1
> +
> +/* MIPI_CSI1A */
> +
> +#define CLK_MIPI1A_CSR_CSI_EN_1A 0
> +#define CLK_MIPI_RX_ANA_CSI1A_NR_CLK 1
> +
> +/* MIPI_CSI1B */
> +
> +#define CLK_MIPI1B_CSR_CSI_EN_1B 0
> +#define CLK_MIPI_RX_ANA_CSI1B_NR_CLK 1
> +
> +/* MIPI_CSI2A */
> +
> +#define CLK_MIPI2A_CSR_CSI_EN_2A 0
> +#define CLK_MIPI_RX_ANA_CSI2A_NR_CLK 1
> +
> +/* MIPI_CSI2B */
> +
> +#define CLK_MIPI2B_CSR_CSI_EN_2B 0
> +#define CLK_MIPI_RX_ANA_CSI2B_NR_CLK 1
> +
> +/* MCUCFG */
> +
> +#define CLK_MCU_BUS_SEL 0
> +#define CLK_MCU_NR_CLK 1
> +
> +/* MFGCFG */
> +
> +#define CLK_MFG_BG3D 0
> +#define CLK_MFG_MBIST_DIAG 1
> +#define CLK_MFG_NR_CLK 2
> +
> +/* MMSYS */
> +
> +#define CLK_MM_MM_MDP_RDMA0 0
> +#define CLK_MM_MM_MDP_CCORR0 1
> +#define CLK_MM_MM_MDP_RSZ0 2
> +#define CLK_MM_MM_MDP_RSZ1 3
> +#define CLK_MM_MM_MDP_TDSHP0 4
> +#define CLK_MM_MM_MDP_WROT0 5
> +#define CLK_MM_MM_MDP_WDMA0 6
> +#define CLK_MM_MM_DISP_OVL0 7
> +#define CLK_MM_MM_DISP_OVL0_21 8
> +#define CLK_MM_MM_DISP_RSZ0 9
> +#define CLK_MM_MM_DISP_RDMA0 10
> +#define CLK_MM_MM_DISP_WDMA0 11
> +#define CLK_MM_MM_DISP_COLOR0 12
> +#define CLK_MM_MM_DISP_CCORR0 13
> +#define CLK_MM_MM_DISP_AAL0 14
> +#define CLK_MM_MM_DISP_GAMMA0 15
> +#define CLK_MM_MM_DISP_DITHER0 16
> +#define CLK_MM_MM_DSI0 17
> +#define CLK_MM_MM_DISP_RDMA1 18
> +#define CLK_MM_MM_MDP_RDMA1 19
> +#define CLK_MM_DPI0_DPI0 20
> +#define CLK_MM_MM_FAKE 21
> +#define CLK_MM_MM_SMI_COMMON 22
> +#define CLK_MM_MM_SMI_LARB0 23
> +#define CLK_MM_MM_SMI_COMM0 24
> +#define CLK_MM_MM_SMI_COMM1 25
> +#define CLK_MM_MM_CAM_MDP 26
> +#define CLK_MM_MM_SMI_IMG 27
> +#define CLK_MM_MM_SMI_CAM 28
> +#define CLK_MM_IMG_IMG_DL_RELAY 29
> +#define CLK_MM_IMG_IMG_DL_ASYNC_TOP 30
> +#define CLK_MM_DSI0_DIG_DSI 31
> +#define CLK_MM_26M_HRTWT 32
> +#define CLK_MM_MM_DPI0 33
> +#define CLK_MM_LVDSTX_PXL 34
> +#define CLK_MM_LVDSTX_CTS 35
> +#define CLK_MM_NR_CLK 36
> +
> +/* IMGSYS */
> +
> +#define CLK_CAM_LARB2 0
> +#define CLK_CAM 1
> +#define CLK_CAMTG 2
> +#define CLK_CAM_SENIF 3
> +#define CLK_CAMSV0 4
> +#define CLK_CAMSV1 5
> +#define CLK_CAM_FDVT 6
> +#define CLK_CAM_WPE 7
> +#define CLK_CAM_NR_CLK 8
> +
> +/* VDECSYS */
> +
> +#define CLK_VDEC_VDEC 0
> +#define CLK_VDEC_LARB1 1
> +#define CLK_VDEC_NR_CLK 2
> +
> +/* VENCSYS */
> +
> +#define CLK_VENC 0
> +#define CLK_VENC_JPGENC 1
> +#define CLK_VENC_NR_CLK 2
> +
> +/* APUSYS */
> +
> +#define CLK_APU_IPU_CK 0
> +#define CLK_APU_AXI 1
> +#define CLK_APU_JTAG 2
> +#define CLK_APU_IF_CK 3
> +#define CLK_APU_EDMA 4
> +#define CLK_APU_AHB 5
> +#define CLK_APU_NR_CLK 6
> +
> +#endif /* _DT_BINDINGS_CLK_MT8175_H */
> --
> 2.31.0
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/3] clk: mediatek: Add MT8175 clock driver
@ 2021-03-29 19:27 Fabien Parent
0 siblings, 0 replies; 6+ messages in thread
From: Fabien Parent @ 2021-03-29 19:27 UTC (permalink / raw)
To: u-boot
Add the topckgen, apmixedsys and infracfg clock driver for the MT8175
SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8175.c | 785 +++++++++++++++++++++++++
include/dt-bindings/clock/mt8175-clk.h | 392 ++++++++++++
3 files changed, 1178 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8175.c
create mode 100644 include/dt-bindings/clock/mt8175-clk.h
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 522e72422144..0f3135eca39c 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_MT8512) += clk-mt8512.o
obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
+obj-$(CONFIG_TARGET_MT8175) += clk-mt8175.o
obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
diff --git a/drivers/clk/mediatek/clk-mt8175.c b/drivers/clk/mediatek/clk-mt8175.c
new file mode 100644
index 000000000000..cb5841181d2d
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8175.c
@@ -0,0 +1,785 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8175 SoC
+ *
+ * Copyright (C) 2021 BayLibre, SAS
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Fabien Parent <fparent@baylibre.com>
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt8175-clk.h>
+
+#include "clk-mtk.h"
+
+#define MT8175_PLL_FMAX (3800UL * MHZ)
+#define MT8175_PLL_FMIN (1500UL * MHZ)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .rst_bar_mask = BIT(23), \
+ .fmax = MT8175_PLL_FMAX, \
+ .flags = _flags, \
+ .pcwbits = _pcwbits, \
+ .pcwibits = 8, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001, 0, 22, 0x0310, 24,
+ 0x0310, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0xFF000001, HAVE_RST_BAR, 22,
+ 0x022C, 24, 0x022C, 0),
+ PLL(CLK_APMIXED_UNIVPLL, 0x0208, 0x0214, 0xFF000001, HAVE_RST_BAR, 22,
+ 0x020C, 24, 0x020C, 0),
+ PLL(CLK_APMIXED_MFGPLL, 0x0218, 0x0224, 0x00000001, 0, 22, 0x021C, 24,
+ 0x021C, 0),
+ PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001, 0, 22, 0x0354, 24,
+ 0x0354, 0),
+ PLL(CLK_APMIXED_MMPLL, 0x0330, 0x033C, 0x00000001, 0, 22, 0x0334, 24,
+ 0x0334, 0),
+ PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001, 0, 32, 0x0320, 24,
+ 0x0324, 0),
+ PLL(CLK_APMIXED_APLL2, 0x0360, 0x0370, 0x00000001, 0, 32, 0x0364, 24,
+ 0x0368, 0),
+ PLL(CLK_APMIXED_LVDSPLL, 0x0374, 0x0380, 0x00000001, 0, 22, 0x0378, 24,
+ 0x0378, 0),
+ PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x00000001, 0, 22, 0x0394, 24,
+ 0x0394, 0),
+ PLL(CLK_APMIXED_APUPLL, 0x03A0, 0x03AC, 0x00000001, 0, 22, 0x03A4, 24,
+ 0x03A4, 0),
+};
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 0),
+ FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, CLK_TOP_CLK26M, 75000000),
+ FIXED_CLK(CLK_TOP_VPLL_DPIX, CLK_TOP_CLK26M, 75000000),
+ FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, CLK_TOP_CLK26M, 52500000),
+ FIXED_CLK(CLK_TOP_CLK26M, CLK_XTAL, 26000000),
+ FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+ FACTOR(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL, 1, 2, CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12,
+ CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24,
+ CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_UNIVPLL2_D32, CLK_TOP_UNIVPLL, 1, 96,
+ CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10,
+ CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20,
+ CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_MMPLL, CLK_APMIXED_MMPLL, 1, 1,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_MFGPLL, CLK_APMIXED_MFGPLL, 1, 1,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_LVDSPLL_D2, CLK_APMIXED_LVDSPLL, 1, 2,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_LVDSPLL_D4, CLK_APMIXED_LVDSPLL, 1, 4,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_LVDSPLL_D8, CLK_APMIXED_LVDSPLL, 1, 8,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_LVDSPLL_D16, CLK_APMIXED_LVDSPLL, 1, 16,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_USB20_192M, CLK_TOP_UNIVPLL, 1, 1, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_USB20_192M_D4, CLK_TOP_USB20_192M, 1, 4,
+ CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_USB20_192M_D8, CLK_TOP_USB20_192M, 1, 8,
+ CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_USB20_192M_D16, CLK_TOP_USB20_192M, 1, 16,
+ CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_USB20_192M_D32, CLK_TOP_USB20_192M, 1, 32,
+ CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1, CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_APLL1_D2, CLK_TOP_APLL1, 1, 2, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 4, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_APLL1_D8, CLK_TOP_APLL1, 1, 8, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1, CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_APLL2_D4, CLK_TOP_APLL2, 1, 4, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_APLL2_D8, CLK_TOP_APLL2, 1, 8, CLK_PARENT_TOPCKGEN),
+ FACTOR(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1, CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2,
+ CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_DSPPLL, CLK_APMIXED_DSPPLL, 1, 1, CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_DSPPLL_D2, CLK_APMIXED_DSPPLL, 1, 2, CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_DSPPLL_D4, CLK_APMIXED_DSPPLL, 1, 4, CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_DSPPLL_D8, CLK_APMIXED_DSPPLL, 1, 8, CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_APUPLL, CLK_APMIXED_APUPLL, 1, 1, CLK_PARENT_APMIXED),
+ FACTOR(CLK_TOP_CLK26M_D52, CLK_TOP_CLK26M, 1, 52, CLK_PARENT_TOPCKGEN),
+};
+
+static const int axi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL_D7,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYSPLL3_D2
+};
+
+static const int mem_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MMPLL,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_SYSPLL1_D2
+};
+
+static const int mm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MMPLL,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_SYSPLL_D5,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_UNIVPLL_D5,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_MMPLL_D2,
+};
+
+static const int scp_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL4_D2,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_UNIVPLL_D3
+};
+
+static const int mfg_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MFGPLL,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_UNIVPLL_D3
+};
+
+static const int atb_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYSPLL1_D2
+};
+
+static const int camtg_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_USB20_192M_D8,
+ CLK_TOP_UNIVPLL2_D8,
+ CLK_TOP_USB20_192M_D4,
+ CLK_TOP_UNIVPLL2_D32,
+ CLK_TOP_USB20_192M_D16,
+ CLK_TOP_USB20_192M_D32,
+};
+
+static const int uart_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const int spi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const int msdc50_0_hc_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_SYSPLL2_D2
+};
+
+static const int msdc50_0_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MSDCPLL,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL_D5,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_SYSPLL4_D2
+};
+
+static const int msdc50_2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MSDCPLL,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4
+};
+
+static const int msdc30_1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MSDCPLL_D2,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYSPLL2_D4,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const int audio_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL3_D4,
+ CLK_TOP_SYSPLL4_D4,
+ CLK_TOP_SYSPLL1_D16
+};
+
+static const int aud_intbus_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYSPLL4_D2
+};
+
+static const int aud_1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL1
+};
+
+static const int aud_2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL2
+};
+
+static const int aud_engen1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL1_D2,
+ CLK_TOP_APLL1_D4,
+ CLK_TOP_APLL1_D8
+};
+
+static const int aud_engen2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL2_D2,
+ CLK_TOP_APLL2_D4,
+ CLK_TOP_APLL2_D8,
+};
+
+static const int aud_spdif_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D2
+};
+
+static const int disp_pwm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D4
+};
+
+static const int dxcc_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYSPLL1_D8
+};
+
+static const int ssusb_sys_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_UNIVPLL3_D2
+};
+
+static const int spm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D8
+};
+
+static const int i2c_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_UNIVPLL3_D2,
+ CLK_TOP_SYSPLL1_D8,
+ CLK_TOP_SYSPLL2_D8
+};
+
+static const int pwm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_SYSPLL1_D8
+};
+
+static const int senif_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_UNIVPLL2_D2
+};
+
+static const int aes_fde_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MSDCPLL,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D2
+};
+
+static const int dpi0_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_LVDSPLL_D2,
+ CLK_TOP_LVDSPLL_D4,
+ CLK_TOP_LVDSPLL_D8,
+ CLK_TOP_LVDSPLL_D16
+};
+
+static const int dsp_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYS_26M_D2,
+ CLK_TOP_DSPPLL,
+ CLK_TOP_DSPPLL_D2,
+ CLK_TOP_DSPPLL_D4,
+ CLK_TOP_DSPPLL_D8
+};
+
+static const int nfi2x_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_SYSPLL_D7,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_SYSPLL2_D4,
+ CLK_TOP_MSDCPLL_D2,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_UNIVPLL_D5
+};
+
+static const int nfiecc_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL4_D2,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_SYSPLL_D7,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL_D5
+};
+
+static const int ecc_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_SYSPLL_D2
+};
+
+static const int eth_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D8,
+ CLK_TOP_SYSPLL4_D4,
+ CLK_TOP_SYSPLL1_D8,
+ CLK_TOP_SYSPLL4_D2
+};
+
+static const int gcpu_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_SYSPLL2_D2
+};
+
+static const int gcpu_cpm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL2_D2
+};
+
+static const int apu_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D2,
+ CLK_APMIXED_APUPLL,
+ CLK_TOP_MMPLL,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_SYSPLL1_D4
+};
+
+static const struct mtk_composite top_muxes[] = {
+ /* CLK_CFG_0 */
+ MUX(CLK_TOP_AXI_SEL, axi_parents, 0x040, 0, 2),
+ MUX(CLK_TOP_MEM_SEL, mem_parents, 0x040, 8, 2),
+ MUX(CLK_TOP_MM_SEL, mm_parents, 0x040, 16, 3),
+ MUX(CLK_TOP_SCP_SEL, scp_parents, 0x040, 24, 3),
+ /* CLK_CFG_1 */
+ MUX(CLK_TOP_MFG_SEL, mfg_parents, 0x050, 0, 2),
+ MUX(CLK_TOP_ATB_SEL, atb_parents, 0x050, 8, 2),
+ MUX(CLK_TOP_CAMTG_SEL, camtg_parents, 0x050, 16, 3),
+ MUX(CLK_TOP_CAMTG1_SEL, camtg_parents, 0x050, 24, 3),
+ /* CLK_CFG_2 */
+ MUX(CLK_TOP_UART_SEL, uart_parents, 0x060, 0, 1),
+ MUX(CLK_TOP_SPI_SEL, spi_parents, 0x060, 8, 2),
+ MUX(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents, 0x060, 16, 2),
+ MUX(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents, 0x060, 24, 2),
+ /* CLK_CFG_3 */
+ MUX(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, 0x070, 0, 3),
+ MUX(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents, 0x070, 8, 3),
+ MUX(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x070, 16, 3),
+ MUX(CLK_TOP_AUDIO_SEL, audio_parents, 0x070, 24, 2),
+ /* CLK_CFG_4 */
+ MUX(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x080, 0, 2),
+ MUX(CLK_TOP_AUD_1_SEL, aud_1_parents, 0x080, 8, 1),
+ MUX(CLK_TOP_AUD_2_SEL, aud_2_parents, 0x080, 16, 1),
+ MUX(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x080, 24, 2),
+ /* CLK_CFG_5 */
+ MUX(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x090, 0, 2),
+ MUX(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents, 0x090, 8, 1),
+ MUX(CLK_TOP_DISP_PWM_SEL, disp_pwm_parents, 0x090, 16, 2),
+ /* CLK_CFG_6 */
+ MUX(CLK_TOP_DXCC_SEL, dxcc_parents, 0x0a0, 0, 2),
+ MUX(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents, 0x0a0, 8, 2),
+ MUX(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents, 0x0a0, 16, 2),
+ MUX(CLK_TOP_SPM_SEL, spm_parents, 0x0a0, 24, 1),
+ /* CLK_CFG_7 */
+ MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x0b0, 0, 3),
+ MUX(CLK_TOP_PWM_SEL, pwm_parents, 0x0b0, 8, 2),
+ MUX(CLK_TOP_SENIF_SEL, senif_parents, 0x0b0, 16, 2),
+ MUX(CLK_TOP_AES_FDE_SEL, aes_fde_parents, 0x0b0, 24, 3),
+ /* CLK_CFG_8 */
+ MUX(CLK_TOP_CAMTM_SEL, senif_parents, 0x0c0, 0, 2),
+ MUX(CLK_TOP_DPI0_SEL, dpi0_parents, 0x0c0, 8, 3),
+ MUX(CLK_TOP_DPI1_SEL, dpi0_parents, 0x0c0, 16, 3),
+ MUX(CLK_TOP_DSP_SEL, dsp_parents, 0x0c0, 24, 3),
+ /* CLK_CFG_9 */
+ MUX(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x0d0, 0, 3),
+ MUX(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x0d0, 8, 3),
+ MUX(CLK_TOP_ECC_SEL, ecc_parents, 0x0d0, 16, 3),
+ MUX(CLK_TOP_ETH_SEL, eth_parents, 0x0d0, 24, 3),
+ /* CLK_CFG_10 */
+ MUX(CLK_TOP_GCPU_SEL, gcpu_parents, 0x0e0, 0, 3),
+ MUX(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents, 0x0e0, 8, 2),
+ MUX(CLK_TOP_APU_SEL, apu_parents, 0x0e0, 16, 3),
+ MUX(CLK_TOP_APU_IF_SEL, apu_parents, 0x0e0, 24, 3),
+};
+
+static const struct mtk_clk_tree mt8175_clk_tree = {
+ .xtal_rate = 26 * MHZ,
+ .xtal2_rate = 26 * MHZ,
+ .fdivs_offs = CLK_TOP_SYSPLL_D2,
+ .muxes_offs = CLK_TOP_AXI_SEL,
+ .plls = apmixed_plls,
+ .fclks = top_fixed_clks,
+ .fdivs = top_fixed_divs,
+ .muxes = top_muxes,
+};
+
+static const struct mtk_gate_regs infra2_cg_regs = {
+ .set_ofs = 0x80,
+ .clr_ofs = 0x84,
+ .sta_ofs = 0x90,
+};
+
+static const struct mtk_gate_regs infra3_cg_regs = {
+ .set_ofs = 0x88,
+ .clr_ofs = 0x8c,
+ .sta_ofs = 0x94,
+};
+
+static const struct mtk_gate_regs infra4_cg_regs = {
+ .set_ofs = 0xa4,
+ .clr_ofs = 0xa8,
+ .sta_ofs = 0xac,
+};
+
+static const struct mtk_gate_regs infra5_cg_regs = {
+ .set_ofs = 0xc0,
+ .clr_ofs = 0xc4,
+ .sta_ofs = 0xc8,
+};
+
+static const struct mtk_gate_regs infra6_cg_regs = {
+ .set_ofs = 0xd0,
+ .clr_ofs = 0xd4,
+ .sta_ofs = 0xd8,
+};
+
+#define GATE_INFRA2(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_INFRA3(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra3_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_INFRA4(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra4_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_INFRA5(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra5_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_INFRA6(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra6_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate infra_clks[] = {
+ /* IFR2 */
+ GATE_INFRA2(CLK_IFR_PMIC_TMR, CLK_TOP_CLK26M, 0),
+ GATE_INFRA2(CLK_IFR_PMIC_AP, CLK_TOP_CLK26M, 1),
+ GATE_INFRA2(CLK_IFR_PMIC_MD, CLK_TOP_CLK26M, 2),
+ GATE_INFRA2(CLK_IFR_PMIC_CONN, CLK_TOP_CLK26M, 3),
+ GATE_INFRA2(CLK_IFR_ICUSB, CLK_TOP_AXI_SEL, 8),
+ GATE_INFRA2(CLK_IFR_GCE, CLK_TOP_AXI_SEL, 9),
+ GATE_INFRA2(CLK_IFR_THERM, CLK_TOP_AXI_SEL, 10),
+ GATE_INFRA2(CLK_IFR_PWM_HCLK, CLK_TOP_AXI_SEL, 15),
+ GATE_INFRA2(CLK_IFR_PWM1, CLK_TOP_PWM_SEL, 16),
+ GATE_INFRA2(CLK_IFR_PWM2, CLK_TOP_PWM_SEL, 17),
+ GATE_INFRA2(CLK_IFR_PWM3, CLK_TOP_PWM_SEL, 18),
+ GATE_INFRA2(CLK_IFR_PWM4, CLK_TOP_PWM_SEL, 19),
+ GATE_INFRA2(CLK_IFR_PWM5, CLK_TOP_PWM_SEL, 20),
+ GATE_INFRA2(CLK_IFR_PWM, CLK_TOP_PWM_SEL, 21),
+ GATE_INFRA2(CLK_IFR_UART0, CLK_TOP_UART_SEL, 22),
+ GATE_INFRA2(CLK_IFR_UART1, CLK_TOP_UART_SEL, 23),
+ GATE_INFRA2(CLK_IFR_UART2, CLK_TOP_UART_SEL, 24),
+ GATE_INFRA2(CLK_IFR_DSP_UART, CLK_TOP_UART_SEL, 26),
+ GATE_INFRA2(CLK_IFR_GCE_26M, CLK_TOP_CLK26M, 27),
+ GATE_INFRA2(CLK_IFR_CQ_DMA_FPC, CLK_TOP_AXI_SEL, 28),
+ GATE_INFRA2(CLK_IFR_BTIF, CLK_TOP_AXI_SEL, 31),
+ /* IFR3 */
+ GATE_INFRA3(CLK_IFR_SPI0, CLK_TOP_SPI_SEL, 1),
+ GATE_INFRA3(CLK_IFR_MSDC0_HCLK, CLK_TOP_MSDC50_0_HC_SEL, 2),
+ GATE_INFRA3(CLK_IFR_MSDC2_HCLK, CLK_TOP_MSDC2_2_HC_SEL, 3),
+ GATE_INFRA3(CLK_IFR_MSDC1_HCLK, CLK_TOP_AXI_SEL, 4),
+ GATE_INFRA3(CLK_IFR_DVFSRC, CLK_TOP_CLK26M, 7),
+ GATE_INFRA3(CLK_IFR_GCPU, CLK_TOP_AXI_SEL, 8),
+ GATE_INFRA3(CLK_IFR_TRNG, CLK_TOP_AXI_SEL, 9),
+ GATE_INFRA3(CLK_IFR_AUXADC, CLK_TOP_CLK26M, 10),
+ GATE_INFRA3(CLK_IFR_AUXADC_MD, CLK_TOP_CLK26M, 14),
+ GATE_INFRA3(CLK_IFR_AP_DMA, CLK_TOP_AXI_SEL, 18),
+ GATE_INFRA3(CLK_IFR_DEBUGSYS, CLK_TOP_AXI_SEL, 24),
+ GATE_INFRA3(CLK_IFR_AUDIO, CLK_TOP_AXI_SEL, 25),
+ /* IFR4 */
+ GATE_INFRA4(CLK_IFR_PWM_FBCLK6, CLK_TOP_PWM_SEL, 0),
+ GATE_INFRA4(CLK_IFR_DISP_PWM, CLK_TOP_DISP_PWM_SEL, 2),
+ GATE_INFRA4(CLK_IFR_AUD_26M_BK, CLK_TOP_CLK26M, 4),
+ GATE_INFRA4(CLK_IFR_CQ_DMA, CLK_TOP_AXI_SEL, 27),
+ /* IFR5 */
+ GATE_INFRA5(CLK_IFR_MSDC0_SF, CLK_TOP_MSDC50_0_SEL, 0),
+ GATE_INFRA5(CLK_IFR_MSDC1_SF, CLK_TOP_MSDC50_0_SEL, 1),
+ GATE_INFRA5(CLK_IFR_MSDC2_SF, CLK_TOP_MSDC50_0_SEL, 2),
+ GATE_INFRA5(CLK_IFR_AP_MSDC0, CLK_TOP_MSDC50_0_SEL, 7),
+ GATE_INFRA5(CLK_IFR_MD_MSDC0, CLK_TOP_MSDC50_0_SEL, 8),
+ GATE_INFRA5(CLK_IFR_MSDC0_SRC, CLK_TOP_MSDC50_0_SEL, 9),
+ GATE_INFRA5(CLK_IFR_MSDC1_SRC, CLK_TOP_MSDC30_1_SEL, 10),
+ GATE_INFRA5(CLK_IFR_MSDC2_SRC, CLK_TOP_MSDC50_2_SEL, 11),
+ GATE_INFRA5(CLK_IFR_PWRAP_TMR, CLK_TOP_CLK26M, 12),
+ GATE_INFRA5(CLK_IFR_PWRAP_SPI, CLK_TOP_CLK26M, 13),
+ GATE_INFRA5(CLK_IFR_PWRAP_SYS, CLK_TOP_CLK26M, 14),
+ GATE_INFRA5(CLK_IFR_IRRX_26M, CLK_TOP_CLK26M, 22),
+ GATE_INFRA5(CLK_IFR_IRRX_32K, CLK_TOP_CLK32K, 23),
+ GATE_INFRA5(CLK_IFR_I2C0_AXI, CLK_TOP_I2C_SEL, 24),
+ GATE_INFRA5(CLK_IFR_I2C1_AXI, CLK_TOP_I2C_SEL, 25),
+ GATE_INFRA5(CLK_IFR_I2C2_AXI, CLK_TOP_I2C_SEL, 26),
+ GATE_INFRA5(CLK_IFR_I2C3_AXI, CLK_TOP_I2C_SEL, 27),
+ GATE_INFRA5(CLK_IFR_NIC_AXI, CLK_TOP_AXI_SEL, 28),
+ GATE_INFRA5(CLK_IFR_NIC_SLV_AXI, CLK_TOP_AXI_SEL, 29),
+ GATE_INFRA5(CLK_IFR_APU_AXI, CLK_TOP_AXI_SEL, 30),
+ /* IFR6 */
+ GATE_INFRA6(CLK_IFR_NFIECC, CLK_TOP_NFIECC_SEL, 0),
+ GATE_INFRA6(CLK_IFR_NFI1X_BK, CLK_TOP_NFI2X_SEL, 1),
+ GATE_INFRA6(CLK_IFR_NFIECC_BK, CLK_TOP_NFI2X_SEL, 2),
+ GATE_INFRA6(CLK_IFR_NFI_BK, CLK_TOP_AXI_SEL, 3),
+ GATE_INFRA6(CLK_IFR_MSDC2_AP_BK, CLK_TOP_AXI_SEL, 4),
+ GATE_INFRA6(CLK_IFR_MSDC2_MD_BK, CLK_TOP_AXI_SEL, 5),
+ GATE_INFRA6(CLK_IFR_MSDC2_BK, CLK_TOP_AXI_SEL, 6),
+ GATE_INFRA6(CLK_IFR_SUSB_133_BK, CLK_TOP_AXI_SEL, 7),
+ GATE_INFRA6(CLK_IFR_SUSB_66_BK, CLK_TOP_AXI_SEL, 8),
+ GATE_INFRA6(CLK_IFR_SSUSB_SYS, CLK_TOP_SSUSB_SYS_SEL, 9),
+ GATE_INFRA6(CLK_IFR_SSUSB_REF, CLK_TOP_SSUSB_SYS_SEL, 10),
+ GATE_INFRA6(CLK_IFR_SSUSB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11),
+};
+
+static const struct mtk_gate_regs top0_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x0,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x104,
+ .sta_ofs = 0x104,
+};
+
+#define GATE_TOP0(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP1_I(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate top_clks[] = {
+ /* TOP0 */
+ GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10),
+ GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11),
+ GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16),
+ GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17),
+ /* TOP1 */
+ GATE_TOP1_I(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4, 8),
+ GATE_TOP1_I(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4, 9),
+ GATE_TOP1_I(CLK_TOP_LVDSTX_CLKDIG_EN, CLK_TOP_LVDSTX_CLKDIG_CTS, 20),
+ GATE_TOP1_I(CLK_TOP_VPLL_DPIX_EN, CLK_TOP_VPLL_DPIX, 21),
+ GATE_TOP1_I(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22),
+ GATE_TOP1_I(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23),
+};
+
+static int mt8175_apmixedsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8175_clk_tree);
+}
+
+static int mt8175_topckgen_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8175_clk_tree);
+}
+
+static int mt8175_topckgen_cg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt8175_clk_tree, top_clks);
+}
+
+static int mt8175_infracfg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt8175_clk_tree, infra_clks);
+}
+
+static const struct udevice_id mt8175_apmixed_compat[] = {
+ { .compatible = "mediatek,mt8175-apmixedsys", },
+ { }
+};
+
+static const struct udevice_id mt8175_topckgen_compat[] = {
+ { .compatible = "mediatek,mt8175-topckgen", },
+ { }
+};
+
+static const struct udevice_id mt8175_topckgen_cg_compat[] = {
+ { .compatible = "mediatek,mt8175-topckgen-cg", },
+ { }
+};
+
+static const struct udevice_id mt8175_infracfg_compat[] = {
+ { .compatible = "mediatek,mt8175-infracfg", },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+ .name = "mt8175-apmixedsys",
+ .id = UCLASS_CLK,
+ .of_match = mt8175_apmixed_compat,
+ .probe = mt8175_apmixedsys_probe,
+ .priv_auto = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_apmixedsys_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+ .name = "mt8175-topckgen",
+ .id = UCLASS_CLK,
+ .of_match = mt8175_topckgen_compat,
+ .probe = mt8175_topckgen_probe,
+ .priv_auto = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_topckgen_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
+ .name = "mt8175-topckgen-cg",
+ .id = UCLASS_CLK,
+ .of_match = mt8175_topckgen_cg_compat,
+ .probe = mt8175_topckgen_cg_probe,
+ .priv_auto = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_infracfg) = {
+ .name = "mt8175-infracfg",
+ .id = UCLASS_CLK,
+ .of_match = mt8175_infracfg_compat,
+ .probe = mt8175_infracfg_probe,
+ .priv_auto = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/include/dt-bindings/clock/mt8175-clk.h b/include/dt-bindings/clock/mt8175-clk.h
new file mode 100644
index 000000000000..4f5992db3ec9
--- /dev/null
+++ b/include/dt-bindings/clock/mt8175-clk.h
@@ -0,0 +1,392 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8175_H
+#define _DT_BINDINGS_CLK_MT8175_H
+
+/* TOPCKGEN */
+
+#define CLK_TOP_CLK_NULL 0
+#define CLK_TOP_DSI0_LNTC_DSICK 1
+#define CLK_TOP_VPLL_DPIX 2
+#define CLK_TOP_LVDSTX_CLKDIG_CTS 3
+#define CLK_TOP_CLK26M 4
+#define CLK_TOP_CLK32K 5
+#define CLK_TOP_I2S0_BCK 6
+#define CLK_TOP_SYS_26M_D2 7
+#define CLK_TOP_SYSPLL_D2 8
+#define CLK_TOP_SYSPLL1_D2 9
+#define CLK_TOP_SYSPLL1_D4 10
+#define CLK_TOP_SYSPLL1_D8 11
+#define CLK_TOP_SYSPLL1_D16 12
+#define CLK_TOP_SYSPLL_D3 13
+#define CLK_TOP_SYSPLL2_D2 14
+#define CLK_TOP_SYSPLL2_D4 15
+#define CLK_TOP_SYSPLL2_D8 16
+#define CLK_TOP_SYSPLL_D5 17
+#define CLK_TOP_SYSPLL3_D2 18
+#define CLK_TOP_SYSPLL3_D4 19
+#define CLK_TOP_SYSPLL_D7 20
+#define CLK_TOP_SYSPLL4_D2 21
+#define CLK_TOP_SYSPLL4_D4 22
+#define CLK_TOP_UNIVPLL 23
+#define CLK_TOP_UNIVPLL_D2 24
+#define CLK_TOP_UNIVPLL1_D2 25
+#define CLK_TOP_UNIVPLL1_D4 26
+#define CLK_TOP_UNIVPLL_D3 27
+#define CLK_TOP_UNIVPLL2_D2 28
+#define CLK_TOP_UNIVPLL2_D4 29
+#define CLK_TOP_UNIVPLL2_D8 30
+#define CLK_TOP_UNIVPLL2_D32 31
+#define CLK_TOP_UNIVPLL_D5 32
+#define CLK_TOP_UNIVPLL3_D2 33
+#define CLK_TOP_UNIVPLL3_D4 34
+#define CLK_TOP_MMPLL 35
+#define CLK_TOP_MMPLL_D2 36
+#define CLK_TOP_MFGPLL 37
+#define CLK_TOP_LVDSPLL_D2 38
+#define CLK_TOP_LVDSPLL_D4 39
+#define CLK_TOP_LVDSPLL_D8 40
+#define CLK_TOP_LVDSPLL_D16 41
+#define CLK_TOP_USB20_192M 42
+#define CLK_TOP_USB20_192M_D4 43
+#define CLK_TOP_USB20_192M_D8 44
+#define CLK_TOP_USB20_192M_D16 45
+#define CLK_TOP_USB20_192M_D32 46
+#define CLK_TOP_APLL1 47
+#define CLK_TOP_APLL1_D2 48
+#define CLK_TOP_APLL1_D4 49
+#define CLK_TOP_APLL1_D8 50
+#define CLK_TOP_APLL2 51
+#define CLK_TOP_APLL2_D2 52
+#define CLK_TOP_APLL2_D4 53
+#define CLK_TOP_APLL2_D8 54
+#define CLK_TOP_MSDCPLL 55
+#define CLK_TOP_MSDCPLL_D2 56
+#define CLK_TOP_DSPPLL 57
+#define CLK_TOP_DSPPLL_D2 58
+#define CLK_TOP_DSPPLL_D4 59
+#define CLK_TOP_DSPPLL_D8 60
+#define CLK_TOP_APUPLL 61
+#define CLK_TOP_CLK26M_D52 62
+#define CLK_TOP_AXI_SEL 63
+#define CLK_TOP_MEM_SEL 64
+#define CLK_TOP_MM_SEL 65
+#define CLK_TOP_SCP_SEL 66
+#define CLK_TOP_MFG_SEL 67
+#define CLK_TOP_ATB_SEL 68
+#define CLK_TOP_CAMTG_SEL 69
+#define CLK_TOP_CAMTG1_SEL 70
+#define CLK_TOP_UART_SEL 71
+#define CLK_TOP_SPI_SEL 72
+#define CLK_TOP_MSDC50_0_HC_SEL 73
+#define CLK_TOP_MSDC2_2_HC_SEL 74
+#define CLK_TOP_MSDC50_0_SEL 75
+#define CLK_TOP_MSDC50_2_SEL 76
+#define CLK_TOP_MSDC30_1_SEL 77
+#define CLK_TOP_AUDIO_SEL 78
+#define CLK_TOP_AUD_INTBUS_SEL 79
+#define CLK_TOP_AUD_1_SEL 80
+#define CLK_TOP_AUD_2_SEL 81
+#define CLK_TOP_AUD_ENGEN1_SEL 82
+#define CLK_TOP_AUD_ENGEN2_SEL 83
+#define CLK_TOP_AUD_SPDIF_SEL 84
+#define CLK_TOP_DISP_PWM_SEL 85
+#define CLK_TOP_DXCC_SEL 86
+#define CLK_TOP_SSUSB_SYS_SEL 87
+#define CLK_TOP_SSUSB_XHCI_SEL 88
+#define CLK_TOP_SPM_SEL 89
+#define CLK_TOP_I2C_SEL 90
+#define CLK_TOP_PWM_SEL 91
+#define CLK_TOP_SENIF_SEL 92
+#define CLK_TOP_AES_FDE_SEL 93
+#define CLK_TOP_CAMTM_SEL 94
+#define CLK_TOP_DPI0_SEL 95
+#define CLK_TOP_DPI1_SEL 96
+#define CLK_TOP_DSP_SEL 97
+#define CLK_TOP_NFI2X_SEL 98
+#define CLK_TOP_NFIECC_SEL 99
+#define CLK_TOP_ECC_SEL 100
+#define CLK_TOP_ETH_SEL 101
+#define CLK_TOP_GCPU_SEL 102
+#define CLK_TOP_GCPU_CPM_SEL 103
+#define CLK_TOP_APU_SEL 104
+#define CLK_TOP_APU_IF_SEL 105
+#define CLK_TOP_MBIST_DIAG_SEL 106
+#define CLK_TOP_APLL_I2S0_SEL 107
+#define CLK_TOP_APLL_I2S1_SEL 108
+#define CLK_TOP_APLL_I2S2_SEL 109
+#define CLK_TOP_APLL_I2S3_SEL 110
+#define CLK_TOP_APLL_TDMOUT_SEL 111
+#define CLK_TOP_APLL_TDMIN_SEL 112
+#define CLK_TOP_APLL_SPDIF_SEL 113
+#define CLK_TOP_APLL12_CK_DIV0 114
+#define CLK_TOP_APLL12_CK_DIV1 115
+#define CLK_TOP_APLL12_CK_DIV2 116
+#define CLK_TOP_APLL12_CK_DIV3 117
+#define CLK_TOP_APLL12_CK_DIV4 118
+#define CLK_TOP_APLL12_CK_DIV4B 119
+#define CLK_TOP_APLL12_CK_DIV5 120
+#define CLK_TOP_APLL12_CK_DIV5B 121
+#define CLK_TOP_APLL12_CK_DIV6 122
+#define CLK_TOP_NR_CLK 123
+
+/* TOPCKGEN Gates */
+#define CLK_TOP_CONN_32K 0
+#define CLK_TOP_CONN_26M 1
+#define CLK_TOP_DSP_32K 2
+#define CLK_TOP_DSP_26M 3
+#define CLK_TOP_USB20_48M_EN 4
+#define CLK_TOP_UNIVPLL_48M_EN 5
+#define CLK_TOP_LVDSTX_CLKDIG_EN 6
+#define CLK_TOP_VPLL_DPIX_EN 7
+#define CLK_TOP_SSUSB_TOP_CK_EN 8
+#define CLK_TOP_SSUSB_PHY_CK_EN 9
+#define CLK_TOP_AUD_I2S0_M 10
+#define CLK_TOP_AUD_I2S1_M 11
+#define CLK_TOP_AUD_I2S2_M 12
+#define CLK_TOP_AUD_I2S3_M 13
+#define CLK_TOP_AUD_TDMOUT_M 14
+#define CLK_TOP_AUD_TDMOUT_B 15
+#define CLK_TOP_AUD_TDMIN_M 16
+#define CLK_TOP_AUD_TDMIN_B 17
+#define CLK_TOP_AUD_SPDIF_M 18
+
+/* INFRACFG */
+
+#define CLK_IFR_PMIC_TMR 0
+#define CLK_IFR_PMIC_AP 1
+#define CLK_IFR_PMIC_MD 2
+#define CLK_IFR_PMIC_CONN 3
+#define CLK_IFR_ICUSB 4
+#define CLK_IFR_GCE 5
+#define CLK_IFR_THERM 6
+#define CLK_IFR_PWM_HCLK 7
+#define CLK_IFR_PWM1 8
+#define CLK_IFR_PWM2 9
+#define CLK_IFR_PWM3 10
+#define CLK_IFR_PWM4 11
+#define CLK_IFR_PWM5 12
+#define CLK_IFR_PWM 13
+#define CLK_IFR_UART0 14
+#define CLK_IFR_UART1 15
+#define CLK_IFR_UART2 16
+#define CLK_IFR_DSP_UART 17
+#define CLK_IFR_GCE_26M 18
+#define CLK_IFR_CQ_DMA_FPC 19
+#define CLK_IFR_BTIF 20
+#define CLK_IFR_SPI0 21
+#define CLK_IFR_MSDC0_HCLK 22
+#define CLK_IFR_MSDC2_HCLK 23
+#define CLK_IFR_MSDC1_HCLK 24
+#define CLK_IFR_DVFSRC 25
+#define CLK_IFR_GCPU 26
+#define CLK_IFR_TRNG 27
+#define CLK_IFR_AUXADC 28
+#define CLK_IFR_AUXADC_MD 29
+#define CLK_IFR_AP_DMA 30
+#define CLK_IFR_DEBUGSYS 31
+#define CLK_IFR_AUDIO 32
+#define CLK_IFR_PWM_FBCLK6 33
+#define CLK_IFR_DISP_PWM 34
+#define CLK_IFR_AUD_26M_BK 35
+#define CLK_IFR_CQ_DMA 36
+#define CLK_IFR_MSDC0_SF 37
+#define CLK_IFR_MSDC1_SF 38
+#define CLK_IFR_MSDC2_SF 39
+#define CLK_IFR_AP_MSDC0 40
+#define CLK_IFR_MD_MSDC0 41
+#define CLK_IFR_MSDC0_SRC 42
+#define CLK_IFR_MSDC1_SRC 43
+#define CLK_IFR_MSDC2_SRC 44
+#define CLK_IFR_PWRAP_TMR 45
+#define CLK_IFR_PWRAP_SPI 46
+#define CLK_IFR_PWRAP_SYS 47
+#define CLK_IFR_IRRX_26M 48
+#define CLK_IFR_IRRX_32K 49
+#define CLK_IFR_I2C0_AXI 50
+#define CLK_IFR_I2C1_AXI 51
+#define CLK_IFR_I2C2_AXI 52
+#define CLK_IFR_I2C3_AXI 53
+#define CLK_IFR_NIC_AXI 54
+#define CLK_IFR_NIC_SLV_AXI 55
+#define CLK_IFR_APU_AXI 56
+#define CLK_IFR_NFIECC 57
+#define CLK_IFR_NFI1X_BK 58
+#define CLK_IFR_NFIECC_BK 59
+#define CLK_IFR_NFI_BK 60
+#define CLK_IFR_MSDC2_AP_BK 61
+#define CLK_IFR_MSDC2_MD_BK 62
+#define CLK_IFR_MSDC2_BK 63
+#define CLK_IFR_SUSB_133_BK 64
+#define CLK_IFR_SUSB_66_BK 65
+#define CLK_IFR_SSUSB_SYS 66
+#define CLK_IFR_SSUSB_REF 67
+#define CLK_IFR_SSUSB_XHCI 68
+#define CLK_IFR_NR_CLK 69
+
+/* PERICFG */
+
+#define CLK_PERIAXI 0
+#define CLK_PERI_NR_CLK 1
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL 0
+#define CLK_APMIXED_MAINPLL 1
+#define CLK_APMIXED_UNIVPLL 2
+#define CLK_APMIXED_MFGPLL 3
+#define CLK_APMIXED_MSDCPLL 4
+#define CLK_APMIXED_MMPLL 5
+#define CLK_APMIXED_APLL1 6
+#define CLK_APMIXED_APLL2 7
+#define CLK_APMIXED_LVDSPLL 8
+#define CLK_APMIXED_DSPPLL 9
+#define CLK_APMIXED_APUPLL 10
+#define CLK_APMIXED_NR_CLK 11
+
+/* GCE */
+
+#define CLK_GCE_FAXI 0
+#define CLK_GCE_NR_CLK 1
+
+/* AUDIOTOP */
+
+#define CLK_AUD_AFE 0
+#define CLK_AUD_I2S 1
+#define CLK_AUD_22M 2
+#define CLK_AUD_24M 3
+#define CLK_AUD_INTDIR 4
+#define CLK_AUD_APLL2_TUNER 5
+#define CLK_AUD_APLL_TUNER 6
+#define CLK_AUD_SPDF 7
+#define CLK_AUD_HDMI 8
+#define CLK_AUD_HDMI_IN 9
+#define CLK_AUD_ADC 10
+#define CLK_AUD_DAC 11
+#define CLK_AUD_DAC_PREDIS 12
+#define CLK_AUD_TML 13
+#define CLK_AUD_I2S1_BK 14
+#define CLK_AUD_I2S2_BK 15
+#define CLK_AUD_I2S3_BK 16
+#define CLK_AUD_I2S4_BK 17
+#define CLK_AUD_NR_CLK 18
+
+/* MIPI_CSI0A */
+
+#define CLK_MIPI0A_CSR_CSI_EN_0A 0
+#define CLK_MIPI_RX_ANA_CSI0A_NR_CLK 1
+
+/* MIPI_CSI0B */
+
+#define CLK_MIPI0B_CSR_CSI_EN_0B 0
+#define CLK_MIPI_RX_ANA_CSI0B_NR_CLK 1
+
+/* MIPI_CSI1A */
+
+#define CLK_MIPI1A_CSR_CSI_EN_1A 0
+#define CLK_MIPI_RX_ANA_CSI1A_NR_CLK 1
+
+/* MIPI_CSI1B */
+
+#define CLK_MIPI1B_CSR_CSI_EN_1B 0
+#define CLK_MIPI_RX_ANA_CSI1B_NR_CLK 1
+
+/* MIPI_CSI2A */
+
+#define CLK_MIPI2A_CSR_CSI_EN_2A 0
+#define CLK_MIPI_RX_ANA_CSI2A_NR_CLK 1
+
+/* MIPI_CSI2B */
+
+#define CLK_MIPI2B_CSR_CSI_EN_2B 0
+#define CLK_MIPI_RX_ANA_CSI2B_NR_CLK 1
+
+/* MCUCFG */
+
+#define CLK_MCU_BUS_SEL 0
+#define CLK_MCU_NR_CLK 1
+
+/* MFGCFG */
+
+#define CLK_MFG_BG3D 0
+#define CLK_MFG_MBIST_DIAG 1
+#define CLK_MFG_NR_CLK 2
+
+/* MMSYS */
+
+#define CLK_MM_MM_MDP_RDMA0 0
+#define CLK_MM_MM_MDP_CCORR0 1
+#define CLK_MM_MM_MDP_RSZ0 2
+#define CLK_MM_MM_MDP_RSZ1 3
+#define CLK_MM_MM_MDP_TDSHP0 4
+#define CLK_MM_MM_MDP_WROT0 5
+#define CLK_MM_MM_MDP_WDMA0 6
+#define CLK_MM_MM_DISP_OVL0 7
+#define CLK_MM_MM_DISP_OVL0_21 8
+#define CLK_MM_MM_DISP_RSZ0 9
+#define CLK_MM_MM_DISP_RDMA0 10
+#define CLK_MM_MM_DISP_WDMA0 11
+#define CLK_MM_MM_DISP_COLOR0 12
+#define CLK_MM_MM_DISP_CCORR0 13
+#define CLK_MM_MM_DISP_AAL0 14
+#define CLK_MM_MM_DISP_GAMMA0 15
+#define CLK_MM_MM_DISP_DITHER0 16
+#define CLK_MM_MM_DSI0 17
+#define CLK_MM_MM_DISP_RDMA1 18
+#define CLK_MM_MM_MDP_RDMA1 19
+#define CLK_MM_DPI0_DPI0 20
+#define CLK_MM_MM_FAKE 21
+#define CLK_MM_MM_SMI_COMMON 22
+#define CLK_MM_MM_SMI_LARB0 23
+#define CLK_MM_MM_SMI_COMM0 24
+#define CLK_MM_MM_SMI_COMM1 25
+#define CLK_MM_MM_CAM_MDP 26
+#define CLK_MM_MM_SMI_IMG 27
+#define CLK_MM_MM_SMI_CAM 28
+#define CLK_MM_IMG_IMG_DL_RELAY 29
+#define CLK_MM_IMG_IMG_DL_ASYNC_TOP 30
+#define CLK_MM_DSI0_DIG_DSI 31
+#define CLK_MM_26M_HRTWT 32
+#define CLK_MM_MM_DPI0 33
+#define CLK_MM_LVDSTX_PXL 34
+#define CLK_MM_LVDSTX_CTS 35
+#define CLK_MM_NR_CLK 36
+
+/* IMGSYS */
+
+#define CLK_CAM_LARB2 0
+#define CLK_CAM 1
+#define CLK_CAMTG 2
+#define CLK_CAM_SENIF 3
+#define CLK_CAMSV0 4
+#define CLK_CAMSV1 5
+#define CLK_CAM_FDVT 6
+#define CLK_CAM_WPE 7
+#define CLK_CAM_NR_CLK 8
+
+/* VDECSYS */
+
+#define CLK_VDEC_VDEC 0
+#define CLK_VDEC_LARB1 1
+#define CLK_VDEC_NR_CLK 2
+
+/* VENCSYS */
+
+#define CLK_VENC 0
+#define CLK_VENC_JPGENC 1
+#define CLK_VENC_NR_CLK 2
+
+/* APUSYS */
+
+#define CLK_APU_IPU_CK 0
+#define CLK_APU_AXI 1
+#define CLK_APU_JTAG 2
+#define CLK_APU_IF_CK 3
+#define CLK_APU_EDMA 4
+#define CLK_APU_AHB 5
+#define CLK_APU_NR_CLK 6
+
+#endif /* _DT_BINDINGS_CLK_MT8175_H */
--
2.31.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-04-19 15:48 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2021-03-30 14:30 [PATCH 1/3] clk: mediatek: Add MT8175 clock driver Fabien Parent
2021-03-30 14:30 ` [PATCH 2/3] ARM: mediatek: Add MT8175 support Fabien Parent
2021-04-01 1:42 ` Chunfeng Yun
2021-03-30 14:30 ` [PATCH 3/3] board: Add MT8175 pumpkin board support Fabien Parent
2021-04-19 15:48 ` [PATCH 1/3] clk: mediatek: Add MT8175 clock driver Fabien Parent
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2021-03-29 19:27 Fabien Parent
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