From: Sean Anderson <seanga2@gmail.com>
To: u-boot@lists.denx.de
Subject: [PATCH v3 04/11] clk: k210: Remove k210_register_pll
Date: Thu, 8 Apr 2021 22:13:06 -0400 [thread overview]
Message-ID: <20210409021313.433558-5-seanga2@gmail.com> (raw)
In-Reply-To: <20210409021313.433558-1-seanga2@gmail.com>
This simplifies the PLL creation process, since we don't have to pass all
the parameters individually.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
---
(no changes since v2)
Changes in v2:
- New
drivers/clk/kendryte/clk.c | 10 +++-------
drivers/clk/kendryte/pll.c | 21 ---------------------
include/kendryte/pll.h | 4 ----
3 files changed, 3 insertions(+), 32 deletions(-)
diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
index 3b674a998e..ab86533bb4 100644
--- a/drivers/clk/kendryte/clk.c
+++ b/drivers/clk/kendryte/clk.c
@@ -528,14 +528,10 @@ static int k210_clk_probe(struct udevice *dev)
return -ENOMEM;
}
- {
- const struct k210_pll_params *params = &k210_plls[1];
-
+ pll = k210_create_pll(&k210_plls[1], base);
+ if (pll)
clk_dm(K210_CLK_PLL1,
- k210_register_pll("pll1", in0, base + params->off,
- base + params->lock_off, params->shift,
- params->width));
- }
+ k210_register_pll_struct("pll1", in0, pll));
/* PLL2 is muxed, so set up a composite clock */
mux = k210_create_mux(&k210_muxes[MUXIFY(K210_CLK_PLL2)], base);
diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c
index d46fd0ebbf..184f37aaf2 100644
--- a/drivers/clk/kendryte/pll.c
+++ b/drivers/clk/kendryte/pll.c
@@ -578,27 +578,6 @@ struct clk *k210_register_pll_struct(const char *name, const char *parent_name,
return clk;
}
-struct clk *k210_register_pll(const char *name, const char *parent_name,
- void __iomem *reg, void __iomem *lock, u8 shift,
- u8 width)
-{
- struct clk *clk;
- struct k210_pll *pll;
-
- pll = kzalloc(sizeof(*pll), GFP_KERNEL);
- if (!pll)
- return ERR_PTR(-ENOMEM);
- pll->reg = reg;
- pll->lock = lock;
- pll->shift = shift;
- pll->width = width;
-
- clk = k210_register_pll_struct(name, parent_name, pll);
- if (IS_ERR(clk))
- kfree(pll);
- return clk;
-}
-
U_BOOT_DRIVER(k210_pll) = {
.name = CLK_K210_PLL,
.id = UCLASS_CLK,
diff --git a/include/kendryte/pll.h b/include/kendryte/pll.h
index 55a40b9c97..95b8494f40 100644
--- a/include/kendryte/pll.h
+++ b/include/kendryte/pll.h
@@ -55,8 +55,4 @@ extern const struct clk_ops k210_pll_ops;
struct clk *k210_register_pll_struct(const char *name, const char *parent_name,
struct k210_pll *pll);
-struct clk *k210_register_pll(const char *name, const char *parent_name,
- void __iomem *reg, void __iomem *lock, u8 shift,
- u8 width);
-
#endif /* K210_PLL_H */
--
2.31.0
next prev parent reply other threads:[~2021-04-09 2:13 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-09 2:13 [PATCH v3 00/11] riscv: k210: Enable use of AI ram bank Sean Anderson
2021-04-09 2:13 ` [PATCH v3 01/11] clk: Warn on failure to assign rate Sean Anderson
2021-04-09 2:13 ` [PATCH v3 02/11] clk: k210: Fix PLLs not being enabled Sean Anderson
2021-04-09 2:45 ` Damien Le Moal
2021-04-09 2:13 ` [PATCH v3 03/11] clk: k210: Fix PLL enable always getting taken Sean Anderson
2021-04-09 2:13 ` Sean Anderson [this message]
2021-04-09 2:13 ` [PATCH v3 05/11] clk: k210: Move the clint clock to under aclk Sean Anderson
2021-04-09 2:54 ` Damien Le Moal
2021-04-09 2:57 ` Sean Anderson
2021-04-09 3:00 ` Damien Le Moal
2021-04-09 2:58 ` Damien Le Moal
2021-04-09 3:09 ` Sean Anderson
2021-04-09 2:13 ` [PATCH v3 06/11] clk: Add support for the k210 clock driver pre-relocation Sean Anderson
2021-04-09 2:13 ` [PATCH v3 07/11] riscv: Enable some devices pre-relocation Sean Anderson
2021-04-09 2:13 ` [PATCH v3 08/11] riscv: Enable AI ram on K210 Sean Anderson
2021-04-09 2:13 ` [PATCH v3 09/11] riscv: k210: Rename airam to aisram Sean Anderson
2021-04-09 2:13 ` [PATCH v3 10/11] riscv: k210: Use AI as the parent clock of aisram, not PLL1 Sean Anderson
2021-04-09 2:13 ` [PATCH v3 11/11] riscv: Don't reserve AI ram in k210 dts Sean Anderson
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