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From: Damien Le Moal <Damien.LeMoal@wdc.com>
To: u-boot@lists.denx.de
Subject: [PATCH v3 05/11] clk: k210: Move the clint clock to under aclk
Date: Fri, 9 Apr 2021 02:54:01 +0000	[thread overview]
Message-ID: <BL0PR04MB651421D06FBFBF74E55FB672E7739@BL0PR04MB6514.namprd04.prod.outlook.com> (raw)
In-Reply-To: 20210409021313.433558-6-seanga2@gmail.com

On 2021/04/09 11:13, Sean Anderson wrote:
> No other (real) clocks have the cpu clock as their parent; instead they are
> children of aclk. Move the clint clock under aclk to match them.
> 
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> ---
> 
> (no changes since v2)
> 
> Changes in v2:
> - New
> 
>  drivers/clk/kendryte/clk.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
> index ab86533bb4..5091f07eb0 100644
> --- a/drivers/clk/kendryte/clk.c
> +++ b/drivers/clk/kendryte/clk.c
> @@ -643,7 +643,7 @@ static int k210_clk_probe(struct udevice *dev)
>  
>  	/* The MTIME register in CLINT runs at one 50th the CPU clock speed */
>  	clk_dm(K210_CLK_CLINT,
> -	       clk_register_fixed_factor(NULL, "clint", "cpu", 0, 1, 50));
> +	       clk_register_fixed_factor(NULL, "clint", "aclk", 0, 1, 50));
>  
>  	return 0;
>  }
> 

Looks good, but representing this clock is in fact useless, at least in Linux,
since the clint driver does not use it directly and derives its rate from
riscv_timebase which is set from the timebase-frequency DT property.

Not sure how u-boot handles that though. Since your code allows changing the
PLLs frequency, the timebase-frequency property may end up being buggy if it is
not changed too.

-- 
Damien Le Moal
Western Digital Research

  reply	other threads:[~2021-04-09  2:54 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-09  2:13 [PATCH v3 00/11] riscv: k210: Enable use of AI ram bank Sean Anderson
2021-04-09  2:13 ` [PATCH v3 01/11] clk: Warn on failure to assign rate Sean Anderson
2021-04-09  2:13 ` [PATCH v3 02/11] clk: k210: Fix PLLs not being enabled Sean Anderson
2021-04-09  2:45   ` Damien Le Moal
2021-04-09  2:13 ` [PATCH v3 03/11] clk: k210: Fix PLL enable always getting taken Sean Anderson
2021-04-09  2:13 ` [PATCH v3 04/11] clk: k210: Remove k210_register_pll Sean Anderson
2021-04-09  2:13 ` [PATCH v3 05/11] clk: k210: Move the clint clock to under aclk Sean Anderson
2021-04-09  2:54   ` Damien Le Moal [this message]
2021-04-09  2:57     ` Sean Anderson
2021-04-09  3:00       ` Damien Le Moal
2021-04-09  2:58     ` Damien Le Moal
2021-04-09  3:09       ` Sean Anderson
2021-04-09  2:13 ` [PATCH v3 06/11] clk: Add support for the k210 clock driver pre-relocation Sean Anderson
2021-04-09  2:13 ` [PATCH v3 07/11] riscv: Enable some devices pre-relocation Sean Anderson
2021-04-09  2:13 ` [PATCH v3 08/11] riscv: Enable AI ram on K210 Sean Anderson
2021-04-09  2:13 ` [PATCH v3 09/11] riscv: k210: Rename airam to aisram Sean Anderson
2021-04-09  2:13 ` [PATCH v3 10/11] riscv: k210: Use AI as the parent clock of aisram, not PLL1 Sean Anderson
2021-04-09  2:13 ` [PATCH v3 11/11] riscv: Don't reserve AI ram in k210 dts Sean Anderson

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