Re: [PATCH v4 2/2] pwm: visconti: Add Toshiba Visconti SoC PWM support

From: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
To: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
Cc: Rob Herring <robh+dt@kernel.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Lee Jones <lee.jones@linaro.org>,
	devicetree@vger.kernel.org, linux-pwm@vger.kernel.org,
	punit1.agrawal@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 2/2] pwm: visconti: Add Toshiba Visconti SoC PWM support
Date: Fri, 16 Apr 2021 21:15:23 +0900	[thread overview]
Message-ID: <20210416121523.c34trzsrlcjuzirl@toshiba.co.jp> (raw)
In-Reply-To: <20210416094426.x4gyw3drp2fcwczs@pengutronix.de>

Hi Uwe,

Thanks for your comment.

On Fri, Apr 16, 2021 at 11:44:26AM +0200, Uwe Kleine-König wrote:
> Hello Nobuhiro,
> 
> On Fri, Apr 16, 2021 at 05:07:21PM +0900, Nobuhiro Iwamatsu wrote:
> > On Mon, Apr 12, 2021 at 09:02:32AM +0200, Uwe Kleine-König wrote:
> > > On Mon, Apr 12, 2021 at 11:55:36AM +0900, Nobuhiro Iwamatsu wrote:
> > > > On Sat, Apr 10, 2021 at 03:53:21PM +0200, Uwe Kleine-König wrote:
> > > > > Can you please put a paragraph analogous to the one in pwm-sifive in the
> > > > > same format. This simplified keeping an overview about the oddities of
> > > > > the various supported chips.
> > > > 
> > > > OK, I will check pwm-sifive's, and add.
> > 
> > I will add the following :
> > 
> >  * Limitations:
> >  * - PIPGM_PWMC is a 2-bit divider (00: 1, 01: 2, 10: 4, 11: 8) for the input
> >  *   clock running at 1 MHz.
> 
> I would strip that to:
> 
>  - Fixed input clock running at 1 MHz
> 

OK, I will update.

> >  * - When the settings of the PWM are modified, the new values are shadowed
> >  *   in hardware until the PIPGM_PCSR register is written and the currently
> >  *   running period is completed. This way the hardware switches atomically
> >  *   from the old setting to the new.
> >  * - Disabling the hardware completes the currently running period and keeps
> >  *   the output at low level at all times.
> 
> This looks fine.
>  
> > > For me the critical (and only) difference between "off" and
> > > "duty cycle = 0" is that when a new configuration is to be applied. In
> > > the "off" state a new period can (and should) start immediately, while
> > > with "duty_cycle = 0" the rising edge should be delayed until the
> > > currently running period is over.[1]
> > > 
> > > So the thing to do here (IMHO) is:
> > > 
> > > Iff with PIPGM_PCSR = 0 configuring a new setting (that is finalized
> > > with writing a non-zero value to PIPGM_PCSR) completes the currently
> > > running period, then always assume the PWM as enabled.
> > 
> > Yes, this device works that way.
> 
> OK, then please use
> 
> 	state->enabled = true
> 
> unconditionally in visconti_pwm_get_state().
> 

Please let me check.
If I unconditionally add 'state->enabled = true' to visconti_pwm_get_state(),
state->enabled is set to true because visconti_pwm_get_state() is called when
the device is created (this is when I write the device number to the export of
/sys/class/pwm/pwmchip0 ).
And since PIPGM_PCSR is 0 in this state, the pulse by PWM is not output.
However, I think this means that the device is working as this driver.
Is this correct?

> Best regards
> Uwe
> 

Best regards,
  Nobuhiro