[PATCH 0/4] drm/i915: Fix older platforms

[PATCH 0/4] drm/i915: Fix older platforms

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Fix a div-by-zero on gen2, and make the L-shaped memory detection
actually work on cl/ctg. Atm the SWIZZLE_UNKNOWN stuff just trips
some GEM_BUG_ONs. This doesn't fix those but since I populate all
my memory channels symmetrically I get to avoid the GEM_BUG_ONs
by correctly detecting that I don't have an L-shaped memory
configuration.

Ville Syrjälä (4):
  drm/i915: Avoid div-by-zero on gen2
  drm/i915: Read C0DRB3/C1DRB3 as 16 bits again
  drm/i915: Give C0DRB3/C1DRB3 a _BW suffix
  drm/i915: Rewrite CL/CTG L-shaped memory detection

 drivers/gpu/drm/i915/gem/i915_gem_mman.c     |  2 +-
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 19 ++++++++++---------
 drivers/gpu/drm/i915/i915_debugfs.c          | 16 ++++++++++++----
 drivers/gpu/drm/i915/i915_reg.h              |  8 ++++++--
 4 files changed, 29 insertions(+), 16 deletions(-)

-- 
2.26.3

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[Intel-gfx] [PATCH 0/4] drm/i915: Fix older platforms

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Fix a div-by-zero on gen2, and make the L-shaped memory detection
actually work on cl/ctg. Atm the SWIZZLE_UNKNOWN stuff just trips
some GEM_BUG_ONs. This doesn't fix those but since I populate all
my memory channels symmetrically I get to avoid the GEM_BUG_ONs
by correctly detecting that I don't have an L-shaped memory
configuration.

Ville Syrjälä (4):
  drm/i915: Avoid div-by-zero on gen2
  drm/i915: Read C0DRB3/C1DRB3 as 16 bits again
  drm/i915: Give C0DRB3/C1DRB3 a _BW suffix
  drm/i915: Rewrite CL/CTG L-shaped memory detection

 drivers/gpu/drm/i915/gem/i915_gem_mman.c     |  2 +-
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 19 ++++++++++---------
 drivers/gpu/drm/i915/i915_debugfs.c          | 16 ++++++++++++----
 drivers/gpu/drm/i915/i915_reg.h              |  8 ++++++--
 4 files changed, 29 insertions(+), 16 deletions(-)

-- 
2.26.3

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[PATCH 1/4] drm/i915: Avoid div-by-zero on gen2

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Gen2 tiles are 2KiB in size so i915_gem_object_get_tile_row_size()
can in fact return <4KiB, which leads to div-by-zero here.
Avoid that.

Not sure i915_gem_object_get_tile_row_size() is entirely
sane anyway since it doesn't account for the different tile
layouts on i8xx/i915...

I'm not able to hit this before commit 6846895fde05 ("drm/i915:
Replace PIN_NONFAULT with calls to PIN_NOEVICT") and it looks
like I also need to run recent version of Mesa. With those in
place xonotic trips on this quite easily on my 85x.

Cc: stable@vger.kernel.org
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 2561a2f1e54f..8598a1c78a4c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -189,7 +189,7 @@ compute_partial_view(const struct drm_i915_gem_object *obj,
 	struct i915_ggtt_view view;
 
 	if (i915_gem_object_is_tiled(obj))
-		chunk = roundup(chunk, tile_row_pages(obj));
+		chunk = roundup(chunk, tile_row_pages(obj) ?: 1);
 
 	view.type = I915_GGTT_VIEW_PARTIAL;
 	view.partial.offset = rounddown(page_offset, chunk);
-- 
2.26.3

[Intel-gfx] [PATCH 1/4] drm/i915: Avoid div-by-zero on gen2

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Gen2 tiles are 2KiB in size so i915_gem_object_get_tile_row_size()
can in fact return <4KiB, which leads to div-by-zero here.
Avoid that.

Not sure i915_gem_object_get_tile_row_size() is entirely
sane anyway since it doesn't account for the different tile
layouts on i8xx/i915...

I'm not able to hit this before commit 6846895fde05 ("drm/i915:
Replace PIN_NONFAULT with calls to PIN_NOEVICT") and it looks
like I also need to run recent version of Mesa. With those in
place xonotic trips on this quite easily on my 85x.

Cc: stable@vger.kernel.org
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 2561a2f1e54f..8598a1c78a4c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -189,7 +189,7 @@ compute_partial_view(const struct drm_i915_gem_object *obj,
 	struct i915_ggtt_view view;
 
 	if (i915_gem_object_is_tiled(obj))
-		chunk = roundup(chunk, tile_row_pages(obj));
+		chunk = roundup(chunk, tile_row_pages(obj) ?: 1);
 
 	view.type = I915_GGTT_VIEW_PARTIAL;
 	view.partial.offset = rounddown(page_offset, chunk);
-- 
2.26.3

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[PATCH 1/4] drm/i915: Avoid div-by-zero on gen2

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Gen2 tiles are 2KiB in size so i915_gem_object_get_tile_row_size()
can in fact return <4KiB, which leads to div-by-zero here.
Avoid that.

Not sure i915_gem_object_get_tile_row_size() is entirely
sane anyway since it doesn't account for the different tile
layouts on i8xx/i915...

I'm not able to hit this before commit 6846895fde05 ("drm/i915:
Replace PIN_NONFAULT with calls to PIN_NOEVICT") and it looks
like I also need to run recent version of Mesa. With those in
place xonotic trips on this quite easily on my 85x.

Cc: stable@vger.kernel.org
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 2561a2f1e54f..8598a1c78a4c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -189,7 +189,7 @@ compute_partial_view(const struct drm_i915_gem_object *obj,
 	struct i915_ggtt_view view;
 
 	if (i915_gem_object_is_tiled(obj))
-		chunk = roundup(chunk, tile_row_pages(obj));
+		chunk = roundup(chunk, tile_row_pages(obj) ?: 1);
 
 	view.type = I915_GGTT_VIEW_PARTIAL;
 	view.partial.offset = rounddown(page_offset, chunk);
-- 
2.26.3

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[PATCH 2/4] drm/i915: Read C0DRB3/C1DRB3 as 16 bits again

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We've defined C0DRB3/C0DRB3 as 16 bit registers, so access them
as such.

Fixes: 1c8242c3a4b2 ("drm/i915: Use unchecked writes for setting up the fences")
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index e72b7a0dc316..8a322594210c 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -653,8 +653,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
 		 * banks of memory are paired and unswizzled on the
 		 * uneven portion, so leave that as unknown.
 		 */
-		if (intel_uncore_read(uncore, C0DRB3) ==
-		    intel_uncore_read(uncore, C1DRB3)) {
+		if (intel_uncore_read16(uncore, C0DRB3) ==
+		    intel_uncore_read16(uncore, C1DRB3)) {
 			swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 			swizzle_y = I915_BIT_6_SWIZZLE_9;
 		}
-- 
2.26.3

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[Intel-gfx] [PATCH 2/4] drm/i915: Read C0DRB3/C1DRB3 as 16 bits again

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We've defined C0DRB3/C0DRB3 as 16 bit registers, so access them
as such.

Fixes: 1c8242c3a4b2 ("drm/i915: Use unchecked writes for setting up the fences")
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index e72b7a0dc316..8a322594210c 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -653,8 +653,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
 		 * banks of memory are paired and unswizzled on the
 		 * uneven portion, so leave that as unknown.
 		 */
-		if (intel_uncore_read(uncore, C0DRB3) ==
-		    intel_uncore_read(uncore, C1DRB3)) {
+		if (intel_uncore_read16(uncore, C0DRB3) ==
+		    intel_uncore_read16(uncore, C1DRB3)) {
 			swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 			swizzle_y = I915_BIT_6_SWIZZLE_9;
 		}
-- 
2.26.3

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[PATCH 3/4] drm/i915: Give C0DRB3/C1DRB3 a _BW suffix

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

These are the 965g/g45/g33 specific DRB registers. Give them
a suitable suffix so we can add their counterparts for other
platforms.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 4 ++--
 drivers/gpu/drm/i915/i915_debugfs.c          | 4 ++--
 drivers/gpu/drm/i915/i915_reg.h              | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index 8a322594210c..0fa6c38893f7 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -653,8 +653,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
 		 * banks of memory are paired and unswizzled on the
 		 * uneven portion, so leave that as unknown.
 		 */
-		if (intel_uncore_read16(uncore, C0DRB3) ==
-		    intel_uncore_read16(uncore, C1DRB3)) {
+		if (intel_uncore_read16(uncore, C0DRB3_BW) ==
+		    intel_uncore_read16(uncore, C1DRB3_BW)) {
 			swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 			swizzle_y = I915_BIT_6_SWIZZLE_9;
 		}
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b654b7498bcd..8dd374691102 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -622,9 +622,9 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
 		seq_printf(m, "DDC2 = 0x%08x\n",
 			   intel_uncore_read(uncore, DCC2));
 		seq_printf(m, "C0DRB3 = 0x%04x\n",
-			   intel_uncore_read16(uncore, C0DRB3));
+			   intel_uncore_read16(uncore, C0DRB3_BW));
 		seq_printf(m, "C1DRB3 = 0x%04x\n",
-			   intel_uncore_read16(uncore, C1DRB3));
+			   intel_uncore_read16(uncore, C1DRB3_BW));
 	} else if (INTEL_GEN(dev_priv) >= 6) {
 		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
 			   intel_uncore_read(uncore, MAD_DIMM_C0));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 66a902b3bb8e..0587b2455ea1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3787,8 +3787,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define CSHRDDR3CTL_DDR3       (1 << 2)
 
 /* 965 MCH register controlling DRAM channel configuration */
-#define C0DRB3			_MMIO(MCHBAR_MIRROR_BASE + 0x206)
-#define C1DRB3			_MMIO(MCHBAR_MIRROR_BASE + 0x606)
+#define C0DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x206)
+#define C1DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x606)
 
 /* snb MCH registers for reading the DRAM channel configuration */
 #define MAD_DIMM_C0			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
-- 
2.26.3

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[Intel-gfx] [PATCH 3/4] drm/i915: Give C0DRB3/C1DRB3 a _BW suffix

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

These are the 965g/g45/g33 specific DRB registers. Give them
a suitable suffix so we can add their counterparts for other
platforms.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 4 ++--
 drivers/gpu/drm/i915/i915_debugfs.c          | 4 ++--
 drivers/gpu/drm/i915/i915_reg.h              | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index 8a322594210c..0fa6c38893f7 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -653,8 +653,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
 		 * banks of memory are paired and unswizzled on the
 		 * uneven portion, so leave that as unknown.
 		 */
-		if (intel_uncore_read16(uncore, C0DRB3) ==
-		    intel_uncore_read16(uncore, C1DRB3)) {
+		if (intel_uncore_read16(uncore, C0DRB3_BW) ==
+		    intel_uncore_read16(uncore, C1DRB3_BW)) {
 			swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 			swizzle_y = I915_BIT_6_SWIZZLE_9;
 		}
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b654b7498bcd..8dd374691102 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -622,9 +622,9 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
 		seq_printf(m, "DDC2 = 0x%08x\n",
 			   intel_uncore_read(uncore, DCC2));
 		seq_printf(m, "C0DRB3 = 0x%04x\n",
-			   intel_uncore_read16(uncore, C0DRB3));
+			   intel_uncore_read16(uncore, C0DRB3_BW));
 		seq_printf(m, "C1DRB3 = 0x%04x\n",
-			   intel_uncore_read16(uncore, C1DRB3));
+			   intel_uncore_read16(uncore, C1DRB3_BW));
 	} else if (INTEL_GEN(dev_priv) >= 6) {
 		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
 			   intel_uncore_read(uncore, MAD_DIMM_C0));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 66a902b3bb8e..0587b2455ea1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3787,8 +3787,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define CSHRDDR3CTL_DDR3       (1 << 2)
 
 /* 965 MCH register controlling DRAM channel configuration */
-#define C0DRB3			_MMIO(MCHBAR_MIRROR_BASE + 0x206)
-#define C1DRB3			_MMIO(MCHBAR_MIRROR_BASE + 0x606)
+#define C0DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x206)
+#define C1DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x606)
 
 /* snb MCH registers for reading the DRAM channel configuration */
 #define MAD_DIMM_C0			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
-- 
2.26.3

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[PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we try to detect a symmetric memory configurations
using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is
either only set on a very specific subset of machines or it
just does not exist (it's not mentioned in any public chipset
datasheets I've found). As it happens my CL/CTG machines never
set said bit, even if I populate the channels with identical
sticks.

So let's do the L-shaped memory detection the same way as the
desktop variants, ie. just look at the DRAM rank boundary
registers to see if both channels have an identical size.

With this my CL/CTG no longer claim L-shaped memory when I use
identical sticks. Also tested with non-matching sticks just to
make sure the L-shaped memory is still properly detected.

And for completeness let's update the debugfs code to dump
the correct set of registers on each platform.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 15 ++++++++-------
 drivers/gpu/drm/i915/i915_debugfs.c          | 16 ++++++++++++----
 drivers/gpu/drm/i915/i915_reg.h              |  4 ++++
 3 files changed, 24 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index 0fa6c38893f7..754f20768de5 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -693,14 +693,15 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
 				swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
 				swizzle_y = I915_BIT_6_SWIZZLE_9_17;
 			}
-			break;
-		}
 
-		/* check for L-shaped memory aka modified enhanced addressing */
-		if (IS_GEN(i915, 4) &&
-		    !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
-			swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
-			swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
+			/* check for L-shaped memory aka modified enhanced addressing */
+			if (IS_GEN(i915, 4) &&
+			    intel_uncore_read16(uncore, C0DRB3_CL) !=
+			    intel_uncore_read16(uncore, C1DRB3_CL)) {
+				swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
+				swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
+			}
+			break;
 		}
 
 		if (dcc == 0xffffffff) {
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8dd374691102..6de11ffcde38 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -621,10 +621,18 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
 			   intel_uncore_read(uncore, DCC));
 		seq_printf(m, "DDC2 = 0x%08x\n",
 			   intel_uncore_read(uncore, DCC2));
-		seq_printf(m, "C0DRB3 = 0x%04x\n",
-			   intel_uncore_read16(uncore, C0DRB3_BW));
-		seq_printf(m, "C1DRB3 = 0x%04x\n",
-			   intel_uncore_read16(uncore, C1DRB3_BW));
+
+		if (IS_G45(dev_priv) || IS_I965G(dev_priv) || IS_G33(dev_priv)) {
+			seq_printf(m, "C0DRB3 = 0x%04x\n",
+				   intel_uncore_read16(uncore, C0DRB3_BW));
+			seq_printf(m, "C1DRB3 = 0x%04x\n",
+				   intel_uncore_read16(uncore, C1DRB3_BW));
+		} else if (IS_GEN(dev_priv, 4)) {
+			seq_printf(m, "C0DRB3 = 0x%04x\n",
+				   intel_uncore_read16(uncore, C0DRB3_CL));
+			seq_printf(m, "C1DRB3 = 0x%04x\n",
+				   intel_uncore_read16(uncore, C1DRB3_CL));
+		}
 	} else if (INTEL_GEN(dev_priv) >= 6) {
 		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
 			   intel_uncore_read(uncore, MAD_DIMM_C0));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0587b2455ea1..055c258179a1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3790,6 +3790,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define C0DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x206)
 #define C1DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x606)
 
+/* 965gm,ctg DRAM channel configuration */
+#define C0DRB3_CL		_MMIO(MCHBAR_MIRROR_BASE + 0x1206)
+#define C1DRB3_CL		_MMIO(MCHBAR_MIRROR_BASE + 0x1306)
+
 /* snb MCH registers for reading the DRAM channel configuration */
 #define MAD_DIMM_C0			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
 #define MAD_DIMM_C1			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
-- 
2.26.3

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[Intel-gfx] [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we try to detect a symmetric memory configurations
using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is
either only set on a very specific subset of machines or it
just does not exist (it's not mentioned in any public chipset
datasheets I've found). As it happens my CL/CTG machines never
set said bit, even if I populate the channels with identical
sticks.

So let's do the L-shaped memory detection the same way as the
desktop variants, ie. just look at the DRAM rank boundary
registers to see if both channels have an identical size.

With this my CL/CTG no longer claim L-shaped memory when I use
identical sticks. Also tested with non-matching sticks just to
make sure the L-shaped memory is still properly detected.

And for completeness let's update the debugfs code to dump
the correct set of registers on each platform.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 15 ++++++++-------
 drivers/gpu/drm/i915/i915_debugfs.c          | 16 ++++++++++++----
 drivers/gpu/drm/i915/i915_reg.h              |  4 ++++
 3 files changed, 24 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index 0fa6c38893f7..754f20768de5 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -693,14 +693,15 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
 				swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
 				swizzle_y = I915_BIT_6_SWIZZLE_9_17;
 			}
-			break;
-		}
 
-		/* check for L-shaped memory aka modified enhanced addressing */
-		if (IS_GEN(i915, 4) &&
-		    !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
-			swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
-			swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
+			/* check for L-shaped memory aka modified enhanced addressing */
+			if (IS_GEN(i915, 4) &&
+			    intel_uncore_read16(uncore, C0DRB3_CL) !=
+			    intel_uncore_read16(uncore, C1DRB3_CL)) {
+				swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
+				swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
+			}
+			break;
 		}
 
 		if (dcc == 0xffffffff) {
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8dd374691102..6de11ffcde38 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -621,10 +621,18 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
 			   intel_uncore_read(uncore, DCC));
 		seq_printf(m, "DDC2 = 0x%08x\n",
 			   intel_uncore_read(uncore, DCC2));
-		seq_printf(m, "C0DRB3 = 0x%04x\n",
-			   intel_uncore_read16(uncore, C0DRB3_BW));
-		seq_printf(m, "C1DRB3 = 0x%04x\n",
-			   intel_uncore_read16(uncore, C1DRB3_BW));
+
+		if (IS_G45(dev_priv) || IS_I965G(dev_priv) || IS_G33(dev_priv)) {
+			seq_printf(m, "C0DRB3 = 0x%04x\n",
+				   intel_uncore_read16(uncore, C0DRB3_BW));
+			seq_printf(m, "C1DRB3 = 0x%04x\n",
+				   intel_uncore_read16(uncore, C1DRB3_BW));
+		} else if (IS_GEN(dev_priv, 4)) {
+			seq_printf(m, "C0DRB3 = 0x%04x\n",
+				   intel_uncore_read16(uncore, C0DRB3_CL));
+			seq_printf(m, "C1DRB3 = 0x%04x\n",
+				   intel_uncore_read16(uncore, C1DRB3_CL));
+		}
 	} else if (INTEL_GEN(dev_priv) >= 6) {
 		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
 			   intel_uncore_read(uncore, MAD_DIMM_C0));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0587b2455ea1..055c258179a1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3790,6 +3790,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define C0DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x206)
 #define C1DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x606)
 
+/* 965gm,ctg DRAM channel configuration */
+#define C0DRB3_CL		_MMIO(MCHBAR_MIRROR_BASE + 0x1206)
+#define C1DRB3_CL		_MMIO(MCHBAR_MIRROR_BASE + 0x1306)
+
 /* snb MCH registers for reading the DRAM channel configuration */
 #define MAD_DIMM_C0			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
 #define MAD_DIMM_C1			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
-- 
2.26.3

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Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection

[Daniel Vetter]

On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently we try to detect a symmetric memory configurations
> using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is
> either only set on a very specific subset of machines or it
> just does not exist (it's not mentioned in any public chipset
> datasheets I've found). As it happens my CL/CTG machines never
> set said bit, even if I populate the channels with identical
> sticks.
> 
> So let's do the L-shaped memory detection the same way as the
> desktop variants, ie. just look at the DRAM rank boundary
> registers to see if both channels have an identical size.
> 
> With this my CL/CTG no longer claim L-shaped memory when I use
> identical sticks. Also tested with non-matching sticks just to
> make sure the L-shaped memory is still properly detected.
> 
> And for completeness let's update the debugfs code to dump
> the correct set of registers on each platform.
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Did you check this with the swapping igt? I have some vague memories of
bug reports where somehow the machine was acting like it's L-shaped memory
despite that banks were populated equally. I've iirc tried all kinds of
tricks to figure it out, all to absolutely no avail.

tbh I'd just not touch this, not really worth it.
-Daniel
> ---
>  drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 15 ++++++++-------
>  drivers/gpu/drm/i915/i915_debugfs.c          | 16 ++++++++++++----
>  drivers/gpu/drm/i915/i915_reg.h              |  4 ++++
>  3 files changed, 24 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> index 0fa6c38893f7..754f20768de5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> @@ -693,14 +693,15 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
>  				swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
>  				swizzle_y = I915_BIT_6_SWIZZLE_9_17;
>  			}
> -			break;
> -		}
>  
> -		/* check for L-shaped memory aka modified enhanced addressing */
> -		if (IS_GEN(i915, 4) &&
> -		    !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
> -			swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> -			swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> +			/* check for L-shaped memory aka modified enhanced addressing */
> +			if (IS_GEN(i915, 4) &&
> +			    intel_uncore_read16(uncore, C0DRB3_CL) !=
> +			    intel_uncore_read16(uncore, C1DRB3_CL)) {
> +				swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> +				swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> +			}
> +			break;
>  		}
>  
>  		if (dcc == 0xffffffff) {
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 8dd374691102..6de11ffcde38 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -621,10 +621,18 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
>  			   intel_uncore_read(uncore, DCC));
>  		seq_printf(m, "DDC2 = 0x%08x\n",
>  			   intel_uncore_read(uncore, DCC2));
> -		seq_printf(m, "C0DRB3 = 0x%04x\n",
> -			   intel_uncore_read16(uncore, C0DRB3_BW));
> -		seq_printf(m, "C1DRB3 = 0x%04x\n",
> -			   intel_uncore_read16(uncore, C1DRB3_BW));
> +
> +		if (IS_G45(dev_priv) || IS_I965G(dev_priv) || IS_G33(dev_priv)) {
> +			seq_printf(m, "C0DRB3 = 0x%04x\n",
> +				   intel_uncore_read16(uncore, C0DRB3_BW));
> +			seq_printf(m, "C1DRB3 = 0x%04x\n",
> +				   intel_uncore_read16(uncore, C1DRB3_BW));
> +		} else if (IS_GEN(dev_priv, 4)) {
> +			seq_printf(m, "C0DRB3 = 0x%04x\n",
> +				   intel_uncore_read16(uncore, C0DRB3_CL));
> +			seq_printf(m, "C1DRB3 = 0x%04x\n",
> +				   intel_uncore_read16(uncore, C1DRB3_CL));
> +		}
>  	} else if (INTEL_GEN(dev_priv) >= 6) {
>  		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
>  			   intel_uncore_read(uncore, MAD_DIMM_C0));
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0587b2455ea1..055c258179a1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3790,6 +3790,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define C0DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x206)
>  #define C1DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x606)
>  
> +/* 965gm,ctg DRAM channel configuration */
> +#define C0DRB3_CL		_MMIO(MCHBAR_MIRROR_BASE + 0x1206)
> +#define C1DRB3_CL		_MMIO(MCHBAR_MIRROR_BASE + 0x1306)
> +
>  /* snb MCH registers for reading the DRAM channel configuration */
>  #define MAD_DIMM_C0			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
>  #define MAD_DIMM_C1			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
> -- 
> 2.26.3
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection

[Daniel Vetter]

On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently we try to detect a symmetric memory configurations
> using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is
> either only set on a very specific subset of machines or it
> just does not exist (it's not mentioned in any public chipset
> datasheets I've found). As it happens my CL/CTG machines never
> set said bit, even if I populate the channels with identical
> sticks.
> 
> So let's do the L-shaped memory detection the same way as the
> desktop variants, ie. just look at the DRAM rank boundary
> registers to see if both channels have an identical size.
> 
> With this my CL/CTG no longer claim L-shaped memory when I use
> identical sticks. Also tested with non-matching sticks just to
> make sure the L-shaped memory is still properly detected.
> 
> And for completeness let's update the debugfs code to dump
> the correct set of registers on each platform.
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Did you check this with the swapping igt? I have some vague memories of
bug reports where somehow the machine was acting like it's L-shaped memory
despite that banks were populated equally. I've iirc tried all kinds of
tricks to figure it out, all to absolutely no avail.

tbh I'd just not touch this, not really worth it.
-Daniel
> ---
>  drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 15 ++++++++-------
>  drivers/gpu/drm/i915/i915_debugfs.c          | 16 ++++++++++++----
>  drivers/gpu/drm/i915/i915_reg.h              |  4 ++++
>  3 files changed, 24 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> index 0fa6c38893f7..754f20768de5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> @@ -693,14 +693,15 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
>  				swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
>  				swizzle_y = I915_BIT_6_SWIZZLE_9_17;
>  			}
> -			break;
> -		}
>  
> -		/* check for L-shaped memory aka modified enhanced addressing */
> -		if (IS_GEN(i915, 4) &&
> -		    !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
> -			swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> -			swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> +			/* check for L-shaped memory aka modified enhanced addressing */
> +			if (IS_GEN(i915, 4) &&
> +			    intel_uncore_read16(uncore, C0DRB3_CL) !=
> +			    intel_uncore_read16(uncore, C1DRB3_CL)) {
> +				swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> +				swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> +			}
> +			break;
>  		}
>  
>  		if (dcc == 0xffffffff) {
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 8dd374691102..6de11ffcde38 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -621,10 +621,18 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
>  			   intel_uncore_read(uncore, DCC));
>  		seq_printf(m, "DDC2 = 0x%08x\n",
>  			   intel_uncore_read(uncore, DCC2));
> -		seq_printf(m, "C0DRB3 = 0x%04x\n",
> -			   intel_uncore_read16(uncore, C0DRB3_BW));
> -		seq_printf(m, "C1DRB3 = 0x%04x\n",
> -			   intel_uncore_read16(uncore, C1DRB3_BW));
> +
> +		if (IS_G45(dev_priv) || IS_I965G(dev_priv) || IS_G33(dev_priv)) {
> +			seq_printf(m, "C0DRB3 = 0x%04x\n",
> +				   intel_uncore_read16(uncore, C0DRB3_BW));
> +			seq_printf(m, "C1DRB3 = 0x%04x\n",
> +				   intel_uncore_read16(uncore, C1DRB3_BW));
> +		} else if (IS_GEN(dev_priv, 4)) {
> +			seq_printf(m, "C0DRB3 = 0x%04x\n",
> +				   intel_uncore_read16(uncore, C0DRB3_CL));
> +			seq_printf(m, "C1DRB3 = 0x%04x\n",
> +				   intel_uncore_read16(uncore, C1DRB3_CL));
> +		}
>  	} else if (INTEL_GEN(dev_priv) >= 6) {
>  		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
>  			   intel_uncore_read(uncore, MAD_DIMM_C0));
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0587b2455ea1..055c258179a1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3790,6 +3790,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define C0DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x206)
>  #define C1DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x606)
>  
> +/* 965gm,ctg DRAM channel configuration */
> +#define C0DRB3_CL		_MMIO(MCHBAR_MIRROR_BASE + 0x1206)
> +#define C1DRB3_CL		_MMIO(MCHBAR_MIRROR_BASE + 0x1306)
> +
>  /* snb MCH registers for reading the DRAM channel configuration */
>  #define MAD_DIMM_C0			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
>  #define MAD_DIMM_C1			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
> -- 
> 2.26.3
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
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Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection

[Ville Syrjälä]

On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote:
> On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Currently we try to detect a symmetric memory configurations
> > using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is
> > either only set on a very specific subset of machines or it
> > just does not exist (it's not mentioned in any public chipset
> > datasheets I've found). As it happens my CL/CTG machines never
> > set said bit, even if I populate the channels with identical
> > sticks.
> > 
> > So let's do the L-shaped memory detection the same way as the
> > desktop variants, ie. just look at the DRAM rank boundary
> > registers to see if both channels have an identical size.
> > 
> > With this my CL/CTG no longer claim L-shaped memory when I use
> > identical sticks. Also tested with non-matching sticks just to
> > make sure the L-shaped memory is still properly detected.
> > 
> > And for completeness let's update the debugfs code to dump
> > the correct set of registers on each platform.
> > 
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Did you check this with the swapping igt? I have some vague memories of
> bug reports where somehow the machine was acting like it's L-shaped memory
> despite that banks were populated equally. I've iirc tried all kinds of
> tricks to figure it out, all to absolutely no avail.

Did you have a specific test in mind? I ran a bunch of things
that seemed swizzle related. All passed just fine.

Chris did have similar concerns and suggested we should have
better tests. I guess what I should try to do is some selftests
which make sure we test both high and low physical addresses
and check the swizzle pattern is as expected. But haven't 
found the time to do that yet.

> 
> tbh I'd just not touch this, not really worth it.

It's totally worth it to get gen4 machines working again.


> -Daniel
> > ---
> >  drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 15 ++++++++-------
> >  drivers/gpu/drm/i915/i915_debugfs.c          | 16 ++++++++++++----
> >  drivers/gpu/drm/i915/i915_reg.h              |  4 ++++
> >  3 files changed, 24 insertions(+), 11 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > index 0fa6c38893f7..754f20768de5 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > @@ -693,14 +693,15 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
> >  				swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
> >  				swizzle_y = I915_BIT_6_SWIZZLE_9_17;
> >  			}
> > -			break;
> > -		}
> >  
> > -		/* check for L-shaped memory aka modified enhanced addressing */
> > -		if (IS_GEN(i915, 4) &&
> > -		    !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
> > -			swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> > -			swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> > +			/* check for L-shaped memory aka modified enhanced addressing */
> > +			if (IS_GEN(i915, 4) &&
> > +			    intel_uncore_read16(uncore, C0DRB3_CL) !=
> > +			    intel_uncore_read16(uncore, C1DRB3_CL)) {
> > +				swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> > +				swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> > +			}
> > +			break;
> >  		}
> >  
> >  		if (dcc == 0xffffffff) {
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 8dd374691102..6de11ffcde38 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -621,10 +621,18 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
> >  			   intel_uncore_read(uncore, DCC));
> >  		seq_printf(m, "DDC2 = 0x%08x\n",
> >  			   intel_uncore_read(uncore, DCC2));
> > -		seq_printf(m, "C0DRB3 = 0x%04x\n",
> > -			   intel_uncore_read16(uncore, C0DRB3_BW));
> > -		seq_printf(m, "C1DRB3 = 0x%04x\n",
> > -			   intel_uncore_read16(uncore, C1DRB3_BW));
> > +
> > +		if (IS_G45(dev_priv) || IS_I965G(dev_priv) || IS_G33(dev_priv)) {
> > +			seq_printf(m, "C0DRB3 = 0x%04x\n",
> > +				   intel_uncore_read16(uncore, C0DRB3_BW));
> > +			seq_printf(m, "C1DRB3 = 0x%04x\n",
> > +				   intel_uncore_read16(uncore, C1DRB3_BW));
> > +		} else if (IS_GEN(dev_priv, 4)) {
> > +			seq_printf(m, "C0DRB3 = 0x%04x\n",
> > +				   intel_uncore_read16(uncore, C0DRB3_CL));
> > +			seq_printf(m, "C1DRB3 = 0x%04x\n",
> > +				   intel_uncore_read16(uncore, C1DRB3_CL));
> > +		}
> >  	} else if (INTEL_GEN(dev_priv) >= 6) {
> >  		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
> >  			   intel_uncore_read(uncore, MAD_DIMM_C0));
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 0587b2455ea1..055c258179a1 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3790,6 +3790,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> >  #define C0DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x206)
> >  #define C1DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x606)
> >  
> > +/* 965gm,ctg DRAM channel configuration */
> > +#define C0DRB3_CL		_MMIO(MCHBAR_MIRROR_BASE + 0x1206)
> > +#define C1DRB3_CL		_MMIO(MCHBAR_MIRROR_BASE + 0x1306)
> > +
> >  /* snb MCH registers for reading the DRAM channel configuration */
> >  #define MAD_DIMM_C0			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
> >  #define MAD_DIMM_C1			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
> > -- 
> > 2.26.3
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection

[Ville Syrjälä]

On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote:
> On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Currently we try to detect a symmetric memory configurations
> > using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is
> > either only set on a very specific subset of machines or it
> > just does not exist (it's not mentioned in any public chipset
> > datasheets I've found). As it happens my CL/CTG machines never
> > set said bit, even if I populate the channels with identical
> > sticks.
> > 
> > So let's do the L-shaped memory detection the same way as the
> > desktop variants, ie. just look at the DRAM rank boundary
> > registers to see if both channels have an identical size.
> > 
> > With this my CL/CTG no longer claim L-shaped memory when I use
> > identical sticks. Also tested with non-matching sticks just to
> > make sure the L-shaped memory is still properly detected.
> > 
> > And for completeness let's update the debugfs code to dump
> > the correct set of registers on each platform.
> > 
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Did you check this with the swapping igt? I have some vague memories of
> bug reports where somehow the machine was acting like it's L-shaped memory
> despite that banks were populated equally. I've iirc tried all kinds of
> tricks to figure it out, all to absolutely no avail.

Did you have a specific test in mind? I ran a bunch of things
that seemed swizzle related. All passed just fine.

Chris did have similar concerns and suggested we should have
better tests. I guess what I should try to do is some selftests
which make sure we test both high and low physical addresses
and check the swizzle pattern is as expected. But haven't 
found the time to do that yet.

> 
> tbh I'd just not touch this, not really worth it.

It's totally worth it to get gen4 machines working again.


> -Daniel
> > ---
> >  drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 15 ++++++++-------
> >  drivers/gpu/drm/i915/i915_debugfs.c          | 16 ++++++++++++----
> >  drivers/gpu/drm/i915/i915_reg.h              |  4 ++++
> >  3 files changed, 24 insertions(+), 11 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > index 0fa6c38893f7..754f20768de5 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > @@ -693,14 +693,15 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
> >  				swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
> >  				swizzle_y = I915_BIT_6_SWIZZLE_9_17;
> >  			}
> > -			break;
> > -		}
> >  
> > -		/* check for L-shaped memory aka modified enhanced addressing */
> > -		if (IS_GEN(i915, 4) &&
> > -		    !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
> > -			swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> > -			swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> > +			/* check for L-shaped memory aka modified enhanced addressing */
> > +			if (IS_GEN(i915, 4) &&
> > +			    intel_uncore_read16(uncore, C0DRB3_CL) !=
> > +			    intel_uncore_read16(uncore, C1DRB3_CL)) {
> > +				swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> > +				swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> > +			}
> > +			break;
> >  		}
> >  
> >  		if (dcc == 0xffffffff) {
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 8dd374691102..6de11ffcde38 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -621,10 +621,18 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
> >  			   intel_uncore_read(uncore, DCC));
> >  		seq_printf(m, "DDC2 = 0x%08x\n",
> >  			   intel_uncore_read(uncore, DCC2));
> > -		seq_printf(m, "C0DRB3 = 0x%04x\n",
> > -			   intel_uncore_read16(uncore, C0DRB3_BW));
> > -		seq_printf(m, "C1DRB3 = 0x%04x\n",
> > -			   intel_uncore_read16(uncore, C1DRB3_BW));
> > +
> > +		if (IS_G45(dev_priv) || IS_I965G(dev_priv) || IS_G33(dev_priv)) {
> > +			seq_printf(m, "C0DRB3 = 0x%04x\n",
> > +				   intel_uncore_read16(uncore, C0DRB3_BW));
> > +			seq_printf(m, "C1DRB3 = 0x%04x\n",
> > +				   intel_uncore_read16(uncore, C1DRB3_BW));
> > +		} else if (IS_GEN(dev_priv, 4)) {
> > +			seq_printf(m, "C0DRB3 = 0x%04x\n",
> > +				   intel_uncore_read16(uncore, C0DRB3_CL));
> > +			seq_printf(m, "C1DRB3 = 0x%04x\n",
> > +				   intel_uncore_read16(uncore, C1DRB3_CL));
> > +		}
> >  	} else if (INTEL_GEN(dev_priv) >= 6) {
> >  		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
> >  			   intel_uncore_read(uncore, MAD_DIMM_C0));
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 0587b2455ea1..055c258179a1 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3790,6 +3790,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> >  #define C0DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x206)
> >  #define C1DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x606)
> >  
> > +/* 965gm,ctg DRAM channel configuration */
> > +#define C0DRB3_CL		_MMIO(MCHBAR_MIRROR_BASE + 0x1206)
> > +#define C1DRB3_CL		_MMIO(MCHBAR_MIRROR_BASE + 0x1306)
> > +
> >  /* snb MCH registers for reading the DRAM channel configuration */
> >  #define MAD_DIMM_C0			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
> >  #define MAD_DIMM_C1			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
> > -- 
> > 2.26.3
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection

[Daniel Vetter]

On Thu, Apr 22, 2021 at 04:11:22PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote:
> > On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Currently we try to detect a symmetric memory configurations
> > > using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is
> > > either only set on a very specific subset of machines or it
> > > just does not exist (it's not mentioned in any public chipset
> > > datasheets I've found). As it happens my CL/CTG machines never
> > > set said bit, even if I populate the channels with identical
> > > sticks.
> > > 
> > > So let's do the L-shaped memory detection the same way as the
> > > desktop variants, ie. just look at the DRAM rank boundary
> > > registers to see if both channels have an identical size.
> > > 
> > > With this my CL/CTG no longer claim L-shaped memory when I use
> > > identical sticks. Also tested with non-matching sticks just to
> > > make sure the L-shaped memory is still properly detected.
> > > 
> > > And for completeness let's update the debugfs code to dump
> > > the correct set of registers on each platform.
> > > 
> > > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Did you check this with the swapping igt? I have some vague memories of
> > bug reports where somehow the machine was acting like it's L-shaped memory
> > despite that banks were populated equally. I've iirc tried all kinds of
> > tricks to figure it out, all to absolutely no avail.
> 
> Did you have a specific test in mind? I ran a bunch of things
> that seemed swizzle related. All passed just fine.

gem_tiled_swapping should be the one. It tries to cycle your entire system
memory through tiled buffers into swap and out of it.
-Daniel

> 
> Chris did have similar concerns and suggested we should have
> better tests. I guess what I should try to do is some selftests
> which make sure we test both high and low physical addresses
> and check the swizzle pattern is as expected. But haven't 
> found the time to do that yet.
> 
> > 
> > tbh I'd just not touch this, not really worth it.
> 
> It's totally worth it to get gen4 machines working again.
> 
> 
> > -Daniel
> > > ---
> > >  drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 15 ++++++++-------
> > >  drivers/gpu/drm/i915/i915_debugfs.c          | 16 ++++++++++++----
> > >  drivers/gpu/drm/i915/i915_reg.h              |  4 ++++
> > >  3 files changed, 24 insertions(+), 11 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > > index 0fa6c38893f7..754f20768de5 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > > @@ -693,14 +693,15 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
> > >  				swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
> > >  				swizzle_y = I915_BIT_6_SWIZZLE_9_17;
> > >  			}
> > > -			break;
> > > -		}
> > >  
> > > -		/* check for L-shaped memory aka modified enhanced addressing */
> > > -		if (IS_GEN(i915, 4) &&
> > > -		    !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
> > > -			swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> > > -			swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> > > +			/* check for L-shaped memory aka modified enhanced addressing */
> > > +			if (IS_GEN(i915, 4) &&
> > > +			    intel_uncore_read16(uncore, C0DRB3_CL) !=
> > > +			    intel_uncore_read16(uncore, C1DRB3_CL)) {
> > > +				swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> > > +				swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> > > +			}
> > > +			break;
> > >  		}
> > >  
> > >  		if (dcc == 0xffffffff) {
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index 8dd374691102..6de11ffcde38 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -621,10 +621,18 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
> > >  			   intel_uncore_read(uncore, DCC));
> > >  		seq_printf(m, "DDC2 = 0x%08x\n",
> > >  			   intel_uncore_read(uncore, DCC2));
> > > -		seq_printf(m, "C0DRB3 = 0x%04x\n",
> > > -			   intel_uncore_read16(uncore, C0DRB3_BW));
> > > -		seq_printf(m, "C1DRB3 = 0x%04x\n",
> > > -			   intel_uncore_read16(uncore, C1DRB3_BW));
> > > +
> > > +		if (IS_G45(dev_priv) || IS_I965G(dev_priv) || IS_G33(dev_priv)) {
> > > +			seq_printf(m, "C0DRB3 = 0x%04x\n",
> > > +				   intel_uncore_read16(uncore, C0DRB3_BW));
> > > +			seq_printf(m, "C1DRB3 = 0x%04x\n",
> > > +				   intel_uncore_read16(uncore, C1DRB3_BW));
> > > +		} else if (IS_GEN(dev_priv, 4)) {
> > > +			seq_printf(m, "C0DRB3 = 0x%04x\n",
> > > +				   intel_uncore_read16(uncore, C0DRB3_CL));
> > > +			seq_printf(m, "C1DRB3 = 0x%04x\n",
> > > +				   intel_uncore_read16(uncore, C1DRB3_CL));
> > > +		}
> > >  	} else if (INTEL_GEN(dev_priv) >= 6) {
> > >  		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
> > >  			   intel_uncore_read(uncore, MAD_DIMM_C0));
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 0587b2455ea1..055c258179a1 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -3790,6 +3790,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> > >  #define C0DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x206)
> > >  #define C1DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x606)
> > >  
> > > +/* 965gm,ctg DRAM channel configuration */
> > > +#define C0DRB3_CL		_MMIO(MCHBAR_MIRROR_BASE + 0x1206)
> > > +#define C1DRB3_CL		_MMIO(MCHBAR_MIRROR_BASE + 0x1306)
> > > +
> > >  /* snb MCH registers for reading the DRAM channel configuration */
> > >  #define MAD_DIMM_C0			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
> > >  #define MAD_DIMM_C1			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
> > > -- 
> > > 2.26.3
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
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dri-devel@lists.freedesktop.org
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Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection

[Daniel Vetter]

On Thu, Apr 22, 2021 at 04:11:22PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote:
> > On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Currently we try to detect a symmetric memory configurations
> > > using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is
> > > either only set on a very specific subset of machines or it
> > > just does not exist (it's not mentioned in any public chipset
> > > datasheets I've found). As it happens my CL/CTG machines never
> > > set said bit, even if I populate the channels with identical
> > > sticks.
> > > 
> > > So let's do the L-shaped memory detection the same way as the
> > > desktop variants, ie. just look at the DRAM rank boundary
> > > registers to see if both channels have an identical size.
> > > 
> > > With this my CL/CTG no longer claim L-shaped memory when I use
> > > identical sticks. Also tested with non-matching sticks just to
> > > make sure the L-shaped memory is still properly detected.
> > > 
> > > And for completeness let's update the debugfs code to dump
> > > the correct set of registers on each platform.
> > > 
> > > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Did you check this with the swapping igt? I have some vague memories of
> > bug reports where somehow the machine was acting like it's L-shaped memory
> > despite that banks were populated equally. I've iirc tried all kinds of
> > tricks to figure it out, all to absolutely no avail.
> 
> Did you have a specific test in mind? I ran a bunch of things
> that seemed swizzle related. All passed just fine.

gem_tiled_swapping should be the one. It tries to cycle your entire system
memory through tiled buffers into swap and out of it.
-Daniel

> 
> Chris did have similar concerns and suggested we should have
> better tests. I guess what I should try to do is some selftests
> which make sure we test both high and low physical addresses
> and check the swizzle pattern is as expected. But haven't 
> found the time to do that yet.
> 
> > 
> > tbh I'd just not touch this, not really worth it.
> 
> It's totally worth it to get gen4 machines working again.
> 
> 
> > -Daniel
> > > ---
> > >  drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 15 ++++++++-------
> > >  drivers/gpu/drm/i915/i915_debugfs.c          | 16 ++++++++++++----
> > >  drivers/gpu/drm/i915/i915_reg.h              |  4 ++++
> > >  3 files changed, 24 insertions(+), 11 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > > index 0fa6c38893f7..754f20768de5 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > > @@ -693,14 +693,15 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
> > >  				swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
> > >  				swizzle_y = I915_BIT_6_SWIZZLE_9_17;
> > >  			}
> > > -			break;
> > > -		}
> > >  
> > > -		/* check for L-shaped memory aka modified enhanced addressing */
> > > -		if (IS_GEN(i915, 4) &&
> > > -		    !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
> > > -			swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> > > -			swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> > > +			/* check for L-shaped memory aka modified enhanced addressing */
> > > +			if (IS_GEN(i915, 4) &&
> > > +			    intel_uncore_read16(uncore, C0DRB3_CL) !=
> > > +			    intel_uncore_read16(uncore, C1DRB3_CL)) {
> > > +				swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> > > +				swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> > > +			}
> > > +			break;
> > >  		}
> > >  
> > >  		if (dcc == 0xffffffff) {
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index 8dd374691102..6de11ffcde38 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -621,10 +621,18 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
> > >  			   intel_uncore_read(uncore, DCC));
> > >  		seq_printf(m, "DDC2 = 0x%08x\n",
> > >  			   intel_uncore_read(uncore, DCC2));
> > > -		seq_printf(m, "C0DRB3 = 0x%04x\n",
> > > -			   intel_uncore_read16(uncore, C0DRB3_BW));
> > > -		seq_printf(m, "C1DRB3 = 0x%04x\n",
> > > -			   intel_uncore_read16(uncore, C1DRB3_BW));
> > > +
> > > +		if (IS_G45(dev_priv) || IS_I965G(dev_priv) || IS_G33(dev_priv)) {
> > > +			seq_printf(m, "C0DRB3 = 0x%04x\n",
> > > +				   intel_uncore_read16(uncore, C0DRB3_BW));
> > > +			seq_printf(m, "C1DRB3 = 0x%04x\n",
> > > +				   intel_uncore_read16(uncore, C1DRB3_BW));
> > > +		} else if (IS_GEN(dev_priv, 4)) {
> > > +			seq_printf(m, "C0DRB3 = 0x%04x\n",
> > > +				   intel_uncore_read16(uncore, C0DRB3_CL));
> > > +			seq_printf(m, "C1DRB3 = 0x%04x\n",
> > > +				   intel_uncore_read16(uncore, C1DRB3_CL));
> > > +		}
> > >  	} else if (INTEL_GEN(dev_priv) >= 6) {
> > >  		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
> > >  			   intel_uncore_read(uncore, MAD_DIMM_C0));
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 0587b2455ea1..055c258179a1 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -3790,6 +3790,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> > >  #define C0DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x206)
> > >  #define C1DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x606)
> > >  
> > > +/* 965gm,ctg DRAM channel configuration */
> > > +#define C0DRB3_CL		_MMIO(MCHBAR_MIRROR_BASE + 0x1206)
> > > +#define C1DRB3_CL		_MMIO(MCHBAR_MIRROR_BASE + 0x1306)
> > > +
> > >  /* snb MCH registers for reading the DRAM channel configuration */
> > >  #define MAD_DIMM_C0			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
> > >  #define MAD_DIMM_C1			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
> > > -- 
> > > 2.26.3
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection

[Ville Syrjälä]

On Mon, Apr 26, 2021 at 06:08:59PM +0200, Daniel Vetter wrote:
> On Thu, Apr 22, 2021 at 04:11:22PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote:
> > > On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > Currently we try to detect a symmetric memory configurations
> > > > using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is
> > > > either only set on a very specific subset of machines or it
> > > > just does not exist (it's not mentioned in any public chipset
> > > > datasheets I've found). As it happens my CL/CTG machines never
> > > > set said bit, even if I populate the channels with identical
> > > > sticks.
> > > > 
> > > > So let's do the L-shaped memory detection the same way as the
> > > > desktop variants, ie. just look at the DRAM rank boundary
> > > > registers to see if both channels have an identical size.
> > > > 
> > > > With this my CL/CTG no longer claim L-shaped memory when I use
> > > > identical sticks. Also tested with non-matching sticks just to
> > > > make sure the L-shaped memory is still properly detected.
> > > > 
> > > > And for completeness let's update the debugfs code to dump
> > > > the correct set of registers on each platform.
> > > > 
> > > > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Did you check this with the swapping igt? I have some vague memories of
> > > bug reports where somehow the machine was acting like it's L-shaped memory
> > > despite that banks were populated equally. I've iirc tried all kinds of
> > > tricks to figure it out, all to absolutely no avail.
> > 
> > Did you have a specific test in mind? I ran a bunch of things
> > that seemed swizzle related. All passed just fine.
> 
> gem_tiled_swapping should be the one. It tries to cycle your entire system
> memory through tiled buffers into swap and out of it.

Passes with symmetric config, fails with L-shaped config (if I hack
out the L-shape detection of course). So seems pretty solid.

A kernel based self test that looks at the physical address would
still be nice I suppose. Though depending on the size of your RAM
sticks figuring out where exactly the switchover from two channels
to one channels happens probably requires a bit of work due to
the PCI hole/etc.

Both my cl and ctg report this btw:
 bit6 swizzle for X-tiling = bit9/bit10/bit11
 bit6 swizzle for Y-tiling = bit9/bit11
so unfortunately can't be sure the other swizzle modes would be
correctly detected.

-- 
Ville Syrjälä
Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection

[Ville Syrjälä]

On Mon, Apr 26, 2021 at 06:08:59PM +0200, Daniel Vetter wrote:
> On Thu, Apr 22, 2021 at 04:11:22PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote:
> > > On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > Currently we try to detect a symmetric memory configurations
> > > > using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is
> > > > either only set on a very specific subset of machines or it
> > > > just does not exist (it's not mentioned in any public chipset
> > > > datasheets I've found). As it happens my CL/CTG machines never
> > > > set said bit, even if I populate the channels with identical
> > > > sticks.
> > > > 
> > > > So let's do the L-shaped memory detection the same way as the
> > > > desktop variants, ie. just look at the DRAM rank boundary
> > > > registers to see if both channels have an identical size.
> > > > 
> > > > With this my CL/CTG no longer claim L-shaped memory when I use
> > > > identical sticks. Also tested with non-matching sticks just to
> > > > make sure the L-shaped memory is still properly detected.
> > > > 
> > > > And for completeness let's update the debugfs code to dump
> > > > the correct set of registers on each platform.
> > > > 
> > > > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Did you check this with the swapping igt? I have some vague memories of
> > > bug reports where somehow the machine was acting like it's L-shaped memory
> > > despite that banks were populated equally. I've iirc tried all kinds of
> > > tricks to figure it out, all to absolutely no avail.
> > 
> > Did you have a specific test in mind? I ran a bunch of things
> > that seemed swizzle related. All passed just fine.
> 
> gem_tiled_swapping should be the one. It tries to cycle your entire system
> memory through tiled buffers into swap and out of it.

Passes with symmetric config, fails with L-shaped config (if I hack
out the L-shape detection of course). So seems pretty solid.

A kernel based self test that looks at the physical address would
still be nice I suppose. Though depending on the size of your RAM
sticks figuring out where exactly the switchover from two channels
to one channels happens probably requires a bit of work due to
the PCI hole/etc.

Both my cl and ctg report this btw:
 bit6 swizzle for X-tiling = bit9/bit10/bit11
 bit6 swizzle for Y-tiling = bit9/bit11
so unfortunately can't be sure the other swizzle modes would be
correctly detected.

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection

[Daniel Vetter]

On Mon, Apr 26, 2021 at 08:18:39PM +0300, Ville Syrjälä wrote:
> On Mon, Apr 26, 2021 at 06:08:59PM +0200, Daniel Vetter wrote:
> > On Thu, Apr 22, 2021 at 04:11:22PM +0300, Ville Syrjälä wrote:
> > > On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote:
> > > > On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
> > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > 
> > > > > Currently we try to detect a symmetric memory configurations
> > > > > using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is
> > > > > either only set on a very specific subset of machines or it
> > > > > just does not exist (it's not mentioned in any public chipset
> > > > > datasheets I've found). As it happens my CL/CTG machines never
> > > > > set said bit, even if I populate the channels with identical
> > > > > sticks.
> > > > > 
> > > > > So let's do the L-shaped memory detection the same way as the
> > > > > desktop variants, ie. just look at the DRAM rank boundary
> > > > > registers to see if both channels have an identical size.
> > > > > 
> > > > > With this my CL/CTG no longer claim L-shaped memory when I use
> > > > > identical sticks. Also tested with non-matching sticks just to
> > > > > make sure the L-shaped memory is still properly detected.
> > > > > 
> > > > > And for completeness let's update the debugfs code to dump
> > > > > the correct set of registers on each platform.
> > > > > 
> > > > > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > Did you check this with the swapping igt? I have some vague memories of
> > > > bug reports where somehow the machine was acting like it's L-shaped memory
> > > > despite that banks were populated equally. I've iirc tried all kinds of
> > > > tricks to figure it out, all to absolutely no avail.
> > > 
> > > Did you have a specific test in mind? I ran a bunch of things
> > > that seemed swizzle related. All passed just fine.
> > 
> > gem_tiled_swapping should be the one. It tries to cycle your entire system
> > memory through tiled buffers into swap and out of it.
> 
> Passes with symmetric config, fails with L-shaped config (if I hack
> out the L-shape detection of course). So seems pretty solid.
> 
> A kernel based self test that looks at the physical address would
> still be nice I suppose. Though depending on the size of your RAM
> sticks figuring out where exactly the switchover from two channels
> to one channels happens probably requires a bit of work due to
> the PCI hole/etc.
> 
> Both my cl and ctg report this btw:
>  bit6 swizzle for X-tiling = bit9/bit10/bit11
>  bit6 swizzle for Y-tiling = bit9/bit11
> so unfortunately can't be sure the other swizzle modes would be
> correctly detected.

I think testing-wise this is as good as it gets.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection

[Daniel Vetter]

On Mon, Apr 26, 2021 at 08:18:39PM +0300, Ville Syrjälä wrote:
> On Mon, Apr 26, 2021 at 06:08:59PM +0200, Daniel Vetter wrote:
> > On Thu, Apr 22, 2021 at 04:11:22PM +0300, Ville Syrjälä wrote:
> > > On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote:
> > > > On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
> > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > 
> > > > > Currently we try to detect a symmetric memory configurations
> > > > > using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is
> > > > > either only set on a very specific subset of machines or it
> > > > > just does not exist (it's not mentioned in any public chipset
> > > > > datasheets I've found). As it happens my CL/CTG machines never
> > > > > set said bit, even if I populate the channels with identical
> > > > > sticks.
> > > > > 
> > > > > So let's do the L-shaped memory detection the same way as the
> > > > > desktop variants, ie. just look at the DRAM rank boundary
> > > > > registers to see if both channels have an identical size.
> > > > > 
> > > > > With this my CL/CTG no longer claim L-shaped memory when I use
> > > > > identical sticks. Also tested with non-matching sticks just to
> > > > > make sure the L-shaped memory is still properly detected.
> > > > > 
> > > > > And for completeness let's update the debugfs code to dump
> > > > > the correct set of registers on each platform.
> > > > > 
> > > > > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > Did you check this with the swapping igt? I have some vague memories of
> > > > bug reports where somehow the machine was acting like it's L-shaped memory
> > > > despite that banks were populated equally. I've iirc tried all kinds of
> > > > tricks to figure it out, all to absolutely no avail.
> > > 
> > > Did you have a specific test in mind? I ran a bunch of things
> > > that seemed swizzle related. All passed just fine.
> > 
> > gem_tiled_swapping should be the one. It tries to cycle your entire system
> > memory through tiled buffers into swap and out of it.
> 
> Passes with symmetric config, fails with L-shaped config (if I hack
> out the L-shape detection of course). So seems pretty solid.
> 
> A kernel based self test that looks at the physical address would
> still be nice I suppose. Though depending on the size of your RAM
> sticks figuring out where exactly the switchover from two channels
> to one channels happens probably requires a bit of work due to
> the PCI hole/etc.
> 
> Both my cl and ctg report this btw:
>  bit6 swizzle for X-tiling = bit9/bit10/bit11
>  bit6 swizzle for Y-tiling = bit9/bit11
> so unfortunately can't be sure the other swizzle modes would be
> correctly detected.

I think testing-wise this is as good as it gets.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection

[Ville Syrjälä]

On Tue, Apr 27, 2021 at 10:58:07AM +0200, Daniel Vetter wrote:
> On Mon, Apr 26, 2021 at 08:18:39PM +0300, Ville Syrjälä wrote:
> > On Mon, Apr 26, 2021 at 06:08:59PM +0200, Daniel Vetter wrote:
> > > On Thu, Apr 22, 2021 at 04:11:22PM +0300, Ville Syrjälä wrote:
> > > > On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote:
> > > > > On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
> > > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > > 
> > > > > > Currently we try to detect a symmetric memory configurations
> > > > > > using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is
> > > > > > either only set on a very specific subset of machines or it
> > > > > > just does not exist (it's not mentioned in any public chipset
> > > > > > datasheets I've found). As it happens my CL/CTG machines never
> > > > > > set said bit, even if I populate the channels with identical
> > > > > > sticks.
> > > > > > 
> > > > > > So let's do the L-shaped memory detection the same way as the
> > > > > > desktop variants, ie. just look at the DRAM rank boundary
> > > > > > registers to see if both channels have an identical size.
> > > > > > 
> > > > > > With this my CL/CTG no longer claim L-shaped memory when I use
> > > > > > identical sticks. Also tested with non-matching sticks just to
> > > > > > make sure the L-shaped memory is still properly detected.
> > > > > > 
> > > > > > And for completeness let's update the debugfs code to dump
> > > > > > the correct set of registers on each platform.
> > > > > > 
> > > > > > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > 
> > > > > Did you check this with the swapping igt? I have some vague memories of
> > > > > bug reports where somehow the machine was acting like it's L-shaped memory
> > > > > despite that banks were populated equally. I've iirc tried all kinds of
> > > > > tricks to figure it out, all to absolutely no avail.
> > > > 
> > > > Did you have a specific test in mind? I ran a bunch of things
> > > > that seemed swizzle related. All passed just fine.
> > > 
> > > gem_tiled_swapping should be the one. It tries to cycle your entire system
> > > memory through tiled buffers into swap and out of it.
> > 
> > Passes with symmetric config, fails with L-shaped config (if I hack
> > out the L-shape detection of course). So seems pretty solid.
> > 
> > A kernel based self test that looks at the physical address would
> > still be nice I suppose. Though depending on the size of your RAM
> > sticks figuring out where exactly the switchover from two channels
> > to one channels happens probably requires a bit of work due to
> > the PCI hole/etc.
> > 
> > Both my cl and ctg report this btw:
> >  bit6 swizzle for X-tiling = bit9/bit10/bit11
> >  bit6 swizzle for Y-tiling = bit9/bit11
> > so unfortunately can't be sure the other swizzle modes would be
> > correctly detected.
> 
> I think testing-wise this is as good as it gets.

So what do we think about putting this in? Currently this only works by
sheer luck more or less. On my machines we have a false positive which
is safe now that the pin quirk got fixed, but if some other machines
have a false negative then things are not going to go so well.

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection

[Ville Syrjälä]

On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote:
> On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Currently we try to detect a symmetric memory configurations
> > using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is
> > either only set on a very specific subset of machines or it
> > just does not exist (it's not mentioned in any public chipset
> > datasheets I've found). As it happens my CL/CTG machines never
> > set said bit, even if I populate the channels with identical
> > sticks.
> > 
> > So let's do the L-shaped memory detection the same way as the
> > desktop variants, ie. just look at the DRAM rank boundary
> > registers to see if both channels have an identical size.
> > 
> > With this my CL/CTG no longer claim L-shaped memory when I use
> > identical sticks. Also tested with non-matching sticks just to
> > make sure the L-shaped memory is still properly detected.
> > 
> > And for completeness let's update the debugfs code to dump
> > the correct set of registers on each platform.
> > 
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Did you check this with the swapping igt? I have some vague memories of
> bug reports where somehow the machine was acting like it's L-shaped memory
> despite that banks were populated equally. I've iirc tried all kinds of
> tricks to figure it out, all to absolutely no avail.

BTW looking at the patches/dumps in eg.
https://bugs.freedesktop.org/show_bug.cgi?id=28813
I can't immediately see a single thing that is actually using
the correct register offsets for cl/ctg. So I'm a bit sceptical
about how well this was researched in the past.

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 4/4] drm/i915: Rewrite CL/CTG L-shaped memory detection

[Ville Syrjälä]

On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote:
> On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Currently we try to detect a symmetric memory configurations
> > using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is
> > either only set on a very specific subset of machines or it
> > just does not exist (it's not mentioned in any public chipset
> > datasheets I've found). As it happens my CL/CTG machines never
> > set said bit, even if I populate the channels with identical
> > sticks.
> > 
> > So let's do the L-shaped memory detection the same way as the
> > desktop variants, ie. just look at the DRAM rank boundary
> > registers to see if both channels have an identical size.
> > 
> > With this my CL/CTG no longer claim L-shaped memory when I use
> > identical sticks. Also tested with non-matching sticks just to
> > make sure the L-shaped memory is still properly detected.
> > 
> > And for completeness let's update the debugfs code to dump
> > the correct set of registers on each platform.
> > 
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Did you check this with the swapping igt? I have some vague memories of
> bug reports where somehow the machine was acting like it's L-shaped memory
> despite that banks were populated equally. I've iirc tried all kinds of
> tricks to figure it out, all to absolutely no avail.

BTW looking at the patches/dumps in eg.
https://bugs.freedesktop.org/show_bug.cgi?id=28813
I can't immediately see a single thing that is actually using
the correct register offsets for cl/ctg. So I'm a bit sceptical
about how well this was researched in the past.

-- 
Ville Syrjälä
Intel
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Fix older platforms

[Patchwork]

== Series Details ==

Series: drm/i915: Fix older platforms
URL   : https://patchwork.freedesktop.org/series/89306/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser'


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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix older platforms

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 3612 bytes --]

== Series Details ==

Series: drm/i915: Fix older platforms
URL   : https://patchwork.freedesktop.org/series/89306/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9993 -> Patchwork_19964
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/index.html

Known issues
------------

  Here are the changes found in Patchwork_19964 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@late_gt_pm:
    - fi-bsw-nick:        [PASS][1] -> [DMESG-FAIL][2] ([i915#2927])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html

  * igt@runner@aborted:
    - fi-bsw-nick:        NOTRUN -> [FAIL][3] ([i915#1436])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/fi-bsw-nick/igt@runner@aborted.html
    - fi-bdw-5557u:       NOTRUN -> [FAIL][4] ([i915#1602] / [i915#2029])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/fi-bdw-5557u/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
    - fi-kbl-soraka:      [FAIL][5] ([i915#2346]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/fi-kbl-soraka/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/fi-kbl-soraka/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html

  * igt@kms_frontbuffer_tracking@basic:
    - {fi-rkl-11500t}:    [SKIP][7] ([i915#1849] / [i915#3180]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/fi-rkl-11500t/igt@kms_frontbuffer_tracking@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/fi-rkl-11500t/igt@kms_frontbuffer_tracking@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
  [i915#3180]: https://gitlab.freedesktop.org/drm/intel/issues/3180
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303


Participating hosts (42 -> 40)
------------------------------

  Missing    (2): fi-bsw-cyan fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9993 -> Patchwork_19964

  CI-20190529: 20190529
  CI_DRM_9993: 629d3809e6d926c77ba5e9c5405e64eeba564560 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6072: 0a51f49df9f5ca535fc0206a27a6780de6b52320 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19964: 6766ff3915c2cde9f06f0804dbeed9afdcd4b7e6 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

6766ff3915c2 drm/i915: Rewrite CL/CTG L-shaped memory detection
f45d17839535 drm/i915: Give C0DRB3/C1DRB3 a _BW suffix
f2d7009113f9 drm/i915: Read C0DRB3/C1DRB3 as 16 bits again
7faa6f9fd08d drm/i915: Avoid div-by-zero on gen2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/index.html

[-- Attachment #1.2: Type: text/html, Size: 4281 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix older platforms

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 27402 bytes --]

== Series Details ==

Series: drm/i915: Fix older platforms
URL   : https://patchwork.freedesktop.org/series/89306/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9993_full -> Patchwork_19964_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_19964_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_persistence@process:
    - shard-snb:          NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +4 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-snb7/igt@gem_ctx_persistence@process.html

  * igt@gem_eio@unwedge-stress:
    - shard-tglb:         [PASS][2] -> [TIMEOUT][3] ([i915#2369] / [i915#3063])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-tglb1/igt@gem_eio@unwedge-stress.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-tglb2/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-apl:          NOTRUN -> [FAIL][4] ([i915#2846])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-apl7/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-flow@rcs0:
    - shard-skl:          NOTRUN -> [SKIP][5] ([fdo#109271]) +72 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl10/igt@gem_exec_fair@basic-flow@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
    - shard-tglb:         [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-tglb5/igt@gem_exec_fair@basic-pace@vcs0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-tglb5/igt@gem_exec_fair@basic-pace@vcs0.html

  * igt@gem_exec_whisper@basic-contexts-priority-all:
    - shard-glk:          [PASS][10] -> [DMESG-WARN][11] ([i915#118] / [i915#95])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-glk8/igt@gem_exec_whisper@basic-contexts-priority-all.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-glk2/igt@gem_exec_whisper@basic-contexts-priority-all.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [PASS][12] -> [SKIP][13] ([i915#2190])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-tglb3/igt@gem_huc_copy@huc-copy.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-tglb6/igt@gem_huc_copy@huc-copy.html
    - shard-skl:          NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#2190])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl1/igt@gem_huc_copy@huc-copy.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-snb:          NOTRUN -> [WARN][15] ([i915#2658])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-snb7/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_userptr_blits@input-checking:
    - shard-snb:          NOTRUN -> [DMESG-WARN][16] ([i915#3002])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-snb2/igt@gem_userptr_blits@input-checking.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-apl:          NOTRUN -> [FAIL][17] ([i915#3318])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-apl3/igt@gem_userptr_blits@vma-merge.html

  * igt@gem_vm_create@destroy-race:
    - shard-tglb:         [PASS][18] -> [TIMEOUT][19] ([i915#2795])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-tglb5/igt@gem_vm_create@destroy-race.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-tglb5/igt@gem_vm_create@destroy-race.html

  * igt@gen9_exec_parse@bb-large:
    - shard-skl:          NOTRUN -> [FAIL][20] ([i915#3296])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl9/igt@gen9_exec_parse@bb-large.html

  * igt@i915_hangman@engine-error@vecs0:
    - shard-kbl:          NOTRUN -> [SKIP][21] ([fdo#109271]) +72 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl1/igt@i915_hangman@engine-error@vecs0.html

  * igt@i915_selftest@live@hangcheck:
    - shard-snb:          NOTRUN -> [INCOMPLETE][22] ([i915#2782])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-snb6/igt@i915_selftest@live@hangcheck.html

  * igt@i915_suspend@debugfs-reader:
    - shard-skl:          [PASS][23] -> [INCOMPLETE][24] ([i915#198])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl4/igt@i915_suspend@debugfs-reader.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl1/igt@i915_suspend@debugfs-reader.html

  * igt@kms_async_flips@test-time-stamp:
    - shard-tglb:         [PASS][25] -> [FAIL][26] ([i915#2574])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-tglb2/igt@kms_async_flips@test-time-stamp.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-tglb3/igt@kms_async_flips@test-time-stamp.html

  * igt@kms_ccs@pipe-a-ccs-on-another-bo:
    - shard-snb:          NOTRUN -> [SKIP][27] ([fdo#109271]) +257 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-snb2/igt@kms_ccs@pipe-a-ccs-on-another-bo.html

  * igt@kms_chamelium@dp-mode-timings:
    - shard-apl:          NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +17 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-apl2/igt@kms_chamelium@dp-mode-timings.html

  * igt@kms_color_chamelium@pipe-a-degamma:
    - shard-kbl:          NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +5 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl3/igt@kms_color_chamelium@pipe-a-degamma.html

  * igt@kms_color_chamelium@pipe-c-ctm-negative:
    - shard-skl:          NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +5 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl9/igt@kms_color_chamelium@pipe-c-ctm-negative.html

  * igt@kms_color_chamelium@pipe-c-ctm-red-to-blue:
    - shard-snb:          NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +16 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-snb7/igt@kms_color_chamelium@pipe-c-ctm-red-to-blue.html

  * igt@kms_content_protection@atomic:
    - shard-apl:          NOTRUN -> [TIMEOUT][32] ([i915#1319])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-apl7/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@uevent:
    - shard-kbl:          NOTRUN -> [FAIL][33] ([i915#2105])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl1/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [PASS][34] -> [DMESG-WARN][35] ([i915#180]) +6 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-tglb:         [PASS][36] -> [FAIL][37] ([i915#2346])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-tglb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-tglb6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-skl:          [PASS][38] -> [FAIL][39] ([i915#79]) +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl8/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
    - shard-kbl:          NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#2672])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
    - shard-apl:          NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#2642])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-apl2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
    - shard-apl:          NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#2672])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-apl2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render:
    - shard-skl:          [PASS][43] -> [FAIL][44] ([i915#49])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl9/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - shard-apl:          NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#533]) +4 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-apl1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
    - shard-kbl:          NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#533])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl3/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
    - shard-skl:          NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#533])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl1/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
    - shard-kbl:          [PASS][48] -> [INCOMPLETE][49] ([i915#155])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
    - shard-kbl:          NOTRUN -> [FAIL][50] ([i915#265])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl1/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
    - shard-skl:          NOTRUN -> [FAIL][51] ([fdo#108145] / [i915#265])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
    - shard-apl:          NOTRUN -> [FAIL][52] ([fdo#108145] / [i915#265]) +1 similar issue
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-apl3/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
    - shard-skl:          NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#2733])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl10/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
    - shard-kbl:          NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#658]) +1 similar issue
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
    - shard-apl:          NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#658]) +4 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-apl3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
    - shard-skl:          NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#658]) +1 similar issue
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl10/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         [PASS][57] -> [SKIP][58] ([fdo#109441]) +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-iclb3/igt@kms_psr@psr2_cursor_blt.html

  * igt@kms_sysfs_edid_timing:
    - shard-kbl:          NOTRUN -> [FAIL][59] ([IGT#2])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl1/igt@kms_sysfs_edid_timing.html

  * igt@kms_vblank@pipe-d-wait-forked-hang:
    - shard-apl:          NOTRUN -> [SKIP][60] ([fdo#109271]) +217 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-apl3/igt@kms_vblank@pipe-d-wait-forked-hang.html

  * igt@kms_writeback@writeback-check-output:
    - shard-apl:          NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#2437]) +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-apl2/igt@kms_writeback@writeback-check-output.html

  * igt@perf@polling:
    - shard-skl:          [PASS][62] -> [FAIL][63] ([i915#1542])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl7/igt@perf@polling.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl8/igt@perf@polling.html

  * igt@sysfs_clients@fair-1:
    - shard-apl:          NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#2994]) +3 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-apl2/igt@sysfs_clients@fair-1.html

  * igt@sysfs_clients@sema-50:
    - shard-kbl:          NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#2994]) +2 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl1/igt@sysfs_clients@sema-50.html

  * igt@sysfs_heartbeat_interval@precise@vecs0:
    - shard-skl:          NOTRUN -> [FAIL][66] ([i915#1755])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl9/igt@sysfs_heartbeat_interval@precise@vecs0.html

  
#### Possible fixes ####

  * igt@gem_create@create-clear:
    - shard-skl:          [FAIL][67] ([i915#1888] / [i915#3160]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl8/igt@gem_create@create-clear.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl9/igt@gem_create@create-clear.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [FAIL][69] ([i915#2842]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-glk:          [FAIL][71] ([i915#2842]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-glk1/igt@gem_exec_fair@basic-throttle@rcs0.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-glk4/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_mmap_gtt@cpuset-big-copy-odd:
    - shard-iclb:         [FAIL][73] ([i915#2428]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy-odd.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-skl:          [INCOMPLETE][75] ([i915#198] / [i915#2405]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl7/igt@gem_workarounds@suspend-resume-fd.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl10/igt@gem_workarounds@suspend-resume-fd.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][77] ([i915#180]) -> [PASS][78] +2 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@flip-vs-cursor-toggle:
    - shard-skl:          [FAIL][79] ([i915#2346]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html

  * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled:
    - shard-glk:          [FAIL][81] ([i915#52] / [i915#54]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-glk3/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-glk4/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1:
    - shard-skl:          [FAIL][83] ([i915#2122]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl2/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl1/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-skl:          [FAIL][85] ([i915#1188]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_psr@psr2_primary_blt:
    - shard-iclb:         [SKIP][87] ([fdo#109441]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb6/igt@kms_psr@psr2_primary_blt.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-iclb2/igt@kms_psr@psr2_primary_blt.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-skl:          [INCOMPLETE][89] ([i915#198] / [i915#2828]) -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl2/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl9/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  
#### Warnings ####

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-iclb:         [FAIL][91] ([i915#2842]) -> [FAIL][92] ([i915#2852])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb4/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-iclb8/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area-3:
    - shard-iclb:         [SKIP][93] ([i915#658]) -> [SKIP][94] ([i915#2920]) +1 similar issue
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb6/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
    - shard-iclb:         [SKIP][95] ([i915#2920]) -> [SKIP][96] ([i915#658])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][97], [FAIL][98], [FAIL][99], [FAIL][100], [FAIL][101], [FAIL][102]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#602]) -> ([FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106], [FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2505] / [i915#3002])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl6/igt@runner@aborted.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl2/igt@runner@aborted.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl6/igt@runner@aborted.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl2/igt@runner@aborted.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl1/igt@runner@aborted.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl1/igt@runner@aborted.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl3/igt@runner@aborted.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl6/igt@runner@aborted.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl2/igt@runner@aborted.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl1/igt@runner@aborted.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl1/igt@runner@aborted.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl7/igt@runner@aborted.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl1/igt@runner@aborted.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl6/igt@runner@aborted.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-kbl2/igt@runner@aborted.html
    - shard-skl:          ([FAIL][112], [FAIL][113], [FAIL][114]) ([i915#1436] / [i915#2722] / [i915#3002]) -> ([FAIL][115], [FAIL][116], [FAIL][117]) ([i915#1436] / [i915#1814] / [i915#2029] / [i915#2722] / [i915#3002])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl10/igt@runner@aborted.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl4/igt@runner@aborted.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl6/igt@runner@aborted.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl6/igt@runner@aborted.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl2/igt@runner@aborted.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/shard-skl4/igt@runner@aborted.html

  
  [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
  [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
  [i915#2105]: https://gitlab.freedesktop.org/drm/intel/issues/2105
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
  [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
  [i915#2428]: https://gitlab.freedesktop.org/drm/intel/issues/2428
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
  [i915#2574]: https://gitlab.freedesktop.org/drm/intel/issues/2574
  [i915#2642]: https://gitlab.freedesktop.org/drm/intel/issues/2642
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
  [i915#2733]: https://gitlab.freedesktop.org/drm/intel/issues/2733
  [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
  [i915#2795]: https://gitlab.freedesktop.org/drm/intel/issues/2795
  [i915#2828]: https://gitlab.freedesktop.org/drm/intel/issues/2828
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#2852]: https://gitlab.freedesktop.org/drm/intel/issues/2852
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
  [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
  [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
  [i915#3160]: https://gitlab.freedesktop.org/drm/intel/issues/3160
  [i915#3296]: https://gitlab.freedesktop.org/drm/intel/issues/3296
  [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#602]: https://gitlab.freedesktop.org/drm/intel/issues/602
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_9993 -> Patchwork_19964

  CI-20190529: 20190529
  CI_DRM_9993: 629d3809e6d926c77ba5e9c5405e64eeba564560 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6072: 0a51f49df9f5ca535fc0206a27a6780de6b52320 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19964: 6766ff3915c2cde9f06f0804dbeed9afdcd4b7e6 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19964/index.html

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