From: Daniel Palmer <daniel@0x0f.com> To: soc@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: olof@lixom.net, arnd@kernel.org, w@1wt.eu, Daniel Palmer <daniel@0x0f.com> Subject: [RFC PATCH 1/2] ARM: mstar: Add header with macros for RIU register access Date: Thu, 22 Apr 2021 23:09:44 +0900 [thread overview] Message-ID: <20210422140945.4131092-2-daniel@0x0f.com> (raw) In-Reply-To: <20210422140945.4131092-1-daniel@0x0f.com> Registers connected to the CPU via "RIU" (Maybe Register Interface Unit) are 16bits wide with a 32bit stride. For IPs that came from 3rd parties that have natively 32bit registers they are annoyingly mapped with the 32bit register split into two 16bit registers. This means that any existing driver (i.e. the usb and ethernet) cannot be used as is and needs to use a special readl()/writel() to fix up the address of the register that needs to be accessed, do two readw()/writel()s and stitch the values together. To avoid having this code in every driver add a header with an implementation of readl()/writel() that patches over the insanity. Signed-off-by: Daniel Palmer <daniel@0x0f.com> --- MAINTAINERS | 1 + include/soc/mstar/riu.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 include/soc/mstar/riu.h diff --git a/MAINTAINERS b/MAINTAINERS index 19dc2eb0d93b..9600291e73a7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2155,6 +2155,7 @@ F: drivers/gpio/gpio-msc313.c F: drivers/pinctrl/pinctrl-msc313.c F: include/dt-bindings/clock/mstar-* F: include/dt-bindings/gpio/msc313-gpio.h +F: include/soc/mstar/ ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT M: Michael Petchkovsky <mkpetch@internode.on.net> diff --git a/include/soc/mstar/riu.h b/include/soc/mstar/riu.h new file mode 100644 index 000000000000..5aeea9c1e7eb --- /dev/null +++ b/include/soc/mstar/riu.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _SOC_MSTAR_RIU_H_ +#define _SOC_MSTAR_RIU_H_ + +#include <linux/io.h> + +static inline u32 riu_readl(__iomem void *base, unsigned int offset) +{ + __iomem void *reg = base + (offset * 2); + + return readw_relaxed(reg + 4) << 16 | readw_relaxed(reg); +} + +static inline void riu_writel(__iomem void *base, unsigned int offset, u32 value) +{ + __iomem void *reg = base + (offset * 2); + + /* + * Do not change this order. For EMAC at least + * the write order must be the lower half and then + * the upper half otherwise it doesn't work. + */ + writew_relaxed(value, reg); + writew_relaxed(value >> 16, reg + 4); +} + +#endif -- 2.31.0
WARNING: multiple messages have this Message-ID (diff)
From: Daniel Palmer <daniel@0x0f.com> To: soc@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: olof@lixom.net, arnd@kernel.org, w@1wt.eu, Daniel Palmer <daniel@0x0f.com> Subject: [RFC PATCH 1/2] ARM: mstar: Add header with macros for RIU register access Date: Thu, 22 Apr 2021 23:09:44 +0900 [thread overview] Message-ID: <20210422140945.4131092-2-daniel@0x0f.com> (raw) Message-ID: <20210422140944.-7X0gnPSQ19CtuO-gXUj-drZL10dW9HDlUVMV_EoUyw@z> (raw) In-Reply-To: <20210422140945.4131092-1-daniel@0x0f.com> Registers connected to the CPU via "RIU" (Maybe Register Interface Unit) are 16bits wide with a 32bit stride. For IPs that came from 3rd parties that have natively 32bit registers they are annoyingly mapped with the 32bit register split into two 16bit registers. This means that any existing driver (i.e. the usb and ethernet) cannot be used as is and needs to use a special readl()/writel() to fix up the address of the register that needs to be accessed, do two readw()/writel()s and stitch the values together. To avoid having this code in every driver add a header with an implementation of readl()/writel() that patches over the insanity. Signed-off-by: Daniel Palmer <daniel@0x0f.com> --- MAINTAINERS | 1 + include/soc/mstar/riu.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 include/soc/mstar/riu.h diff --git a/MAINTAINERS b/MAINTAINERS index 19dc2eb0d93b..9600291e73a7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2155,6 +2155,7 @@ F: drivers/gpio/gpio-msc313.c F: drivers/pinctrl/pinctrl-msc313.c F: include/dt-bindings/clock/mstar-* F: include/dt-bindings/gpio/msc313-gpio.h +F: include/soc/mstar/ ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT M: Michael Petchkovsky <mkpetch@internode.on.net> diff --git a/include/soc/mstar/riu.h b/include/soc/mstar/riu.h new file mode 100644 index 000000000000..5aeea9c1e7eb --- /dev/null +++ b/include/soc/mstar/riu.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _SOC_MSTAR_RIU_H_ +#define _SOC_MSTAR_RIU_H_ + +#include <linux/io.h> + +static inline u32 riu_readl(__iomem void *base, unsigned int offset) +{ + __iomem void *reg = base + (offset * 2); + + return readw_relaxed(reg + 4) << 16 | readw_relaxed(reg); +} + +static inline void riu_writel(__iomem void *base, unsigned int offset, u32 value) +{ + __iomem void *reg = base + (offset * 2); + + /* + * Do not change this order. For EMAC at least + * the write order must be the lower half and then + * the upper half otherwise it doesn't work. + */ + writew_relaxed(value, reg); + writew_relaxed(value >> 16, reg + 4); +} + +#endif -- 2.31.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-04-22 14:10 UTC|newest] Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-22 14:09 [RFC PATCH 0/2] ARM: mstar: Internal bus madness Daniel Palmer 2021-04-22 14:09 ` Daniel Palmer 2021-04-22 14:09 ` Daniel Palmer [this message] 2021-04-22 14:09 ` [RFC PATCH 1/2] ARM: mstar: Add header with macros for RIU register access Daniel Palmer 2021-04-23 13:47 ` Arnd Bergmann 2021-04-23 13:47 ` Arnd Bergmann 2021-04-23 14:02 ` Daniel Palmer 2021-04-23 14:02 ` Daniel Palmer 2021-04-23 14:02 ` Daniel Palmer 2021-04-23 19:52 ` Arnd Bergmann 2021-04-23 19:52 ` Arnd Bergmann 2021-04-22 14:09 ` [RFC PATCH 2/2] ARM: mstar: Add header with macros for XIU " Daniel Palmer 2021-04-22 14:09 ` Daniel Palmer
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