* Re: [RFC 6/8] media: v4l2-dv-timings: Add more CEA/CTA-861 video format timings
@ 2021-04-28 20:35 kernel test robot
0 siblings, 0 replies; 4+ messages in thread
From: kernel test robot @ 2021-04-28 20:35 UTC (permalink / raw)
To: kbuild
[-- Attachment #1: Type: text/plain, Size: 24848 bytes --]
CC: kbuild-all(a)lists.01.org
In-Reply-To: <821e6f76310316cd84c3be47581c92b001e5d4ca.1618937288.git.nelson.costa@synopsys.com>
References: <821e6f76310316cd84c3be47581c92b001e5d4ca.1618937288.git.nelson.costa@synopsys.com>
TO: Nelson Costa <Nelson.Costa@synopsys.com>
Hi Nelson,
[FYI, it's a private test report for your RFC patch.]
[auto build test WARNING on linuxtv-media/master]
[also build test WARNING on linux/master linus/master v5.12 next-20210428]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Nelson-Costa/Add-Synopsys-DesignWare-HDMI-RX-Controller-and-PHY-drivers/20210428-232828
base: git://linuxtv.org/media_tree.git master
:::::: branch date: 5 hours ago
:::::: commit date: 5 hours ago
config: m68k-randconfig-s032-20210428 (attached as .config)
compiler: m68k-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.3-341-g8af24329-dirty
# https://github.com/0day-ci/linux/commit/a0e7878053f9c2570d83cc3165c2ec58b8aa6526
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Nelson-Costa/Add-Synopsys-DesignWare-HDMI-RX-Controller-and-PHY-drivers/20210428-232828
git checkout a0e7878053f9c2570d83cc3165c2ec58b8aa6526
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' W=1 ARCH=m68k
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> drivers/media/v4l2-core/v4l2-dv-timings.c:252:9: sparse: sparse: decimal constant 2376000000 is between LONG_MAX and ULONG_MAX. For C99 that means long long, C90 compilers are very likely to produce unsigned long (and a warning) here
drivers/media/v4l2-core/v4l2-dv-timings.c:253:9: sparse: sparse: decimal constant 2376000000 is between LONG_MAX and ULONG_MAX. For C99 that means long long, C90 compilers are very likely to produce unsigned long (and a warning) here
drivers/media/v4l2-core/v4l2-dv-timings.c:254:9: sparse: sparse: decimal constant 2376000000 is between LONG_MAX and ULONG_MAX. For C99 that means long long, C90 compilers are very likely to produce unsigned long (and a warning) here
drivers/media/v4l2-core/v4l2-dv-timings.c:260:9: sparse: sparse: decimal constant 2376000000 is between LONG_MAX and ULONG_MAX. For C99 that means long long, C90 compilers are very likely to produce unsigned long (and a warning) here
drivers/media/v4l2-core/v4l2-dv-timings.c:261:9: sparse: sparse: decimal constant 2376000000 is between LONG_MAX and ULONG_MAX. For C99 that means long long, C90 compilers are very likely to produce unsigned long (and a warning) here
drivers/media/v4l2-core/v4l2-dv-timings.c:262:9: sparse: sparse: decimal constant 2376000000 is between LONG_MAX and ULONG_MAX. For C99 that means long long, C90 compilers are very likely to produce unsigned long (and a warning) here
drivers/media/v4l2-core/v4l2-dv-timings.c:268:9: sparse: sparse: decimal constant 2970000000 is between LONG_MAX and ULONG_MAX. For C99 that means long long, C90 compilers are very likely to produce unsigned long (and a warning) here
drivers/media/v4l2-core/v4l2-dv-timings.c:269:9: sparse: sparse: decimal constant 2970000000 is between LONG_MAX and ULONG_MAX. For C99 that means long long, C90 compilers are very likely to produce unsigned long (and a warning) here
drivers/media/v4l2-core/v4l2-dv-timings.c:270:9: sparse: sparse: decimal constant 2970000000 is between LONG_MAX and ULONG_MAX. For C99 that means long long, C90 compilers are very likely to produce unsigned long (and a warning) here
vim +252 drivers/media/v4l2-core/v4l2-dv-timings.c
c4885ada88e433 Hans Verkuil 2014-03-04 23
d1c65ad6a44b0f Hans Verkuil 2013-08-19 24 const struct v4l2_dv_timings v4l2_dv_timings_presets[] = {
b18787ed1ce32e Hans Verkuil 2013-07-29 25 V4L2_DV_BT_CEA_640X480P59_94,
b18787ed1ce32e Hans Verkuil 2013-07-29 26 V4L2_DV_BT_CEA_720X480I59_94,
b18787ed1ce32e Hans Verkuil 2013-07-29 27 V4L2_DV_BT_CEA_720X480P59_94,
b18787ed1ce32e Hans Verkuil 2013-07-29 28 V4L2_DV_BT_CEA_720X576I50,
b18787ed1ce32e Hans Verkuil 2013-07-29 29 V4L2_DV_BT_CEA_720X576P50,
b18787ed1ce32e Hans Verkuil 2013-07-29 30 V4L2_DV_BT_CEA_1280X720P24,
b18787ed1ce32e Hans Verkuil 2013-07-29 31 V4L2_DV_BT_CEA_1280X720P25,
b18787ed1ce32e Hans Verkuil 2013-07-29 32 V4L2_DV_BT_CEA_1280X720P30,
b18787ed1ce32e Hans Verkuil 2013-07-29 33 V4L2_DV_BT_CEA_1280X720P50,
b18787ed1ce32e Hans Verkuil 2013-07-29 34 V4L2_DV_BT_CEA_1280X720P60,
b18787ed1ce32e Hans Verkuil 2013-07-29 35 V4L2_DV_BT_CEA_1920X1080P24,
b18787ed1ce32e Hans Verkuil 2013-07-29 36 V4L2_DV_BT_CEA_1920X1080P25,
b18787ed1ce32e Hans Verkuil 2013-07-29 37 V4L2_DV_BT_CEA_1920X1080P30,
b18787ed1ce32e Hans Verkuil 2013-07-29 38 V4L2_DV_BT_CEA_1920X1080I50,
b18787ed1ce32e Hans Verkuil 2013-07-29 39 V4L2_DV_BT_CEA_1920X1080P50,
b18787ed1ce32e Hans Verkuil 2013-07-29 40 V4L2_DV_BT_CEA_1920X1080I60,
b18787ed1ce32e Hans Verkuil 2013-07-29 41 V4L2_DV_BT_CEA_1920X1080P60,
b18787ed1ce32e Hans Verkuil 2013-07-29 42 V4L2_DV_BT_DMT_640X350P85,
b18787ed1ce32e Hans Verkuil 2013-07-29 43 V4L2_DV_BT_DMT_640X400P85,
b18787ed1ce32e Hans Verkuil 2013-07-29 44 V4L2_DV_BT_DMT_720X400P85,
b18787ed1ce32e Hans Verkuil 2013-07-29 45 V4L2_DV_BT_DMT_640X480P72,
b18787ed1ce32e Hans Verkuil 2013-07-29 46 V4L2_DV_BT_DMT_640X480P75,
b18787ed1ce32e Hans Verkuil 2013-07-29 47 V4L2_DV_BT_DMT_640X480P85,
b18787ed1ce32e Hans Verkuil 2013-07-29 48 V4L2_DV_BT_DMT_800X600P56,
b18787ed1ce32e Hans Verkuil 2013-07-29 49 V4L2_DV_BT_DMT_800X600P60,
b18787ed1ce32e Hans Verkuil 2013-07-29 50 V4L2_DV_BT_DMT_800X600P72,
b18787ed1ce32e Hans Verkuil 2013-07-29 51 V4L2_DV_BT_DMT_800X600P75,
b18787ed1ce32e Hans Verkuil 2013-07-29 52 V4L2_DV_BT_DMT_800X600P85,
b18787ed1ce32e Hans Verkuil 2013-07-29 53 V4L2_DV_BT_DMT_800X600P120_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 54 V4L2_DV_BT_DMT_848X480P60,
b18787ed1ce32e Hans Verkuil 2013-07-29 55 V4L2_DV_BT_DMT_1024X768I43,
b18787ed1ce32e Hans Verkuil 2013-07-29 56 V4L2_DV_BT_DMT_1024X768P60,
b18787ed1ce32e Hans Verkuil 2013-07-29 57 V4L2_DV_BT_DMT_1024X768P70,
b18787ed1ce32e Hans Verkuil 2013-07-29 58 V4L2_DV_BT_DMT_1024X768P75,
b18787ed1ce32e Hans Verkuil 2013-07-29 59 V4L2_DV_BT_DMT_1024X768P85,
b18787ed1ce32e Hans Verkuil 2013-07-29 60 V4L2_DV_BT_DMT_1024X768P120_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 61 V4L2_DV_BT_DMT_1152X864P75,
b18787ed1ce32e Hans Verkuil 2013-07-29 62 V4L2_DV_BT_DMT_1280X768P60_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 63 V4L2_DV_BT_DMT_1280X768P60,
b18787ed1ce32e Hans Verkuil 2013-07-29 64 V4L2_DV_BT_DMT_1280X768P75,
b18787ed1ce32e Hans Verkuil 2013-07-29 65 V4L2_DV_BT_DMT_1280X768P85,
b18787ed1ce32e Hans Verkuil 2013-07-29 66 V4L2_DV_BT_DMT_1280X768P120_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 67 V4L2_DV_BT_DMT_1280X800P60_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 68 V4L2_DV_BT_DMT_1280X800P60,
b18787ed1ce32e Hans Verkuil 2013-07-29 69 V4L2_DV_BT_DMT_1280X800P75,
b18787ed1ce32e Hans Verkuil 2013-07-29 70 V4L2_DV_BT_DMT_1280X800P85,
b18787ed1ce32e Hans Verkuil 2013-07-29 71 V4L2_DV_BT_DMT_1280X800P120_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 72 V4L2_DV_BT_DMT_1280X960P60,
b18787ed1ce32e Hans Verkuil 2013-07-29 73 V4L2_DV_BT_DMT_1280X960P85,
b18787ed1ce32e Hans Verkuil 2013-07-29 74 V4L2_DV_BT_DMT_1280X960P120_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 75 V4L2_DV_BT_DMT_1280X1024P60,
b18787ed1ce32e Hans Verkuil 2013-07-29 76 V4L2_DV_BT_DMT_1280X1024P75,
b18787ed1ce32e Hans Verkuil 2013-07-29 77 V4L2_DV_BT_DMT_1280X1024P85,
b18787ed1ce32e Hans Verkuil 2013-07-29 78 V4L2_DV_BT_DMT_1280X1024P120_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 79 V4L2_DV_BT_DMT_1360X768P60,
b18787ed1ce32e Hans Verkuil 2013-07-29 80 V4L2_DV_BT_DMT_1360X768P120_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 81 V4L2_DV_BT_DMT_1366X768P60,
b18787ed1ce32e Hans Verkuil 2013-07-29 82 V4L2_DV_BT_DMT_1366X768P60_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 83 V4L2_DV_BT_DMT_1400X1050P60_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 84 V4L2_DV_BT_DMT_1400X1050P60,
b18787ed1ce32e Hans Verkuil 2013-07-29 85 V4L2_DV_BT_DMT_1400X1050P75,
b18787ed1ce32e Hans Verkuil 2013-07-29 86 V4L2_DV_BT_DMT_1400X1050P85,
b18787ed1ce32e Hans Verkuil 2013-07-29 87 V4L2_DV_BT_DMT_1400X1050P120_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 88 V4L2_DV_BT_DMT_1440X900P60_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 89 V4L2_DV_BT_DMT_1440X900P60,
b18787ed1ce32e Hans Verkuil 2013-07-29 90 V4L2_DV_BT_DMT_1440X900P75,
b18787ed1ce32e Hans Verkuil 2013-07-29 91 V4L2_DV_BT_DMT_1440X900P85,
b18787ed1ce32e Hans Verkuil 2013-07-29 92 V4L2_DV_BT_DMT_1440X900P120_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 93 V4L2_DV_BT_DMT_1600X900P60_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 94 V4L2_DV_BT_DMT_1600X1200P60,
b18787ed1ce32e Hans Verkuil 2013-07-29 95 V4L2_DV_BT_DMT_1600X1200P65,
b18787ed1ce32e Hans Verkuil 2013-07-29 96 V4L2_DV_BT_DMT_1600X1200P70,
b18787ed1ce32e Hans Verkuil 2013-07-29 97 V4L2_DV_BT_DMT_1600X1200P75,
b18787ed1ce32e Hans Verkuil 2013-07-29 98 V4L2_DV_BT_DMT_1600X1200P85,
b18787ed1ce32e Hans Verkuil 2013-07-29 99 V4L2_DV_BT_DMT_1600X1200P120_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 100 V4L2_DV_BT_DMT_1680X1050P60_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 101 V4L2_DV_BT_DMT_1680X1050P60,
b18787ed1ce32e Hans Verkuil 2013-07-29 102 V4L2_DV_BT_DMT_1680X1050P75,
b18787ed1ce32e Hans Verkuil 2013-07-29 103 V4L2_DV_BT_DMT_1680X1050P85,
b18787ed1ce32e Hans Verkuil 2013-07-29 104 V4L2_DV_BT_DMT_1680X1050P120_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 105 V4L2_DV_BT_DMT_1792X1344P60,
b18787ed1ce32e Hans Verkuil 2013-07-29 106 V4L2_DV_BT_DMT_1792X1344P75,
b18787ed1ce32e Hans Verkuil 2013-07-29 107 V4L2_DV_BT_DMT_1792X1344P120_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 108 V4L2_DV_BT_DMT_1856X1392P60,
b18787ed1ce32e Hans Verkuil 2013-07-29 109 V4L2_DV_BT_DMT_1856X1392P75,
b18787ed1ce32e Hans Verkuil 2013-07-29 110 V4L2_DV_BT_DMT_1856X1392P120_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 111 V4L2_DV_BT_DMT_1920X1200P60_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 112 V4L2_DV_BT_DMT_1920X1200P60,
b18787ed1ce32e Hans Verkuil 2013-07-29 113 V4L2_DV_BT_DMT_1920X1200P75,
b18787ed1ce32e Hans Verkuil 2013-07-29 114 V4L2_DV_BT_DMT_1920X1200P85,
b18787ed1ce32e Hans Verkuil 2013-07-29 115 V4L2_DV_BT_DMT_1920X1200P120_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 116 V4L2_DV_BT_DMT_1920X1440P60,
b18787ed1ce32e Hans Verkuil 2013-07-29 117 V4L2_DV_BT_DMT_1920X1440P75,
b18787ed1ce32e Hans Verkuil 2013-07-29 118 V4L2_DV_BT_DMT_1920X1440P120_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 119 V4L2_DV_BT_DMT_2048X1152P60_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 120 V4L2_DV_BT_DMT_2560X1600P60_RB,
b18787ed1ce32e Hans Verkuil 2013-07-29 121 V4L2_DV_BT_DMT_2560X1600P60,
b18787ed1ce32e Hans Verkuil 2013-07-29 122 V4L2_DV_BT_DMT_2560X1600P75,
b18787ed1ce32e Hans Verkuil 2013-07-29 123 V4L2_DV_BT_DMT_2560X1600P85,
b18787ed1ce32e Hans Verkuil 2013-07-29 124 V4L2_DV_BT_DMT_2560X1600P120_RB,
bc96f30c3b96cc Hans Verkuil 2014-04-08 125 V4L2_DV_BT_CEA_3840X2160P24,
bc96f30c3b96cc Hans Verkuil 2014-04-08 126 V4L2_DV_BT_CEA_3840X2160P25,
bc96f30c3b96cc Hans Verkuil 2014-04-08 127 V4L2_DV_BT_CEA_3840X2160P30,
bc96f30c3b96cc Hans Verkuil 2014-04-08 128 V4L2_DV_BT_CEA_3840X2160P50,
bc96f30c3b96cc Hans Verkuil 2014-04-08 129 V4L2_DV_BT_CEA_3840X2160P60,
bc96f30c3b96cc Hans Verkuil 2014-04-08 130 V4L2_DV_BT_CEA_4096X2160P24,
bc96f30c3b96cc Hans Verkuil 2014-04-08 131 V4L2_DV_BT_CEA_4096X2160P25,
bc96f30c3b96cc Hans Verkuil 2014-04-08 132 V4L2_DV_BT_CEA_4096X2160P30,
bc96f30c3b96cc Hans Verkuil 2014-04-08 133 V4L2_DV_BT_CEA_4096X2160P50,
bc96f30c3b96cc Hans Verkuil 2014-04-08 134 V4L2_DV_BT_DMT_4096X2160P59_94_RB,
bc96f30c3b96cc Hans Verkuil 2014-04-08 135 V4L2_DV_BT_CEA_4096X2160P60,
a0e7878053f9c2 Nelson Costa 2021-04-28 136 V4L2_DV_BT_CEA_720X480P60_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 137 V4L2_DV_BT_CEA_720X480I60_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 138 V4L2_DV_BT_CEA_720X240P60_VTOT262_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 139 V4L2_DV_BT_CEA_720X240P60_VTOT263_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 140 V4L2_DV_BT_CEA_720X240P60_VTOT262_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 141 V4L2_DV_BT_CEA_720X240P60_VTOT263_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 142 V4L2_DV_BT_CEA_2880X480I60_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 143 V4L2_DV_BT_CEA_2880X480I60_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 144 V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 145 V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 146 V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 147 V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 148 V4L2_DV_BT_CEA_1440X480P60_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 149 V4L2_DV_BT_CEA_1440X480P60_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 150 V4L2_DV_BT_CEA_720X576P50_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 151 V4L2_DV_BT_CEA_1920X1080I50_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 152 V4L2_DV_BT_CEA_720X576I50_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 153 V4L2_DV_BT_CEA_720X288P50_VTOT312_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 154 V4L2_DV_BT_CEA_720X288P50_VTOT313_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 155 V4L2_DV_BT_CEA_720X288P50_VTOT314_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 156 V4L2_DV_BT_CEA_720X288P50_VTOT312_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 157 V4L2_DV_BT_CEA_720X288P50_VTOT313_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 158 V4L2_DV_BT_CEA_720X288P50_VTOT314_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 159 V4L2_DV_BT_CEA_2880X576I50_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 160 V4L2_DV_BT_CEA_2880X576I50_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 161 V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 162 V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 163 V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 164 V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 165 V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 166 V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 167 V4L2_DV_BT_CEA_1440X576P50_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 168 V4L2_DV_BT_CEA_1440X576P50_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 169 V4L2_DV_BT_CEA_2880X480P60_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 170 V4L2_DV_BT_CEA_2880X480P60_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 171 V4L2_DV_BT_CEA_2880X576P50_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 172 V4L2_DV_BT_CEA_2880X576P50_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 173 V4L2_DV_BT_CEA_1920X1080I50_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 174 V4L2_DV_BT_CEA_1920X1080I100_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 175 V4L2_DV_BT_CEA_1280X720P100_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 176 V4L2_DV_BT_CEA_720X576P100_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 177 V4L2_DV_BT_CEA_720X576P100_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 178 V4L2_DV_BT_CEA_1440X576I100_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 179 V4L2_DV_BT_CEA_1440X576I100_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 180 V4L2_DV_BT_CEA_1920X1080I120_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 181 V4L2_DV_BT_CEA_1280X720P120_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 182 V4L2_DV_BT_CEA_720X480P120_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 183 V4L2_DV_BT_CEA_720X480P120_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 184 V4L2_DV_BT_CEA_1440X480I120_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 185 V4L2_DV_BT_CEA_1440X480I120_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 186 V4L2_DV_BT_CEA_720X576P200_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 187 V4L2_DV_BT_CEA_720X576P200_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 188 V4L2_DV_BT_CEA_1440X576I200_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 189 V4L2_DV_BT_CEA_1440X576I200_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 190 V4L2_DV_BT_CEA_720X480P240_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 191 V4L2_DV_BT_CEA_720X480P240_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 192 V4L2_DV_BT_CEA_1440X480I240_PA4_3,
a0e7878053f9c2 Nelson Costa 2021-04-28 193 V4L2_DV_BT_CEA_1440X480I240_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 194 V4L2_DV_BT_CEA_1920X1080P120_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 195 V4L2_DV_BT_CEA_1920X1080P100_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 196 V4L2_DV_BT_CEA_1280X720P24_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 197 V4L2_DV_BT_CEA_1280X720P25_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 198 V4L2_DV_BT_CEA_1280X720P30_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 199 V4L2_DV_BT_CEA_1280X720P50_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 200 V4L2_DV_BT_CEA_1280X720P60_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 201 V4L2_DV_BT_CEA_1280X720P100_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 202 V4L2_DV_BT_CEA_1280X720P120_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 203 V4L2_DV_BT_CEA_1920X1080P24_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 204 V4L2_DV_BT_CEA_1920X1080P25_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 205 V4L2_DV_BT_CEA_1920X1080P30_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 206 V4L2_DV_BT_CEA_1920X1080P50_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 207 V4L2_DV_BT_CEA_1920X1080P60_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 208 V4L2_DV_BT_CEA_1920X1080P100_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 209 V4L2_DV_BT_CEA_1920X1080P120_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 210 V4L2_DV_BT_CEA_1680X720P24_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 211 V4L2_DV_BT_CEA_1680X720P25_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 212 V4L2_DV_BT_CEA_1680X720P30_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 213 V4L2_DV_BT_CEA_1680X720P50_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 214 V4L2_DV_BT_CEA_1680X720P60_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 215 V4L2_DV_BT_CEA_1680X720P100_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 216 V4L2_DV_BT_CEA_1680X720P120_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 217 V4L2_DV_BT_CEA_2560X1080P24_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 218 V4L2_DV_BT_CEA_2560X1080P25_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 219 V4L2_DV_BT_CEA_2560X1080P30_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 220 V4L2_DV_BT_CEA_2560X1080P50_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 221 V4L2_DV_BT_CEA_2560X1080P60_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 222 V4L2_DV_BT_CEA_2560X1080P100_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 223 V4L2_DV_BT_CEA_2560X1080P120_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 224 V4L2_DV_BT_CEA_3840X2160P24_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 225 V4L2_DV_BT_CEA_3840X2160P25_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 226 V4L2_DV_BT_CEA_3840X2160P30_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 227 V4L2_DV_BT_CEA_3840X2160P50_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 228 V4L2_DV_BT_CEA_3840X2160P60_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 229 V4L2_DV_BT_CEA_1280X720P48_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 230 V4L2_DV_BT_CEA_1280X720P48_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 231 V4L2_DV_BT_CEA_1680X720P48_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 232 V4L2_DV_BT_CEA_1920X1080P48_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 233 V4L2_DV_BT_CEA_1920X1080P48_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 234 V4L2_DV_BT_CEA_3840X2160P48_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 235 V4L2_DV_BT_CEA_4096X2160P48_PA256_135,
a0e7878053f9c2 Nelson Costa 2021-04-28 236 V4L2_DV_BT_CEA_3840X2160P48_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 237 V4L2_DV_BT_CEA_3840X2160P100_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 238 V4L2_DV_BT_CEA_3840X2160P120_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 239 V4L2_DV_BT_CEA_3840X2160P100_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 240 V4L2_DV_BT_CEA_3840X2160P120_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 241 V4L2_DV_BT_CEA_5120X2160P24_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 242 V4L2_DV_BT_CEA_5120X2160P25_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 243 V4L2_DV_BT_CEA_5120X2160P30_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 244 V4L2_DV_BT_CEA_5120X2160P48_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 245 V4L2_DV_BT_CEA_5120X2160P50_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 246 V4L2_DV_BT_CEA_5120X2160P60_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 247 V4L2_DV_BT_CEA_5120X2160P100_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 248 V4L2_DV_BT_CEA_5120X2160P120_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 249 V4L2_DV_BT_CEA_7680X4320P24_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 250 V4L2_DV_BT_CEA_7680X4320P25_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 251 V4L2_DV_BT_CEA_7680X4320P30_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 @252 V4L2_DV_BT_CEA_7680X4320P48_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 253 V4L2_DV_BT_CEA_7680X4320P50_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 254 V4L2_DV_BT_CEA_7680X4320P60_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 255 V4L2_DV_BT_CEA_7680X4320P100_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 256 V4L2_DV_BT_CEA_7680X4320P120_PA16_9,
a0e7878053f9c2 Nelson Costa 2021-04-28 257 V4L2_DV_BT_CEA_7680X4320P24_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 258 V4L2_DV_BT_CEA_7680X4320P25_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 259 V4L2_DV_BT_CEA_7680X4320P30_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 260 V4L2_DV_BT_CEA_7680X4320P48_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 261 V4L2_DV_BT_CEA_7680X4320P50_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 262 V4L2_DV_BT_CEA_7680X4320P60_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 263 V4L2_DV_BT_CEA_7680X4320P100_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 264 V4L2_DV_BT_CEA_7680X4320P120_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 265 V4L2_DV_BT_CEA_10240X4320P24_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 266 V4L2_DV_BT_CEA_10240X4320P25_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 267 V4L2_DV_BT_CEA_10240X4320P30_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 268 V4L2_DV_BT_CEA_10240X4320P48_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 269 V4L2_DV_BT_CEA_10240X4320P50_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 270 V4L2_DV_BT_CEA_10240X4320P60_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 271 V4L2_DV_BT_CEA_10240X4320P100_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 272 V4L2_DV_BT_CEA_10240X4320P120_PA64_27,
a0e7878053f9c2 Nelson Costa 2021-04-28 273 V4L2_DV_BT_CEA_4096X2160P100_PA256_135,
a0e7878053f9c2 Nelson Costa 2021-04-28 274 V4L2_DV_BT_CEA_4096X2160P120_PA256_135,
d1c65ad6a44b0f Hans Verkuil 2013-08-19 275 { }
b18787ed1ce32e Hans Verkuil 2013-07-29 276 };
d1c65ad6a44b0f Hans Verkuil 2013-08-19 277 EXPORT_SYMBOL_GPL(v4l2_dv_timings_presets);
b18787ed1ce32e Hans Verkuil 2013-07-29 278
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 14938 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [RFC 6/8] media: v4l2-dv-timings: Add more CEA/CTA-861 video format timings
2021-04-28 15:25 ` [RFC 6/8] media: v4l2-dv-timings: Add more CEA/CTA-861 video format timings Nelson Costa
2021-04-28 21:00 ` kernel test robot
@ 2021-04-28 23:13 ` kernel test robot
1 sibling, 0 replies; 4+ messages in thread
From: kernel test robot @ 2021-04-28 23:13 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 14229 bytes --]
Hi Nelson,
[FYI, it's a private test report for your RFC patch.]
[auto build test WARNING on linuxtv-media/master]
[also build test WARNING on linux/master linus/master v5.12 next-20210428]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Nelson-Costa/Add-Synopsys-DesignWare-HDMI-RX-Controller-and-PHY-drivers/20210428-232828
base: git://linuxtv.org/media_tree.git master
config: i386-randconfig-p001-20210428 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# https://github.com/0day-ci/linux/commit/a0e7878053f9c2570d83cc3165c2ec58b8aa6526
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Nelson-Costa/Add-Synopsys-DesignWare-HDMI-RX-Controller-and-PHY-drivers/20210428-232828
git checkout a0e7878053f9c2570d83cc3165c2ec58b8aa6526
# save the attached .config to linux build tree
make W=1 W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/media/v4l2-core/v4l2-dv-timings.c:252:2: warning: this decimal constant is unsigned only in ISO C90
252 | V4L2_DV_BT_CEA_7680X4320P48_PA16_9,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/media/v4l2-core/v4l2-dv-timings.c:253:2: warning: this decimal constant is unsigned only in ISO C90
253 | V4L2_DV_BT_CEA_7680X4320P50_PA16_9,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/media/v4l2-core/v4l2-dv-timings.c:254:2: warning: this decimal constant is unsigned only in ISO C90
254 | V4L2_DV_BT_CEA_7680X4320P60_PA16_9,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/media/v4l2-core/v4l2-dv-timings.c:260:2: warning: this decimal constant is unsigned only in ISO C90
260 | V4L2_DV_BT_CEA_7680X4320P48_PA64_27,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/media/v4l2-core/v4l2-dv-timings.c:261:2: warning: this decimal constant is unsigned only in ISO C90
261 | V4L2_DV_BT_CEA_7680X4320P50_PA64_27,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/media/v4l2-core/v4l2-dv-timings.c:262:2: warning: this decimal constant is unsigned only in ISO C90
262 | V4L2_DV_BT_CEA_7680X4320P60_PA64_27,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/media/v4l2-core/v4l2-dv-timings.c:268:2: warning: this decimal constant is unsigned only in ISO C90
268 | V4L2_DV_BT_CEA_10240X4320P48_PA64_27,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/media/v4l2-core/v4l2-dv-timings.c:269:2: warning: this decimal constant is unsigned only in ISO C90
269 | V4L2_DV_BT_CEA_10240X4320P50_PA64_27,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/media/v4l2-core/v4l2-dv-timings.c:270:2: warning: this decimal constant is unsigned only in ISO C90
270 | V4L2_DV_BT_CEA_10240X4320P60_PA64_27,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
vim +252 drivers/media/v4l2-core/v4l2-dv-timings.c
23
24 const struct v4l2_dv_timings v4l2_dv_timings_presets[] = {
25 V4L2_DV_BT_CEA_640X480P59_94,
26 V4L2_DV_BT_CEA_720X480I59_94,
27 V4L2_DV_BT_CEA_720X480P59_94,
28 V4L2_DV_BT_CEA_720X576I50,
29 V4L2_DV_BT_CEA_720X576P50,
30 V4L2_DV_BT_CEA_1280X720P24,
31 V4L2_DV_BT_CEA_1280X720P25,
32 V4L2_DV_BT_CEA_1280X720P30,
33 V4L2_DV_BT_CEA_1280X720P50,
34 V4L2_DV_BT_CEA_1280X720P60,
35 V4L2_DV_BT_CEA_1920X1080P24,
36 V4L2_DV_BT_CEA_1920X1080P25,
37 V4L2_DV_BT_CEA_1920X1080P30,
38 V4L2_DV_BT_CEA_1920X1080I50,
39 V4L2_DV_BT_CEA_1920X1080P50,
40 V4L2_DV_BT_CEA_1920X1080I60,
41 V4L2_DV_BT_CEA_1920X1080P60,
42 V4L2_DV_BT_DMT_640X350P85,
43 V4L2_DV_BT_DMT_640X400P85,
44 V4L2_DV_BT_DMT_720X400P85,
45 V4L2_DV_BT_DMT_640X480P72,
46 V4L2_DV_BT_DMT_640X480P75,
47 V4L2_DV_BT_DMT_640X480P85,
48 V4L2_DV_BT_DMT_800X600P56,
49 V4L2_DV_BT_DMT_800X600P60,
50 V4L2_DV_BT_DMT_800X600P72,
51 V4L2_DV_BT_DMT_800X600P75,
52 V4L2_DV_BT_DMT_800X600P85,
53 V4L2_DV_BT_DMT_800X600P120_RB,
54 V4L2_DV_BT_DMT_848X480P60,
55 V4L2_DV_BT_DMT_1024X768I43,
56 V4L2_DV_BT_DMT_1024X768P60,
57 V4L2_DV_BT_DMT_1024X768P70,
58 V4L2_DV_BT_DMT_1024X768P75,
59 V4L2_DV_BT_DMT_1024X768P85,
60 V4L2_DV_BT_DMT_1024X768P120_RB,
61 V4L2_DV_BT_DMT_1152X864P75,
62 V4L2_DV_BT_DMT_1280X768P60_RB,
63 V4L2_DV_BT_DMT_1280X768P60,
64 V4L2_DV_BT_DMT_1280X768P75,
65 V4L2_DV_BT_DMT_1280X768P85,
66 V4L2_DV_BT_DMT_1280X768P120_RB,
67 V4L2_DV_BT_DMT_1280X800P60_RB,
68 V4L2_DV_BT_DMT_1280X800P60,
69 V4L2_DV_BT_DMT_1280X800P75,
70 V4L2_DV_BT_DMT_1280X800P85,
71 V4L2_DV_BT_DMT_1280X800P120_RB,
72 V4L2_DV_BT_DMT_1280X960P60,
73 V4L2_DV_BT_DMT_1280X960P85,
74 V4L2_DV_BT_DMT_1280X960P120_RB,
75 V4L2_DV_BT_DMT_1280X1024P60,
76 V4L2_DV_BT_DMT_1280X1024P75,
77 V4L2_DV_BT_DMT_1280X1024P85,
78 V4L2_DV_BT_DMT_1280X1024P120_RB,
79 V4L2_DV_BT_DMT_1360X768P60,
80 V4L2_DV_BT_DMT_1360X768P120_RB,
81 V4L2_DV_BT_DMT_1366X768P60,
82 V4L2_DV_BT_DMT_1366X768P60_RB,
83 V4L2_DV_BT_DMT_1400X1050P60_RB,
84 V4L2_DV_BT_DMT_1400X1050P60,
85 V4L2_DV_BT_DMT_1400X1050P75,
86 V4L2_DV_BT_DMT_1400X1050P85,
87 V4L2_DV_BT_DMT_1400X1050P120_RB,
88 V4L2_DV_BT_DMT_1440X900P60_RB,
89 V4L2_DV_BT_DMT_1440X900P60,
90 V4L2_DV_BT_DMT_1440X900P75,
91 V4L2_DV_BT_DMT_1440X900P85,
92 V4L2_DV_BT_DMT_1440X900P120_RB,
93 V4L2_DV_BT_DMT_1600X900P60_RB,
94 V4L2_DV_BT_DMT_1600X1200P60,
95 V4L2_DV_BT_DMT_1600X1200P65,
96 V4L2_DV_BT_DMT_1600X1200P70,
97 V4L2_DV_BT_DMT_1600X1200P75,
98 V4L2_DV_BT_DMT_1600X1200P85,
99 V4L2_DV_BT_DMT_1600X1200P120_RB,
100 V4L2_DV_BT_DMT_1680X1050P60_RB,
101 V4L2_DV_BT_DMT_1680X1050P60,
102 V4L2_DV_BT_DMT_1680X1050P75,
103 V4L2_DV_BT_DMT_1680X1050P85,
104 V4L2_DV_BT_DMT_1680X1050P120_RB,
105 V4L2_DV_BT_DMT_1792X1344P60,
106 V4L2_DV_BT_DMT_1792X1344P75,
107 V4L2_DV_BT_DMT_1792X1344P120_RB,
108 V4L2_DV_BT_DMT_1856X1392P60,
109 V4L2_DV_BT_DMT_1856X1392P75,
110 V4L2_DV_BT_DMT_1856X1392P120_RB,
111 V4L2_DV_BT_DMT_1920X1200P60_RB,
112 V4L2_DV_BT_DMT_1920X1200P60,
113 V4L2_DV_BT_DMT_1920X1200P75,
114 V4L2_DV_BT_DMT_1920X1200P85,
115 V4L2_DV_BT_DMT_1920X1200P120_RB,
116 V4L2_DV_BT_DMT_1920X1440P60,
117 V4L2_DV_BT_DMT_1920X1440P75,
118 V4L2_DV_BT_DMT_1920X1440P120_RB,
119 V4L2_DV_BT_DMT_2048X1152P60_RB,
120 V4L2_DV_BT_DMT_2560X1600P60_RB,
121 V4L2_DV_BT_DMT_2560X1600P60,
122 V4L2_DV_BT_DMT_2560X1600P75,
123 V4L2_DV_BT_DMT_2560X1600P85,
124 V4L2_DV_BT_DMT_2560X1600P120_RB,
125 V4L2_DV_BT_CEA_3840X2160P24,
126 V4L2_DV_BT_CEA_3840X2160P25,
127 V4L2_DV_BT_CEA_3840X2160P30,
128 V4L2_DV_BT_CEA_3840X2160P50,
129 V4L2_DV_BT_CEA_3840X2160P60,
130 V4L2_DV_BT_CEA_4096X2160P24,
131 V4L2_DV_BT_CEA_4096X2160P25,
132 V4L2_DV_BT_CEA_4096X2160P30,
133 V4L2_DV_BT_CEA_4096X2160P50,
134 V4L2_DV_BT_DMT_4096X2160P59_94_RB,
135 V4L2_DV_BT_CEA_4096X2160P60,
136 V4L2_DV_BT_CEA_720X480P60_PA16_9,
137 V4L2_DV_BT_CEA_720X480I60_PA16_9,
138 V4L2_DV_BT_CEA_720X240P60_VTOT262_PA4_3,
139 V4L2_DV_BT_CEA_720X240P60_VTOT263_PA4_3,
140 V4L2_DV_BT_CEA_720X240P60_VTOT262_PA16_9,
141 V4L2_DV_BT_CEA_720X240P60_VTOT263_PA16_9,
142 V4L2_DV_BT_CEA_2880X480I60_PA4_3,
143 V4L2_DV_BT_CEA_2880X480I60_PA16_9,
144 V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA4_3,
145 V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA4_3,
146 V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA16_9,
147 V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA16_9,
148 V4L2_DV_BT_CEA_1440X480P60_PA4_3,
149 V4L2_DV_BT_CEA_1440X480P60_PA16_9,
150 V4L2_DV_BT_CEA_720X576P50_PA16_9,
151 V4L2_DV_BT_CEA_1920X1080I50_PA16_9,
152 V4L2_DV_BT_CEA_720X576I50_PA16_9,
153 V4L2_DV_BT_CEA_720X288P50_VTOT312_PA4_3,
154 V4L2_DV_BT_CEA_720X288P50_VTOT313_PA4_3,
155 V4L2_DV_BT_CEA_720X288P50_VTOT314_PA4_3,
156 V4L2_DV_BT_CEA_720X288P50_VTOT312_PA16_9,
157 V4L2_DV_BT_CEA_720X288P50_VTOT313_PA16_9,
158 V4L2_DV_BT_CEA_720X288P50_VTOT314_PA16_9,
159 V4L2_DV_BT_CEA_2880X576I50_PA4_3,
160 V4L2_DV_BT_CEA_2880X576I50_PA16_9,
161 V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA4_3,
162 V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA4_3,
163 V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA4_3,
164 V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA16_9,
165 V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA16_9,
166 V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA16_9,
167 V4L2_DV_BT_CEA_1440X576P50_PA4_3,
168 V4L2_DV_BT_CEA_1440X576P50_PA16_9,
169 V4L2_DV_BT_CEA_2880X480P60_PA4_3,
170 V4L2_DV_BT_CEA_2880X480P60_PA16_9,
171 V4L2_DV_BT_CEA_2880X576P50_PA4_3,
172 V4L2_DV_BT_CEA_2880X576P50_PA16_9,
173 V4L2_DV_BT_CEA_1920X1080I50_PA16_9,
174 V4L2_DV_BT_CEA_1920X1080I100_PA16_9,
175 V4L2_DV_BT_CEA_1280X720P100_PA16_9,
176 V4L2_DV_BT_CEA_720X576P100_PA4_3,
177 V4L2_DV_BT_CEA_720X576P100_PA16_9,
178 V4L2_DV_BT_CEA_1440X576I100_PA4_3,
179 V4L2_DV_BT_CEA_1440X576I100_PA16_9,
180 V4L2_DV_BT_CEA_1920X1080I120_PA16_9,
181 V4L2_DV_BT_CEA_1280X720P120_PA16_9,
182 V4L2_DV_BT_CEA_720X480P120_PA4_3,
183 V4L2_DV_BT_CEA_720X480P120_PA16_9,
184 V4L2_DV_BT_CEA_1440X480I120_PA4_3,
185 V4L2_DV_BT_CEA_1440X480I120_PA16_9,
186 V4L2_DV_BT_CEA_720X576P200_PA4_3,
187 V4L2_DV_BT_CEA_720X576P200_PA16_9,
188 V4L2_DV_BT_CEA_1440X576I200_PA4_3,
189 V4L2_DV_BT_CEA_1440X576I200_PA16_9,
190 V4L2_DV_BT_CEA_720X480P240_PA4_3,
191 V4L2_DV_BT_CEA_720X480P240_PA16_9,
192 V4L2_DV_BT_CEA_1440X480I240_PA4_3,
193 V4L2_DV_BT_CEA_1440X480I240_PA16_9,
194 V4L2_DV_BT_CEA_1920X1080P120_PA16_9,
195 V4L2_DV_BT_CEA_1920X1080P100_PA16_9,
196 V4L2_DV_BT_CEA_1280X720P24_PA64_27,
197 V4L2_DV_BT_CEA_1280X720P25_PA64_27,
198 V4L2_DV_BT_CEA_1280X720P30_PA64_27,
199 V4L2_DV_BT_CEA_1280X720P50_PA64_27,
200 V4L2_DV_BT_CEA_1280X720P60_PA64_27,
201 V4L2_DV_BT_CEA_1280X720P100_PA64_27,
202 V4L2_DV_BT_CEA_1280X720P120_PA64_27,
203 V4L2_DV_BT_CEA_1920X1080P24_PA64_27,
204 V4L2_DV_BT_CEA_1920X1080P25_PA64_27,
205 V4L2_DV_BT_CEA_1920X1080P30_PA64_27,
206 V4L2_DV_BT_CEA_1920X1080P50_PA64_27,
207 V4L2_DV_BT_CEA_1920X1080P60_PA64_27,
208 V4L2_DV_BT_CEA_1920X1080P100_PA64_27,
209 V4L2_DV_BT_CEA_1920X1080P120_PA64_27,
210 V4L2_DV_BT_CEA_1680X720P24_PA64_27,
211 V4L2_DV_BT_CEA_1680X720P25_PA64_27,
212 V4L2_DV_BT_CEA_1680X720P30_PA64_27,
213 V4L2_DV_BT_CEA_1680X720P50_PA64_27,
214 V4L2_DV_BT_CEA_1680X720P60_PA64_27,
215 V4L2_DV_BT_CEA_1680X720P100_PA64_27,
216 V4L2_DV_BT_CEA_1680X720P120_PA64_27,
217 V4L2_DV_BT_CEA_2560X1080P24_PA64_27,
218 V4L2_DV_BT_CEA_2560X1080P25_PA64_27,
219 V4L2_DV_BT_CEA_2560X1080P30_PA64_27,
220 V4L2_DV_BT_CEA_2560X1080P50_PA64_27,
221 V4L2_DV_BT_CEA_2560X1080P60_PA64_27,
222 V4L2_DV_BT_CEA_2560X1080P100_PA64_27,
223 V4L2_DV_BT_CEA_2560X1080P120_PA64_27,
224 V4L2_DV_BT_CEA_3840X2160P24_PA64_27,
225 V4L2_DV_BT_CEA_3840X2160P25_PA64_27,
226 V4L2_DV_BT_CEA_3840X2160P30_PA64_27,
227 V4L2_DV_BT_CEA_3840X2160P50_PA64_27,
228 V4L2_DV_BT_CEA_3840X2160P60_PA64_27,
229 V4L2_DV_BT_CEA_1280X720P48_PA16_9,
230 V4L2_DV_BT_CEA_1280X720P48_PA64_27,
231 V4L2_DV_BT_CEA_1680X720P48_PA64_27,
232 V4L2_DV_BT_CEA_1920X1080P48_PA16_9,
233 V4L2_DV_BT_CEA_1920X1080P48_PA64_27,
234 V4L2_DV_BT_CEA_3840X2160P48_PA16_9,
235 V4L2_DV_BT_CEA_4096X2160P48_PA256_135,
236 V4L2_DV_BT_CEA_3840X2160P48_PA64_27,
237 V4L2_DV_BT_CEA_3840X2160P100_PA16_9,
238 V4L2_DV_BT_CEA_3840X2160P120_PA16_9,
239 V4L2_DV_BT_CEA_3840X2160P100_PA64_27,
240 V4L2_DV_BT_CEA_3840X2160P120_PA64_27,
241 V4L2_DV_BT_CEA_5120X2160P24_PA64_27,
242 V4L2_DV_BT_CEA_5120X2160P25_PA64_27,
243 V4L2_DV_BT_CEA_5120X2160P30_PA64_27,
244 V4L2_DV_BT_CEA_5120X2160P48_PA64_27,
245 V4L2_DV_BT_CEA_5120X2160P50_PA64_27,
246 V4L2_DV_BT_CEA_5120X2160P60_PA64_27,
247 V4L2_DV_BT_CEA_5120X2160P100_PA64_27,
248 V4L2_DV_BT_CEA_5120X2160P120_PA64_27,
249 V4L2_DV_BT_CEA_7680X4320P24_PA16_9,
250 V4L2_DV_BT_CEA_7680X4320P25_PA16_9,
251 V4L2_DV_BT_CEA_7680X4320P30_PA16_9,
> 252 V4L2_DV_BT_CEA_7680X4320P48_PA16_9,
253 V4L2_DV_BT_CEA_7680X4320P50_PA16_9,
254 V4L2_DV_BT_CEA_7680X4320P60_PA16_9,
255 V4L2_DV_BT_CEA_7680X4320P100_PA16_9,
256 V4L2_DV_BT_CEA_7680X4320P120_PA16_9,
257 V4L2_DV_BT_CEA_7680X4320P24_PA64_27,
258 V4L2_DV_BT_CEA_7680X4320P25_PA64_27,
259 V4L2_DV_BT_CEA_7680X4320P30_PA64_27,
260 V4L2_DV_BT_CEA_7680X4320P48_PA64_27,
261 V4L2_DV_BT_CEA_7680X4320P50_PA64_27,
262 V4L2_DV_BT_CEA_7680X4320P60_PA64_27,
263 V4L2_DV_BT_CEA_7680X4320P100_PA64_27,
264 V4L2_DV_BT_CEA_7680X4320P120_PA64_27,
265 V4L2_DV_BT_CEA_10240X4320P24_PA64_27,
266 V4L2_DV_BT_CEA_10240X4320P25_PA64_27,
267 V4L2_DV_BT_CEA_10240X4320P30_PA64_27,
268 V4L2_DV_BT_CEA_10240X4320P48_PA64_27,
269 V4L2_DV_BT_CEA_10240X4320P50_PA64_27,
270 V4L2_DV_BT_CEA_10240X4320P60_PA64_27,
271 V4L2_DV_BT_CEA_10240X4320P100_PA64_27,
272 V4L2_DV_BT_CEA_10240X4320P120_PA64_27,
273 V4L2_DV_BT_CEA_4096X2160P100_PA256_135,
274 V4L2_DV_BT_CEA_4096X2160P120_PA256_135,
275 { }
276 };
277 EXPORT_SYMBOL_GPL(v4l2_dv_timings_presets);
278
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 42453 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [RFC 6/8] media: v4l2-dv-timings: Add more CEA/CTA-861 video format timings
2021-04-28 15:25 ` [RFC 6/8] media: v4l2-dv-timings: Add more CEA/CTA-861 video format timings Nelson Costa
@ 2021-04-28 21:00 ` kernel test robot
2021-04-28 23:13 ` kernel test robot
1 sibling, 0 replies; 4+ messages in thread
From: kernel test robot @ 2021-04-28 21:00 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 17297 bytes --]
Hi Nelson,
[FYI, it's a private test report for your RFC patch.]
[auto build test WARNING on linuxtv-media/master]
[also build test WARNING on linux/master linus/master v5.12 next-20210428]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Nelson-Costa/Add-Synopsys-DesignWare-HDMI-RX-Controller-and-PHY-drivers/20210428-232828
base: git://linuxtv.org/media_tree.git master
config: powerpc64-randconfig-r034-20210428 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 87fc97169e7901dfe56ca0da0d92da0c02d2ef48)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install powerpc64 cross compiling tool for clang build
# apt-get install binutils-powerpc64-linux-gnu
# https://github.com/0day-ci/linux/commit/a0e7878053f9c2570d83cc3165c2ec58b8aa6526
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Nelson-Costa/Add-Synopsys-DesignWare-HDMI-RX-Controller-and-PHY-drivers/20210428-232828
git checkout a0e7878053f9c2570d83cc3165c2ec58b8aa6526
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=powerpc64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/media/v4l2-core/v4l2-dv-timings.c:252:2: warning: integer literal is too large to be represented in type 'long', interpreting as 'unsigned long' per C89; this literal will have type 'long long' in C99 onwards [-Wc99-compat]
V4L2_DV_BT_CEA_7680X4320P48_PA16_9,
^
include/uapi/linux/v4l2-dv-timings.h:1632:3: note: expanded from macro 'V4L2_DV_BT_CEA_7680X4320P48_PA16_9'
2376000000, 2552, 176, 592, 16, 20, 144, 0, 0, 0, \
^
drivers/media/v4l2-core/v4l2-dv-timings.c:253:2: warning: integer literal is too large to be represented in type 'long', interpreting as 'unsigned long' per C89; this literal will have type 'long long' in C99 onwards [-Wc99-compat]
V4L2_DV_BT_CEA_7680X4320P50_PA16_9,
^
include/uapi/linux/v4l2-dv-timings.h:1644:3: note: expanded from macro 'V4L2_DV_BT_CEA_7680X4320P50_PA16_9'
2376000000, 2352, 176, 592, 16, 20, 44, 0, 0, 0, \
^
drivers/media/v4l2-core/v4l2-dv-timings.c:254:2: warning: integer literal is too large to be represented in type 'long', interpreting as 'unsigned long' per C89; this literal will have type 'long long' in C99 onwards [-Wc99-compat]
V4L2_DV_BT_CEA_7680X4320P60_PA16_9,
^
include/uapi/linux/v4l2-dv-timings.h:1655:3: note: expanded from macro 'V4L2_DV_BT_CEA_7680X4320P60_PA16_9'
2376000000, 552, 176, 592, 16, 20, 44, 0, 0, 0, \
^
drivers/media/v4l2-core/v4l2-dv-timings.c:260:2: warning: integer literal is too large to be represented in type 'long', interpreting as 'unsigned long' per C89; this literal will have type 'long long' in C99 onwards [-Wc99-compat]
V4L2_DV_BT_CEA_7680X4320P48_PA64_27,
^
include/uapi/linux/v4l2-dv-timings.h:1725:3: note: expanded from macro 'V4L2_DV_BT_CEA_7680X4320P48_PA64_27'
2376000000, 2552, 176, 592, 16, 20, 144, 0, 0, 0, \
^
drivers/media/v4l2-core/v4l2-dv-timings.c:261:2: warning: integer literal is too large to be represented in type 'long', interpreting as 'unsigned long' per C89; this literal will have type 'long long' in C99 onwards [-Wc99-compat]
V4L2_DV_BT_CEA_7680X4320P50_PA64_27,
^
include/uapi/linux/v4l2-dv-timings.h:1737:3: note: expanded from macro 'V4L2_DV_BT_CEA_7680X4320P50_PA64_27'
2376000000, 2352, 176, 592, 16, 20, 44, 0, 0, 0, \
^
drivers/media/v4l2-core/v4l2-dv-timings.c:262:2: warning: integer literal is too large to be represented in type 'long', interpreting as 'unsigned long' per C89; this literal will have type 'long long' in C99 onwards [-Wc99-compat]
V4L2_DV_BT_CEA_7680X4320P60_PA64_27,
^
include/uapi/linux/v4l2-dv-timings.h:1748:3: note: expanded from macro 'V4L2_DV_BT_CEA_7680X4320P60_PA64_27'
2376000000, 552, 176, 592, 16, 20, 44, 0, 0, 0, \
^
drivers/media/v4l2-core/v4l2-dv-timings.c:268:2: warning: integer literal is too large to be represented in type 'long', interpreting as 'unsigned long' per C89; this literal will have type 'long long' in C99 onwards [-Wc99-compat]
V4L2_DV_BT_CEA_10240X4320P48_PA64_27,
^
include/uapi/linux/v4l2-dv-timings.h:1818:3: note: expanded from macro 'V4L2_DV_BT_CEA_10240X4320P48_PA64_27'
2970000000, 1492, 176, 592, 16, 20, 594, 0, 0, 0, \
^
drivers/media/v4l2-core/v4l2-dv-timings.c:269:2: warning: integer literal is too large to be represented in type 'long', interpreting as 'unsigned long' per C89; this literal will have type 'long long' in C99 onwards [-Wc99-compat]
V4L2_DV_BT_CEA_10240X4320P50_PA64_27,
^
include/uapi/linux/v4l2-dv-timings.h:1830:3: note: expanded from macro 'V4L2_DV_BT_CEA_10240X4320P50_PA64_27'
2970000000, 2492, 176, 592, 16, 20, 44, 0, 0, 0, \
^
drivers/media/v4l2-core/v4l2-dv-timings.c:270:2: warning: integer literal is too large to be represented in type 'long', interpreting as 'unsigned long' per C89; this literal will have type 'long long' in C99 onwards [-Wc99-compat]
V4L2_DV_BT_CEA_10240X4320P60_PA64_27,
^
include/uapi/linux/v4l2-dv-timings.h:1841:3: note: expanded from macro 'V4L2_DV_BT_CEA_10240X4320P60_PA64_27'
2970000000, 288, 176, 296, 16, 20, 144, 0, 0, 0, \
^
9 warnings generated.
vim +252 drivers/media/v4l2-core/v4l2-dv-timings.c
23
24 const struct v4l2_dv_timings v4l2_dv_timings_presets[] = {
25 V4L2_DV_BT_CEA_640X480P59_94,
26 V4L2_DV_BT_CEA_720X480I59_94,
27 V4L2_DV_BT_CEA_720X480P59_94,
28 V4L2_DV_BT_CEA_720X576I50,
29 V4L2_DV_BT_CEA_720X576P50,
30 V4L2_DV_BT_CEA_1280X720P24,
31 V4L2_DV_BT_CEA_1280X720P25,
32 V4L2_DV_BT_CEA_1280X720P30,
33 V4L2_DV_BT_CEA_1280X720P50,
34 V4L2_DV_BT_CEA_1280X720P60,
35 V4L2_DV_BT_CEA_1920X1080P24,
36 V4L2_DV_BT_CEA_1920X1080P25,
37 V4L2_DV_BT_CEA_1920X1080P30,
38 V4L2_DV_BT_CEA_1920X1080I50,
39 V4L2_DV_BT_CEA_1920X1080P50,
40 V4L2_DV_BT_CEA_1920X1080I60,
41 V4L2_DV_BT_CEA_1920X1080P60,
42 V4L2_DV_BT_DMT_640X350P85,
43 V4L2_DV_BT_DMT_640X400P85,
44 V4L2_DV_BT_DMT_720X400P85,
45 V4L2_DV_BT_DMT_640X480P72,
46 V4L2_DV_BT_DMT_640X480P75,
47 V4L2_DV_BT_DMT_640X480P85,
48 V4L2_DV_BT_DMT_800X600P56,
49 V4L2_DV_BT_DMT_800X600P60,
50 V4L2_DV_BT_DMT_800X600P72,
51 V4L2_DV_BT_DMT_800X600P75,
52 V4L2_DV_BT_DMT_800X600P85,
53 V4L2_DV_BT_DMT_800X600P120_RB,
54 V4L2_DV_BT_DMT_848X480P60,
55 V4L2_DV_BT_DMT_1024X768I43,
56 V4L2_DV_BT_DMT_1024X768P60,
57 V4L2_DV_BT_DMT_1024X768P70,
58 V4L2_DV_BT_DMT_1024X768P75,
59 V4L2_DV_BT_DMT_1024X768P85,
60 V4L2_DV_BT_DMT_1024X768P120_RB,
61 V4L2_DV_BT_DMT_1152X864P75,
62 V4L2_DV_BT_DMT_1280X768P60_RB,
63 V4L2_DV_BT_DMT_1280X768P60,
64 V4L2_DV_BT_DMT_1280X768P75,
65 V4L2_DV_BT_DMT_1280X768P85,
66 V4L2_DV_BT_DMT_1280X768P120_RB,
67 V4L2_DV_BT_DMT_1280X800P60_RB,
68 V4L2_DV_BT_DMT_1280X800P60,
69 V4L2_DV_BT_DMT_1280X800P75,
70 V4L2_DV_BT_DMT_1280X800P85,
71 V4L2_DV_BT_DMT_1280X800P120_RB,
72 V4L2_DV_BT_DMT_1280X960P60,
73 V4L2_DV_BT_DMT_1280X960P85,
74 V4L2_DV_BT_DMT_1280X960P120_RB,
75 V4L2_DV_BT_DMT_1280X1024P60,
76 V4L2_DV_BT_DMT_1280X1024P75,
77 V4L2_DV_BT_DMT_1280X1024P85,
78 V4L2_DV_BT_DMT_1280X1024P120_RB,
79 V4L2_DV_BT_DMT_1360X768P60,
80 V4L2_DV_BT_DMT_1360X768P120_RB,
81 V4L2_DV_BT_DMT_1366X768P60,
82 V4L2_DV_BT_DMT_1366X768P60_RB,
83 V4L2_DV_BT_DMT_1400X1050P60_RB,
84 V4L2_DV_BT_DMT_1400X1050P60,
85 V4L2_DV_BT_DMT_1400X1050P75,
86 V4L2_DV_BT_DMT_1400X1050P85,
87 V4L2_DV_BT_DMT_1400X1050P120_RB,
88 V4L2_DV_BT_DMT_1440X900P60_RB,
89 V4L2_DV_BT_DMT_1440X900P60,
90 V4L2_DV_BT_DMT_1440X900P75,
91 V4L2_DV_BT_DMT_1440X900P85,
92 V4L2_DV_BT_DMT_1440X900P120_RB,
93 V4L2_DV_BT_DMT_1600X900P60_RB,
94 V4L2_DV_BT_DMT_1600X1200P60,
95 V4L2_DV_BT_DMT_1600X1200P65,
96 V4L2_DV_BT_DMT_1600X1200P70,
97 V4L2_DV_BT_DMT_1600X1200P75,
98 V4L2_DV_BT_DMT_1600X1200P85,
99 V4L2_DV_BT_DMT_1600X1200P120_RB,
100 V4L2_DV_BT_DMT_1680X1050P60_RB,
101 V4L2_DV_BT_DMT_1680X1050P60,
102 V4L2_DV_BT_DMT_1680X1050P75,
103 V4L2_DV_BT_DMT_1680X1050P85,
104 V4L2_DV_BT_DMT_1680X1050P120_RB,
105 V4L2_DV_BT_DMT_1792X1344P60,
106 V4L2_DV_BT_DMT_1792X1344P75,
107 V4L2_DV_BT_DMT_1792X1344P120_RB,
108 V4L2_DV_BT_DMT_1856X1392P60,
109 V4L2_DV_BT_DMT_1856X1392P75,
110 V4L2_DV_BT_DMT_1856X1392P120_RB,
111 V4L2_DV_BT_DMT_1920X1200P60_RB,
112 V4L2_DV_BT_DMT_1920X1200P60,
113 V4L2_DV_BT_DMT_1920X1200P75,
114 V4L2_DV_BT_DMT_1920X1200P85,
115 V4L2_DV_BT_DMT_1920X1200P120_RB,
116 V4L2_DV_BT_DMT_1920X1440P60,
117 V4L2_DV_BT_DMT_1920X1440P75,
118 V4L2_DV_BT_DMT_1920X1440P120_RB,
119 V4L2_DV_BT_DMT_2048X1152P60_RB,
120 V4L2_DV_BT_DMT_2560X1600P60_RB,
121 V4L2_DV_BT_DMT_2560X1600P60,
122 V4L2_DV_BT_DMT_2560X1600P75,
123 V4L2_DV_BT_DMT_2560X1600P85,
124 V4L2_DV_BT_DMT_2560X1600P120_RB,
125 V4L2_DV_BT_CEA_3840X2160P24,
126 V4L2_DV_BT_CEA_3840X2160P25,
127 V4L2_DV_BT_CEA_3840X2160P30,
128 V4L2_DV_BT_CEA_3840X2160P50,
129 V4L2_DV_BT_CEA_3840X2160P60,
130 V4L2_DV_BT_CEA_4096X2160P24,
131 V4L2_DV_BT_CEA_4096X2160P25,
132 V4L2_DV_BT_CEA_4096X2160P30,
133 V4L2_DV_BT_CEA_4096X2160P50,
134 V4L2_DV_BT_DMT_4096X2160P59_94_RB,
135 V4L2_DV_BT_CEA_4096X2160P60,
136 V4L2_DV_BT_CEA_720X480P60_PA16_9,
137 V4L2_DV_BT_CEA_720X480I60_PA16_9,
138 V4L2_DV_BT_CEA_720X240P60_VTOT262_PA4_3,
139 V4L2_DV_BT_CEA_720X240P60_VTOT263_PA4_3,
140 V4L2_DV_BT_CEA_720X240P60_VTOT262_PA16_9,
141 V4L2_DV_BT_CEA_720X240P60_VTOT263_PA16_9,
142 V4L2_DV_BT_CEA_2880X480I60_PA4_3,
143 V4L2_DV_BT_CEA_2880X480I60_PA16_9,
144 V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA4_3,
145 V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA4_3,
146 V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA16_9,
147 V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA16_9,
148 V4L2_DV_BT_CEA_1440X480P60_PA4_3,
149 V4L2_DV_BT_CEA_1440X480P60_PA16_9,
150 V4L2_DV_BT_CEA_720X576P50_PA16_9,
151 V4L2_DV_BT_CEA_1920X1080I50_PA16_9,
152 V4L2_DV_BT_CEA_720X576I50_PA16_9,
153 V4L2_DV_BT_CEA_720X288P50_VTOT312_PA4_3,
154 V4L2_DV_BT_CEA_720X288P50_VTOT313_PA4_3,
155 V4L2_DV_BT_CEA_720X288P50_VTOT314_PA4_3,
156 V4L2_DV_BT_CEA_720X288P50_VTOT312_PA16_9,
157 V4L2_DV_BT_CEA_720X288P50_VTOT313_PA16_9,
158 V4L2_DV_BT_CEA_720X288P50_VTOT314_PA16_9,
159 V4L2_DV_BT_CEA_2880X576I50_PA4_3,
160 V4L2_DV_BT_CEA_2880X576I50_PA16_9,
161 V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA4_3,
162 V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA4_3,
163 V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA4_3,
164 V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA16_9,
165 V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA16_9,
166 V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA16_9,
167 V4L2_DV_BT_CEA_1440X576P50_PA4_3,
168 V4L2_DV_BT_CEA_1440X576P50_PA16_9,
169 V4L2_DV_BT_CEA_2880X480P60_PA4_3,
170 V4L2_DV_BT_CEA_2880X480P60_PA16_9,
171 V4L2_DV_BT_CEA_2880X576P50_PA4_3,
172 V4L2_DV_BT_CEA_2880X576P50_PA16_9,
173 V4L2_DV_BT_CEA_1920X1080I50_PA16_9,
174 V4L2_DV_BT_CEA_1920X1080I100_PA16_9,
175 V4L2_DV_BT_CEA_1280X720P100_PA16_9,
176 V4L2_DV_BT_CEA_720X576P100_PA4_3,
177 V4L2_DV_BT_CEA_720X576P100_PA16_9,
178 V4L2_DV_BT_CEA_1440X576I100_PA4_3,
179 V4L2_DV_BT_CEA_1440X576I100_PA16_9,
180 V4L2_DV_BT_CEA_1920X1080I120_PA16_9,
181 V4L2_DV_BT_CEA_1280X720P120_PA16_9,
182 V4L2_DV_BT_CEA_720X480P120_PA4_3,
183 V4L2_DV_BT_CEA_720X480P120_PA16_9,
184 V4L2_DV_BT_CEA_1440X480I120_PA4_3,
185 V4L2_DV_BT_CEA_1440X480I120_PA16_9,
186 V4L2_DV_BT_CEA_720X576P200_PA4_3,
187 V4L2_DV_BT_CEA_720X576P200_PA16_9,
188 V4L2_DV_BT_CEA_1440X576I200_PA4_3,
189 V4L2_DV_BT_CEA_1440X576I200_PA16_9,
190 V4L2_DV_BT_CEA_720X480P240_PA4_3,
191 V4L2_DV_BT_CEA_720X480P240_PA16_9,
192 V4L2_DV_BT_CEA_1440X480I240_PA4_3,
193 V4L2_DV_BT_CEA_1440X480I240_PA16_9,
194 V4L2_DV_BT_CEA_1920X1080P120_PA16_9,
195 V4L2_DV_BT_CEA_1920X1080P100_PA16_9,
196 V4L2_DV_BT_CEA_1280X720P24_PA64_27,
197 V4L2_DV_BT_CEA_1280X720P25_PA64_27,
198 V4L2_DV_BT_CEA_1280X720P30_PA64_27,
199 V4L2_DV_BT_CEA_1280X720P50_PA64_27,
200 V4L2_DV_BT_CEA_1280X720P60_PA64_27,
201 V4L2_DV_BT_CEA_1280X720P100_PA64_27,
202 V4L2_DV_BT_CEA_1280X720P120_PA64_27,
203 V4L2_DV_BT_CEA_1920X1080P24_PA64_27,
204 V4L2_DV_BT_CEA_1920X1080P25_PA64_27,
205 V4L2_DV_BT_CEA_1920X1080P30_PA64_27,
206 V4L2_DV_BT_CEA_1920X1080P50_PA64_27,
207 V4L2_DV_BT_CEA_1920X1080P60_PA64_27,
208 V4L2_DV_BT_CEA_1920X1080P100_PA64_27,
209 V4L2_DV_BT_CEA_1920X1080P120_PA64_27,
210 V4L2_DV_BT_CEA_1680X720P24_PA64_27,
211 V4L2_DV_BT_CEA_1680X720P25_PA64_27,
212 V4L2_DV_BT_CEA_1680X720P30_PA64_27,
213 V4L2_DV_BT_CEA_1680X720P50_PA64_27,
214 V4L2_DV_BT_CEA_1680X720P60_PA64_27,
215 V4L2_DV_BT_CEA_1680X720P100_PA64_27,
216 V4L2_DV_BT_CEA_1680X720P120_PA64_27,
217 V4L2_DV_BT_CEA_2560X1080P24_PA64_27,
218 V4L2_DV_BT_CEA_2560X1080P25_PA64_27,
219 V4L2_DV_BT_CEA_2560X1080P30_PA64_27,
220 V4L2_DV_BT_CEA_2560X1080P50_PA64_27,
221 V4L2_DV_BT_CEA_2560X1080P60_PA64_27,
222 V4L2_DV_BT_CEA_2560X1080P100_PA64_27,
223 V4L2_DV_BT_CEA_2560X1080P120_PA64_27,
224 V4L2_DV_BT_CEA_3840X2160P24_PA64_27,
225 V4L2_DV_BT_CEA_3840X2160P25_PA64_27,
226 V4L2_DV_BT_CEA_3840X2160P30_PA64_27,
227 V4L2_DV_BT_CEA_3840X2160P50_PA64_27,
228 V4L2_DV_BT_CEA_3840X2160P60_PA64_27,
229 V4L2_DV_BT_CEA_1280X720P48_PA16_9,
230 V4L2_DV_BT_CEA_1280X720P48_PA64_27,
231 V4L2_DV_BT_CEA_1680X720P48_PA64_27,
232 V4L2_DV_BT_CEA_1920X1080P48_PA16_9,
233 V4L2_DV_BT_CEA_1920X1080P48_PA64_27,
234 V4L2_DV_BT_CEA_3840X2160P48_PA16_9,
235 V4L2_DV_BT_CEA_4096X2160P48_PA256_135,
236 V4L2_DV_BT_CEA_3840X2160P48_PA64_27,
237 V4L2_DV_BT_CEA_3840X2160P100_PA16_9,
238 V4L2_DV_BT_CEA_3840X2160P120_PA16_9,
239 V4L2_DV_BT_CEA_3840X2160P100_PA64_27,
240 V4L2_DV_BT_CEA_3840X2160P120_PA64_27,
241 V4L2_DV_BT_CEA_5120X2160P24_PA64_27,
242 V4L2_DV_BT_CEA_5120X2160P25_PA64_27,
243 V4L2_DV_BT_CEA_5120X2160P30_PA64_27,
244 V4L2_DV_BT_CEA_5120X2160P48_PA64_27,
245 V4L2_DV_BT_CEA_5120X2160P50_PA64_27,
246 V4L2_DV_BT_CEA_5120X2160P60_PA64_27,
247 V4L2_DV_BT_CEA_5120X2160P100_PA64_27,
248 V4L2_DV_BT_CEA_5120X2160P120_PA64_27,
249 V4L2_DV_BT_CEA_7680X4320P24_PA16_9,
250 V4L2_DV_BT_CEA_7680X4320P25_PA16_9,
251 V4L2_DV_BT_CEA_7680X4320P30_PA16_9,
> 252 V4L2_DV_BT_CEA_7680X4320P48_PA16_9,
253 V4L2_DV_BT_CEA_7680X4320P50_PA16_9,
254 V4L2_DV_BT_CEA_7680X4320P60_PA16_9,
255 V4L2_DV_BT_CEA_7680X4320P100_PA16_9,
256 V4L2_DV_BT_CEA_7680X4320P120_PA16_9,
257 V4L2_DV_BT_CEA_7680X4320P24_PA64_27,
258 V4L2_DV_BT_CEA_7680X4320P25_PA64_27,
259 V4L2_DV_BT_CEA_7680X4320P30_PA64_27,
260 V4L2_DV_BT_CEA_7680X4320P48_PA64_27,
261 V4L2_DV_BT_CEA_7680X4320P50_PA64_27,
262 V4L2_DV_BT_CEA_7680X4320P60_PA64_27,
263 V4L2_DV_BT_CEA_7680X4320P100_PA64_27,
264 V4L2_DV_BT_CEA_7680X4320P120_PA64_27,
265 V4L2_DV_BT_CEA_10240X4320P24_PA64_27,
266 V4L2_DV_BT_CEA_10240X4320P25_PA64_27,
267 V4L2_DV_BT_CEA_10240X4320P30_PA64_27,
268 V4L2_DV_BT_CEA_10240X4320P48_PA64_27,
269 V4L2_DV_BT_CEA_10240X4320P50_PA64_27,
270 V4L2_DV_BT_CEA_10240X4320P60_PA64_27,
271 V4L2_DV_BT_CEA_10240X4320P100_PA64_27,
272 V4L2_DV_BT_CEA_10240X4320P120_PA64_27,
273 V4L2_DV_BT_CEA_4096X2160P100_PA256_135,
274 V4L2_DV_BT_CEA_4096X2160P120_PA256_135,
275 { }
276 };
277 EXPORT_SYMBOL_GPL(v4l2_dv_timings_presets);
278
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 38255 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
* [RFC 6/8] media: v4l2-dv-timings: Add more CEA/CTA-861 video format timings
2021-04-28 15:25 [RFC 0/8] Add Synopsys DesignWare HDMI RX Controller and PHY drivers Nelson Costa
@ 2021-04-28 15:25 ` Nelson Costa
2021-04-28 21:00 ` kernel test robot
2021-04-28 23:13 ` kernel test robot
0 siblings, 2 replies; 4+ messages in thread
From: Nelson Costa @ 2021-04-28 15:25 UTC (permalink / raw)
To: linux-media, linux-kernel, devicetree
Cc: Mauro Carvalho Chehab, Hans Verkuil, Laurent Pinchart,
Kishon Vijay Abraham I, Vinod Koul, Rob Herring, Jose Abreu,
Nelson Costa
This extends the support for more video format timings based
on SPECs CEA-861-F and CTA-861-G.
NOTE: For the newer SPECs the CEA was unified to the CTA.
The CTA-861-G then includes the CEA-861-F timings besides
the new timings that are specified.
CEA-861-F: Specifies the Video timings for VICs 1-107.
CTA-861-G: Specifies the Video timings for VICs 1-107, 108-127, 193-219.
With this patch, the array v4l2_dv_timings_presets has support for
all video timings specified in CTA-861-G.
Signed-off-by: Nelson Costa <nelson.costa@synopsys.com>
---
drivers/media/v4l2-core/v4l2-dv-timings.c | 139 +++
include/uapi/linux/v4l2-dv-timings.h | 1595 ++++++++++++++++++++++++++++-
2 files changed, 1733 insertions(+), 1 deletion(-)
diff --git a/drivers/media/v4l2-core/v4l2-dv-timings.c b/drivers/media/v4l2-core/v4l2-dv-timings.c
index 230d65a..0766e0c 100644
--- a/drivers/media/v4l2-core/v4l2-dv-timings.c
+++ b/drivers/media/v4l2-core/v4l2-dv-timings.c
@@ -133,6 +133,145 @@ const struct v4l2_dv_timings v4l2_dv_timings_presets[] = {
V4L2_DV_BT_CEA_4096X2160P50,
V4L2_DV_BT_DMT_4096X2160P59_94_RB,
V4L2_DV_BT_CEA_4096X2160P60,
+ V4L2_DV_BT_CEA_720X480P60_PA16_9,
+ V4L2_DV_BT_CEA_720X480I60_PA16_9,
+ V4L2_DV_BT_CEA_720X240P60_VTOT262_PA4_3,
+ V4L2_DV_BT_CEA_720X240P60_VTOT263_PA4_3,
+ V4L2_DV_BT_CEA_720X240P60_VTOT262_PA16_9,
+ V4L2_DV_BT_CEA_720X240P60_VTOT263_PA16_9,
+ V4L2_DV_BT_CEA_2880X480I60_PA4_3,
+ V4L2_DV_BT_CEA_2880X480I60_PA16_9,
+ V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA4_3,
+ V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA4_3,
+ V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA16_9,
+ V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA16_9,
+ V4L2_DV_BT_CEA_1440X480P60_PA4_3,
+ V4L2_DV_BT_CEA_1440X480P60_PA16_9,
+ V4L2_DV_BT_CEA_720X576P50_PA16_9,
+ V4L2_DV_BT_CEA_1920X1080I50_PA16_9,
+ V4L2_DV_BT_CEA_720X576I50_PA16_9,
+ V4L2_DV_BT_CEA_720X288P50_VTOT312_PA4_3,
+ V4L2_DV_BT_CEA_720X288P50_VTOT313_PA4_3,
+ V4L2_DV_BT_CEA_720X288P50_VTOT314_PA4_3,
+ V4L2_DV_BT_CEA_720X288P50_VTOT312_PA16_9,
+ V4L2_DV_BT_CEA_720X288P50_VTOT313_PA16_9,
+ V4L2_DV_BT_CEA_720X288P50_VTOT314_PA16_9,
+ V4L2_DV_BT_CEA_2880X576I50_PA4_3,
+ V4L2_DV_BT_CEA_2880X576I50_PA16_9,
+ V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA4_3,
+ V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA4_3,
+ V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA4_3,
+ V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA16_9,
+ V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA16_9,
+ V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA16_9,
+ V4L2_DV_BT_CEA_1440X576P50_PA4_3,
+ V4L2_DV_BT_CEA_1440X576P50_PA16_9,
+ V4L2_DV_BT_CEA_2880X480P60_PA4_3,
+ V4L2_DV_BT_CEA_2880X480P60_PA16_9,
+ V4L2_DV_BT_CEA_2880X576P50_PA4_3,
+ V4L2_DV_BT_CEA_2880X576P50_PA16_9,
+ V4L2_DV_BT_CEA_1920X1080I50_PA16_9,
+ V4L2_DV_BT_CEA_1920X1080I100_PA16_9,
+ V4L2_DV_BT_CEA_1280X720P100_PA16_9,
+ V4L2_DV_BT_CEA_720X576P100_PA4_3,
+ V4L2_DV_BT_CEA_720X576P100_PA16_9,
+ V4L2_DV_BT_CEA_1440X576I100_PA4_3,
+ V4L2_DV_BT_CEA_1440X576I100_PA16_9,
+ V4L2_DV_BT_CEA_1920X1080I120_PA16_9,
+ V4L2_DV_BT_CEA_1280X720P120_PA16_9,
+ V4L2_DV_BT_CEA_720X480P120_PA4_3,
+ V4L2_DV_BT_CEA_720X480P120_PA16_9,
+ V4L2_DV_BT_CEA_1440X480I120_PA4_3,
+ V4L2_DV_BT_CEA_1440X480I120_PA16_9,
+ V4L2_DV_BT_CEA_720X576P200_PA4_3,
+ V4L2_DV_BT_CEA_720X576P200_PA16_9,
+ V4L2_DV_BT_CEA_1440X576I200_PA4_3,
+ V4L2_DV_BT_CEA_1440X576I200_PA16_9,
+ V4L2_DV_BT_CEA_720X480P240_PA4_3,
+ V4L2_DV_BT_CEA_720X480P240_PA16_9,
+ V4L2_DV_BT_CEA_1440X480I240_PA4_3,
+ V4L2_DV_BT_CEA_1440X480I240_PA16_9,
+ V4L2_DV_BT_CEA_1920X1080P120_PA16_9,
+ V4L2_DV_BT_CEA_1920X1080P100_PA16_9,
+ V4L2_DV_BT_CEA_1280X720P24_PA64_27,
+ V4L2_DV_BT_CEA_1280X720P25_PA64_27,
+ V4L2_DV_BT_CEA_1280X720P30_PA64_27,
+ V4L2_DV_BT_CEA_1280X720P50_PA64_27,
+ V4L2_DV_BT_CEA_1280X720P60_PA64_27,
+ V4L2_DV_BT_CEA_1280X720P100_PA64_27,
+ V4L2_DV_BT_CEA_1280X720P120_PA64_27,
+ V4L2_DV_BT_CEA_1920X1080P24_PA64_27,
+ V4L2_DV_BT_CEA_1920X1080P25_PA64_27,
+ V4L2_DV_BT_CEA_1920X1080P30_PA64_27,
+ V4L2_DV_BT_CEA_1920X1080P50_PA64_27,
+ V4L2_DV_BT_CEA_1920X1080P60_PA64_27,
+ V4L2_DV_BT_CEA_1920X1080P100_PA64_27,
+ V4L2_DV_BT_CEA_1920X1080P120_PA64_27,
+ V4L2_DV_BT_CEA_1680X720P24_PA64_27,
+ V4L2_DV_BT_CEA_1680X720P25_PA64_27,
+ V4L2_DV_BT_CEA_1680X720P30_PA64_27,
+ V4L2_DV_BT_CEA_1680X720P50_PA64_27,
+ V4L2_DV_BT_CEA_1680X720P60_PA64_27,
+ V4L2_DV_BT_CEA_1680X720P100_PA64_27,
+ V4L2_DV_BT_CEA_1680X720P120_PA64_27,
+ V4L2_DV_BT_CEA_2560X1080P24_PA64_27,
+ V4L2_DV_BT_CEA_2560X1080P25_PA64_27,
+ V4L2_DV_BT_CEA_2560X1080P30_PA64_27,
+ V4L2_DV_BT_CEA_2560X1080P50_PA64_27,
+ V4L2_DV_BT_CEA_2560X1080P60_PA64_27,
+ V4L2_DV_BT_CEA_2560X1080P100_PA64_27,
+ V4L2_DV_BT_CEA_2560X1080P120_PA64_27,
+ V4L2_DV_BT_CEA_3840X2160P24_PA64_27,
+ V4L2_DV_BT_CEA_3840X2160P25_PA64_27,
+ V4L2_DV_BT_CEA_3840X2160P30_PA64_27,
+ V4L2_DV_BT_CEA_3840X2160P50_PA64_27,
+ V4L2_DV_BT_CEA_3840X2160P60_PA64_27,
+ V4L2_DV_BT_CEA_1280X720P48_PA16_9,
+ V4L2_DV_BT_CEA_1280X720P48_PA64_27,
+ V4L2_DV_BT_CEA_1680X720P48_PA64_27,
+ V4L2_DV_BT_CEA_1920X1080P48_PA16_9,
+ V4L2_DV_BT_CEA_1920X1080P48_PA64_27,
+ V4L2_DV_BT_CEA_3840X2160P48_PA16_9,
+ V4L2_DV_BT_CEA_4096X2160P48_PA256_135,
+ V4L2_DV_BT_CEA_3840X2160P48_PA64_27,
+ V4L2_DV_BT_CEA_3840X2160P100_PA16_9,
+ V4L2_DV_BT_CEA_3840X2160P120_PA16_9,
+ V4L2_DV_BT_CEA_3840X2160P100_PA64_27,
+ V4L2_DV_BT_CEA_3840X2160P120_PA64_27,
+ V4L2_DV_BT_CEA_5120X2160P24_PA64_27,
+ V4L2_DV_BT_CEA_5120X2160P25_PA64_27,
+ V4L2_DV_BT_CEA_5120X2160P30_PA64_27,
+ V4L2_DV_BT_CEA_5120X2160P48_PA64_27,
+ V4L2_DV_BT_CEA_5120X2160P50_PA64_27,
+ V4L2_DV_BT_CEA_5120X2160P60_PA64_27,
+ V4L2_DV_BT_CEA_5120X2160P100_PA64_27,
+ V4L2_DV_BT_CEA_5120X2160P120_PA64_27,
+ V4L2_DV_BT_CEA_7680X4320P24_PA16_9,
+ V4L2_DV_BT_CEA_7680X4320P25_PA16_9,
+ V4L2_DV_BT_CEA_7680X4320P30_PA16_9,
+ V4L2_DV_BT_CEA_7680X4320P48_PA16_9,
+ V4L2_DV_BT_CEA_7680X4320P50_PA16_9,
+ V4L2_DV_BT_CEA_7680X4320P60_PA16_9,
+ V4L2_DV_BT_CEA_7680X4320P100_PA16_9,
+ V4L2_DV_BT_CEA_7680X4320P120_PA16_9,
+ V4L2_DV_BT_CEA_7680X4320P24_PA64_27,
+ V4L2_DV_BT_CEA_7680X4320P25_PA64_27,
+ V4L2_DV_BT_CEA_7680X4320P30_PA64_27,
+ V4L2_DV_BT_CEA_7680X4320P48_PA64_27,
+ V4L2_DV_BT_CEA_7680X4320P50_PA64_27,
+ V4L2_DV_BT_CEA_7680X4320P60_PA64_27,
+ V4L2_DV_BT_CEA_7680X4320P100_PA64_27,
+ V4L2_DV_BT_CEA_7680X4320P120_PA64_27,
+ V4L2_DV_BT_CEA_10240X4320P24_PA64_27,
+ V4L2_DV_BT_CEA_10240X4320P25_PA64_27,
+ V4L2_DV_BT_CEA_10240X4320P30_PA64_27,
+ V4L2_DV_BT_CEA_10240X4320P48_PA64_27,
+ V4L2_DV_BT_CEA_10240X4320P50_PA64_27,
+ V4L2_DV_BT_CEA_10240X4320P60_PA64_27,
+ V4L2_DV_BT_CEA_10240X4320P100_PA64_27,
+ V4L2_DV_BT_CEA_10240X4320P120_PA64_27,
+ V4L2_DV_BT_CEA_4096X2160P100_PA256_135,
+ V4L2_DV_BT_CEA_4096X2160P120_PA256_135,
{ }
};
EXPORT_SYMBOL_GPL(v4l2_dv_timings_presets);
diff --git a/include/uapi/linux/v4l2-dv-timings.h b/include/uapi/linux/v4l2-dv-timings.h
index b52b67c..e7d143c 100644
--- a/include/uapi/linux/v4l2-dv-timings.h
+++ b/include/uapi/linux/v4l2-dv-timings.h
@@ -29,7 +29,14 @@
.bt = { _width , ## args }
#endif
-/* CEA-861-F timings (i.e. standard HDTV timings) */
+/* CEA-861-F timings (i.e. standard HDTV timings)
+ * NOTE: For the newer SPECs the CEA was unified to the CTA.
+ * The CTA-861-G includes the CEA-861-F timings besides the
+ * new timings that are specified.
+ *
+ * CEA-861-F: Specifies the Video timings for VICs 1-107
+ * CTA-861-G: Specifies the Video timings for VICs 1-107, 108-127, 193-219
+ */
#define V4L2_DV_BT_CEA_640X480P59_94 { \
.type = V4L2_DV_BT_656_1120, \
@@ -297,6 +304,1592 @@
V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 102) \
}
+/* VIC=3 */
+#define V4L2_DV_BT_CEA_720X480P60_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
+ 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 3) \
+}
+
+/* VIC=7 */
+/* Note: these are the nominal timings, for HDMI links this format is typically
+ * double-clocked to meet the minimum pixelclock requirements.
+ */
+#define V4L2_DV_BT_CEA_720X480I60_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \
+ 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE | \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 7) \
+}
+
+/* VIC=8 */
+/* Note: these are the nominal timings, for HDMI links this format is typically
+ * double-clocked to meet the minimum pixelclock requirements.
+ */
+#define V4L2_DV_BT_CEA_720X240P60_VTOT262_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 240, 0, 0, \
+ 13500000, 19, 62, 57, 4, 3, 15, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 4, 3 }, 8) \
+}
+
+/* VIC=8 */
+/* Note: these are the nominal timings, for HDMI links this format is typically
+ * double-clocked to meet the minimum pixelclock requirements.
+ */
+#define V4L2_DV_BT_CEA_720X240P60_VTOT263_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 240, 0, 0, \
+ 13500000, 19, 62, 57, 5, 3, 15, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 4, 3 }, 8) \
+}
+
+/* VIC=9 */
+/* Note: these are the nominal timings, for HDMI links this format is typically
+ * double-clocked to meet the minimum pixelclock requirements.
+ */
+#define V4L2_DV_BT_CEA_720X240P60_VTOT262_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 240, 0, 0, \
+ 13500000, 19, 62, 57, 4, 3, 15, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 9) \
+}
+
+/* VIC=9 */
+/* Note: these are the nominal timings, for HDMI links this format is typically
+ * double-clocked to meet the minimum pixelclock requirements.
+ */
+#define V4L2_DV_BT_CEA_720X240P60_VTOT263_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 240, 0, 0, \
+ 13500000, 19, 62, 57, 5, 3, 15, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 9) \
+}
+
+/* VIC=10 */
+#define V4L2_DV_BT_CEA_2880X480I60_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2880, 480, 1, 0, \
+ 54000000, 76, 248, 228, 4, 3, 15, 4, 3, 16, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE | \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 10) \
+}
+
+/* VIC=11 */
+#define V4L2_DV_BT_CEA_2880X480I60_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2880, 480, 1, 0, \
+ 54000000, 76, 248, 228, 4, 3, 15, 4, 3, 16, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE | \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 11) \
+}
+
+/* VIC=12 */
+#define V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2880, 240, 0, 0, \
+ 54000000, 76, 248, 228, 4, 3, 15, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 4, 3 }, 12) \
+}
+
+/* VIC=12 */
+#define V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2880, 240, 0, 0, \
+ 54000000, 76, 248, 228, 5, 3, 15, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 4, 3 }, 12) \
+}
+
+/* VIC=13 */
+#define V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2880, 240, 0, 0, \
+ 54000000, 76, 248, 228, 4, 3, 15, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 13) \
+}
+
+/* VIC=13 */
+#define V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2880, 240, 0, 0, \
+ 54000000, 76, 248, 228, 5, 3, 15, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 13) \
+}
+
+/* VIC=14 */
+#define V4L2_DV_BT_CEA_1440X480P60_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1440, 480, 0, 0, \
+ 54000000, 32, 124, 120, 9, 6, 30, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 4, 3 }, 14) \
+}
+
+/* VIC=15 */
+#define V4L2_DV_BT_CEA_1440X480P60_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1440, 480, 0, 0, \
+ 54000000, 32, 124, 120, 9, 6, 30, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 15) \
+}
+
+/* VIC=18 */
+#define V4L2_DV_BT_CEA_720X576P50_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
+ 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 18) \
+}
+
+/* VIC=22 */
+/* Note: these are the nominal timings, for HDMI links this format is typically
+ * double-clocked to meet the minimum pixelclock requirements.
+ */
+#define V4L2_DV_BT_CEA_720X576I50_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \
+ 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 22) \
+}
+
+/* VIC=23 */
+/* Note: these are the nominal timings, for HDMI links this format is typically
+ * double-clocked to meet the minimum pixelclock requirements.
+ */
+#define V4L2_DV_BT_CEA_720X288P50_VTOT312_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 288, 0, 0, \
+ 13500000, 12, 63, 69, 2, 3, 19, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 23) \
+}
+
+/* VIC=23 */
+/* Note: these are the nominal timings, for HDMI links this format is typically
+ * double-clocked to meet the minimum pixelclock requirements.
+ */
+#define V4L2_DV_BT_CEA_720X288P50_VTOT313_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 288, 0, 0, \
+ 13500000, 12, 63, 69, 3, 3, 19, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 23) \
+}
+
+/* VIC=23 */
+/* Note: these are the nominal timings, for HDMI links this format is typically
+ * double-clocked to meet the minimum pixelclock requirements.
+ */
+#define V4L2_DV_BT_CEA_720X288P50_VTOT314_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 288, 0, 0, \
+ 13500000, 12, 63, 69, 4, 3, 19, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 23) \
+}
+
+/* VIC=24 */
+/* Note: these are the nominal timings, for HDMI links this format is typically
+ * double-clocked to meet the minimum pixelclock requirements.
+ */
+#define V4L2_DV_BT_CEA_720X288P50_VTOT312_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 288, 0, 0, \
+ 13500000, 12, 63, 69, 2, 3, 19, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 24) \
+}
+
+/* VIC=24 */
+/* Note: these are the nominal timings, for HDMI links this format is typically
+ * double-clocked to meet the minimum pixelclock requirements.
+ */
+#define V4L2_DV_BT_CEA_720X288P50_VTOT313_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 288, 0, 0, \
+ 13500000, 12, 63, 69, 3, 3, 19, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 24) \
+}
+
+/* VIC=24 */
+/* Note: these are the nominal timings, for HDMI links this format is typically
+ * double-clocked to meet the minimum pixelclock requirements.
+ */
+#define V4L2_DV_BT_CEA_720X288P50_VTOT314_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 288, 0, 0, \
+ 13500000, 12, 63, 69, 4, 3, 19, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 24) \
+}
+
+/* VIC=25 */
+#define V4L2_DV_BT_CEA_2880X576I50_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2880, 576, 1, 0, \
+ 54000000, 48, 252, 276, 2, 3, 19, 2, 3, 20, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 4, 3 }, 25) \
+}
+
+/* VIC=26 */
+#define V4L2_DV_BT_CEA_2880X576I50_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2880, 576, 1, 0, \
+ 54000000, 48, 252, 276, 2, 3, 19, 2, 3, 20, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 26) \
+}
+
+/* VIC=27 */
+#define V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2880, 288, 0, 0, \
+ 54000000, 48, 252, 276, 2, 3, 19, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 27) \
+}
+
+/* VIC=27 */
+#define V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2880, 288, 0, 0, \
+ 54000000, 48, 252, 276, 3, 3, 19, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 27) \
+}
+
+/* VIC=27 */
+#define V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2880, 288, 0, 0, \
+ 54000000, 48, 252, 276, 4, 3, 19, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 27) \
+}
+
+/* VIC=28 */
+#define V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2880, 288, 0, 0, \
+ 54000000, 48, 252, 276, 2, 3, 19, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 28) \
+}
+
+/* VIC=28 */
+#define V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2880, 288, 0, 0, \
+ 54000000, 48, 252, 276, 3, 3, 19, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 28) \
+}
+
+/* VIC=28 */
+#define V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2880, 288, 0, 0, \
+ 54000000, 48, 252, 276, 4, 3, 19, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 28) \
+}
+
+/* VIC=29 */
+#define V4L2_DV_BT_CEA_1440X576P50_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1440, 576, 0, 0, \
+ 54000000, 24, 128, 136, 5, 5, 39, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 29) \
+}
+
+/* VIC=30 */
+#define V4L2_DV_BT_CEA_1440X576P50_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1440, 576, 0, 0, \
+ 54000000, 24, 128, 136, 5, 5, 39, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 30) \
+}
+
+/* VIC=35 */
+#define V4L2_DV_BT_CEA_2880X480P60_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2880, 480, 0, 0, \
+ 108000000, 64, 248, 240, 9, 6, 30, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 4, 3 }, 35) \
+}
+
+/* VIC=36 */
+#define V4L2_DV_BT_CEA_2880X480P60_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2880, 480, 0, 0, \
+ 108000000, 64, 248, 240, 9, 6, 30, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 36) \
+}
+
+/* VIC=37 */
+#define V4L2_DV_BT_CEA_2880X576P50_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2880, 576, 0, 0, \
+ 108000000, 48, 256, 272, 5, 5, 39, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 37) \
+}
+
+/* VIC=38 */
+#define V4L2_DV_BT_CEA_2880X576P50_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2880, 576, 0, 0, \
+ 108000000, 48, 256, 272, 5, 5, 39, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 38) \
+}
+
+/* VIC=39 */
+#define V4L2_DV_BT_CEA_1920X1080I50_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1920, 1080, 1, V4L2_DV_HSYNC_POS_POL, \
+ 72000000, 32, 168, 184, 23, 5, 57, 23, 5, 58, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 39) \
+}
+
+/* VIC=40 */
+#define V4L2_DV_BT_CEA_1920X1080I100_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 148500000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 40) \
+}
+
+/* VIC=41 */
+#define V4L2_DV_BT_CEA_1280X720P100_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 148500000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 41) \
+}
+
+/* VIC=42 */
+#define V4L2_DV_BT_CEA_720X576P100_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
+ 54000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 42) \
+}
+
+/* VIC=43 */
+#define V4L2_DV_BT_CEA_720X576P100_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
+ 54000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 43) \
+}
+
+/* VIC=44 */
+#define V4L2_DV_BT_CEA_1440X576I100_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1440, 576, 1, 0, \
+ 54000000, 24, 126, 138, 2, 3, 19, 2, 3, 20, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 4, 3 }, 44) \
+}
+
+/* VIC=45 */
+#define V4L2_DV_BT_CEA_1440X576I100_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1440, 576, 1, 0, \
+ 54000000, 24, 126, 138, 2, 3, 19, 2, 3, 20, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 45) \
+}
+
+/* VIC=46 */
+#define V4L2_DV_BT_CEA_1920X1080I120_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 148500000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE | \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 46) \
+}
+
+/* VIC=47 */
+#define V4L2_DV_BT_CEA_1280X720P120_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 148500000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 47) \
+}
+
+/* VIC=48 */
+#define V4L2_DV_BT_CEA_720X480P120_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
+ 54000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 4, 3 }, 48) \
+}
+
+/* VIC=49 */
+#define V4L2_DV_BT_CEA_720X480P120_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
+ 54000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 49) \
+}
+
+/* VIC=50 */
+#define V4L2_DV_BT_CEA_1440X480I120_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1440, 480, 1, 0, \
+ 54000000, 38, 124, 114, 4, 3, 15, 4, 3, 16, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE | \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 50) \
+}
+
+/* VIC=51 */
+#define V4L2_DV_BT_CEA_1440X480I120_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1440, 480, 1, 0, \
+ 54000000, 38, 124, 114, 4, 3, 15, 4, 3, 16, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE | \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 51) \
+}
+
+/* VIC=52 */
+#define V4L2_DV_BT_CEA_720X576P200_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
+ 108000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 52) \
+}
+
+/* VIC=53 */
+#define V4L2_DV_BT_CEA_720X576P200_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
+ 108000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 53) \
+}
+
+/* VIC=54 */
+#define V4L2_DV_BT_CEA_1440X576I200_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1440, 576, 1, 0, \
+ 108000000, 24, 126, 138, 2, 3, 19, 2, 3, 20, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 4, 3 }, 54) \
+}
+
+/* VIC=55 */
+#define V4L2_DV_BT_CEA_1440X576I200_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1440, 576, 1, 0, \
+ 108000000, 24, 126, 138, 2, 3, 19, 2, 3, 20, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 55) \
+}
+
+/* VIC=56 */
+#define V4L2_DV_BT_CEA_720X480P240_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
+ 108000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 4, 3 }, 56) \
+}
+
+/* VIC=57 */
+#define V4L2_DV_BT_CEA_720X480P240_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
+ 108000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 57) \
+}
+
+/* VIC=58 */
+#define V4L2_DV_BT_CEA_1440X480I240_PA4_3 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1440, 480, 1, 0, \
+ 108000000, 38, 124, 114, 4, 3, 15, 4, 3, 16, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE | \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 58) \
+}
+
+/* VIC=59 */
+#define V4L2_DV_BT_CEA_1440X480I240_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1440, 480, 1, 0, \
+ 108000000, 38, 124, 114, 4, 3, 15, 4, 3, 16, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE | \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 59) \
+}
+
+/* VIC=63 */
+#define V4L2_DV_BT_CEA_1920X1080P120_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 297000000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 63) \
+}
+
+/* VIC=64 */
+#define V4L2_DV_BT_CEA_1920X1080P100_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 297000000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 64) \
+}
+
+/* VIC=65 */
+#define V4L2_DV_BT_CEA_1280X720P24_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 65) \
+}
+
+/* VIC=66 */
+#define V4L2_DV_BT_CEA_1280X720P25_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 66) \
+}
+
+/* VIC=67 */
+#define V4L2_DV_BT_CEA_1280X720P30_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 67) \
+}
+
+/* VIC=68 */
+#define V4L2_DV_BT_CEA_1280X720P50_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 68) \
+}
+
+/* VIC=69 */
+#define V4L2_DV_BT_CEA_1280X720P60_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 69) \
+}
+
+/* VIC=70 */
+#define V4L2_DV_BT_CEA_1280X720P100_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 148500000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 70) \
+}
+
+/* VIC=71 */
+#define V4L2_DV_BT_CEA_1280X720P120_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 148500000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 71) \
+}
+
+/* VIC=72 */
+#define V4L2_DV_BT_CEA_1920X1080P24_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 72) \
+}
+
+/* VIC=73 */
+#define V4L2_DV_BT_CEA_1920X1080P25_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 73) \
+}
+
+/* VIC=74 */
+#define V4L2_DV_BT_CEA_1920X1080P30_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 74) \
+}
+
+/* VIC=75 */
+#define V4L2_DV_BT_CEA_1920X1080P50_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 75) \
+}
+
+/* VIC=76 */
+#define V4L2_DV_BT_CEA_1920X1080P60_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 76) \
+}
+
+/* VIC=77 */
+#define V4L2_DV_BT_CEA_1920X1080P100_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 297000000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 77) \
+}
+
+/* VIC=78 */
+#define V4L2_DV_BT_CEA_1920X1080P120_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 297000000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 78) \
+}
+
+/* VIC=79 */
+#define V4L2_DV_BT_CEA_1680X720P24_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1680, 720, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 59400000, 1360, 40, 220, 5, 5, 20, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 79) \
+}
+
+/* VIC=80 */
+#define V4L2_DV_BT_CEA_1680X720P25_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1680, 720, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 59400000, 1228, 40, 220, 5, 5, 20, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 80) \
+}
+
+/* VIC=81 */
+#define V4L2_DV_BT_CEA_1680X720P30_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1680, 720, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 59400000, 700, 40, 220, 5, 5, 20, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 81) \
+}
+
+/* VIC=82 */
+#define V4L2_DV_BT_CEA_1680X720P50_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1680, 720, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 82500000, 260, 40, 220, 5, 5, 20, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 82) \
+}
+
+/* VIC=83 */
+#define V4L2_DV_BT_CEA_1680X720P60_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1680, 720, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 99000000, 260, 40, 220, 5, 5, 20, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 83) \
+}
+
+/* VIC=84 */
+#define V4L2_DV_BT_CEA_1680X720P100_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1680, 720, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 165000000, 60, 40, 220, 5, 5, 95, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 84) \
+}
+
+/* VIC=85 */
+#define V4L2_DV_BT_CEA_1680X720P120_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1680, 720, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 198000000, 60, 40, 220, 5, 5, 95, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 85) \
+}
+
+/* VIC=86 */
+#define V4L2_DV_BT_CEA_2560X1080P24_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2560, 1080, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 99000000, 998, 44, 148, 4, 5, 11, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 86) \
+}
+
+/* VIC=87 */
+#define V4L2_DV_BT_CEA_2560X1080P25_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2560, 1080, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 90000000, 448, 44, 148, 4, 5, 36, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 87) \
+}
+
+/* VIC=88 */
+#define V4L2_DV_BT_CEA_2560X1080P30_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2560, 1080, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 118800000, 768, 44, 148, 4, 5, 36, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 88) \
+}
+
+/* VIC=89 */
+#define V4L2_DV_BT_CEA_2560X1080P50_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2560, 1080, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 185625000, 548, 44, 148, 4, 5, 36, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 89) \
+}
+
+/* VIC=90 */
+#define V4L2_DV_BT_CEA_2560X1080P60_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2560, 1080, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 198000000, 248, 44, 148, 4, 5, 11, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 90) \
+}
+
+/* VIC=91 */
+#define V4L2_DV_BT_CEA_2560X1080P100_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2560, 1080, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 371250000, 218, 44, 148, 4, 5, 161, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 91) \
+}
+
+/* VIC=92 */
+#define V4L2_DV_BT_CEA_2560X1080P120_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(2560, 1080, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 495000000, 548, 44, 148, 4, 5, 161, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 92) \
+}
+
+/* VIC=103 */
+#define V4L2_DV_BT_CEA_3840X2160P24_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 103) \
+}
+
+/* VIC=104 */
+#define V4L2_DV_BT_CEA_3840X2160P25_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 104) \
+}
+
+/* VIC=105 */
+#define V4L2_DV_BT_CEA_3840X2160P30_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 105) \
+}
+
+/* VIC=106 */
+#define V4L2_DV_BT_CEA_3840X2160P50_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 106) \
+}
+
+/* VIC=107 */
+#define V4L2_DV_BT_CEA_3840X2160P60_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 107) \
+}
+
+/* VIC=108 */
+#define V4L2_DV_BT_CEA_1280X720P48_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 90000000, 960, 40, 220, 5, 5, 20, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 108) \
+}
+
+/* VIC=109 */
+#define V4L2_DV_BT_CEA_1280X720P48_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 90000000, 960, 40, 220, 5, 5, 20, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 109) \
+}
+
+/* VIC=110 */
+#define V4L2_DV_BT_CEA_1680X720P48_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1680, 720, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 99000000, 810, 40, 220, 5, 5, 20, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 110) \
+}
+
+/* VIC=111 */
+#define V4L2_DV_BT_CEA_1920X1080P48_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 148500000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 111) \
+}
+
+/* VIC=112 */
+#define V4L2_DV_BT_CEA_1920X1080P48_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 148500000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 112) \
+}
+
+/* VIC=114 */
+#define V4L2_DV_BT_CEA_3840X2160P48_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 594000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 114) \
+}
+
+/* VIC=115 */
+#define V4L2_DV_BT_CEA_4096X2160P48_PA256_135 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 594000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 256, 135 }, 115) \
+}
+
+/* VIC=116 */
+#define V4L2_DV_BT_CEA_3840X2160P48_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 594000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 116) \
+}
+
+/* VIC=117 */
+#define V4L2_DV_BT_CEA_3840X2160P100_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 1188000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 117) \
+}
+
+/* VIC=118 */
+#define V4L2_DV_BT_CEA_3840X2160P120_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 1188000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 118) \
+}
+
+/* VIC=119 */
+#define V4L2_DV_BT_CEA_3840X2160P100_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 1188000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 119) \
+}
+
+/* VIC=120 */
+#define V4L2_DV_BT_CEA_3840X2160P120_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 1188000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 120) \
+}
+
+/* VIC=121 */
+#define V4L2_DV_BT_CEA_5120X2160P24_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(5120, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 396000000, 1996, 88, 296, 8, 10, 22, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 121) \
+}
+
+/* VIC=122 */
+#define V4L2_DV_BT_CEA_5120X2160P25_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(5120, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 396000000, 1696, 88, 296, 8, 10, 22, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 122) \
+}
+
+/* VIC=123 */
+#define V4L2_DV_BT_CEA_5120X2160P30_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(5120, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 396000000, 664, 88, 296, 8, 10, 22, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 123) \
+}
+
+/* VIC=124 */
+#define V4L2_DV_BT_CEA_5120X2160P48_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(5120, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 742500000, 746, 88, 296, 8, 10, 297, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 124) \
+}
+
+/* VIC=125 */
+#define V4L2_DV_BT_CEA_5120X2160P50_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(5120, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 742500000, 1096, 88, 296, 8, 10, 72, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 125) \
+}
+
+/* VIC=126 */
+#define V4L2_DV_BT_CEA_5120X2160P60_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(5120, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 742500000, 164, 88, 128, 8, 10, 72, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 126) \
+}
+
+/* VIC=127 */
+#define V4L2_DV_BT_CEA_5120X2160P100_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(5120, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 1485000000, 1096, 88, 296, 8, 10, 72, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 127) \
+}
+
+/* VIC=193 */
+#define V4L2_DV_BT_CEA_5120X2160P120_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(5120, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 1485000000, 154, 88, 296, 8, 10, 72, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 193) \
+}
+
+/* VIC=194 */
+#define V4L2_DV_BT_CEA_7680X4320P24_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 1188000000, 2552, 176, 592, 16, 20, 144, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 194) \
+}
+
+/* VIC=195 */
+#define V4L2_DV_BT_CEA_7680X4320P25_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 1188000000, 2352, 176, 592, 16, 20, 44, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 195) \
+}
+
+/* VIC=196 */
+#define V4L2_DV_BT_CEA_7680X4320P30_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 1188000000, 552, 176, 592, 16, 20, 44, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 196) \
+}
+
+/* VIC=197 */
+#define V4L2_DV_BT_CEA_7680X4320P48_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 2376000000, 2552, 176, 592, 16, 20, 144, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 197) \
+}
+
+/* VIC=198 */
+#define V4L2_DV_BT_CEA_7680X4320P50_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 2376000000, 2352, 176, 592, 16, 20, 44, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 198) \
+}
+
+/* VIC=199 */
+#define V4L2_DV_BT_CEA_7680X4320P60_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 2376000000, 552, 176, 592, 16, 20, 44, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 199) \
+}
+
+/* VIC=200 */
+#define V4L2_DV_BT_CEA_7680X4320P100_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 4752000000, 2112, 176, 592, 16, 20, 144, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 16, 9 }, 200) \
+}
+
+/* VIC=201 */
+#define V4L2_DV_BT_CEA_7680X4320P120_PA16_9 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 4752000000, 352, 176, 592, 16, 20, 144, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 16, 9 }, 201) \
+}
+
+/* VIC=202 */
+#define V4L2_DV_BT_CEA_7680X4320P24_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 1188000000, 2552, 176, 592, 16, 20, 144, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 202) \
+}
+
+/* VIC=203 */
+#define V4L2_DV_BT_CEA_7680X4320P25_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 1188000000, 2352, 176, 592, 16, 20, 44, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 203) \
+}
+
+/* VIC=204 */
+#define V4L2_DV_BT_CEA_7680X4320P30_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 1188000000, 552, 176, 592, 16, 20, 44, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 204) \
+}
+
+/* VIC=205 */
+#define V4L2_DV_BT_CEA_7680X4320P48_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 2376000000, 2552, 176, 592, 16, 20, 144, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 205) \
+}
+
+/* VIC=206 */
+#define V4L2_DV_BT_CEA_7680X4320P50_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 2376000000, 2352, 176, 592, 16, 20, 44, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 206) \
+}
+
+/* VIC=207 */
+#define V4L2_DV_BT_CEA_7680X4320P60_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 2376000000, 552, 176, 592, 16, 20, 44, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 207) \
+}
+
+/* VIC=208 */
+#define V4L2_DV_BT_CEA_7680X4320P100_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 4752000000, 2112, 176, 592, 16, 20, 144, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 208) \
+}
+
+/* VIC=209 */
+#define V4L2_DV_BT_CEA_7680X4320P120_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(7680, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 4752000000, 352, 176, 592, 16, 20, 144, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 209) \
+}
+
+/* VIC=210 */
+#define V4L2_DV_BT_CEA_10240X4320P24_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(10240, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 1485000000, 1492, 176, 592, 16, 20, 594, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 210) \
+}
+
+/* VIC=211 */
+#define V4L2_DV_BT_CEA_10240X4320P25_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(10240, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 1485000000, 2492, 176, 592, 16, 20, 44, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 211) \
+}
+
+/* VIC=212 */
+#define V4L2_DV_BT_CEA_10240X4320P30_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(10240, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 1485000000, 288, 176, 296, 16, 20, 144, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 212) \
+}
+
+/* VIC=213 */
+#define V4L2_DV_BT_CEA_10240X4320P48_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(10240, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 2970000000, 1492, 176, 592, 16, 20, 594, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 213) \
+}
+
+/* VIC=214 */
+#define V4L2_DV_BT_CEA_10240X4320P50_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(10240, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 2970000000, 2492, 176, 592, 16, 20, 44, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 214) \
+}
+
+/* VIC=215 */
+#define V4L2_DV_BT_CEA_10240X4320P60_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(10240, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 2970000000, 288, 176, 296, 16, 20, 144, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 215) \
+}
+
+/* VIC=216 */
+#define V4L2_DV_BT_CEA_10240X4320P100_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(10240, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 5940000000, 2192, 176, 592, 16, 20, 144, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 64, 27 }, 216) \
+}
+
+/* VIC=217 */
+#define V4L2_DV_BT_CEA_10240X4320P120_PA64_27 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(10240, 4320, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 5940000000, 288, 176, 296, 16, 20, 144, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 64, 27 }, 217) \
+}
+
+/* VIC=218 */
+#define V4L2_DV_BT_CEA_4096X2160P100_PA256_135 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 1188000000, 800, 88, 296, 8, 10, 72, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
+ V4L2_DV_FL_HAS_CEA861_VIC, { 256, 135 }, 218) \
+}
+
+/* VIC=219 */
+#define V4L2_DV_BT_CEA_4096X2160P120_PA256_135 { \
+ .type = V4L2_DV_BT_656_1120, \
+ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+ 1188000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
+ V4L2_DV_BT_STD_CEA861, \
+ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
+ { 256, 135 }, 219) \
+}
/* VESA Discrete Monitor Timings as per version 1.0, revision 12 */
--
2.7.4
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