Re: [PATCH 1/1] i915/query: Correlate engine and cpu timestamps with better accuracy

From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
To: Jason Ekstrand <jason@jlekstrand.net>
Cc: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>,
	Intel GFX <intel-gfx@lists.freedesktop.org>,
	Maling list - DRI developers <dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH 1/1] i915/query: Correlate engine and cpu timestamps with better accuracy
Date: Mon, 3 May 2021 11:29:14 -0700	[thread overview]
Message-ID: <20210503182914.GB50683@orsosgc001.ra.intel.com> (raw)
In-Reply-To: <179288a4d58.2817.c6988b7ea6112e3e892765a0d4287e0c@jlekstrand.net>

On Sat, May 01, 2021 at 10:27:03AM -0500, Jason Ekstrand wrote:
>   On April 30, 2021 23:01:44 "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
>   wrote:
>
>     On Fri, 30 Apr 2021 19:19:59 -0700, Umesh Nerlige Ramappa wrote:
>
>       On Fri, Apr 30, 2021 at 07:35:41PM -0500, Jason Ekstrand wrote:
>
>         On April 30, 2021 18:00:58 "Dixit, Ashutosh"
>         <ashutosh.dixit@intel.com>
>         wrote:
>         On Fri, 30 Apr 2021 15:26:09 -0700, Umesh Nerlige Ramappa wrote:
>         Looks like the engine can be dropped since all timestamps are in
>         sync.
>         I
>         just have one more question here. The timestamp itself is 36 bits.
>          Should
>         the uapi also report the timestamp width to the user OR should I
>         just
>         return the lower 32 bits of the timestamp?
>         Yeah, I think reporting the timestamp width is a good idea since
>         we're
>         reporting the period/frequency here.
>
>       Actually, I forgot that we are handling the overflow before returning
>       the
>       cs_cycles to the user and overflow handling was the only reason I
>       thought
>       user should know the width. Would you stil recommend returning the
>       width in
>       the uapi?
>
>     The width is needed for userspace to figure out if overflow has occured
>     between two successive query calls. I don't think I see this happening
>     in
>     the code.
>
>   Right... We (UMDs) currently just hard-code it to 36 bits because that's
>   what we've had on all platforms since close enough to forever. We bake in
>   the frequency based on PCI ID. Returning the number of bits, like I said,
>   goes nicely with the frequency. It's not necessary, assuming sufficiently
>   smart userspace (neither is frequency), but it seems to go with it. I
>   guess I don't care much either way.
>   Coming back to the multi-tile issue we discussed internally, I think that
>   is something we should care about. Since this works by reading the
>   timestamp register on an engine, I think leaving the engine specifier in
>   there is fine. Userspace should know that there's actually only one clock
>   and just query one of them (probably RCS). For crazy multi-device cases,
>   we'll either query per logical device (read tile) or we'll have to make
>   them look like a single device and sync the timestamps somehow in the UMD
>   by carrying around an offset factor.
>   As is, this patch is
>   Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

Thanks, I will add the width here and post the final version.

Regards,
Umesh

>   I still need to review the ANV patch before we can land this though.
>   --Jason
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