From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: matthew.brost@intel.com, tvrtko.ursulin@intel.com, daniele.ceraolospurio@intel.com, jason.ekstrand@intel.com, jon.bloomfield@intel.com, daniel.vetter@intel.com, john.c.harrison@intel.com Subject: [RFC PATCH 21/97] drm/i915/guc: Update MMIO based communication Date: Thu, 6 May 2021 12:13:35 -0700 [thread overview] Message-ID: <20210506191451.77768-22-matthew.brost@intel.com> (raw) In-Reply-To: <20210506191451.77768-1-matthew.brost@intel.com> From: Michal Wajdeczko <michal.wajdeczko@intel.com> The MMIO based Host-to-GuC communication protocol has been updated to use unified HXG messages. Update our intel_guc_send_mmio() function by correctly handle BUSY, RETRY and FAILURE replies. Also update our documentation. GuC: 55.0.0 Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Cc: Piotr Piórkowski <piotr.piorkowski@intel.com> Cc: Michal Winiarski <michal.winiarski@intel.com> --- .../gt/uc/abi/guc_communication_mmio_abi.h | 47 ++++-------- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 75 ++++++++++++++----- 2 files changed, 70 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h index be066a62e9e0..fef51499386b 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h @@ -7,44 +7,27 @@ #define _ABI_GUC_COMMUNICATION_MMIO_ABI_H /** - * DOC: MMIO based communication + * DOC: GuC MMIO based communication * - * The MMIO based communication between Host and GuC uses software scratch - * registers, where first register holds data treated as message header, - * and other registers are used to hold message payload. + * The MMIO based communication between Host and GuC relies on special + * hardware registers which format could be defined by the software + * (so called scratch registers). * - * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8, - * but no H2G command takes more than 8 parameters and the GuC FW - * itself uses an 8-element array to store the H2G message. - * - * +-----------+---------+---------+---------+ - * | MMIO[0] | MMIO[1] | ... | MMIO[n] | - * +-----------+---------+---------+---------+ - * | header | optional payload | - * +======+====+=========+=========+=========+ - * | 31:28|type| | | | - * +------+----+ | | | - * | 27:16|data| | | | - * +------+----+ | | | - * | 15:0|code| | | | - * +------+----+---------+---------+---------+ + * Each MMIO based message, both Host to GuC (H2G) and GuC to Host (G2H) + * messages, which maximum length depends on number of available scratch + * registers, is directly written into those scratch registers. * - * The message header consists of: - * - * - **type**, indicates message type - * - **code**, indicates message code, is specific for **type** - * - **data**, indicates message data, optional, depends on **code** + * For Gen9+, there are 16 software scratch registers 0xC180-0xC1B8, + * but no H2G command takes more than 8 parameters and the GuC firmware + * itself uses an 8-element array to store the H2G message. * - * The following message **types** are supported: + * For Gen11+, there are additional 4 registers 0x190240-0x19024C, which + * are, regardless on lower count, preffered over legacy ones. * - * - **REQUEST**, indicates Host-to-GuC request, requested GuC action code - * must be priovided in **code** field. Optional action specific parameters - * can be provided in remaining payload registers or **data** field. + * The MMIO based communication is mainly used during driver initialization + * phase to setup the CTB based communication that will be used afterwards. * - * - **RESPONSE**, indicates GuC-to-Host response from earlier GuC request, - * action response status will be provided in **code** field. Optional - * response data can be returned in remaining payload registers or **data** - * field. + * Format of the MMIO messages follows definitions of `HXG Message`_. */ #define GUC_MAX_MMIO_MSG_LEN 8 diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index ab2c8fe8cdfa..454c8d886499 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -385,29 +385,27 @@ void intel_guc_fini(struct intel_guc *guc) /* * This function implements the MMIO based host to GuC interface. */ -int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, +int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len, u32 *response_buf, u32 response_buf_size) { + struct drm_i915_private *i915 = guc_to_gt(guc)->i915; struct intel_uncore *uncore = guc_to_gt(guc)->uncore; - u32 status; + u32 header; int i; int ret; GEM_BUG_ON(!len); GEM_BUG_ON(len > guc->send_regs.count); - /* We expect only action code */ - GEM_BUG_ON(*action & ~INTEL_GUC_MSG_CODE_MASK); - - /* If CT is available, we expect to use MMIO only during init/fini */ - GEM_BUG_ON(*action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER && - *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER); + GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) != GUC_HXG_ORIGIN_HOST); + GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) != GUC_HXG_TYPE_REQUEST); mutex_lock(&guc->send_mutex); intel_uncore_forcewake_get(uncore, guc->send_regs.fw_domains); +retry: for (i = 0; i < len; i++) - intel_uncore_write(uncore, guc_send_reg(guc, i), action[i]); + intel_uncore_write(uncore, guc_send_reg(guc, i), request[i]); intel_uncore_posting_read(uncore, guc_send_reg(guc, i - 1)); @@ -419,17 +417,54 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, */ ret = __intel_wait_for_register_fw(uncore, guc_send_reg(guc, 0), - INTEL_GUC_MSG_TYPE_MASK, - INTEL_GUC_MSG_TYPE_RESPONSE << - INTEL_GUC_MSG_TYPE_SHIFT, - 10, 10, &status); - /* If GuC explicitly returned an error, convert it to -EIO */ - if (!ret && !INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(status)) - ret = -EIO; + GUC_HXG_MSG_0_ORIGIN, + FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, + GUC_HXG_ORIGIN_GUC), + 10, 10, &header); + if (unlikely(ret)) { +timeout: + drm_err(&i915->drm, "mmio request %#x: no reply %x\n", + request[0], header); + goto out; + } - if (ret) { - DRM_ERROR("MMIO: GuC action %#x failed with error %d %#x\n", - action[0], ret, status); + if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_BUSY) { +#define done ({ header = intel_uncore_read(uncore, guc_send_reg(guc, 0)); \ + FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != GUC_HXG_ORIGIN_GUC || \ + FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_NO_RESPONSE_BUSY; }) + + ret = wait_for(done, 1000); + if (unlikely(ret)) + goto timeout; + if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != + GUC_HXG_ORIGIN_GUC)) + goto proto; +#undef done + } + + if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) { + u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header); + + drm_dbg(&i915->drm, "mmio request %#x: retrying, reason %u\n", + request[0], reason); + goto retry; + } + + if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_RESPONSE_FAILURE) { + u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header); + u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header); + + drm_err(&i915->drm, "mmio request %#x: failure %x/%u\n", + request[0], error, hint); + ret = -ENXIO; + goto out; + } + + if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_RESPONSE_SUCCESS) { +proto: + drm_err(&i915->drm, "mmio request %#x: unexpected reply %#x\n", + request[0], header); + ret = -EPROTO; goto out; } @@ -442,7 +477,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, } /* Use data from the GuC response as our return value */ - ret = INTEL_GUC_MSG_TO_DATA(status); + ret = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header); out: intel_uncore_forcewake_put(uncore, guc->send_regs.fw_domains); -- 2.28.0
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: jason.ekstrand@intel.com, daniel.vetter@intel.com Subject: [Intel-gfx] [RFC PATCH 21/97] drm/i915/guc: Update MMIO based communication Date: Thu, 6 May 2021 12:13:35 -0700 [thread overview] Message-ID: <20210506191451.77768-22-matthew.brost@intel.com> (raw) In-Reply-To: <20210506191451.77768-1-matthew.brost@intel.com> From: Michal Wajdeczko <michal.wajdeczko@intel.com> The MMIO based Host-to-GuC communication protocol has been updated to use unified HXG messages. Update our intel_guc_send_mmio() function by correctly handle BUSY, RETRY and FAILURE replies. Also update our documentation. GuC: 55.0.0 Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Cc: Piotr Piórkowski <piotr.piorkowski@intel.com> Cc: Michal Winiarski <michal.winiarski@intel.com> --- .../gt/uc/abi/guc_communication_mmio_abi.h | 47 ++++-------- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 75 ++++++++++++++----- 2 files changed, 70 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h index be066a62e9e0..fef51499386b 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h @@ -7,44 +7,27 @@ #define _ABI_GUC_COMMUNICATION_MMIO_ABI_H /** - * DOC: MMIO based communication + * DOC: GuC MMIO based communication * - * The MMIO based communication between Host and GuC uses software scratch - * registers, where first register holds data treated as message header, - * and other registers are used to hold message payload. + * The MMIO based communication between Host and GuC relies on special + * hardware registers which format could be defined by the software + * (so called scratch registers). * - * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8, - * but no H2G command takes more than 8 parameters and the GuC FW - * itself uses an 8-element array to store the H2G message. - * - * +-----------+---------+---------+---------+ - * | MMIO[0] | MMIO[1] | ... | MMIO[n] | - * +-----------+---------+---------+---------+ - * | header | optional payload | - * +======+====+=========+=========+=========+ - * | 31:28|type| | | | - * +------+----+ | | | - * | 27:16|data| | | | - * +------+----+ | | | - * | 15:0|code| | | | - * +------+----+---------+---------+---------+ + * Each MMIO based message, both Host to GuC (H2G) and GuC to Host (G2H) + * messages, which maximum length depends on number of available scratch + * registers, is directly written into those scratch registers. * - * The message header consists of: - * - * - **type**, indicates message type - * - **code**, indicates message code, is specific for **type** - * - **data**, indicates message data, optional, depends on **code** + * For Gen9+, there are 16 software scratch registers 0xC180-0xC1B8, + * but no H2G command takes more than 8 parameters and the GuC firmware + * itself uses an 8-element array to store the H2G message. * - * The following message **types** are supported: + * For Gen11+, there are additional 4 registers 0x190240-0x19024C, which + * are, regardless on lower count, preffered over legacy ones. * - * - **REQUEST**, indicates Host-to-GuC request, requested GuC action code - * must be priovided in **code** field. Optional action specific parameters - * can be provided in remaining payload registers or **data** field. + * The MMIO based communication is mainly used during driver initialization + * phase to setup the CTB based communication that will be used afterwards. * - * - **RESPONSE**, indicates GuC-to-Host response from earlier GuC request, - * action response status will be provided in **code** field. Optional - * response data can be returned in remaining payload registers or **data** - * field. + * Format of the MMIO messages follows definitions of `HXG Message`_. */ #define GUC_MAX_MMIO_MSG_LEN 8 diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index ab2c8fe8cdfa..454c8d886499 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -385,29 +385,27 @@ void intel_guc_fini(struct intel_guc *guc) /* * This function implements the MMIO based host to GuC interface. */ -int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, +int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len, u32 *response_buf, u32 response_buf_size) { + struct drm_i915_private *i915 = guc_to_gt(guc)->i915; struct intel_uncore *uncore = guc_to_gt(guc)->uncore; - u32 status; + u32 header; int i; int ret; GEM_BUG_ON(!len); GEM_BUG_ON(len > guc->send_regs.count); - /* We expect only action code */ - GEM_BUG_ON(*action & ~INTEL_GUC_MSG_CODE_MASK); - - /* If CT is available, we expect to use MMIO only during init/fini */ - GEM_BUG_ON(*action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER && - *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER); + GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) != GUC_HXG_ORIGIN_HOST); + GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) != GUC_HXG_TYPE_REQUEST); mutex_lock(&guc->send_mutex); intel_uncore_forcewake_get(uncore, guc->send_regs.fw_domains); +retry: for (i = 0; i < len; i++) - intel_uncore_write(uncore, guc_send_reg(guc, i), action[i]); + intel_uncore_write(uncore, guc_send_reg(guc, i), request[i]); intel_uncore_posting_read(uncore, guc_send_reg(guc, i - 1)); @@ -419,17 +417,54 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, */ ret = __intel_wait_for_register_fw(uncore, guc_send_reg(guc, 0), - INTEL_GUC_MSG_TYPE_MASK, - INTEL_GUC_MSG_TYPE_RESPONSE << - INTEL_GUC_MSG_TYPE_SHIFT, - 10, 10, &status); - /* If GuC explicitly returned an error, convert it to -EIO */ - if (!ret && !INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(status)) - ret = -EIO; + GUC_HXG_MSG_0_ORIGIN, + FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, + GUC_HXG_ORIGIN_GUC), + 10, 10, &header); + if (unlikely(ret)) { +timeout: + drm_err(&i915->drm, "mmio request %#x: no reply %x\n", + request[0], header); + goto out; + } - if (ret) { - DRM_ERROR("MMIO: GuC action %#x failed with error %d %#x\n", - action[0], ret, status); + if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_BUSY) { +#define done ({ header = intel_uncore_read(uncore, guc_send_reg(guc, 0)); \ + FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != GUC_HXG_ORIGIN_GUC || \ + FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_NO_RESPONSE_BUSY; }) + + ret = wait_for(done, 1000); + if (unlikely(ret)) + goto timeout; + if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != + GUC_HXG_ORIGIN_GUC)) + goto proto; +#undef done + } + + if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) { + u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header); + + drm_dbg(&i915->drm, "mmio request %#x: retrying, reason %u\n", + request[0], reason); + goto retry; + } + + if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_RESPONSE_FAILURE) { + u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header); + u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header); + + drm_err(&i915->drm, "mmio request %#x: failure %x/%u\n", + request[0], error, hint); + ret = -ENXIO; + goto out; + } + + if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_RESPONSE_SUCCESS) { +proto: + drm_err(&i915->drm, "mmio request %#x: unexpected reply %#x\n", + request[0], header); + ret = -EPROTO; goto out; } @@ -442,7 +477,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, } /* Use data from the GuC response as our return value */ - ret = INTEL_GUC_MSG_TO_DATA(status); + ret = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header); out: intel_uncore_forcewake_put(uncore, guc->send_regs.fw_domains); -- 2.28.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-05-06 18:58 UTC|newest] Thread overview: 504+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-06 19:13 [RFC PATCH 00/97] Basic GuC submission support in the i915 Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:12 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for " Patchwork 2021-05-06 19:13 ` [RFC PATCH 01/97] drm/i915/gt: Move engine setup out of set_default_submission Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-19 0:25 ` Matthew Brost 2021-05-19 0:25 ` [Intel-gfx] " Matthew Brost 2021-05-25 8:44 ` Tvrtko Ursulin 2021-05-25 8:44 ` Tvrtko Ursulin 2021-05-06 19:13 ` [RFC PATCH 02/97] drm/i915/gt: Move submission_method into intel_gt Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-19 3:10 ` Matthew Brost 2021-05-19 3:10 ` [Intel-gfx] " Matthew Brost 2021-05-25 8:44 ` Tvrtko Ursulin 2021-05-25 8:44 ` Tvrtko Ursulin 2021-05-06 19:13 ` [RFC PATCH 03/97] drm/i915/gt: Move CS interrupt handler to the backend Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-19 3:31 ` Matthew Brost 2021-05-19 3:31 ` [Intel-gfx] " Matthew Brost 2021-05-25 8:45 ` Tvrtko Ursulin 2021-05-25 8:45 ` Tvrtko Ursulin 2021-05-06 19:13 ` [RFC PATCH 04/97] drm/i915/guc: skip disabling CTBs before sanitizing the GuC Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-20 16:47 ` Matthew Brost 2021-05-20 16:47 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 05/97] drm/i915/guc: use probe_error log for CT enablement failure Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 10:30 ` Michal Wajdeczko 2021-05-24 10:30 ` [Intel-gfx] " Michal Wajdeczko 2021-05-06 19:13 ` [RFC PATCH 06/97] drm/i915/guc: enable only the user interrupt when using GuC submission Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 0:31 ` Matthew Brost 2021-05-25 0:31 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 07/97] drm/i915/guc: Remove sample_forcewake h2g action Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 10:48 ` Michal Wajdeczko 2021-05-24 10:48 ` [Intel-gfx] " Michal Wajdeczko 2021-05-25 0:36 ` Matthew Brost 2021-05-25 0:36 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 08/97] drm/i915/guc: Keep strict GuC ABI definitions Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 23:52 ` Michał Winiarski 2021-05-24 23:52 ` [Intel-gfx] " Michał Winiarski 2021-05-06 19:13 ` [RFC PATCH 09/97] drm/i915/guc: Stop using fence/status from CTB descriptor Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 2:38 ` Matthew Brost 2021-05-25 2:38 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 10/97] drm/i915: Promote ptrdiff() to i915_utils.h Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 0:42 ` Matthew Brost 2021-05-25 0:42 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 11/97] drm/i915/guc: Only rely on own CTB size Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 2:47 ` Matthew Brost 2021-05-25 2:47 ` [Intel-gfx] " Matthew Brost 2021-05-25 12:48 ` Michal Wajdeczko 2021-05-25 12:48 ` Michal Wajdeczko 2021-05-06 19:13 ` [RFC PATCH 12/97] drm/i915/guc: Don't repeat CTB layout calculations Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 2:53 ` Matthew Brost 2021-05-25 2:53 ` [Intel-gfx] " Matthew Brost 2021-05-25 13:07 ` Michal Wajdeczko 2021-05-25 13:07 ` [Intel-gfx] " Michal Wajdeczko 2021-05-25 16:56 ` Matthew Brost 2021-05-25 16:56 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 13/97] drm/i915/guc: Replace CTB array with explicit members Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 3:15 ` Matthew Brost 2021-05-25 3:15 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 14/97] drm/i915/guc: Update sizes of CTB buffers Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 2:56 ` Matthew Brost 2021-05-25 2:56 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 15/97] drm/i915/guc: Relax CTB response timeout Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 18:08 ` Matthew Brost 2021-05-25 18:08 ` [Intel-gfx] " Matthew Brost 2021-05-25 19:37 ` Michal Wajdeczko 2021-05-25 19:37 ` Michal Wajdeczko 2021-05-06 19:13 ` [RFC PATCH 16/97] drm/i915/guc: Start protecting access to CTB descriptors Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 3:21 ` Matthew Brost 2021-05-25 3:21 ` [Intel-gfx] " Matthew Brost 2021-05-25 13:10 ` Michal Wajdeczko 2021-05-25 3:21 ` Matthew Brost 2021-05-25 3:21 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 17/97] drm/i915/guc: Stop using mutex while sending CTB messages Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 16:14 ` Matthew Brost 2021-05-25 16:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 18/97] drm/i915/guc: Don't receive all G2H messages in irq handler Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 18:15 ` Matthew Brost 2021-05-25 18:15 ` [Intel-gfx] " Matthew Brost 2021-05-25 19:43 ` Michal Wajdeczko 2021-05-25 19:43 ` Michal Wajdeczko 2021-05-06 19:13 ` [RFC PATCH 19/97] drm/i915/guc: Always copy CT message to new allocation Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 18:25 ` Matthew Brost 2021-05-25 18:25 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 20/97] drm/i915/guc: Introduce unified HXG messages Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-11 15:16 ` Daniel Vetter 2021-05-11 15:16 ` [Intel-gfx] " Daniel Vetter 2021-05-11 17:59 ` Matthew Brost 2021-05-11 17:59 ` [Intel-gfx] " Matthew Brost 2021-05-11 22:11 ` Michal Wajdeczko 2021-05-11 22:11 ` [Intel-gfx] " Michal Wajdeczko 2021-05-12 8:40 ` Daniel Vetter 2021-05-12 8:40 ` [Intel-gfx] " Daniel Vetter 2021-05-06 19:13 ` Matthew Brost [this message] 2021-05-06 19:13 ` [Intel-gfx] [RFC PATCH 21/97] drm/i915/guc: Update MMIO based communication Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 22/97] drm/i915/guc: Update CTB response status Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 23/97] drm/i915/guc: Support per context scheduling policies Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 1:15 ` Matthew Brost 2021-05-25 1:15 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 24/97] drm/i915/guc: Add flag for mark broken CTB Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-27 19:44 ` Matthew Brost 2021-05-27 19:44 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 25/97] drm/i915/guc: New definition of the CTB descriptor Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 26/97] drm/i915/guc: New definition of the CTB registration action Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 27/97] drm/i915/guc: New CTB based communication Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 28/97] drm/i915/guc: Kill guc_clients.ct_pool Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 1:01 ` Matthew Brost 2021-05-25 1:01 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 29/97] drm/i915/guc: Update firmware to v60.1.2 Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 30/97] drm/i915/uc: turn on GuC/HuC auto mode by default Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 11:00 ` Michal Wajdeczko 2021-05-24 11:00 ` [Intel-gfx] " Michal Wajdeczko 2021-05-06 19:13 ` [RFC PATCH 31/97] drm/i915/guc: Early initialization of GuC send registers Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-26 20:28 ` Matthew Brost 2021-05-26 20:28 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 32/97] drm/i915: Introduce i915_sched_engine object Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-11 15:18 ` Daniel Vetter 2021-05-11 15:18 ` [Intel-gfx] " Daniel Vetter 2021-05-11 17:56 ` Matthew Brost 2021-05-11 17:56 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 33/97] drm/i915: Engine relative MMIO Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 9:05 ` Tvrtko Ursulin 2021-05-25 9:05 ` Tvrtko Ursulin 2021-05-06 19:13 ` [RFC PATCH 34/97] drm/i915/guc: Use guc_class instead of engine_class in fw interface Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-26 20:41 ` Matthew Brost 2021-05-26 20:41 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 35/97] drm/i915/guc: Improve error message for unsolicited CT response Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 11:59 ` Michal Wajdeczko 2021-05-24 11:59 ` [Intel-gfx] " Michal Wajdeczko 2021-05-25 17:32 ` Matthew Brost 2021-05-25 17:32 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 36/97] drm/i915/guc: Add non blocking CTB send function Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 12:21 ` Michal Wajdeczko 2021-05-24 12:21 ` [Intel-gfx] " Michal Wajdeczko 2021-05-25 17:30 ` Matthew Brost 2021-05-25 17:30 ` [Intel-gfx] " Matthew Brost 2021-05-25 9:21 ` Tvrtko Ursulin 2021-05-25 9:21 ` Tvrtko Ursulin 2021-05-25 17:21 ` Matthew Brost 2021-05-25 17:21 ` Matthew Brost 2021-05-26 8:57 ` Tvrtko Ursulin 2021-05-26 8:57 ` Tvrtko Ursulin 2021-05-26 18:10 ` Matthew Brost 2021-05-26 18:10 ` Matthew Brost 2021-05-27 10:02 ` Tvrtko Ursulin 2021-05-27 10:02 ` Tvrtko Ursulin 2021-05-27 14:35 ` Matthew Brost 2021-05-27 14:35 ` Matthew Brost 2021-05-27 15:11 ` Tvrtko Ursulin 2021-05-27 15:11 ` Tvrtko Ursulin 2021-06-07 17:31 ` Matthew Brost 2021-06-07 17:31 ` Matthew Brost 2021-06-08 8:39 ` Tvrtko Ursulin 2021-06-08 8:39 ` Tvrtko Ursulin 2021-06-08 8:46 ` Daniel Vetter 2021-06-08 8:46 ` Daniel Vetter 2021-06-09 23:10 ` Matthew Brost 2021-06-09 23:10 ` Matthew Brost 2021-06-10 15:27 ` Daniel Vetter 2021-06-10 15:27 ` Daniel Vetter 2021-06-24 16:38 ` Matthew Brost 2021-06-24 16:38 ` Matthew Brost 2021-06-24 17:25 ` Daniel Vetter 2021-06-24 17:25 ` Daniel Vetter 2021-06-09 13:58 ` Michal Wajdeczko 2021-06-09 13:58 ` Michal Wajdeczko 2021-06-09 23:05 ` Matthew Brost 2021-06-09 23:05 ` Matthew Brost 2021-06-09 14:14 ` Michal Wajdeczko 2021-06-09 14:14 ` Michal Wajdeczko 2021-06-09 23:13 ` Matthew Brost 2021-06-09 23:13 ` Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 37/97] drm/i915/guc: Add stall timer to " Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 12:58 ` Michal Wajdeczko 2021-05-24 12:58 ` [Intel-gfx] " Michal Wajdeczko 2021-05-24 18:35 ` Matthew Brost 2021-05-24 18:35 ` [Intel-gfx] " Matthew Brost 2021-05-25 14:15 ` Michal Wajdeczko 2021-05-25 14:15 ` [Intel-gfx] " Michal Wajdeczko 2021-05-25 16:54 ` Matthew Brost 2021-05-25 16:54 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 38/97] drm/i915/guc: Optimize CTB writes and reads Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 13:31 ` Michal Wajdeczko 2021-05-24 13:31 ` [Intel-gfx] " Michal Wajdeczko 2021-05-25 17:39 ` Matthew Brost 2021-05-25 17:39 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 39/97] drm/i915/guc: Increase size of CTB buffers Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 13:43 ` Michal Wajdeczko 2021-05-24 13:43 ` Michal Wajdeczko 2021-05-24 18:40 ` Matthew Brost 2021-05-24 18:40 ` Matthew Brost 2021-05-25 9:24 ` Tvrtko Ursulin 2021-05-25 9:24 ` Tvrtko Ursulin 2021-05-25 17:15 ` Matthew Brost 2021-05-25 17:15 ` Matthew Brost 2021-05-26 9:30 ` Tvrtko Ursulin 2021-05-26 9:30 ` Tvrtko Ursulin 2021-05-26 18:20 ` Matthew Brost 2021-05-26 18:20 ` Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 40/97] drm/i915/guc: Module load failure test for CT buffer creation Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-24 13:45 ` Michal Wajdeczko 2021-05-24 13:45 ` [Intel-gfx] " Michal Wajdeczko 2021-05-06 19:13 ` [RFC PATCH 41/97] drm/i915/guc: Add new GuC interface defines and structures Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 42/97] drm/i915/guc: Remove GuC stage descriptor, add lrc descriptor Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 43/97] drm/i915/guc: Add lrc descriptor context lookup array Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-11 15:26 ` Daniel Vetter 2021-05-11 15:26 ` [Intel-gfx] " Daniel Vetter 2021-05-11 17:01 ` Matthew Brost 2021-05-11 17:01 ` [Intel-gfx] " Matthew Brost 2021-05-11 17:43 ` Daniel Vetter 2021-05-11 17:43 ` [Intel-gfx] " Daniel Vetter 2021-05-11 19:34 ` Matthew Brost 2021-05-11 19:34 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 44/97] drm/i915/guc: Implement GuC submission tasklet Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-25 9:43 ` Tvrtko Ursulin 2021-05-25 9:43 ` Tvrtko Ursulin 2021-05-25 17:10 ` Matthew Brost 2021-05-25 17:10 ` Matthew Brost 2021-05-06 19:13 ` [RFC PATCH 45/97] drm/i915/guc: Add bypass tasklet submission path to GuC Matthew Brost 2021-05-06 19:13 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 46/97] drm/i915/guc: Implement GuC context operations for new inteface Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-29 20:32 ` Michal Wajdeczko 2021-05-29 20:32 ` [Intel-gfx] " Michal Wajdeczko 2021-05-06 19:14 ` [RFC PATCH 47/97] drm/i915/guc: Insert fence on context when deregistering Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 48/97] drm/i915/guc: Defer context unpin until scheduling is disabled Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 49/97] drm/i915/guc: Disable engine barriers with GuC during unpin Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-11 15:37 ` Daniel Vetter 2021-05-11 15:37 ` [Intel-gfx] " Daniel Vetter 2021-05-11 16:31 ` Matthew Brost 2021-05-11 16:31 ` [Intel-gfx] " Matthew Brost 2021-05-26 10:26 ` Tvrtko Ursulin 2021-05-26 10:26 ` Tvrtko Ursulin 2021-05-06 19:14 ` [RFC PATCH 50/97] drm/i915/guc: Extend deregistration fence to schedule disable Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 51/97] drm/i915: Disable preempt busywait when using GuC scheduling Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 52/97] drm/i915/guc: Ensure request ordering via completion fences Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 53/97] drm/i915/guc: Disable semaphores when using GuC scheduling Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-25 9:52 ` Tvrtko Ursulin 2021-05-25 9:52 ` Tvrtko Ursulin 2021-05-25 17:01 ` Matthew Brost 2021-05-25 17:01 ` Matthew Brost 2021-05-26 9:25 ` Tvrtko Ursulin 2021-05-26 9:25 ` Tvrtko Ursulin 2021-05-26 18:15 ` Matthew Brost 2021-05-26 18:15 ` Matthew Brost 2021-05-27 8:41 ` Tvrtko Ursulin 2021-05-27 8:41 ` Tvrtko Ursulin 2021-05-27 14:38 ` Matthew Brost 2021-05-27 14:38 ` Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 54/97] drm/i915/guc: Ensure G2H response has space in buffer Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 55/97] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-07 5:56 ` kernel test robot 2021-05-25 10:06 ` Tvrtko Ursulin 2021-05-25 10:06 ` Tvrtko Ursulin 2021-05-25 17:07 ` Matthew Brost 2021-05-25 17:07 ` Matthew Brost 2021-05-26 9:21 ` Tvrtko Ursulin 2021-05-26 9:21 ` Tvrtko Ursulin 2021-05-26 18:18 ` Matthew Brost 2021-05-26 18:18 ` Matthew Brost 2021-05-27 9:02 ` Tvrtko Ursulin 2021-05-27 9:02 ` Tvrtko Ursulin 2021-05-27 14:37 ` Matthew Brost 2021-05-27 14:37 ` Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 56/97] drm/i915/guc: Update GuC debugfs to support new GuC Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 57/97] drm/i915/guc: Add several request trace points Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 58/97] drm/i915: Add intel_context tracing Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 59/97] drm/i915/guc: GuC virtual engines Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 60/97] drm/i915: Track 'serial' counts for " Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-25 10:16 ` Tvrtko Ursulin 2021-05-25 10:16 ` Tvrtko Ursulin 2021-05-25 17:52 ` Matthew Brost 2021-05-25 17:52 ` Matthew Brost 2021-05-26 8:40 ` Tvrtko Ursulin 2021-05-26 8:40 ` Tvrtko Ursulin 2021-05-26 18:45 ` John Harrison 2021-05-26 18:45 ` John Harrison 2021-05-27 8:53 ` Tvrtko Ursulin 2021-05-27 8:53 ` Tvrtko Ursulin 2021-05-27 17:01 ` John Harrison 2021-05-27 17:01 ` John Harrison 2021-06-01 9:31 ` Tvrtko Ursulin 2021-06-01 9:31 ` Tvrtko Ursulin 2021-06-02 1:20 ` John Harrison 2021-06-02 1:20 ` John Harrison 2021-06-02 12:04 ` Tvrtko Ursulin 2021-06-02 12:04 ` Tvrtko Ursulin 2021-06-02 12:09 ` Tvrtko Ursulin 2021-06-02 12:09 ` Tvrtko Ursulin 2021-05-06 19:14 ` [RFC PATCH 61/97] drm/i915: Hold reference to intel_context over life of i915_request Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-06-02 12:18 ` Tvrtko Ursulin 2021-06-02 12:18 ` Tvrtko Ursulin 2021-05-06 19:14 ` [RFC PATCH 62/97] drm/i915/guc: Disable bonding extension with GuC submission Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 63/97] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-06-02 13:31 ` Tvrtko Ursulin 2021-06-02 13:31 ` Tvrtko Ursulin 2021-05-06 19:14 ` [RFC PATCH 64/97] drm/i915/guc: Reset implementation for new GuC interface Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-06-02 14:33 ` Tvrtko Ursulin 2021-06-02 14:33 ` Tvrtko Ursulin 2021-06-04 3:17 ` Matthew Brost 2021-06-04 3:17 ` Matthew Brost 2021-06-04 8:16 ` Daniel Vetter 2021-06-04 8:16 ` Daniel Vetter 2021-06-04 18:02 ` Matthew Brost 2021-06-04 18:02 ` Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 65/97] drm/i915: Reset GPU immediately if submission is disabled Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-06-02 14:36 ` Tvrtko Ursulin 2021-06-02 14:36 ` Tvrtko Ursulin 2021-05-06 19:14 ` [RFC PATCH 66/97] drm/i915/guc: Add disable interrupts to guc sanitize Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-11 8:16 ` [drm/i915/guc] 07336fb545: WARNING:at_drivers/gpu/drm/i915/gt/uc/intel_uc.c:#__uc_sanitize[i915] kernel test robot 2021-05-11 8:16 ` kernel test robot 2021-05-11 8:16 ` [Intel-gfx] " kernel test robot 2021-05-11 8:16 ` kernel test robot 2021-05-06 19:14 ` [RFC PATCH 67/97] drm/i915/guc: Suspend/resume implementation for new interface Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 68/97] drm/i915/guc: Handle context reset notification Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-11 16:25 ` Daniel Vetter 2021-05-11 16:25 ` Daniel Vetter 2021-05-06 19:14 ` [RFC PATCH 69/97] drm/i915/guc: Handle engine reset failure notification Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 70/97] drm/i915/guc: Enable the timer expired interrupt for GuC Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 71/97] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 72/97] drm/i915/guc: Don't complain about reset races Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 73/97] drm/i915/guc: Enable GuC engine reset Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 74/97] drm/i915/guc: Capture error state on context reset Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-11 16:28 ` Daniel Vetter 2021-05-11 16:28 ` Daniel Vetter 2021-05-11 17:12 ` Matthew Brost 2021-05-11 17:12 ` Matthew Brost 2021-05-11 17:45 ` Daniel Vetter 2021-05-11 17:45 ` Daniel Vetter 2021-05-06 19:14 ` [RFC PATCH 75/97] drm/i915/guc: Fix for error capture after full GPU reset with GuC Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 76/97] drm/i915/guc: Hook GuC scheduling policies up Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 77/97] drm/i915/guc: Connect reset modparam updates to GuC policy flags Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 78/97] drm/i915/guc: Include scheduling policies in the debugfs state dump Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 79/97] drm/i915/guc: Don't call ring_is_idle in GuC submission Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 80/97] drm/i915/guc: Implement banned contexts for " Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 81/97] drm/i915/guc: Allow flexible number of context ids Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 82/97] drm/i915/guc: Connect the number of guc_ids to debugfs Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 83/97] drm/i915/guc: Don't return -EAGAIN to user when guc_ids exhausted Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-07 6:06 ` kernel test robot 2021-05-06 19:14 ` [RFC PATCH 84/97] drm/i915/guc: Don't allow requests not ready to consume all guc_ids Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 85/97] drm/i915/guc: Introduce guc_submit_engine object Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 86/97] drm/i915/guc: Add golden context to GuC ADS Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 87/97] drm/i915/guc: Implement GuC priority management Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 88/97] drm/i915/guc: Support request cancellation Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 89/97] drm/i915/guc: Check return of __xa_store when registering a context Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 90/97] drm/i915/guc: Non-static lrc descriptor registration buffer Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 91/97] drm/i915/guc: Take GT PM ref when deregistering context Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 92/97] drm/i915: Add GT PM delayed worker Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 93/97] drm/i915/guc: Take engine PM when a context is pinned with GuC submission Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 94/97] drm/i915/guc: Don't call switch_to_kernel_context " Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 95/97] drm/i915/guc: Selftest for GuC flow control Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 96/97] drm/i915/guc: Update GuC documentation Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-06 19:14 ` [RFC PATCH 97/97] drm/i915/guc: Unblock GuC submission on Gen11+ Matthew Brost 2021-05-06 19:14 ` [Intel-gfx] " Matthew Brost 2021-05-09 17:12 ` [RFC PATCH 00/97] Basic GuC submission support in the i915 Martin Peres 2021-05-09 17:12 ` [Intel-gfx] " Martin Peres 2021-05-09 23:11 ` Jason Ekstrand 2021-05-09 23:11 ` [Intel-gfx] " Jason Ekstrand 2021-05-10 13:55 ` Martin Peres 2021-05-10 13:55 ` [Intel-gfx] " Martin Peres 2021-05-10 16:25 ` Jason Ekstrand 2021-05-10 16:25 ` [Intel-gfx] " Jason Ekstrand 2021-05-11 8:01 ` Martin Peres 2021-05-11 8:01 ` [Intel-gfx] " Martin Peres 2021-05-10 16:33 ` Daniel Vetter 2021-05-10 16:33 ` [Intel-gfx] " Daniel Vetter 2021-05-10 18:30 ` Francisco Jerez 2021-05-10 18:30 ` Francisco Jerez 2021-05-11 8:06 ` Martin Peres 2021-05-11 8:06 ` [Intel-gfx] " Martin Peres 2021-05-11 15:26 ` Bloomfield, Jon 2021-05-11 15:26 ` [Intel-gfx] " Bloomfield, Jon 2021-05-11 16:39 ` Matthew Brost 2021-05-11 16:39 ` [Intel-gfx] " Matthew Brost 2021-05-12 6:26 ` Martin Peres 2021-05-12 6:26 ` [Intel-gfx] " Martin Peres 2021-05-14 16:31 ` Jason Ekstrand 2021-05-14 16:31 ` [Intel-gfx] " Jason Ekstrand 2021-05-25 15:37 ` Alex Deucher 2021-05-25 15:37 ` [Intel-gfx] " Alex Deucher 2021-05-11 2:58 ` Dixit, Ashutosh 2021-05-11 2:58 ` [Intel-gfx] " Dixit, Ashutosh 2021-05-11 7:47 ` Martin Peres 2021-05-11 7:47 ` [Intel-gfx] " Martin Peres 2021-05-14 11:11 ` Tvrtko Ursulin 2021-05-14 11:11 ` Tvrtko Ursulin 2021-05-14 16:36 ` Jason Ekstrand 2021-05-14 16:36 ` Jason Ekstrand 2021-05-14 16:46 ` Matthew Brost 2021-05-14 16:46 ` Matthew Brost 2021-05-14 16:41 ` Matthew Brost 2021-05-14 16:41 ` Matthew Brost 2021-05-25 10:32 ` Tvrtko Ursulin 2021-05-25 10:32 ` Tvrtko Ursulin 2021-05-25 16:45 ` Matthew Brost 2021-05-25 16:45 ` Matthew Brost 2021-06-02 15:27 ` Tvrtko Ursulin 2021-06-02 15:27 ` Tvrtko Ursulin 2021-06-02 18:57 ` Daniel Vetter 2021-06-02 18:57 ` Daniel Vetter 2021-06-03 3:41 ` Matthew Brost 2021-06-03 3:41 ` Matthew Brost 2021-06-03 4:47 ` Daniel Vetter 2021-06-03 4:47 ` Daniel Vetter 2021-06-03 9:49 ` Tvrtko Ursulin 2021-06-03 9:49 ` Tvrtko Ursulin 2021-06-03 10:52 ` Tvrtko Ursulin 2021-06-03 10:52 ` Tvrtko Ursulin 2021-06-03 4:10 ` Matthew Brost 2021-06-03 4:10 ` Matthew Brost 2021-06-03 8:51 ` Tvrtko Ursulin 2021-06-03 8:51 ` Tvrtko Ursulin 2021-06-03 16:34 ` Matthew Brost 2021-06-03 16:34 ` Matthew Brost
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