* [PATCH 01/12] firmware: ti_sci: Update ti_sci_cmd_rm_udmap_tx_ch_cfg() API to the latest
2021-05-10 14:36 [PATCH 00/12] AM64x: DMA and ethernet support Vignesh Raghavendra
@ 2021-05-10 14:36 ` Vignesh Raghavendra
2021-05-10 14:36 ` [PATCH 02/12] soc: ti: k3-navss-ringacc: Add AM64 ringacc support Vignesh Raghavendra
` (11 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Vignesh Raghavendra @ 2021-05-10 14:36 UTC (permalink / raw)
To: u-boot
Update struct ti_sci_msg_rm_udmap_tx_ch_cfg_req to latest ABI to support
AM64x BCDMA Block copy channels.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
drivers/firmware/ti_sci.c | 3 +++
drivers/firmware/ti_sci.h | 18 ++++++++++++++++++
include/linux/soc/ti/ti_sci_protocol.h | 14 ++++++++++++++
3 files changed, 35 insertions(+)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index 0cdfb0e91a..2aec2e34d3 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -2466,6 +2466,9 @@ static int ti_sci_cmd_rm_udmap_tx_ch_cfg(
req.tx_orderid = params->tx_orderid;
req.fdepth = params->fdepth;
req.tx_sched_priority = params->tx_sched_priority;
+ req.tx_burst_size = params->tx_burst_size;
+ req.tx_tdtype = params->tx_tdtype;
+ req.extended_ch_type = params->extended_ch_type;
ret = ti_sci_do_xfer(info, xfer);
if (ret) {
diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
index 327bb820f3..eec488f065 100644
--- a/drivers/firmware/ti_sci.h
+++ b/drivers/firmware/ti_sci.h
@@ -998,6 +998,9 @@ struct ti_sci_msg_psil_unpair {
* 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt
* 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
* 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
+ * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size
+ * 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype
+ * 16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type
*
* @nav_id: SoC device ID of Navigator Subsystem where tx channel is located
*
@@ -1058,6 +1061,18 @@ struct ti_sci_msg_psil_unpair {
* @tx_sched_priority: UDMAP transmit channel tx scheduling priority
* configuration to be programmed into the priority field of the channel's
* TCHAN_TST_SCHED register.
+ *
+ * @tx_burst_size: UDMAP transmit channel burst size configuration to be
+ * programmed into the tx_burst_size field of the TCHAN_TCFG register.
+ *
+ * @tx_tdtype: UDMAP transmit channel teardown type configuration to be
+ * programmed into the tdtype field of the TCHAN_TCFG register:
+ * 0 - Return immediately
+ * 1 - Wait for completion message from remote peer
+ *
+ * @extended_ch_type: Valid for BCDMA.
+ * 0 - the channel is split tx channel (tchan)
+ * 1 - the channel is block copy channel (bchan)
*/
struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
struct ti_sci_msg_hdr hdr;
@@ -1078,6 +1093,9 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
u8 tx_orderid;
u16 fdepth;
u8 tx_sched_priority;
+ u8 tx_burst_size;
+ u8 tx_tdtype;
+ u8 extended_ch_type;
} __packed;
/**
diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
index eb916ba101..794737923c 100644
--- a/include/linux/soc/ti/ti_sci_protocol.h
+++ b/include/linux/soc/ti/ti_sci_protocol.h
@@ -379,6 +379,13 @@ struct ti_sci_rm_psil_ops {
#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0
#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2
+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES 1
+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES 2
+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES 3
+
+#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_TCHAN 0
+#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN 1
+
/* UDMAP TX/RX channel valid_params common declarations */
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1)
@@ -389,6 +396,7 @@ struct ti_sci_rm_psil_ops {
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID BIT(14)
/**
* Configures a Navigator Subsystem UDMAP transmit channel
@@ -403,6 +411,8 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg {
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID BIT(15)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID BIT(16)
u16 nav_id;
u16 index;
u8 tx_pause_on_err;
@@ -419,6 +429,9 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg {
u8 tx_orderid;
u16 fdepth;
u8 tx_sched_priority;
+ u8 tx_burst_size;
+ u8 tx_tdtype;
+ u8 extended_ch_type;
};
/**
@@ -448,6 +461,7 @@ struct ti_sci_msg_rm_udmap_rx_ch_cfg {
u8 rx_chan_type;
u8 rx_ignore_short;
u8 rx_ignore_long;
+ u8 rx_burst_size;
};
/**
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 02/12] soc: ti: k3-navss-ringacc: Add AM64 ringacc support
2021-05-10 14:36 [PATCH 00/12] AM64x: DMA and ethernet support Vignesh Raghavendra
2021-05-10 14:36 ` [PATCH 01/12] firmware: ti_sci: Update ti_sci_cmd_rm_udmap_tx_ch_cfg() API to the latest Vignesh Raghavendra
@ 2021-05-10 14:36 ` Vignesh Raghavendra
2021-05-10 14:36 ` [PATCH 03/12] soc: ti: k3-navss-ringacc: Remove unused ring modes Vignesh Raghavendra
` (10 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Vignesh Raghavendra @ 2021-05-10 14:36 UTC (permalink / raw)
To: u-boot
AM64 dual mode rings are modeled as pair of Rings objects which has common
configuration and memory buffer, but separate real-time control register
sets for each direction mem2dev (forward) and dev2mem (reverse).
AM64 rings must be requested only using k3_ringacc_request_rings_pair(),
and forward ring must always be initialized/configured. After this any
other Ringacc APIs can be used without any callers changes.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
drivers/soc/ti/k3-navss-ringacc.c | 273 +++++++++++++++++++++++-
include/linux/soc/ti/k3-navss-ringacc.h | 15 ++
2 files changed, 283 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c
index c5099ad084..10ef6be720 100644
--- a/drivers/soc/ti/k3-navss-ringacc.c
+++ b/drivers/soc/ti/k3-navss-ringacc.c
@@ -23,6 +23,7 @@
#include <linux/err.h>
#include <linux/soc/ti/k3-navss-ringacc.h>
#include <linux/soc/ti/ti_sci_protocol.h>
+#include <linux/soc/ti/cppi5.h>
#define set_bit(bit, bitmap) __set_bit(bit, bitmap)
#define clear_bit(bit, bitmap) __clear_bit(bit, bitmap)
@@ -56,6 +57,7 @@ static u32 ringacc_readl(void __iomem *reg)
}
#define KNAV_RINGACC_CFG_RING_SIZE_ELCNT_MASK GENMASK(19, 0)
+#define K3_DMARING_RING_CFG_RING_SIZE_ELCNT_MASK GENMASK(15, 0)
/**
* struct k3_nav_ring_rt_regs - The RA Control/Status Registers region
@@ -71,6 +73,13 @@ struct k3_nav_ring_rt_regs {
};
#define KNAV_RINGACC_RT_REGS_STEP 0x1000
+#define K3_DMARING_RING_RT_REGS_STEP 0x2000
+#define K3_DMARING_RING_RT_REGS_REVERSE_OFS 0x1000
+#define KNAV_RINGACC_RT_OCC_MASK GENMASK(20, 0)
+#define K3_DMARING_RING_RT_OCC_TDOWN_COMPLETE BIT(31)
+#define K3_DMARING_RING_RT_DB_ENTRY_MASK GENMASK(7, 0)
+#define K3_DMARING_RING_RT_DB_TDOWN_ACK BIT(31)
+
/**
* struct k3_nav_ring_fifo_regs - The Ring Accelerator Queues Registers region
@@ -173,6 +182,7 @@ struct k3_nav_ring {
u32 flags;
#define KNAV_RING_FLAG_BUSY BIT(1)
#define K3_NAV_RING_FLAG_SHARED BIT(2)
+#define K3_NAV_RING_FLAG_REVERSE BIT(3)
struct k3_nav_ring_state state;
u32 ring_id;
struct k3_nav_ringacc *parent;
@@ -200,6 +210,7 @@ struct k3_nav_ringacc_ops {
* @tisci_ring_ops - ti-sci rings ops
* @tisci_dev_id - ti-sci device id
* @ops: SoC specific ringacc operation
+ * @dual_ring: indicate k3_dmaring dual ring support
*/
struct k3_nav_ringacc {
struct udevice *dev;
@@ -220,8 +231,24 @@ struct k3_nav_ringacc {
u32 tisci_dev_id;
const struct k3_nav_ringacc_ops *ops;
+ bool dual_ring;
};
+static int k3_nav_ringacc_ring_read_occ(struct k3_nav_ring *ring)
+{
+ return readl(&ring->rt->occ) & KNAV_RINGACC_RT_OCC_MASK;
+}
+
+static void k3_nav_ringacc_ring_update_occ(struct k3_nav_ring *ring)
+{
+ u32 val;
+
+ val = readl(&ring->rt->occ);
+
+ ring->state.occ = val & KNAV_RINGACC_RT_OCC_MASK;
+ ring->state.tdown_complete = !!(val & K3_DMARING_RING_RT_OCC_TDOWN_COMPLETE);
+}
+
static long k3_nav_ringacc_ring_get_fifo_pos(struct k3_nav_ring *ring)
{
return KNAV_RINGACC_FIFO_WINDOW_SIZE_BYTES -
@@ -235,12 +262,23 @@ static void *k3_nav_ringacc_get_elm_addr(struct k3_nav_ring *ring, u32 idx)
static int k3_nav_ringacc_ring_push_mem(struct k3_nav_ring *ring, void *elem);
static int k3_nav_ringacc_ring_pop_mem(struct k3_nav_ring *ring, void *elem);
+static int k3_dmaring_ring_fwd_pop_mem(struct k3_nav_ring *ring, void *elem);
+static int k3_dmaring_ring_reverse_pop_mem(struct k3_nav_ring *ring, void *elem);
static struct k3_nav_ring_ops k3_nav_mode_ring_ops = {
.push_tail = k3_nav_ringacc_ring_push_mem,
.pop_head = k3_nav_ringacc_ring_pop_mem,
};
+static struct k3_nav_ring_ops k3_dmaring_fwd_ring_ops = {
+ .push_tail = k3_nav_ringacc_ring_push_mem,
+ .pop_head = k3_dmaring_ring_fwd_pop_mem,
+};
+
+static struct k3_nav_ring_ops k3_dmaring_reverse_ring_ops = {
+ .pop_head = k3_dmaring_ring_reverse_pop_mem,
+};
+
static int k3_nav_ringacc_ring_push_io(struct k3_nav_ring *ring, void *elem);
static int k3_nav_ringacc_ring_pop_io(struct k3_nav_ring *ring, void *elem);
static int k3_nav_ringacc_ring_push_head_io(struct k3_nav_ring *ring,
@@ -328,6 +366,27 @@ error:
return NULL;
}
+static int k3_dmaring_ring_request_rings_pair(struct k3_nav_ringacc *ringacc,
+ int fwd_id, int compl_id,
+ struct k3_nav_ring **fwd_ring,
+ struct k3_nav_ring **compl_ring)
+{
+ /* k3_dmaring: fwd_id == compl_id, so we ignore compl_id */
+ if (fwd_id < 0)
+ return -EINVAL;
+
+ if (test_bit(fwd_id, ringacc->rings_inuse))
+ return -EBUSY;
+
+ *fwd_ring = &ringacc->rings[fwd_id];
+ *compl_ring = &ringacc->rings[fwd_id + ringacc->num_rings];
+ set_bit(fwd_id, ringacc->rings_inuse);
+ ringacc->rings[fwd_id].use_count++;
+ dev_dbg(ringacc->dev, "Giving ring#%d\n", fwd_id);
+
+ return 0;
+}
+
int k3_nav_ringacc_request_rings_pair(struct k3_nav_ringacc *ringacc,
int fwd_id, int compl_id,
struct k3_nav_ring **fwd_ring,
@@ -338,6 +397,10 @@ int k3_nav_ringacc_request_rings_pair(struct k3_nav_ringacc *ringacc,
if (!fwd_ring || !compl_ring)
return -EINVAL;
+ if (ringacc->dual_ring)
+ return k3_dmaring_ring_request_rings_pair(ringacc, fwd_id, compl_id,
+ fwd_ring, compl_ring);
+
*fwd_ring = k3_nav_ringacc_request_ring(ringacc, fwd_id, 0);
if (!(*fwd_ring))
return -ENODEV;
@@ -493,6 +556,13 @@ int k3_nav_ringacc_ring_free(struct k3_nav_ring *ring)
ringacc = ring->parent;
+ /*
+ * k3_dmaring: rings shared memory and configuration, only forward ring is
+ * configured and reverse ring considered as slave.
+ */
+ if (ringacc->dual_ring && (ring->flags & K3_NAV_RING_FLAG_REVERSE))
+ return 0;
+
pr_debug("%s flags: 0x%08x\n", __func__, ring->flags);
if (!test_bit(ring->ring_id, ringacc->rings_inuse))
@@ -562,6 +632,76 @@ static int k3_nav_ringacc_ring_cfg_sci(struct k3_nav_ring *ring)
return ret;
}
+static int k3_dmaring_ring_cfg(struct k3_nav_ring *ring, struct k3_nav_ring_cfg *cfg)
+{
+ struct k3_nav_ringacc *ringacc;
+ struct k3_nav_ring *reverse_ring;
+ int ret = 0;
+
+ if (cfg->elm_size != K3_NAV_RINGACC_RING_ELSIZE_8 ||
+ cfg->mode != K3_NAV_RINGACC_RING_MODE_RING ||
+ cfg->size & ~K3_DMARING_RING_CFG_RING_SIZE_ELCNT_MASK)
+ return -EINVAL;
+
+ ringacc = ring->parent;
+
+ /*
+ * k3_dmaring: rings shared memory and configuration, only forward ring is
+ * configured and reverse ring considered as slave.
+ */
+ if (ringacc->dual_ring && (ring->flags & K3_NAV_RING_FLAG_REVERSE))
+ return 0;
+
+ if (!test_bit(ring->ring_id, ringacc->rings_inuse))
+ return -EINVAL;
+
+ ring->size = cfg->size;
+ ring->elm_size = cfg->elm_size;
+ ring->mode = cfg->mode;
+ memset(&ring->state, 0, sizeof(ring->state));
+
+ ring->ops = &k3_dmaring_fwd_ring_ops;
+
+ ring->ring_mem_virt =
+ dma_alloc_coherent(ring->size * (4 << ring->elm_size),
+ (unsigned long *)&ring->ring_mem_dma);
+ if (!ring->ring_mem_virt) {
+ dev_err(ringacc->dev, "Failed to alloc ring mem\n");
+ ret = -ENOMEM;
+ goto err_free_ops;
+ }
+
+ ret = k3_nav_ringacc_ring_cfg_sci(ring);
+ if (ret)
+ goto err_free_mem;
+
+ ring->flags |= KNAV_RING_FLAG_BUSY;
+
+ /* k3_dmaring: configure reverse ring */
+ reverse_ring = &ringacc->rings[ring->ring_id + ringacc->num_rings];
+ reverse_ring->size = cfg->size;
+ reverse_ring->elm_size = cfg->elm_size;
+ reverse_ring->mode = cfg->mode;
+ memset(&reverse_ring->state, 0, sizeof(reverse_ring->state));
+ reverse_ring->ops = &k3_dmaring_reverse_ring_ops;
+
+ reverse_ring->ring_mem_virt = ring->ring_mem_virt;
+ reverse_ring->ring_mem_dma = ring->ring_mem_dma;
+ reverse_ring->flags |= KNAV_RING_FLAG_BUSY;
+
+ return 0;
+
+err_free_mem:
+ dma_free_coherent(ringacc->dev,
+ ring->size * (4 << ring->elm_size),
+ ring->ring_mem_virt,
+ ring->ring_mem_dma);
+err_free_ops:
+ ring->ops = NULL;
+ ring->proxy = NULL;
+ return ret;
+}
+
int k3_nav_ringacc_ring_cfg(struct k3_nav_ring *ring,
struct k3_nav_ring_cfg *cfg)
{
@@ -570,6 +710,10 @@ int k3_nav_ringacc_ring_cfg(struct k3_nav_ring *ring,
if (!ring || !cfg)
return -EINVAL;
+
+ if (ringacc->dual_ring)
+ return k3_dmaring_ring_cfg(ring, cfg);
+
if (cfg->elm_size > K3_NAV_RINGACC_RING_ELSIZE_256 ||
cfg->mode > K3_NAV_RINGACC_RING_MODE_QM ||
cfg->size & ~KNAV_RINGACC_CFG_RING_SIZE_ELCNT_MASK ||
@@ -839,6 +983,63 @@ static int k3_nav_ringacc_ring_pop_tail_io(struct k3_nav_ring *ring, void *elem)
ring, elem, K3_RINGACC_ACCESS_MODE_POP_HEAD);
}
+static int k3_dmaring_ring_fwd_pop_mem(struct k3_nav_ring *ring, void *elem)
+{
+ void *elem_ptr;
+ u32 elem_idx;
+
+ /*
+ * k3_dmaring: forward ring is always tied DMA channel and HW does not
+ * maintain any state data required for POP operation and its unknown
+ * how much elements were consumed by HW. So, to actually
+ * do POP, the read pointer has to be recalculated every time.
+ */
+ ring->state.occ = k3_nav_ringacc_ring_read_occ(ring);
+ if (ring->state.windex >= ring->state.occ)
+ elem_idx = ring->state.windex - ring->state.occ;
+ else
+ elem_idx = ring->size - (ring->state.occ - ring->state.windex);
+
+ elem_ptr = k3_nav_ringacc_get_elm_addr(ring, elem_idx);
+ invalidate_dcache_range((unsigned long)ring->ring_mem_virt,
+ ALIGN((unsigned long)ring->ring_mem_virt +
+ ring->size * (4 << ring->elm_size),
+ ARCH_DMA_MINALIGN));
+
+ memcpy(elem, elem_ptr, (4 << ring->elm_size));
+
+ ring->state.occ--;
+ writel(-1, &ring->rt->db);
+
+ dev_dbg(ring->parent->dev, "%s: occ%d Windex%d Rindex%d pos_ptr%px\n",
+ __func__, ring->state.occ, ring->state.windex, elem_idx,
+ elem_ptr);
+ return 0;
+}
+
+static int k3_dmaring_ring_reverse_pop_mem(struct k3_nav_ring *ring, void *elem)
+{
+ void *elem_ptr;
+
+ elem_ptr = k3_nav_ringacc_get_elm_addr(ring, ring->state.rindex);
+
+ if (ring->state.occ) {
+ invalidate_dcache_range((unsigned long)ring->ring_mem_virt,
+ ALIGN((unsigned long)ring->ring_mem_virt +
+ ring->size * (4 << ring->elm_size),
+ ARCH_DMA_MINALIGN));
+
+ memcpy(elem, elem_ptr, (4 << ring->elm_size));
+ ring->state.rindex = (ring->state.rindex + 1) % ring->size;
+ ring->state.occ--;
+ writel(-1 & K3_DMARING_RING_RT_DB_ENTRY_MASK, &ring->rt->db);
+ }
+
+ dev_dbg(ring->parent->dev, "%s: occ%d index%d pos_ptr%px\n",
+ __func__, ring->state.occ, ring->state.rindex, elem_ptr);
+ return 0;
+}
+
static int k3_nav_ringacc_ring_push_mem(struct k3_nav_ring *ring, void *elem)
{
void *elem_ptr;
@@ -930,7 +1131,7 @@ int k3_nav_ringacc_ring_pop(struct k3_nav_ring *ring, void *elem)
return -EINVAL;
if (!ring->state.occ)
- ring->state.occ = k3_nav_ringacc_ring_get_occ(ring);
+ k3_nav_ringacc_ring_update_occ(ring);
pr_debug("ring_pop%d: occ%d index%d\n",
ring->ring_id, ring->state.occ, ring->state.rindex);
@@ -952,7 +1153,7 @@ int k3_nav_ringacc_ring_pop_tail(struct k3_nav_ring *ring, void *elem)
return -EINVAL;
if (!ring->state.occ)
- ring->state.occ = k3_nav_ringacc_ring_get_occ(ring);
+ k3_nav_ringacc_ring_update_occ(ring);
pr_debug("ring_pop_tail: occ%d index%d\n",
ring->state.occ, ring->state.rindex);
@@ -969,6 +1170,7 @@ int k3_nav_ringacc_ring_pop_tail(struct k3_nav_ring *ring, void *elem)
static int k3_nav_ringacc_probe_dt(struct k3_nav_ringacc *ringacc)
{
struct udevice *dev = ringacc->dev;
+ struct udevice *devp = dev;
struct udevice *tisci_dev = NULL;
int ret;
@@ -981,7 +1183,7 @@ static int k3_nav_ringacc_probe_dt(struct k3_nav_ringacc *ringacc)
ringacc->dma_ring_reset_quirk =
dev_read_bool(dev, "ti,dma-ring-reset-quirk");
- ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev,
+ ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, devp,
"ti,sci", &tisci_dev);
if (ret) {
pr_debug("TISCI RA RM get failed (%d)\n", ret);
@@ -991,14 +1193,14 @@ static int k3_nav_ringacc_probe_dt(struct k3_nav_ringacc *ringacc)
ringacc->tisci = (struct ti_sci_handle *)
(ti_sci_get_handle_from_sysfw(tisci_dev));
- ret = dev_read_u32_default(dev, "ti,sci", 0);
+ ret = dev_read_u32_default(devp, "ti,sci", 0);
if (!ret) {
dev_err(dev, "TISCI RA RM disabled\n");
ringacc->tisci = NULL;
return ret;
}
- ret = dev_read_u32(dev, "ti,sci-dev-id", &ringacc->tisci_dev_id);
+ ret = dev_read_u32(devp, "ti,sci-dev-id", &ringacc->tisci_dev_id);
if (ret) {
dev_err(dev, "ti,sci-dev-id read failure %d\n", ret);
ringacc->tisci = NULL;
@@ -1089,6 +1291,67 @@ static int k3_nav_ringacc_init(struct udevice *dev, struct k3_nav_ringacc *ringa
return 0;
}
+struct k3_nav_ringacc *k3_ringacc_dmarings_init(struct udevice *dev,
+ struct k3_ringacc_init_data *data)
+{
+ struct k3_nav_ringacc *ringacc;
+ void __iomem *base_rt;
+ int i;
+
+ ringacc = devm_kzalloc(dev, sizeof(*ringacc), GFP_KERNEL);
+ if (!ringacc)
+ return ERR_PTR(-ENOMEM);
+
+ ringacc->dual_ring = true;
+
+ ringacc->dev = dev;
+ ringacc->num_rings = data->num_rings;
+ ringacc->tisci = data->tisci;
+ ringacc->tisci_dev_id = data->tisci_dev_id;
+
+ base_rt = (uint32_t *)devfdt_get_addr_name(dev, "ringrt");
+ if (IS_ERR(base_rt))
+ return base_rt;
+
+ ringacc->rings = devm_kzalloc(dev,
+ sizeof(*ringacc->rings) *
+ ringacc->num_rings * 2,
+ GFP_KERNEL);
+ ringacc->rings_inuse = devm_kcalloc(dev,
+ BITS_TO_LONGS(ringacc->num_rings),
+ sizeof(unsigned long), GFP_KERNEL);
+
+ if (!ringacc->rings || !ringacc->rings_inuse)
+ return ERR_PTR(-ENOMEM);
+
+ for (i = 0; i < ringacc->num_rings; i++) {
+ struct k3_nav_ring *ring = &ringacc->rings[i];
+
+ ring->rt = base_rt + K3_DMARING_RING_RT_REGS_STEP * i;
+ ring->parent = ringacc;
+ ring->ring_id = i;
+ ring->proxy_id = K3_RINGACC_PROXY_NOT_USED;
+
+ ring = &ringacc->rings[ringacc->num_rings + i];
+ ring->rt = base_rt + K3_DMARING_RING_RT_REGS_STEP * i +
+ K3_DMARING_RING_RT_REGS_REVERSE_OFS;
+ ring->parent = ringacc;
+ ring->ring_id = i;
+ ring->proxy_id = K3_RINGACC_PROXY_NOT_USED;
+ ring->flags = K3_NAV_RING_FLAG_REVERSE;
+ }
+
+ ringacc->tisci_ring_ops = &ringacc->tisci->ops.rm_ring_ops;
+
+ dev_info(dev, "k3_dmaring Ring probed rings:%u, sci-dev-id:%u\n",
+ ringacc->num_rings,
+ ringacc->tisci_dev_id);
+ dev_info(dev, "dma-ring-reset-quirk: %s\n",
+ ringacc->dma_ring_reset_quirk ? "enabled" : "disabled");
+
+ return ringacc;
+}
+
struct ringacc_match_data {
struct k3_nav_ringacc_ops ops;
};
diff --git a/include/linux/soc/ti/k3-navss-ringacc.h b/include/linux/soc/ti/k3-navss-ringacc.h
index 9176277ff0..1e9b7d9125 100644
--- a/include/linux/soc/ti/k3-navss-ringacc.h
+++ b/include/linux/soc/ti/k3-navss-ringacc.h
@@ -238,4 +238,19 @@ int k3_nav_ringacc_ring_push_head(struct k3_nav_ring *ring, void *elem);
*/
int k3_nav_ringacc_ring_pop_tail(struct k3_nav_ring *ring, void *elem);
+/* DMA ring support */
+struct ti_sci_handle;
+
+/**
+ * struct struct k3_ringacc_init_data - Initialization data for DMA rings
+ */
+struct k3_ringacc_init_data {
+ const struct ti_sci_handle *tisci;
+ u32 tisci_dev_id;
+ u32 num_rings;
+};
+
+struct k3_nav_ringacc *k3_ringacc_dmarings_init(struct udevice *dev,
+ struct k3_ringacc_init_data *data);
+
#endif /* __SOC_TI_K3_NAVSS_RINGACC_API_H_ */
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 03/12] soc: ti: k3-navss-ringacc: Remove unused ring modes
2021-05-10 14:36 [PATCH 00/12] AM64x: DMA and ethernet support Vignesh Raghavendra
2021-05-10 14:36 ` [PATCH 01/12] firmware: ti_sci: Update ti_sci_cmd_rm_udmap_tx_ch_cfg() API to the latest Vignesh Raghavendra
2021-05-10 14:36 ` [PATCH 02/12] soc: ti: k3-navss-ringacc: Add AM64 ringacc support Vignesh Raghavendra
@ 2021-05-10 14:36 ` Vignesh Raghavendra
2021-05-10 14:36 ` [PATCH 04/12] dma: ti: k3-psil-am654: Drop unused PSIL EP static data Vignesh Raghavendra
` (9 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Vignesh Raghavendra @ 2021-05-10 14:36 UTC (permalink / raw)
To: u-boot
With AM64x supporting only K3_NAV_RINGACC_RING_MODE_RING or the exposed
ring mode, all other K3 SoCs have also been moved to this common
baseline. Therefore drop other modes such as
K3_NAV_RINGACC_RING_MODE_MESSAGE (and proxy) to save on SPL footprint.
There is a saving of ~800 bytes with this change for am65x_evm_r5_defconfig.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
---
drivers/soc/ti/k3-navss-ringacc.c | 311 +-----------------------
include/linux/soc/ti/k3-navss-ringacc.h | 7 +-
2 files changed, 8 insertions(+), 310 deletions(-)
diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c
index 10ef6be720..b5a5c9da98 100644
--- a/drivers/soc/ti/k3-navss-ringacc.c
+++ b/drivers/soc/ti/k3-navss-ringacc.c
@@ -91,36 +91,6 @@ struct k3_nav_ring_fifo_regs {
u32 peek_tail_data[128]; /* Ring Peek Tail Entry Data Regs */
};
-/**
- * struct k3_ringacc_proxy_gcfg_regs - RA Proxy Global Config MMIO Region
- */
-struct k3_ringacc_proxy_gcfg_regs {
- u32 revision; /* Revision Register */
- u32 config; /* Config Register */
-};
-
-#define K3_RINGACC_PROXY_CFG_THREADS_MASK GENMASK(15, 0)
-
-/**
- * struct k3_ringacc_proxy_target_regs - RA Proxy Datapath MMIO Region
- */
-struct k3_ringacc_proxy_target_regs {
- u32 control; /* Proxy Control Register */
- u32 status; /* Proxy Status Register */
- u8 resv_512[504];
- u32 data[128]; /* Proxy Data Register */
-};
-
-#define K3_RINGACC_PROXY_TARGET_STEP 0x1000
-#define K3_RINGACC_PROXY_NOT_USED (-1)
-
-enum k3_ringacc_proxy_access_mode {
- PROXY_ACCESS_MODE_HEAD = 0,
- PROXY_ACCESS_MODE_TAIL = 1,
- PROXY_ACCESS_MODE_PEEK_HEAD = 2,
- PROXY_ACCESS_MODE_PEEK_TAIL = 3,
-};
-
#define KNAV_RINGACC_FIFO_WINDOW_SIZE_BYTES (512U)
#define KNAV_RINGACC_FIFO_REGS_STEP 0x1000
#define KNAV_RINGACC_MAX_DB_RING_CNT (127U)
@@ -156,7 +126,6 @@ struct k3_nav_ring_state {
*
* @rt - Ring control/status registers
* @fifos - Ring queues registers
- * @proxy - Ring Proxy Datapath registers
* @ring_mem_dma - Ring buffer dma address
* @ring_mem_virt - Ring buffer virt address
* @ops - Ring operations
@@ -167,12 +136,10 @@ struct k3_nav_ring_state {
* @ring_id - Ring Id
* @parent - Pointer on struct @k3_nav_ringacc
* @use_count - Use count for shared rings
- * @proxy_id - RA Ring Proxy Id (only if @K3_NAV_RINGACC_RING_USE_PROXY)
*/
struct k3_nav_ring {
struct k3_nav_ring_rt_regs __iomem *rt;
struct k3_nav_ring_fifo_regs __iomem *fifos;
- struct k3_ringacc_proxy_target_regs __iomem *proxy;
dma_addr_t ring_mem_dma;
void *ring_mem_virt;
struct k3_nav_ring_ops *ops;
@@ -187,7 +154,6 @@ struct k3_nav_ring {
u32 ring_id;
struct k3_nav_ringacc *parent;
u32 use_count;
- int proxy_id;
};
struct k3_nav_ringacc_ops {
@@ -198,8 +164,6 @@ struct k3_nav_ringacc_ops {
* struct k3_nav_ringacc - Rings accelerator descriptor
*
* @dev - pointer on RA device
- * @proxy_gcfg - RA proxy global config registers
- * @proxy_target_base - RA proxy datapath region
* @num_rings - number of ring in RA
* @rm_gp_range - general purpose rings range from tisci
* @dma_ring_reset_quirk - DMA reset w/a enable
@@ -214,14 +178,11 @@ struct k3_nav_ringacc_ops {
*/
struct k3_nav_ringacc {
struct udevice *dev;
- struct k3_ringacc_proxy_gcfg_regs __iomem *proxy_gcfg;
- void __iomem *proxy_target_base;
u32 num_rings; /* number of rings in Ringacc module */
unsigned long *rings_inuse;
struct ti_sci_resource *rm_gp_range;
bool dma_ring_reset_quirk;
u32 num_proxies;
- unsigned long *proxy_inuse;
struct k3_nav_ring *rings;
struct list_head list;
@@ -249,12 +210,6 @@ static void k3_nav_ringacc_ring_update_occ(struct k3_nav_ring *ring)
ring->state.tdown_complete = !!(val & K3_DMARING_RING_RT_OCC_TDOWN_COMPLETE);
}
-static long k3_nav_ringacc_ring_get_fifo_pos(struct k3_nav_ring *ring)
-{
- return KNAV_RINGACC_FIFO_WINDOW_SIZE_BYTES -
- (4 << ring->elm_size);
-}
-
static void *k3_nav_ringacc_get_elm_addr(struct k3_nav_ring *ring, u32 idx)
{
return (idx * (4 << ring->elm_size) + ring->ring_mem_virt);
@@ -279,44 +234,14 @@ static struct k3_nav_ring_ops k3_dmaring_reverse_ring_ops = {
.pop_head = k3_dmaring_ring_reverse_pop_mem,
};
-static int k3_nav_ringacc_ring_push_io(struct k3_nav_ring *ring, void *elem);
-static int k3_nav_ringacc_ring_pop_io(struct k3_nav_ring *ring, void *elem);
-static int k3_nav_ringacc_ring_push_head_io(struct k3_nav_ring *ring,
- void *elem);
-static int k3_nav_ringacc_ring_pop_tail_io(struct k3_nav_ring *ring,
- void *elem);
-
-static struct k3_nav_ring_ops k3_nav_mode_msg_ops = {
- .push_tail = k3_nav_ringacc_ring_push_io,
- .push_head = k3_nav_ringacc_ring_push_head_io,
- .pop_tail = k3_nav_ringacc_ring_pop_tail_io,
- .pop_head = k3_nav_ringacc_ring_pop_io,
-};
-
-static int k3_ringacc_ring_push_head_proxy(struct k3_nav_ring *ring,
- void *elem);
-static int k3_ringacc_ring_push_tail_proxy(struct k3_nav_ring *ring,
- void *elem);
-static int k3_ringacc_ring_pop_head_proxy(struct k3_nav_ring *ring, void *elem);
-static int k3_ringacc_ring_pop_tail_proxy(struct k3_nav_ring *ring, void *elem);
-
-static struct k3_nav_ring_ops k3_nav_mode_proxy_ops = {
- .push_tail = k3_ringacc_ring_push_tail_proxy,
- .push_head = k3_ringacc_ring_push_head_proxy,
- .pop_tail = k3_ringacc_ring_pop_tail_proxy,
- .pop_head = k3_ringacc_ring_pop_head_proxy,
-};
-
struct udevice *k3_nav_ringacc_get_dev(struct k3_nav_ringacc *ringacc)
{
return ringacc->dev;
}
struct k3_nav_ring *k3_nav_ringacc_request_ring(struct k3_nav_ringacc *ringacc,
- int id, u32 flags)
+ int id)
{
- int proxy_id = K3_RINGACC_PROXY_NOT_USED;
-
if (id == K3_NAV_RINGACC_RING_ID_ANY) {
/* Request for any general purpose ring */
struct ti_sci_resource_desc *gp_rings =
@@ -338,24 +263,10 @@ struct k3_nav_ring *k3_nav_ringacc_request_ring(struct k3_nav_ringacc *ringacc,
else if (ringacc->rings[id].flags & K3_NAV_RING_FLAG_SHARED)
goto out;
- if (flags & K3_NAV_RINGACC_RING_USE_PROXY) {
- proxy_id = find_next_zero_bit(ringacc->proxy_inuse,
- ringacc->num_proxies, 0);
- if (proxy_id == ringacc->num_proxies)
- goto error;
- }
-
if (!try_module_get(ringacc->dev->driver->owner))
goto error;
- if (proxy_id != K3_RINGACC_PROXY_NOT_USED) {
- set_bit(proxy_id, ringacc->proxy_inuse);
- ringacc->rings[id].proxy_id = proxy_id;
- pr_debug("Giving ring#%d proxy#%d\n",
- id, proxy_id);
- } else {
- pr_debug("Giving ring#%d\n", id);
- }
+ pr_debug("Giving ring#%d\n", id);
set_bit(id, ringacc->rings_inuse);
out:
@@ -401,11 +312,11 @@ int k3_nav_ringacc_request_rings_pair(struct k3_nav_ringacc *ringacc,
return k3_dmaring_ring_request_rings_pair(ringacc, fwd_id, compl_id,
fwd_ring, compl_ring);
- *fwd_ring = k3_nav_ringacc_request_ring(ringacc, fwd_id, 0);
+ *fwd_ring = k3_nav_ringacc_request_ring(ringacc, fwd_id);
if (!(*fwd_ring))
return -ENODEV;
- *compl_ring = k3_nav_ringacc_request_ring(ringacc, compl_id, 0);
+ *compl_ring = k3_nav_ringacc_request_ring(ringacc, compl_id);
if (!(*compl_ring)) {
k3_nav_ringacc_ring_free(*fwd_ring);
ret = -ENODEV;
@@ -581,11 +492,6 @@ int k3_nav_ringacc_ring_free(struct k3_nav_ring *ring)
ring->ring_mem_virt, ring->ring_mem_dma);
ring->flags &= ~KNAV_RING_FLAG_BUSY;
ring->ops = NULL;
- if (ring->proxy_id != K3_RINGACC_PROXY_NOT_USED) {
- clear_bit(ring->proxy_id, ringacc->proxy_inuse);
- ring->proxy = NULL;
- ring->proxy_id = K3_RINGACC_PROXY_NOT_USED;
- }
no_init:
clear_bit(ring->ring_id, ringacc->rings_inuse);
@@ -698,7 +604,6 @@ err_free_mem:
ring->ring_mem_dma);
err_free_ops:
ring->ops = NULL;
- ring->proxy = NULL;
return ret;
}
@@ -728,32 +633,14 @@ int k3_nav_ringacc_ring_cfg(struct k3_nav_ring *ring,
ring->mode = cfg->mode;
memset(&ring->state, 0, sizeof(ring->state));
- if (ring->proxy_id != K3_RINGACC_PROXY_NOT_USED)
- ring->proxy = ringacc->proxy_target_base +
- ring->proxy_id * K3_RINGACC_PROXY_TARGET_STEP;
-
switch (ring->mode) {
case K3_NAV_RINGACC_RING_MODE_RING:
ring->ops = &k3_nav_mode_ring_ops;
break;
- case K3_NAV_RINGACC_RING_MODE_QM:
- /*
- * In Queue mode elm_size can be 8 only and each operation
- * uses 2 element slots
- */
- if (cfg->elm_size != K3_NAV_RINGACC_RING_ELSIZE_8 ||
- cfg->size % 2)
- goto err_free_proxy;
- case K3_NAV_RINGACC_RING_MODE_MESSAGE:
- if (ring->proxy)
- ring->ops = &k3_nav_mode_proxy_ops;
- else
- ring->ops = &k3_nav_mode_msg_ops;
- break;
default:
ring->ops = NULL;
ret = -EINVAL;
- goto err_free_proxy;
+ goto err_free_ops;
};
ring->ring_mem_virt =
@@ -784,8 +671,6 @@ err_free_mem:
ring->ring_mem_dma);
err_free_ops:
ring->ops = NULL;
-err_free_proxy:
- ring->proxy = NULL;
return ret;
}
@@ -830,159 +715,6 @@ enum k3_ringacc_access_mode {
K3_RINGACC_ACCESS_MODE_PEEK_TAIL,
};
-static int k3_ringacc_ring_cfg_proxy(struct k3_nav_ring *ring,
- enum k3_ringacc_proxy_access_mode mode)
-{
- u32 val;
-
- val = ring->ring_id;
- val |= mode << 16;
- val |= ring->elm_size << 24;
- ringacc_writel(val, &ring->proxy->control);
- return 0;
-}
-
-static int k3_nav_ringacc_ring_access_proxy(
- struct k3_nav_ring *ring, void *elem,
- enum k3_ringacc_access_mode access_mode)
-{
- void __iomem *ptr;
-
- ptr = (void __iomem *)&ring->proxy->data;
-
- switch (access_mode) {
- case K3_RINGACC_ACCESS_MODE_PUSH_HEAD:
- case K3_RINGACC_ACCESS_MODE_POP_HEAD:
- k3_ringacc_ring_cfg_proxy(ring, PROXY_ACCESS_MODE_HEAD);
- break;
- case K3_RINGACC_ACCESS_MODE_PUSH_TAIL:
- case K3_RINGACC_ACCESS_MODE_POP_TAIL:
- k3_ringacc_ring_cfg_proxy(ring, PROXY_ACCESS_MODE_TAIL);
- break;
- default:
- return -EINVAL;
- }
-
- ptr += k3_nav_ringacc_ring_get_fifo_pos(ring);
-
- switch (access_mode) {
- case K3_RINGACC_ACCESS_MODE_POP_HEAD:
- case K3_RINGACC_ACCESS_MODE_POP_TAIL:
- pr_debug("proxy:memcpy_fromio(x): --> ptr(%p), mode:%d\n",
- ptr, access_mode);
- memcpy_fromio(elem, ptr, (4 << ring->elm_size));
- ring->state.occ--;
- break;
- case K3_RINGACC_ACCESS_MODE_PUSH_TAIL:
- case K3_RINGACC_ACCESS_MODE_PUSH_HEAD:
- pr_debug("proxy:memcpy_toio(x): --> ptr(%p), mode:%d\n",
- ptr, access_mode);
- memcpy_toio(ptr, elem, (4 << ring->elm_size));
- ring->state.free--;
- break;
- default:
- return -EINVAL;
- }
-
- pr_debug("proxy: free%d occ%d\n",
- ring->state.free, ring->state.occ);
- return 0;
-}
-
-static int k3_ringacc_ring_push_head_proxy(struct k3_nav_ring *ring, void *elem)
-{
- return k3_nav_ringacc_ring_access_proxy(
- ring, elem, K3_RINGACC_ACCESS_MODE_PUSH_HEAD);
-}
-
-static int k3_ringacc_ring_push_tail_proxy(struct k3_nav_ring *ring, void *elem)
-{
- return k3_nav_ringacc_ring_access_proxy(
- ring, elem, K3_RINGACC_ACCESS_MODE_PUSH_TAIL);
-}
-
-static int k3_ringacc_ring_pop_head_proxy(struct k3_nav_ring *ring, void *elem)
-{
- return k3_nav_ringacc_ring_access_proxy(
- ring, elem, K3_RINGACC_ACCESS_MODE_POP_HEAD);
-}
-
-static int k3_ringacc_ring_pop_tail_proxy(struct k3_nav_ring *ring, void *elem)
-{
- return k3_nav_ringacc_ring_access_proxy(
- ring, elem, K3_RINGACC_ACCESS_MODE_POP_HEAD);
-}
-
-static int k3_nav_ringacc_ring_access_io(
- struct k3_nav_ring *ring, void *elem,
- enum k3_ringacc_access_mode access_mode)
-{
- void __iomem *ptr;
-
- switch (access_mode) {
- case K3_RINGACC_ACCESS_MODE_PUSH_HEAD:
- case K3_RINGACC_ACCESS_MODE_POP_HEAD:
- ptr = (void __iomem *)&ring->fifos->head_data;
- break;
- case K3_RINGACC_ACCESS_MODE_PUSH_TAIL:
- case K3_RINGACC_ACCESS_MODE_POP_TAIL:
- ptr = (void __iomem *)&ring->fifos->tail_data;
- break;
- default:
- return -EINVAL;
- }
-
- ptr += k3_nav_ringacc_ring_get_fifo_pos(ring);
-
- switch (access_mode) {
- case K3_RINGACC_ACCESS_MODE_POP_HEAD:
- case K3_RINGACC_ACCESS_MODE_POP_TAIL:
- pr_debug("memcpy_fromio(x): --> ptr(%p), mode:%d\n",
- ptr, access_mode);
- memcpy_fromio(elem, ptr, (4 << ring->elm_size));
- ring->state.occ--;
- break;
- case K3_RINGACC_ACCESS_MODE_PUSH_TAIL:
- case K3_RINGACC_ACCESS_MODE_PUSH_HEAD:
- pr_debug("memcpy_toio(x): --> ptr(%p), mode:%d\n",
- ptr, access_mode);
- memcpy_toio(ptr, elem, (4 << ring->elm_size));
- ring->state.free--;
- break;
- default:
- return -EINVAL;
- }
-
- pr_debug("free%d index%d occ%d index%d\n",
- ring->state.free, ring->state.windex, ring->state.occ, ring->state.rindex);
- return 0;
-}
-
-static int k3_nav_ringacc_ring_push_head_io(struct k3_nav_ring *ring,
- void *elem)
-{
- return k3_nav_ringacc_ring_access_io(
- ring, elem, K3_RINGACC_ACCESS_MODE_PUSH_HEAD);
-}
-
-static int k3_nav_ringacc_ring_push_io(struct k3_nav_ring *ring, void *elem)
-{
- return k3_nav_ringacc_ring_access_io(
- ring, elem, K3_RINGACC_ACCESS_MODE_PUSH_TAIL);
-}
-
-static int k3_nav_ringacc_ring_pop_io(struct k3_nav_ring *ring, void *elem)
-{
- return k3_nav_ringacc_ring_access_io(
- ring, elem, K3_RINGACC_ACCESS_MODE_POP_HEAD);
-}
-
-static int k3_nav_ringacc_ring_pop_tail_io(struct k3_nav_ring *ring, void *elem)
-{
- return k3_nav_ringacc_ring_access_io(
- ring, elem, K3_RINGACC_ACCESS_MODE_POP_HEAD);
-}
-
static int k3_dmaring_ring_fwd_pop_mem(struct k3_nav_ring *ring, void *elem)
{
void *elem_ptr;
@@ -1219,7 +951,7 @@ static int k3_nav_ringacc_probe_dt(struct k3_nav_ringacc *ringacc)
static int k3_nav_ringacc_init(struct udevice *dev, struct k3_nav_ringacc *ringacc)
{
- void __iomem *base_fifo, *base_rt;
+ void __iomem *base_rt;
int ret, i;
ret = k3_nav_ringacc_probe_dt(ringacc);
@@ -1231,24 +963,6 @@ static int k3_nav_ringacc_init(struct udevice *dev, struct k3_nav_ringacc *ringa
if (IS_ERR(base_rt))
return PTR_ERR(base_rt);
- base_fifo = (uint32_t *)devfdt_get_addr_name(dev, "fifos");
- pr_debug("fifos %p\n", base_fifo);
- if (IS_ERR(base_fifo))
- return PTR_ERR(base_fifo);
-
- ringacc->proxy_gcfg = (struct k3_ringacc_proxy_gcfg_regs __iomem *)
- devfdt_get_addr_name(dev, "proxy_gcfg");
- if (IS_ERR(ringacc->proxy_gcfg))
- return PTR_ERR(ringacc->proxy_gcfg);
- ringacc->proxy_target_base =
- (struct k3_ringacc_proxy_gcfg_regs __iomem *)
- devfdt_get_addr_name(dev, "proxy_target");
- if (IS_ERR(ringacc->proxy_target_base))
- return PTR_ERR(ringacc->proxy_target_base);
-
- ringacc->num_proxies = ringacc_readl(&ringacc->proxy_gcfg->config) &
- K3_RINGACC_PROXY_CFG_THREADS_MASK;
-
ringacc->rings = devm_kzalloc(dev,
sizeof(*ringacc->rings) *
ringacc->num_rings,
@@ -1256,21 +970,15 @@ static int k3_nav_ringacc_init(struct udevice *dev, struct k3_nav_ringacc *ringa
ringacc->rings_inuse = devm_kcalloc(dev,
BITS_TO_LONGS(ringacc->num_rings),
sizeof(unsigned long), GFP_KERNEL);
- ringacc->proxy_inuse = devm_kcalloc(dev,
- BITS_TO_LONGS(ringacc->num_proxies),
- sizeof(unsigned long), GFP_KERNEL);
- if (!ringacc->rings || !ringacc->rings_inuse || !ringacc->proxy_inuse)
+ if (!ringacc->rings || !ringacc->rings_inuse)
return -ENOMEM;
for (i = 0; i < ringacc->num_rings; i++) {
ringacc->rings[i].rt = base_rt +
KNAV_RINGACC_RT_REGS_STEP * i;
- ringacc->rings[i].fifos = base_fifo +
- KNAV_RINGACC_FIFO_REGS_STEP * i;
ringacc->rings[i].parent = ringacc;
ringacc->rings[i].ring_id = i;
- ringacc->rings[i].proxy_id = K3_RINGACC_PROXY_NOT_USED;
}
dev_set_drvdata(dev, ringacc);
@@ -1285,9 +993,6 @@ static int k3_nav_ringacc_init(struct udevice *dev, struct k3_nav_ringacc *ringa
ringacc->tisci_dev_id);
dev_info(dev, "dma-ring-reset-quirk: %s\n",
ringacc->dma_ring_reset_quirk ? "enabled" : "disabled");
- dev_info(dev, "RA Proxy rev. %08x, num_proxies:%u\n",
- ringacc_readl(&ringacc->proxy_gcfg->revision),
- ringacc->num_proxies);
return 0;
}
@@ -1330,14 +1035,12 @@ struct k3_nav_ringacc *k3_ringacc_dmarings_init(struct udevice *dev,
ring->rt = base_rt + K3_DMARING_RING_RT_REGS_STEP * i;
ring->parent = ringacc;
ring->ring_id = i;
- ring->proxy_id = K3_RINGACC_PROXY_NOT_USED;
ring = &ringacc->rings[ringacc->num_rings + i];
ring->rt = base_rt + K3_DMARING_RING_RT_REGS_STEP * i +
K3_DMARING_RING_RT_REGS_REVERSE_OFS;
ring->parent = ringacc;
ring->ring_id = i;
- ring->proxy_id = K3_RINGACC_PROXY_NOT_USED;
ring->flags = K3_NAV_RING_FLAG_REVERSE;
}
diff --git a/include/linux/soc/ti/k3-navss-ringacc.h b/include/linux/soc/ti/k3-navss-ringacc.h
index 1e9b7d9125..0ad8f203da 100644
--- a/include/linux/soc/ti/k3-navss-ringacc.h
+++ b/include/linux/soc/ti/k3-navss-ringacc.h
@@ -83,22 +83,17 @@ struct k3_nav_ring_cfg {
};
#define K3_NAV_RINGACC_RING_ID_ANY (-1)
-#define K3_NAV_RINGACC_RING_USE_PROXY BIT(1)
/**
* k3_nav_ringacc_request_ring - request ring from ringacc
* @ringacc: pointer on ringacc
* @id: ring id or K3_NAV_RINGACC_RING_ID_ANY for any general purpose ring
- * @flags:
- * @K3_NAV_RINGACC_RING_USE_PROXY: if set - proxy will be allocated and
- * used to access ring memory. Sopported only for rings in
- * Message/Credentials/Queue mode.
*
* Returns pointer on the Ring - struct k3_nav_ring
* or NULL in case of failure.
*/
struct k3_nav_ring *k3_nav_ringacc_request_ring(struct k3_nav_ringacc *ringacc,
- int id, u32 flags);
+ int id);
int k3_nav_ringacc_request_rings_pair(struct k3_nav_ringacc *ringacc,
int fwd_id, int compl_id,
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 04/12] dma: ti: k3-psil-am654: Drop unused PSIL EP static data
2021-05-10 14:36 [PATCH 00/12] AM64x: DMA and ethernet support Vignesh Raghavendra
` (2 preceding siblings ...)
2021-05-10 14:36 ` [PATCH 03/12] soc: ti: k3-navss-ringacc: Remove unused ring modes Vignesh Raghavendra
@ 2021-05-10 14:36 ` Vignesh Raghavendra
2021-05-10 14:36 ` [PATCH 05/12] dma: ti: k3-psil: Extend PSIL EP data extension for AM64 Vignesh Raghavendra
` (8 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Vignesh Raghavendra @ 2021-05-10 14:36 UTC (permalink / raw)
To: u-boot
ICSSG Ethernet driver uses two src threads per port (one per slice).
Similarly CPSW uses one src thread.
Drop PSIL EP static data for other src threads in order to reduce
R5 SPL footprint. This makes AM65x board bootable again.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
drivers/dma/ti/k3-psil-am654.c | 32 +++++++-------------------------
1 file changed, 7 insertions(+), 25 deletions(-)
diff --git a/drivers/dma/ti/k3-psil-am654.c b/drivers/dma/ti/k3-psil-am654.c
index f95d99cfd3..d16c07566b 100644
--- a/drivers/dma/ti/k3-psil-am654.c
+++ b/drivers/dma/ti/k3-psil-am654.c
@@ -44,40 +44,22 @@ static struct psil_ep am654_src_ep_map[] = {
static struct psil_ep am654_dst_ep_map[] = {
/* PRU_ICSSG0 */
PSIL_ETHERNET(0xc100),
- PSIL_ETHERNET(0xc101),
- PSIL_ETHERNET(0xc102),
- PSIL_ETHERNET(0xc103),
+ /* PSIL: 0xc101 - 0xc103 unused */
PSIL_ETHERNET(0xc104),
- PSIL_ETHERNET(0xc105),
- PSIL_ETHERNET(0xc106),
- PSIL_ETHERNET(0xc107),
+ /* PSIL: 0xc105 - 0xc107 unused */
/* PRU_ICSSG1 */
PSIL_ETHERNET(0xc200),
- PSIL_ETHERNET(0xc201),
- PSIL_ETHERNET(0xc202),
- PSIL_ETHERNET(0xc203),
+ /* PSIL: 0xc201 - 0xc203 unused */
PSIL_ETHERNET(0xc204),
- PSIL_ETHERNET(0xc205),
- PSIL_ETHERNET(0xc206),
- PSIL_ETHERNET(0xc207),
+ /* PSIL: 0xc205 - 0xc207 unused */
/* PRU_ICSSG2 */
PSIL_ETHERNET(0xc300),
- PSIL_ETHERNET(0xc301),
- PSIL_ETHERNET(0xc302),
- PSIL_ETHERNET(0xc303),
+ /* PSIL: 0xc301 - 0xc303 unused */
PSIL_ETHERNET(0xc304),
- PSIL_ETHERNET(0xc305),
- PSIL_ETHERNET(0xc306),
- PSIL_ETHERNET(0xc307),
+ /* PSIL: 0xc305 - 0xc307 unused */
/* CPSW0 */
PSIL_ETHERNET(0xf000),
- PSIL_ETHERNET(0xf001),
- PSIL_ETHERNET(0xf002),
- PSIL_ETHERNET(0xf003),
- PSIL_ETHERNET(0xf004),
- PSIL_ETHERNET(0xf005),
- PSIL_ETHERNET(0xf006),
- PSIL_ETHERNET(0xf007),
+ /* PSIL: 0xf001 - 0xf007 unused */
};
struct psil_ep_map am654_ep_map = {
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 05/12] dma: ti: k3-psil: Extend PSIL EP data extension for AM64
2021-05-10 14:36 [PATCH 00/12] AM64x: DMA and ethernet support Vignesh Raghavendra
` (3 preceding siblings ...)
2021-05-10 14:36 ` [PATCH 04/12] dma: ti: k3-psil-am654: Drop unused PSIL EP static data Vignesh Raghavendra
@ 2021-05-10 14:36 ` Vignesh Raghavendra
2021-05-10 14:36 ` [PATCH 06/12] dma: ti: k3-psil-am64: Add AM64 PSIL endpoint data Vignesh Raghavendra
` (7 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Vignesh Raghavendra @ 2021-05-10 14:36 UTC (permalink / raw)
To: u-boot
Extend PSIL EP data to include AM64 DMA specific information
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
drivers/dma/ti/k3-psil.h | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/dma/ti/k3-psil.h b/drivers/dma/ti/k3-psil.h
index 53c61b4595..1e0fe06c0a 100644
--- a/drivers/dma/ti/k3-psil.h
+++ b/drivers/dma/ti/k3-psil.h
@@ -50,6 +50,15 @@ enum psil_endpoint_type {
* @channel_tpl: Desired throughput level for the channel
* @pdma_acc32: ACC32 must be enabled on the PDMA side
* @pdma_burst: BURST must be enabled on the PDMA side
+ * @mapped_channel_id: PKTDMA thread to channel mapping for mapped
+ * channels. The thread must be serviced by the specified
+ * channel if mapped_channel_id is >= 0 in case of PKTDMA
+ * @flow_start: PKTDMA flow range start of mapped channel. Unmapped
+ * channels use flow_id == chan_id
+ * @flow_num: PKTDMA flow count of mapped channel. Unmapped
+ * channels use flow_id == chan_id
+ * @default_flow_id: PKTDMA default (r)flow index of mapped channel.
+ * Must be within the flow range of the mapped channel.
*/
struct psil_endpoint_config {
enum psil_endpoint_type ep_type;
@@ -63,5 +72,12 @@ struct psil_endpoint_config {
/* PDMA properties, valid for PSIL_EP_PDMA_* */
unsigned pdma_acc32:1;
unsigned pdma_burst:1;
+
+ /* PKTDMA mapped channel */
+ int mapped_channel_id;
+ /* PKTDMA tflow and rflow ranges for mapped channel */
+ u16 flow_start;
+ u16 flow_num;
+ u16 default_flow_id;
};
#endif /* K3_PSIL_H_ */
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 06/12] dma: ti: k3-psil-am64: Add AM64 PSIL endpoint data
2021-05-10 14:36 [PATCH 00/12] AM64x: DMA and ethernet support Vignesh Raghavendra
` (4 preceding siblings ...)
2021-05-10 14:36 ` [PATCH 05/12] dma: ti: k3-psil: Extend PSIL EP data extension for AM64 Vignesh Raghavendra
@ 2021-05-10 14:36 ` Vignesh Raghavendra
2021-05-10 14:36 ` [PATCH 07/12] dma: ti: k3-udma: Add BCDMA and PKTDMA support Vignesh Raghavendra
` (6 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Vignesh Raghavendra @ 2021-05-10 14:36 UTC (permalink / raw)
To: u-boot
Add AM64 SoC specific channel mapping and endpoint data.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
drivers/dma/ti/Makefile | 1 +
drivers/dma/ti/k3-psil-am64.c | 156 ++++++++++++++++++++++++++++++++++
drivers/dma/ti/k3-psil-priv.h | 1 +
drivers/dma/ti/k3-psil.c | 2 +
4 files changed, 160 insertions(+)
create mode 100644 drivers/dma/ti/k3-psil-am64.c
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index 4ea9c626cc..0391cd3d80 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_TI_K3_PSIL) += k3-psil-data.o
k3-psil-data-y += k3-psil.o
k3-psil-data-$(CONFIG_SOC_K3_AM6) += k3-psil-am654.o
k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o
+k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o
diff --git a/drivers/dma/ti/k3-psil-am64.c b/drivers/dma/ti/k3-psil-am64.c
new file mode 100644
index 0000000000..15742c3723
--- /dev/null
+++ b/drivers/dma/ti/k3-psil-am64.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
+ * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
+ */
+
+#include <linux/kernel.h>
+
+#include "k3-psil-priv.h"
+
+#define PSIL_PDMA_XY_TR(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .mapped_channel_id = -1, \
+ }, \
+ }
+
+#define PSIL_PDMA_XY_PKT(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .mapped_channel_id = -1, \
+ .pkt_mode = 1, \
+ }, \
+ }
+
+#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1, \
+ .psd_size = 16, \
+ .mapped_channel_id = ch, \
+ .flow_start = flow_base, \
+ .flow_num = flow_cnt, \
+ .default_flow_id = flow_base, \
+ }, \
+ }
+
+#define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1, \
+ .psd_size = 64, \
+ .mapped_channel_id = ch, \
+ .flow_start = flow_base, \
+ .flow_num = flow_cnt, \
+ .default_flow_id = default_flow, \
+ .notdpkt = tx, \
+ }, \
+ }
+
+/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
+static struct psil_ep am64_src_ep_map[] = {
+ /* SAUL */
+ PSIL_SAUL(0x4000, 17, 32, 8, 32, 0),
+ PSIL_SAUL(0x4001, 18, 32, 8, 33, 0),
+ PSIL_SAUL(0x4002, 19, 40, 8, 40, 0),
+ PSIL_SAUL(0x4003, 20, 40, 8, 41, 0),
+ /* ICSS_G0 */
+ PSIL_ETHERNET(0x4100, 21, 48, 16),
+ PSIL_ETHERNET(0x4101, 22, 64, 16),
+ PSIL_ETHERNET(0x4102, 23, 80, 16),
+ PSIL_ETHERNET(0x4103, 24, 96, 16),
+ /* ICSS_G1 */
+ PSIL_ETHERNET(0x4200, 25, 112, 16),
+ PSIL_ETHERNET(0x4201, 26, 128, 16),
+ PSIL_ETHERNET(0x4202, 27, 144, 16),
+ PSIL_ETHERNET(0x4203, 28, 160, 16),
+ /* PDMA_MAIN0 - SPI0-3 */
+ PSIL_PDMA_XY_PKT(0x4300),
+ PSIL_PDMA_XY_PKT(0x4301),
+ PSIL_PDMA_XY_PKT(0x4302),
+ PSIL_PDMA_XY_PKT(0x4303),
+ PSIL_PDMA_XY_PKT(0x4304),
+ PSIL_PDMA_XY_PKT(0x4305),
+ PSIL_PDMA_XY_PKT(0x4306),
+ PSIL_PDMA_XY_PKT(0x4307),
+ PSIL_PDMA_XY_PKT(0x4308),
+ PSIL_PDMA_XY_PKT(0x4309),
+ PSIL_PDMA_XY_PKT(0x430a),
+ PSIL_PDMA_XY_PKT(0x430b),
+ PSIL_PDMA_XY_PKT(0x430c),
+ PSIL_PDMA_XY_PKT(0x430d),
+ PSIL_PDMA_XY_PKT(0x430e),
+ PSIL_PDMA_XY_PKT(0x430f),
+ /* PDMA_MAIN0 - USART0-1 */
+ PSIL_PDMA_XY_PKT(0x4310),
+ PSIL_PDMA_XY_PKT(0x4311),
+ /* PDMA_MAIN1 - SPI4 */
+ PSIL_PDMA_XY_PKT(0x4400),
+ PSIL_PDMA_XY_PKT(0x4401),
+ PSIL_PDMA_XY_PKT(0x4402),
+ PSIL_PDMA_XY_PKT(0x4403),
+ /* PDMA_MAIN1 - USART2-6 */
+ PSIL_PDMA_XY_PKT(0x4404),
+ PSIL_PDMA_XY_PKT(0x4405),
+ PSIL_PDMA_XY_PKT(0x4406),
+ PSIL_PDMA_XY_PKT(0x4407),
+ PSIL_PDMA_XY_PKT(0x4408),
+ /* PDMA_MAIN1 - ADCs */
+ PSIL_PDMA_XY_TR(0x440f),
+ PSIL_PDMA_XY_TR(0x4410),
+ /* CPSW2 */
+ PSIL_ETHERNET(0x4500, 16, 16, 16),
+};
+
+/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
+static struct psil_ep am64_dst_ep_map[] = {
+ /* SAUL */
+ PSIL_SAUL(0xc000, 24, 80, 8, 80, 1),
+ PSIL_SAUL(0xc001, 25, 88, 8, 88, 1),
+ /* ICSS_G0 */
+ PSIL_ETHERNET(0xc100, 26, 96, 1),
+ PSIL_ETHERNET(0xc101, 27, 97, 1),
+ PSIL_ETHERNET(0xc102, 28, 98, 1),
+ PSIL_ETHERNET(0xc103, 29, 99, 1),
+ PSIL_ETHERNET(0xc104, 30, 100, 1),
+ PSIL_ETHERNET(0xc105, 31, 101, 1),
+ PSIL_ETHERNET(0xc106, 32, 102, 1),
+ PSIL_ETHERNET(0xc107, 33, 103, 1),
+ /* ICSS_G1 */
+ PSIL_ETHERNET(0xc200, 34, 104, 1),
+ PSIL_ETHERNET(0xc201, 35, 105, 1),
+ PSIL_ETHERNET(0xc202, 36, 106, 1),
+ PSIL_ETHERNET(0xc203, 37, 107, 1),
+ PSIL_ETHERNET(0xc204, 38, 108, 1),
+ PSIL_ETHERNET(0xc205, 39, 109, 1),
+ PSIL_ETHERNET(0xc206, 40, 110, 1),
+ PSIL_ETHERNET(0xc207, 41, 111, 1),
+ /* CPSW2 */
+ PSIL_ETHERNET(0xc500, 16, 16, 8),
+ PSIL_ETHERNET(0xc501, 17, 24, 8),
+ PSIL_ETHERNET(0xc502, 18, 32, 8),
+ PSIL_ETHERNET(0xc503, 19, 40, 8),
+ PSIL_ETHERNET(0xc504, 20, 48, 8),
+ PSIL_ETHERNET(0xc505, 21, 56, 8),
+ PSIL_ETHERNET(0xc506, 22, 64, 8),
+ PSIL_ETHERNET(0xc507, 23, 72, 8),
+};
+
+struct psil_ep_map am64_ep_map = {
+ .name = "am64",
+ .src = am64_src_ep_map,
+ .src_count = ARRAY_SIZE(am64_src_ep_map),
+ .dst = am64_dst_ep_map,
+ .dst_count = ARRAY_SIZE(am64_dst_ep_map),
+};
diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h
index d3a38322b1..02d1c201a9 100644
--- a/drivers/dma/ti/k3-psil-priv.h
+++ b/drivers/dma/ti/k3-psil-priv.h
@@ -39,5 +39,6 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id);
/* SoC PSI-L endpoint maps */
extern struct psil_ep_map am654_ep_map;
extern struct psil_ep_map j721e_ep_map;
+extern struct psil_ep_map am64_ep_map;
#endif /* K3_PSIL_PRIV_H_ */
diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c
index b5c92b2829..e82f807541 100644
--- a/drivers/dma/ti/k3-psil.c
+++ b/drivers/dma/ti/k3-psil.c
@@ -20,6 +20,8 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id)
soc_ep_map = &am654_ep_map;
else if (IS_ENABLED(CONFIG_SOC_K3_J721E))
soc_ep_map = &j721e_ep_map;
+ else if (IS_ENABLED(CONFIG_SOC_K3_AM642))
+ soc_ep_map = &am64_ep_map;
}
if (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET && soc_ep_map->dst) {
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 07/12] dma: ti: k3-udma: Add BCDMA and PKTDMA support
2021-05-10 14:36 [PATCH 00/12] AM64x: DMA and ethernet support Vignesh Raghavendra
` (5 preceding siblings ...)
2021-05-10 14:36 ` [PATCH 06/12] dma: ti: k3-psil-am64: Add AM64 PSIL endpoint data Vignesh Raghavendra
@ 2021-05-10 14:36 ` Vignesh Raghavendra
2021-05-10 14:36 ` [PATCH 08/12] net: ti: am65-cpsw-nuss: Prepare to support non primary ext port Vignesh Raghavendra
` (5 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Vignesh Raghavendra @ 2021-05-10 14:36 UTC (permalink / raw)
To: u-boot
Sync BCDMA and PKTDMA support from Kernel for AM64 SoC
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
drivers/dma/ti/k3-udma.c | 1003 +++++++++++++++++++++++++++++++++++---
1 file changed, 939 insertions(+), 64 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index f3ec827897..601868d7fc 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -28,6 +28,7 @@
#include <linux/soc/ti/cppi5.h>
#include <linux/soc/ti/ti-udma.h>
#include <linux/soc/ti/ti_sci_protocol.h>
+#include <linux/soc/ti/cppi5.h>
#include "k3-udma-hwdef.h"
#include "k3-psil-priv.h"
@@ -36,15 +37,25 @@
struct udma_chan;
+enum k3_dma_type {
+ DMA_TYPE_UDMA = 0,
+ DMA_TYPE_BCDMA,
+ DMA_TYPE_PKTDMA,
+};
+
enum udma_mmr {
MMR_GCFG = 0,
+ MMR_BCHANRT,
MMR_RCHANRT,
MMR_TCHANRT,
MMR_LAST,
};
static const char * const mmr_names[] = {
- "gcfg", "rchanrt", "tchanrt"
+ [MMR_GCFG] = "gcfg",
+ [MMR_BCHANRT] = "bchanrt",
+ [MMR_RCHANRT] = "rchanrt",
+ [MMR_TCHANRT] = "tchanrt",
};
struct udma_tchan {
@@ -53,6 +64,16 @@ struct udma_tchan {
int id;
struct k3_nav_ring *t_ring; /* Transmit ring */
struct k3_nav_ring *tc_ring; /* Transmit Completion ring */
+ int tflow_id; /* applicable only for PKTDMA */
+
+};
+
+#define udma_bchan udma_tchan
+
+struct udma_rflow {
+ int id;
+ struct k3_nav_ring *fd_ring; /* Free Descriptor ring */
+ struct k3_nav_ring *r_ring; /* Receive ring */
};
struct udma_rchan {
@@ -61,32 +82,45 @@ struct udma_rchan {
int id;
};
+struct udma_oes_offsets {
+ /* K3 UDMA Output Event Offset */
+ u32 udma_rchan;
+
+ /* BCDMA Output Event Offsets */
+ u32 bcdma_bchan_data;
+ u32 bcdma_bchan_ring;
+ u32 bcdma_tchan_data;
+ u32 bcdma_tchan_ring;
+ u32 bcdma_rchan_data;
+ u32 bcdma_rchan_ring;
+
+ /* PKTDMA Output Event Offsets */
+ u32 pktdma_tchan_flow;
+ u32 pktdma_rchan_flow;
+};
+
#define UDMA_FLAG_PDMA_ACC32 BIT(0)
#define UDMA_FLAG_PDMA_BURST BIT(1)
#define UDMA_FLAG_TDTYPE BIT(2)
struct udma_match_data {
+ enum k3_dma_type type;
u32 psil_base;
bool enable_memcpy_support;
u32 flags;
u32 statictr_z_mask;
- u32 rchan_oes_offset;
+ struct udma_oes_offsets oes;
u8 tpl_levels;
u32 level_start_idx[];
};
-struct udma_rflow {
- int id;
-
- struct k3_nav_ring *fd_ring; /* Free Descriptor ring */
- struct k3_nav_ring *r_ring; /* Receive ring*/
-};
-
enum udma_rm_range {
- RM_RANGE_TCHAN = 0,
+ RM_RANGE_BCHAN = 0,
+ RM_RANGE_TCHAN,
RM_RANGE_RCHAN,
RM_RANGE_RFLOW,
+ RM_RANGE_TFLOW,
RM_RANGE_LAST,
};
@@ -111,15 +145,21 @@ struct udma_dev {
u32 features;
+ int bchan_cnt;
int tchan_cnt;
int echan_cnt;
int rchan_cnt;
int rflow_cnt;
+ int tflow_cnt;
+ unsigned long *bchan_map;
unsigned long *tchan_map;
unsigned long *rchan_map;
unsigned long *rflow_map;
unsigned long *rflow_map_reserved;
+ unsigned long *rflow_in_use;
+ unsigned long *tflow_map;
+ struct udma_bchan *bchans;
struct udma_tchan *tchans;
struct udma_rchan *rchans;
struct udma_rflow *rflows;
@@ -143,6 +183,11 @@ struct udma_chan_config {
enum psil_endpoint_type ep_type;
enum udma_tp_level channel_tpl; /* Channel Throughput Level */
+ /* PKTDMA mapped channel */
+ int mapped_channel_id;
+ /* PKTDMA default tflow or rflow for mapped channel */
+ int default_flow_id;
+
enum dma_direction dir;
unsigned int pkt_mode:1; /* TR or packet */
@@ -156,6 +201,7 @@ struct udma_chan {
struct udma_dev *ud;
char name[20];
+ struct udma_bchan *bchan;
struct udma_tchan *tchan;
struct udma_rchan *rchan;
struct udma_rflow *rflow;
@@ -289,6 +335,14 @@ static inline char *udma_get_dir_text(enum dma_direction dir)
return "invalid";
}
+static void udma_reset_uchan(struct udma_chan *uc)
+{
+ memset(&uc->config, 0, sizeof(uc->config));
+ uc->config.remote_thread_id = -1;
+ uc->config.mapped_channel_id = -1;
+ uc->config.default_flow_id = -1;
+}
+
static inline bool udma_is_chan_running(struct udma_chan *uc)
{
u32 trt_ctl = 0;
@@ -371,7 +425,7 @@ static void udma_reset_rings(struct udma_chan *uc)
}
if (ring1)
- k3_nav_ringacc_ring_reset_dma(ring1, 0);
+ k3_nav_ringacc_ring_reset_dma(ring1, k3_nav_ringacc_ring_get_occ(ring1));
if (ring2)
k3_nav_ringacc_ring_reset(ring2);
}
@@ -390,8 +444,10 @@ static void udma_reset_counters(struct udma_chan *uc)
val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PCNT_REG);
udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PCNT_REG, val);
- val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG);
- udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG, val);
+ if (!uc->bchan) {
+ val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG);
+ udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG, val);
+ }
}
if (uc->rchan) {
@@ -640,10 +696,32 @@ static int udma_get_tchan(struct udma_chan *uc)
return 0;
}
- uc->tchan = __udma_reserve_tchan(ud, -1);
+ uc->tchan = __udma_reserve_tchan(ud, uc->config.mapped_channel_id);
if (IS_ERR(uc->tchan))
return PTR_ERR(uc->tchan);
+ if (ud->tflow_cnt) {
+ int tflow_id;
+
+ /* Only PKTDMA have support for tx flows */
+ if (uc->config.default_flow_id >= 0)
+ tflow_id = uc->config.default_flow_id;
+ else
+ tflow_id = uc->tchan->id;
+
+ if (test_bit(tflow_id, ud->tflow_map)) {
+ dev_err(ud->dev, "tflow%d is in use\n", tflow_id);
+ __clear_bit(uc->tchan->id, ud->tchan_map);
+ uc->tchan = NULL;
+ return -ENOENT;
+ }
+
+ uc->tchan->tflow_id = tflow_id;
+ __set_bit(tflow_id, ud->tflow_map);
+ } else {
+ uc->tchan->tflow_id = -1;
+ }
+
pr_debug("chan%d: got tchan%d\n", uc->id, uc->tchan->id);
return 0;
@@ -659,7 +737,7 @@ static int udma_get_rchan(struct udma_chan *uc)
return 0;
}
- uc->rchan = __udma_reserve_rchan(ud, -1);
+ uc->rchan = __udma_reserve_rchan(ud, uc->config.mapped_channel_id);
if (IS_ERR(uc->rchan))
return PTR_ERR(uc->rchan);
@@ -751,6 +829,8 @@ static void udma_put_tchan(struct udma_chan *uc)
dev_dbg(ud->dev, "chan%d: put tchan%d\n", uc->id,
uc->tchan->id);
__clear_bit(uc->tchan->id, ud->tchan_map);
+ if (uc->tchan->tflow_id >= 0)
+ __clear_bit(uc->tchan->tflow_id, ud->tflow_map);
uc->tchan = NULL;
}
}
@@ -855,15 +935,24 @@ static int udma_alloc_rx_resources(struct udma_chan *uc)
if (uc->config.dir == DMA_MEM_TO_MEM)
return 0;
- ret = udma_get_rflow(uc, uc->rchan->id);
+ if (uc->config.default_flow_id >= 0)
+ ret = udma_get_rflow(uc, uc->config.default_flow_id);
+ else
+ ret = udma_get_rflow(uc, uc->rchan->id);
+
if (ret) {
ret = -EBUSY;
goto err_rflow;
}
- fd_ring_id = ud->tchan_cnt + ud->echan_cnt + uc->rchan->id;
-
rflow = uc->rflow;
+ if (ud->tflow_cnt) {
+ fd_ring_id = ud->tflow_cnt + rflow->id;
+ } else {
+ fd_ring_id = ud->bchan_cnt + ud->tchan_cnt + ud->echan_cnt +
+ uc->rchan->id;
+ }
+
ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, fd_ring_id, -1,
&rflow->fd_ring, &rflow->r_ring);
if (ret) {
@@ -950,9 +1039,7 @@ static int udma_alloc_rchan_sci_req(struct udma_chan *uc)
req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |
TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID |
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID |
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID;
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID;
req.nav_id = tisci_rm->tisci_dev_id;
req.index = uc->rchan->id;
req.rx_chan_type = mode;
@@ -965,9 +1052,13 @@ static int udma_alloc_rchan_sci_req(struct udma_chan *uc)
0) >> 2;
req.rxcq_qnum = rx_ring;
}
- if (uc->rflow->id != uc->rchan->id && uc->config.dir != DMA_MEM_TO_MEM) {
+ if (ud->match_data->type == DMA_TYPE_UDMA &&
+ uc->rflow->id != uc->rchan->id &&
+ uc->config.dir != DMA_MEM_TO_MEM) {
req.flowid_start = uc->rflow->id;
req.flowid_cnt = 1;
+ req.valid_params |= TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID |
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID;
}
ret = tisci_rm->tisci_udmap_ops->rx_ch_cfg(tisci_rm->tisci, &req);
@@ -1150,12 +1241,58 @@ static void udma_free_chan_resources(struct udma_chan *uc)
uc->config.dir = DMA_MEM_TO_MEM;
}
+static const char * const range_names[] = {
+ [RM_RANGE_BCHAN] = "ti,sci-rm-range-bchan",
+ [RM_RANGE_TCHAN] = "ti,sci-rm-range-tchan",
+ [RM_RANGE_RCHAN] = "ti,sci-rm-range-rchan",
+ [RM_RANGE_RFLOW] = "ti,sci-rm-range-rflow",
+ [RM_RANGE_TFLOW] = "ti,sci-rm-range-tflow",
+};
+
static int udma_get_mmrs(struct udevice *dev)
{
struct udma_dev *ud = dev_get_priv(dev);
+ u32 cap2, cap3, cap4;
int i;
- for (i = 0; i < MMR_LAST; i++) {
+ ud->mmrs[MMR_GCFG] = (uint32_t *)devfdt_get_addr_name(dev, mmr_names[MMR_GCFG]);
+ if (!ud->mmrs[MMR_GCFG])
+ return -EINVAL;
+
+ cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28);
+ cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
+
+ switch (ud->match_data->type) {
+ case DMA_TYPE_UDMA:
+ ud->rflow_cnt = cap3 & 0x3fff;
+ ud->tchan_cnt = cap2 & 0x1ff;
+ ud->echan_cnt = (cap2 >> 9) & 0x1ff;
+ ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
+ break;
+ case DMA_TYPE_BCDMA:
+ ud->bchan_cnt = cap2 & 0x1ff;
+ ud->tchan_cnt = (cap2 >> 9) & 0x1ff;
+ ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
+ break;
+ case DMA_TYPE_PKTDMA:
+ cap4 = udma_read(ud->mmrs[MMR_GCFG], 0x30);
+ ud->tchan_cnt = cap2 & 0x1ff;
+ ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
+ ud->rflow_cnt = cap3 & 0x3fff;
+ ud->tflow_cnt = cap4 & 0x3fff;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ for (i = 1; i < MMR_LAST; i++) {
+ if (i == MMR_BCHANRT && ud->bchan_cnt == 0)
+ continue;
+ if (i == MMR_TCHANRT && ud->tchan_cnt == 0)
+ continue;
+ if (i == MMR_RCHANRT && ud->rchan_cnt == 0)
+ continue;
+
ud->mmrs[i] = (uint32_t *)devfdt_get_addr_name(dev,
mmr_names[i]);
if (!ud->mmrs[i])
@@ -1168,23 +1305,10 @@ static int udma_get_mmrs(struct udevice *dev)
static int udma_setup_resources(struct udma_dev *ud)
{
struct udevice *dev = ud->dev;
- int ch_count, i;
- u32 cap2, cap3;
+ int i;
struct ti_sci_resource_desc *rm_desc;
struct ti_sci_resource *rm_res;
struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
- static const char * const range_names[] = { "ti,sci-rm-range-tchan",
- "ti,sci-rm-range-rchan",
- "ti,sci-rm-range-rflow" };
-
- cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28);
- cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
-
- ud->rflow_cnt = cap3 & 0x3fff;
- ud->tchan_cnt = cap2 & 0x1ff;
- ud->echan_cnt = (cap2 >> 9) & 0x1ff;
- ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
- ch_count = ud->tchan_cnt + ud->rchan_cnt;
ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
sizeof(unsigned long), GFP_KERNEL);
@@ -1215,11 +1339,15 @@ static int udma_setup_resources(struct udma_dev *ud)
bitmap_set(ud->rflow_map_reserved, 0, ud->rchan_cnt);
/* Get resource ranges from tisci */
- for (i = 0; i < RM_RANGE_LAST; i++)
+ for (i = 0; i < RM_RANGE_LAST; i++) {
+ if (i == RM_RANGE_BCHAN || i == RM_RANGE_TFLOW)
+ continue;
+
tisci_rm->rm_ranges[i] =
devm_ti_sci_get_of_resource(tisci_rm->tisci, dev,
tisci_rm->tisci_dev_id,
(char *)range_names[i]);
+ }
/* tchan ranges */
rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
@@ -1266,6 +1394,229 @@ static int udma_setup_resources(struct udma_dev *ud)
}
}
+ return 0;
+}
+
+static int bcdma_setup_resources(struct udma_dev *ud)
+{
+ int i;
+ struct udevice *dev = ud->dev;
+ struct ti_sci_resource_desc *rm_desc;
+ struct ti_sci_resource *rm_res;
+ struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+
+ ud->bchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->bchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->bchans = devm_kcalloc(dev, ud->bchan_cnt, sizeof(*ud->bchans),
+ GFP_KERNEL);
+ ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
+ GFP_KERNEL);
+ ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
+ GFP_KERNEL);
+ /* BCDMA do not really have flows, but the driver expect it */
+ ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt),
+ sizeof(unsigned long),
+ GFP_KERNEL);
+ ud->rflows = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rflows),
+ GFP_KERNEL);
+
+ if (!ud->bchan_map || !ud->tchan_map || !ud->rchan_map ||
+ !ud->rflow_in_use || !ud->bchans || !ud->tchans || !ud->rchans ||
+ !ud->rflows)
+ return -ENOMEM;
+
+ /* Get resource ranges from tisci */
+ for (i = 0; i < RM_RANGE_LAST; i++) {
+ if (i == RM_RANGE_RFLOW || i == RM_RANGE_TFLOW)
+ continue;
+
+ tisci_rm->rm_ranges[i] =
+ devm_ti_sci_get_of_resource(tisci_rm->tisci, dev,
+ tisci_rm->tisci_dev_id,
+ (char *)range_names[i]);
+ }
+
+ /* bchan ranges */
+ rm_res = tisci_rm->rm_ranges[RM_RANGE_BCHAN];
+ if (IS_ERR(rm_res)) {
+ bitmap_zero(ud->bchan_map, ud->bchan_cnt);
+ } else {
+ bitmap_fill(ud->bchan_map, ud->bchan_cnt);
+ for (i = 0; i < rm_res->sets; i++) {
+ rm_desc = &rm_res->desc[i];
+ bitmap_clear(ud->bchan_map, rm_desc->start,
+ rm_desc->num);
+ dev_dbg(dev, "ti-sci-res: bchan: %d:%d\n",
+ rm_desc->start, rm_desc->num);
+ }
+ }
+
+ /* tchan ranges */
+ rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
+ if (IS_ERR(rm_res)) {
+ bitmap_zero(ud->tchan_map, ud->tchan_cnt);
+ } else {
+ bitmap_fill(ud->tchan_map, ud->tchan_cnt);
+ for (i = 0; i < rm_res->sets; i++) {
+ rm_desc = &rm_res->desc[i];
+ bitmap_clear(ud->tchan_map, rm_desc->start,
+ rm_desc->num);
+ dev_dbg(dev, "ti-sci-res: tchan: %d:%d\n",
+ rm_desc->start, rm_desc->num);
+ }
+ }
+
+ /* rchan ranges */
+ rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN];
+ if (IS_ERR(rm_res)) {
+ bitmap_zero(ud->rchan_map, ud->rchan_cnt);
+ } else {
+ bitmap_fill(ud->rchan_map, ud->rchan_cnt);
+ for (i = 0; i < rm_res->sets; i++) {
+ rm_desc = &rm_res->desc[i];
+ bitmap_clear(ud->rchan_map, rm_desc->start,
+ rm_desc->num);
+ dev_dbg(dev, "ti-sci-res: rchan: %d:%d\n",
+ rm_desc->start, rm_desc->num);
+ }
+ }
+
+ return 0;
+}
+
+static int pktdma_setup_resources(struct udma_dev *ud)
+{
+ int i;
+ struct udevice *dev = ud->dev;
+ struct ti_sci_resource *rm_res;
+ struct ti_sci_resource_desc *rm_desc;
+ struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+
+ ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
+ GFP_KERNEL);
+ ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
+ GFP_KERNEL);
+ ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt),
+ sizeof(unsigned long),
+ GFP_KERNEL);
+ ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows),
+ GFP_KERNEL);
+ ud->tflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tflow_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+
+ if (!ud->tchan_map || !ud->rchan_map || !ud->tflow_map || !ud->tchans ||
+ !ud->rchans || !ud->rflows || !ud->rflow_in_use)
+ return -ENOMEM;
+
+ /* Get resource ranges from tisci */
+ for (i = 0; i < RM_RANGE_LAST; i++) {
+ if (i == RM_RANGE_BCHAN)
+ continue;
+
+ tisci_rm->rm_ranges[i] =
+ devm_ti_sci_get_of_resource(tisci_rm->tisci, dev,
+ tisci_rm->tisci_dev_id,
+ (char *)range_names[i]);
+ }
+
+ /* tchan ranges */
+ rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
+ if (IS_ERR(rm_res)) {
+ bitmap_zero(ud->tchan_map, ud->tchan_cnt);
+ } else {
+ bitmap_fill(ud->tchan_map, ud->tchan_cnt);
+ for (i = 0; i < rm_res->sets; i++) {
+ rm_desc = &rm_res->desc[i];
+ bitmap_clear(ud->tchan_map, rm_desc->start,
+ rm_desc->num);
+ dev_dbg(dev, "ti-sci-res: tchan: %d:%d\n",
+ rm_desc->start, rm_desc->num);
+ }
+ }
+
+ /* rchan ranges */
+ rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN];
+ if (IS_ERR(rm_res)) {
+ bitmap_zero(ud->rchan_map, ud->rchan_cnt);
+ } else {
+ bitmap_fill(ud->rchan_map, ud->rchan_cnt);
+ for (i = 0; i < rm_res->sets; i++) {
+ rm_desc = &rm_res->desc[i];
+ bitmap_clear(ud->rchan_map, rm_desc->start,
+ rm_desc->num);
+ dev_dbg(dev, "ti-sci-res: rchan: %d:%d\n",
+ rm_desc->start, rm_desc->num);
+ }
+ }
+
+ /* rflow ranges */
+ rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW];
+ if (IS_ERR(rm_res)) {
+ /* all rflows are assigned exclusively to Linux */
+ bitmap_zero(ud->rflow_in_use, ud->rflow_cnt);
+ } else {
+ bitmap_fill(ud->rflow_in_use, ud->rflow_cnt);
+ for (i = 0; i < rm_res->sets; i++) {
+ rm_desc = &rm_res->desc[i];
+ bitmap_clear(ud->rflow_in_use, rm_desc->start,
+ rm_desc->num);
+ dev_dbg(dev, "ti-sci-res: rflow: %d:%d\n",
+ rm_desc->start, rm_desc->num);
+ }
+ }
+
+ /* tflow ranges */
+ rm_res = tisci_rm->rm_ranges[RM_RANGE_TFLOW];
+ if (IS_ERR(rm_res)) {
+ /* all tflows are assigned exclusively to Linux */
+ bitmap_zero(ud->tflow_map, ud->tflow_cnt);
+ } else {
+ bitmap_fill(ud->tflow_map, ud->tflow_cnt);
+ for (i = 0; i < rm_res->sets; i++) {
+ rm_desc = &rm_res->desc[i];
+ bitmap_clear(ud->tflow_map, rm_desc->start,
+ rm_desc->num);
+ dev_dbg(dev, "ti-sci-res: tflow: %d:%d\n",
+ rm_desc->start, rm_desc->num);
+ }
+ }
+
+ return 0;
+}
+
+static int setup_resources(struct udma_dev *ud)
+{
+ struct udevice *dev = ud->dev;
+ int ch_count, ret;
+
+ switch (ud->match_data->type) {
+ case DMA_TYPE_UDMA:
+ ret = udma_setup_resources(ud);
+ break;
+ case DMA_TYPE_BCDMA:
+ ret = bcdma_setup_resources(ud);
+ break;
+ case DMA_TYPE_PKTDMA:
+ ret = pktdma_setup_resources(ud);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (ret)
+ return ret;
+
+ ch_count = ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt;
+ if (ud->bchan_cnt)
+ ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt);
ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt);
ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt);
if (!ch_count)
@@ -1276,13 +1627,45 @@ static int udma_setup_resources(struct udma_dev *ud)
if (!ud->channels)
return -ENOMEM;
- dev_info(dev,
- "Channels: %d (tchan: %u, echan: %u, rchan: %u, rflow: %u)\n",
- ch_count, ud->tchan_cnt, ud->echan_cnt, ud->rchan_cnt,
- ud->rflow_cnt);
+ switch (ud->match_data->type) {
+ case DMA_TYPE_UDMA:
+ dev_dbg(dev,
+ "Channels: %d (tchan: %u, rchan: %u, gp-rflow: %u)\n",
+ ch_count,
+ ud->tchan_cnt - bitmap_weight(ud->tchan_map,
+ ud->tchan_cnt),
+ ud->rchan_cnt - bitmap_weight(ud->rchan_map,
+ ud->rchan_cnt),
+ ud->rflow_cnt - bitmap_weight(ud->rflow_map,
+ ud->rflow_cnt));
+ break;
+ case DMA_TYPE_BCDMA:
+ dev_dbg(dev,
+ "Channels: %d (bchan: %u, tchan: %u, rchan: %u)\n",
+ ch_count,
+ ud->bchan_cnt - bitmap_weight(ud->bchan_map,
+ ud->bchan_cnt),
+ ud->tchan_cnt - bitmap_weight(ud->tchan_map,
+ ud->tchan_cnt),
+ ud->rchan_cnt - bitmap_weight(ud->rchan_map,
+ ud->rchan_cnt));
+ break;
+ case DMA_TYPE_PKTDMA:
+ dev_dbg(dev,
+ "Channels: %d (tchan: %u, rchan: %u)\n",
+ ch_count,
+ ud->tchan_cnt - bitmap_weight(ud->tchan_map,
+ ud->tchan_cnt),
+ ud->rchan_cnt - bitmap_weight(ud->rchan_map,
+ ud->rchan_cnt));
+ break;
+ default:
+ break;
+ }
return ch_count;
}
+
static int udma_probe(struct udevice *dev)
{
struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
@@ -1294,17 +1677,11 @@ static int udma_probe(struct udevice *dev)
ofnode navss_ofnode = ofnode_get_parent(dev_ofnode(dev));
+ ud->match_data = (void *)dev_get_driver_data(dev);
ret = udma_get_mmrs(dev);
if (ret)
return ret;
- ret = uclass_get_device_by_phandle(UCLASS_MISC, dev,
- "ti,ringacc", &tmp);
- ud->ringacc = dev_get_priv(tmp);
- if (IS_ERR(ud->ringacc))
- return PTR_ERR(ud->ringacc);
-
- ud->match_data = (void *)dev_get_driver_data(dev);
ud->psil_base = ud->match_data->psil_base;
ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev,
@@ -1335,16 +1712,40 @@ static int udma_probe(struct udevice *dev)
tisci_rm->tisci_udmap_ops = &tisci_rm->tisci->ops.rm_udmap_ops;
tisci_rm->tisci_psil_ops = &tisci_rm->tisci->ops.rm_psil_ops;
+ if (ud->match_data->type == DMA_TYPE_UDMA) {
+ ret = uclass_get_device_by_phandle(UCLASS_MISC, dev,
+ "ti,ringacc", &tmp);
+ ud->ringacc = dev_get_priv(tmp);
+ } else {
+ struct k3_ringacc_init_data ring_init_data;
+
+ ring_init_data.tisci = ud->tisci_rm.tisci;
+ ring_init_data.tisci_dev_id = ud->tisci_rm.tisci_dev_id;
+ if (ud->match_data->type == DMA_TYPE_BCDMA) {
+ ring_init_data.num_rings = ud->bchan_cnt +
+ ud->tchan_cnt +
+ ud->rchan_cnt;
+ } else {
+ ring_init_data.num_rings = ud->rflow_cnt +
+ ud->tflow_cnt;
+ }
+
+ ud->ringacc = k3_ringacc_dmarings_init(dev, &ring_init_data);
+ }
+ if (IS_ERR(ud->ringacc))
+ return PTR_ERR(ud->ringacc);
+
ud->dev = dev;
- ud->ch_count = udma_setup_resources(ud);
+ ud->ch_count = setup_resources(ud);
if (ud->ch_count <= 0)
return ud->ch_count;
- dev_info(dev,
- "Number of channels: %u (tchan: %u, echan: %u, rchan: %u dev-id %u)\n",
- ud->ch_count, ud->tchan_cnt, ud->echan_cnt, ud->rchan_cnt,
- tisci_rm->tisci_dev_id);
- dev_info(dev, "Number of rflows: %u\n", ud->rflow_cnt);
+ for (i = 0; i < ud->bchan_cnt; i++) {
+ struct udma_bchan *bchan = &ud->bchans[i];
+
+ bchan->id = i;
+ bchan->reg_rt = ud->mmrs[MMR_BCHANRT] + i * 0x1000;
+ }
for (i = 0; i < ud->tchan_cnt; i++) {
struct udma_tchan *tchan = &ud->tchans[i];
@@ -1372,15 +1773,19 @@ static int udma_probe(struct udevice *dev)
uc->ud = ud;
uc->id = i;
uc->config.remote_thread_id = -1;
+ uc->bchan = NULL;
uc->tchan = NULL;
uc->rchan = NULL;
+ uc->config.mapped_channel_id = -1;
+ uc->config.default_flow_id = -1;
uc->config.dir = DMA_MEM_TO_MEM;
sprintf(uc->name, "UDMA chan%d\n", i);
if (!i)
uc->in_use = true;
}
- pr_debug("UDMA(rev: 0x%08x) CAP0-3: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
+ pr_debug("%s(rev: 0x%08x) CAP0-3: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
+ dev->name,
udma_read(ud->mmrs[MMR_GCFG], 0),
udma_read(ud->mmrs[MMR_GCFG], 0x20),
udma_read(ud->mmrs[MMR_GCFG], 0x24),
@@ -1496,6 +1901,379 @@ static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest,
return 0;
}
+#define TISCI_BCDMA_BCHAN_VALID_PARAMS ( \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID)
+
+#define TISCI_BCDMA_TCHAN_VALID_PARAMS ( \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID)
+
+#define TISCI_BCDMA_RCHAN_VALID_PARAMS ( \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID)
+
+#define TISCI_UDMA_TCHAN_VALID_PARAMS ( \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID)
+
+#define TISCI_UDMA_RCHAN_VALID_PARAMS ( \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID)
+
+static int bcdma_tisci_m2m_channel_config(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+ struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+ const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops;
+ struct ti_sci_msg_rm_udmap_tx_ch_cfg req_tx = { 0 };
+ struct udma_bchan *bchan = uc->bchan;
+ int ret = 0;
+
+ req_tx.valid_params = TISCI_BCDMA_BCHAN_VALID_PARAMS;
+ req_tx.nav_id = tisci_rm->tisci_dev_id;
+ req_tx.extended_ch_type = TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN;
+ req_tx.index = bchan->id;
+
+ ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx);
+ if (ret)
+ dev_err(ud->dev, "bchan%d cfg failed %d\n", bchan->id, ret);
+
+ return ret;
+}
+
+static struct udma_bchan *__bcdma_reserve_bchan(struct udma_dev *ud, int id)
+{
+ if (id >= 0) {
+ if (test_bit(id, ud->bchan_map)) {
+ dev_err(ud->dev, "bchan%d is in use\n", id);
+ return ERR_PTR(-ENOENT);
+ }
+ } else {
+ id = find_next_zero_bit(ud->bchan_map, ud->bchan_cnt, 0);
+ if (id == ud->bchan_cnt)
+ return ERR_PTR(-ENOENT);
+ }
+ __set_bit(id, ud->bchan_map);
+ return &ud->bchans[id];
+}
+
+static int bcdma_get_bchan(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+
+ if (uc->bchan) {
+ dev_err(ud->dev, "chan%d: already have bchan%d allocated\n",
+ uc->id, uc->bchan->id);
+ return 0;
+ }
+
+ uc->bchan = __bcdma_reserve_bchan(ud, -1);
+ if (IS_ERR(uc->bchan))
+ return PTR_ERR(uc->bchan);
+
+ uc->tchan = uc->bchan;
+
+ return 0;
+}
+
+static void bcdma_put_bchan(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+
+ if (uc->bchan) {
+ dev_dbg(ud->dev, "chan%d: put bchan%d\n", uc->id,
+ uc->bchan->id);
+ __clear_bit(uc->bchan->id, ud->bchan_map);
+ uc->bchan = NULL;
+ uc->tchan = NULL;
+ }
+}
+
+static void bcdma_free_bchan_resources(struct udma_chan *uc)
+{
+ if (!uc->bchan)
+ return;
+
+ k3_nav_ringacc_ring_free(uc->bchan->tc_ring);
+ k3_nav_ringacc_ring_free(uc->bchan->t_ring);
+ uc->bchan->tc_ring = NULL;
+ uc->bchan->t_ring = NULL;
+
+ bcdma_put_bchan(uc);
+}
+
+static int bcdma_alloc_bchan_resources(struct udma_chan *uc)
+{
+ struct k3_nav_ring_cfg ring_cfg;
+ struct udma_dev *ud = uc->ud;
+ int ret;
+
+ ret = bcdma_get_bchan(uc);
+ if (ret)
+ return ret;
+
+ ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, uc->bchan->id, -1,
+ &uc->bchan->t_ring,
+ &uc->bchan->tc_ring);
+ if (ret) {
+ ret = -EBUSY;
+ goto err_ring;
+ }
+
+ memset(&ring_cfg, 0, sizeof(ring_cfg));
+ ring_cfg.size = 16;
+ ring_cfg.elm_size = K3_NAV_RINGACC_RING_ELSIZE_8;
+ ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_RING;
+
+ ret = k3_nav_ringacc_ring_cfg(uc->bchan->t_ring, &ring_cfg);
+ if (ret)
+ goto err_ringcfg;
+
+ return 0;
+
+err_ringcfg:
+ k3_nav_ringacc_ring_free(uc->bchan->tc_ring);
+ uc->bchan->tc_ring = NULL;
+ k3_nav_ringacc_ring_free(uc->bchan->t_ring);
+ uc->bchan->t_ring = NULL;
+err_ring:
+ bcdma_put_bchan(uc);
+
+ return ret;
+}
+
+static int bcdma_tisci_tx_channel_config(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+ struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+ const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops;
+ struct udma_tchan *tchan = uc->tchan;
+ struct ti_sci_msg_rm_udmap_tx_ch_cfg req_tx = { 0 };
+ int ret = 0;
+
+ req_tx.valid_params = TISCI_BCDMA_TCHAN_VALID_PARAMS;
+ req_tx.nav_id = tisci_rm->tisci_dev_id;
+ req_tx.index = tchan->id;
+ req_tx.tx_supr_tdpkt = uc->config.notdpkt;
+ if (uc->config.ep_type == PSIL_EP_PDMA_XY &&
+ ud->match_data->flags & UDMA_FLAG_TDTYPE) {
+ /* wait for peer to complete the teardown for PDMAs */
+ req_tx.valid_params |=
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID;
+ req_tx.tx_tdtype = 1;
+ }
+
+ ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx);
+ if (ret)
+ dev_err(ud->dev, "tchan%d cfg failed %d\n", tchan->id, ret);
+
+ return ret;
+}
+
+#define pktdma_tisci_tx_channel_config bcdma_tisci_tx_channel_config
+
+static int pktdma_tisci_rx_channel_config(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+ struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+ const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops;
+ struct ti_sci_msg_rm_udmap_rx_ch_cfg req_rx = { 0 };
+ struct ti_sci_msg_rm_udmap_flow_cfg flow_req = { 0 };
+ int ret = 0;
+
+ req_rx.valid_params = TISCI_BCDMA_RCHAN_VALID_PARAMS;
+ req_rx.nav_id = tisci_rm->tisci_dev_id;
+ req_rx.index = uc->rchan->id;
+
+ ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx);
+ if (ret) {
+ dev_err(ud->dev, "rchan%d cfg failed %d\n", uc->rchan->id, ret);
+ return ret;
+ }
+
+ flow_req.valid_params =
+ TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID |
+ TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID |
+ TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID;
+
+ flow_req.nav_id = tisci_rm->tisci_dev_id;
+ flow_req.flow_index = uc->rflow->id;
+
+ if (uc->config.needs_epib)
+ flow_req.rx_einfo_present = 1;
+ else
+ flow_req.rx_einfo_present = 0;
+ if (uc->config.psd_size)
+ flow_req.rx_psinfo_present = 1;
+ else
+ flow_req.rx_psinfo_present = 0;
+ flow_req.rx_error_handling = 1;
+
+ ret = tisci_ops->rx_flow_cfg(tisci_rm->tisci, &flow_req);
+
+ if (ret)
+ dev_err(ud->dev, "flow%d config failed: %d\n", uc->rflow->id,
+ ret);
+
+ return ret;
+}
+
+static int bcdma_alloc_chan_resources(struct udma_chan *uc)
+{
+ int ret;
+
+ uc->config.pkt_mode = false;
+
+ switch (uc->config.dir) {
+ case DMA_MEM_TO_MEM:
+ /* Non synchronized - mem to mem type of transfer */
+ dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-MEM\n", __func__,
+ uc->id);
+
+ ret = bcdma_alloc_bchan_resources(uc);
+ if (ret)
+ return ret;
+
+ ret = bcdma_tisci_m2m_channel_config(uc);
+ break;
+ default:
+ /* Can not happen */
+ dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n",
+ __func__, uc->id, uc->config.dir);
+ return -EINVAL;
+ }
+
+ /* check if the channel configuration was successful */
+ if (ret)
+ goto err_res_free;
+
+ if (udma_is_chan_running(uc)) {
+ dev_warn(uc->ud->dev, "chan%d: is running!\n", uc->id);
+ udma_stop(uc);
+ if (udma_is_chan_running(uc)) {
+ dev_err(uc->ud->dev, "chan%d: won't stop!\n", uc->id);
+ goto err_res_free;
+ }
+ }
+
+ udma_reset_rings(uc);
+
+ return 0;
+
+err_res_free:
+ bcdma_free_bchan_resources(uc);
+ udma_free_tx_resources(uc);
+ udma_free_rx_resources(uc);
+
+ udma_reset_uchan(uc);
+
+ return ret;
+}
+
+static int pktdma_alloc_chan_resources(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+ int ret;
+
+ switch (uc->config.dir) {
+ case DMA_MEM_TO_DEV:
+ /* Slave transfer synchronized - mem to dev (TX) trasnfer */
+ dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__,
+ uc->id);
+
+ ret = udma_alloc_tx_resources(uc);
+ if (ret) {
+ uc->config.remote_thread_id = -1;
+ return ret;
+ }
+
+ uc->config.src_thread = ud->psil_base + uc->tchan->id;
+ uc->config.dst_thread = uc->config.remote_thread_id;
+ uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET;
+
+ ret = pktdma_tisci_tx_channel_config(uc);
+ break;
+ case DMA_DEV_TO_MEM:
+ /* Slave transfer synchronized - dev to mem (RX) trasnfer */
+ dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__,
+ uc->id);
+
+ ret = udma_alloc_rx_resources(uc);
+ if (ret) {
+ uc->config.remote_thread_id = -1;
+ return ret;
+ }
+
+ uc->config.src_thread = uc->config.remote_thread_id;
+ uc->config.dst_thread = (ud->psil_base + uc->rchan->id) |
+ K3_PSIL_DST_THREAD_ID_OFFSET;
+
+ ret = pktdma_tisci_rx_channel_config(uc);
+ break;
+ default:
+ /* Can not happen */
+ dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n",
+ __func__, uc->id, uc->config.dir);
+ return -EINVAL;
+ }
+
+ /* check if the channel configuration was successful */
+ if (ret)
+ goto err_res_free;
+
+ /* PSI-L pairing */
+ ret = udma_navss_psil_pair(ud, uc->config.src_thread, uc->config.dst_thread);
+ if (ret) {
+ dev_err(ud->dev, "PSI-L pairing failed: 0x%04x -> 0x%04x\n",
+ uc->config.src_thread, uc->config.dst_thread);
+ goto err_res_free;
+ }
+
+ if (udma_is_chan_running(uc)) {
+ dev_warn(ud->dev, "chan%d: is running!\n", uc->id);
+ udma_stop(uc);
+ if (udma_is_chan_running(uc)) {
+ dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
+ goto err_res_free;
+ }
+ }
+
+ udma_reset_rings(uc);
+
+ if (uc->tchan)
+ dev_dbg(ud->dev,
+ "chan%d: tchan%d, tflow%d, Remote thread: 0x%04x\n",
+ uc->id, uc->tchan->id, uc->tchan->tflow_id,
+ uc->config.remote_thread_id);
+ else if (uc->rchan)
+ dev_dbg(ud->dev,
+ "chan%d: rchan%d, rflow%d, Remote thread: 0x%04x\n",
+ uc->id, uc->rchan->id, uc->rflow->id,
+ uc->config.remote_thread_id);
+ return 0;
+
+err_res_free:
+ udma_free_tx_resources(uc);
+ udma_free_rx_resources(uc);
+
+ udma_reset_uchan(uc);
+
+ return ret;
+}
+
static int udma_transfer(struct udevice *dev, int direction,
void *dst, void *src, size_t len)
{
@@ -1505,7 +2283,16 @@ static int udma_transfer(struct udevice *dev, int direction,
dma_addr_t paddr = 0;
int ret;
- ret = udma_alloc_chan_resources(uc);
+ switch (ud->match_data->type) {
+ case DMA_TYPE_UDMA:
+ ret = udma_alloc_chan_resources(uc);
+ break;
+ case DMA_TYPE_BCDMA:
+ ret = bcdma_alloc_chan_resources(uc);
+ break;
+ default:
+ return -EINVAL;
+ };
if (ret)
return ret;
@@ -1514,7 +2301,17 @@ static int udma_transfer(struct udevice *dev, int direction,
udma_poll_completion(uc, &paddr);
udma_stop(uc);
- udma_free_chan_resources(uc);
+ switch (ud->match_data->type) {
+ case DMA_TYPE_UDMA:
+ udma_free_chan_resources(uc);
+ break;
+ case DMA_TYPE_BCDMA:
+ bcdma_free_bchan_resources(uc);
+ break;
+ default:
+ return -EINVAL;
+ };
+
return 0;
}
@@ -1533,7 +2330,19 @@ static int udma_request(struct dma *dma)
uc = &ud->channels[dma->id];
ucc = &uc->config;
- ret = udma_alloc_chan_resources(uc);
+ switch (ud->match_data->type) {
+ case DMA_TYPE_UDMA:
+ ret = udma_alloc_chan_resources(uc);
+ break;
+ case DMA_TYPE_BCDMA:
+ ret = bcdma_alloc_chan_resources(uc);
+ break;
+ case DMA_TYPE_PKTDMA:
+ ret = pktdma_alloc_chan_resources(uc);
+ break;
+ default:
+ return -EINVAL;
+ }
if (ret) {
dev_err(dma->dev, "alloc dma res failed %d\n", ret);
return -EINVAL;
@@ -1573,7 +2382,14 @@ static int udma_rfree(struct dma *dma)
if (udma_is_chan_running(uc))
udma_stop(uc);
- udma_free_chan_resources(uc);
+
+ udma_navss_psil_unpair(ud, uc->config.src_thread,
+ uc->config.dst_thread);
+
+ bcdma_free_bchan_resources(uc);
+ udma_free_tx_resources(uc);
+ udma_free_rx_resources(uc);
+ udma_reset_uchan(uc);
uc->in_use = false;
@@ -1764,6 +2580,15 @@ static int udma_of_xlate(struct dma *dma, struct ofnode_phandle_args *args)
ucc->notdpkt = ep_config->notdpkt;
ucc->ep_type = ep_config->ep_type;
+ if (ud->match_data->type == DMA_TYPE_PKTDMA &&
+ ep_config->mapped_channel_id >= 0) {
+ ucc->mapped_channel_id = ep_config->mapped_channel_id;
+ ucc->default_flow_id = ep_config->default_flow_id;
+ } else {
+ ucc->mapped_channel_id = -1;
+ ucc->default_flow_id = -1;
+ }
+
ucc->needs_epib = ep_config->needs_epib;
ucc->psd_size = ep_config->psd_size;
ucc->metadata_size = (ucc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_SIZE : 0) + ucc->psd_size;
@@ -1859,10 +2684,13 @@ static const struct dma_ops udma_ops = {
};
static struct udma_match_data am654_main_data = {
+ .type = DMA_TYPE_UDMA,
.psil_base = 0x1000,
.enable_memcpy_support = true,
.statictr_z_mask = GENMASK(11, 0),
- .rchan_oes_offset = 0x200,
+ .oes = {
+ .udma_rchan = 0x200,
+ },
.tpl_levels = 2,
.level_start_idx = {
[0] = 8, /* Normal channels */
@@ -1871,10 +2699,13 @@ static struct udma_match_data am654_main_data = {
};
static struct udma_match_data am654_mcu_data = {
+ .type = DMA_TYPE_UDMA,
.psil_base = 0x6000,
.enable_memcpy_support = true,
.statictr_z_mask = GENMASK(11, 0),
- .rchan_oes_offset = 0x200,
+ .oes = {
+ .udma_rchan = 0x200,
+ },
.tpl_levels = 2,
.level_start_idx = {
[0] = 2, /* Normal channels */
@@ -1883,11 +2714,14 @@ static struct udma_match_data am654_mcu_data = {
};
static struct udma_match_data j721e_main_data = {
+ .type = DMA_TYPE_UDMA,
.psil_base = 0x1000,
.enable_memcpy_support = true,
.flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
.statictr_z_mask = GENMASK(23, 0),
- .rchan_oes_offset = 0x400,
+ .oes = {
+ .udma_rchan = 0x400,
+ },
.tpl_levels = 3,
.level_start_idx = {
[0] = 16, /* Normal channels */
@@ -1897,11 +2731,14 @@ static struct udma_match_data j721e_main_data = {
};
static struct udma_match_data j721e_mcu_data = {
+ .type = DMA_TYPE_UDMA,
.psil_base = 0x6000,
.enable_memcpy_support = true,
.flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
.statictr_z_mask = GENMASK(23, 0),
- .rchan_oes_offset = 0x400,
+ .oes = {
+ .udma_rchan = 0x400,
+ },
.tpl_levels = 2,
.level_start_idx = {
[0] = 2, /* Normal channels */
@@ -1909,6 +2746,36 @@ static struct udma_match_data j721e_mcu_data = {
},
};
+static struct udma_match_data am64_bcdma_data = {
+ .type = DMA_TYPE_BCDMA,
+ .psil_base = 0x2000, /* for tchan and rchan, not applicable to bchan */
+ .enable_memcpy_support = true, /* Supported via bchan */
+ .flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
+ .statictr_z_mask = GENMASK(23, 0),
+ .oes = {
+ .bcdma_bchan_data = 0x2200,
+ .bcdma_bchan_ring = 0x2400,
+ .bcdma_tchan_data = 0x2800,
+ .bcdma_tchan_ring = 0x2a00,
+ .bcdma_rchan_data = 0x2e00,
+ .bcdma_rchan_ring = 0x3000,
+ },
+ /* No throughput levels */
+};
+
+static struct udma_match_data am64_pktdma_data = {
+ .type = DMA_TYPE_PKTDMA,
+ .psil_base = 0x1000,
+ .enable_memcpy_support = false,
+ .flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
+ .statictr_z_mask = GENMASK(23, 0),
+ .oes = {
+ .pktdma_tchan_flow = 0x1200,
+ .pktdma_rchan_flow = 0x1600,
+ },
+ /* No throughput levels */
+};
+
static const struct udevice_id udma_ids[] = {
{
.compatible = "ti,am654-navss-main-udmap",
@@ -1924,6 +2791,14 @@ static const struct udevice_id udma_ids[] = {
.compatible = "ti,j721e-navss-mcu-udmap",
.data = (ulong)&j721e_mcu_data,
},
+ {
+ .compatible = "ti,am64-dmss-bcdma",
+ .data = (ulong)&am64_bcdma_data,
+ },
+ {
+ .compatible = "ti,am64-dmss-pktdma",
+ .data = (ulong)&am64_pktdma_data,
+ },
{ /* Sentinel */ },
};
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 08/12] net: ti: am65-cpsw-nuss: Prepare to support non primary ext port
2021-05-10 14:36 [PATCH 00/12] AM64x: DMA and ethernet support Vignesh Raghavendra
` (6 preceding siblings ...)
2021-05-10 14:36 ` [PATCH 07/12] dma: ti: k3-udma: Add BCDMA and PKTDMA support Vignesh Raghavendra
@ 2021-05-10 14:36 ` Vignesh Raghavendra
2021-05-15 19:50 ` Ramon Fried
2021-05-10 14:36 ` [PATCH 09/12] net: ti: am65-cpsw-nuss: Don't cache disabled port ID Vignesh Raghavendra
` (4 subsequent siblings)
12 siblings, 1 reply; 17+ messages in thread
From: Vignesh Raghavendra @ 2021-05-10 14:36 UTC (permalink / raw)
To: u-boot
CPSW NUSS IP on K3 SoCs can have more than one external port (upto 8)
Therefore increase AM65_CPSW_CPSWNU_MAX_PORTS to 9 (8 ext + 1 Root port)
as preparation to allow any one of the 8 ports to be used as ethernet
interface in U-Boot.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
drivers/net/ti/am65-cpsw-nuss.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index e6954b64b7..9f11ce63b9 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -26,7 +26,7 @@
#include "cpsw_mdio.h"
-#define AM65_CPSW_CPSWNU_MAX_PORTS 2
+#define AM65_CPSW_CPSWNU_MAX_PORTS 9
#define AM65_CPSW_SS_BASE 0x0
#define AM65_CPSW_SGMII_BASE 0x100
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 08/12] net: ti: am65-cpsw-nuss: Prepare to support non primary ext port
2021-05-10 14:36 ` [PATCH 08/12] net: ti: am65-cpsw-nuss: Prepare to support non primary ext port Vignesh Raghavendra
@ 2021-05-15 19:50 ` Ramon Fried
0 siblings, 0 replies; 17+ messages in thread
From: Ramon Fried @ 2021-05-15 19:50 UTC (permalink / raw)
To: u-boot
On Mon, May 10, 2021 at 5:36 PM Vignesh Raghavendra <vigneshr@ti.com> wrote:
>
> CPSW NUSS IP on K3 SoCs can have more than one external port (upto 8)
> Therefore increase AM65_CPSW_CPSWNU_MAX_PORTS to 9 (8 ext + 1 Root port)
> as preparation to allow any one of the 8 ports to be used as ethernet
> interface in U-Boot.
>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> ---
> drivers/net/ti/am65-cpsw-nuss.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
> index e6954b64b7..9f11ce63b9 100644
> --- a/drivers/net/ti/am65-cpsw-nuss.c
> +++ b/drivers/net/ti/am65-cpsw-nuss.c
> @@ -26,7 +26,7 @@
>
> #include "cpsw_mdio.h"
>
> -#define AM65_CPSW_CPSWNU_MAX_PORTS 2
> +#define AM65_CPSW_CPSWNU_MAX_PORTS 9
>
> #define AM65_CPSW_SS_BASE 0x0
> #define AM65_CPSW_SGMII_BASE 0x100
> --
> 2.31.1
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 09/12] net: ti: am65-cpsw-nuss: Don't cache disabled port ID
2021-05-10 14:36 [PATCH 00/12] AM64x: DMA and ethernet support Vignesh Raghavendra
` (7 preceding siblings ...)
2021-05-10 14:36 ` [PATCH 08/12] net: ti: am65-cpsw-nuss: Prepare to support non primary ext port Vignesh Raghavendra
@ 2021-05-10 14:36 ` Vignesh Raghavendra
2021-05-15 19:50 ` Ramon Fried
2021-05-10 14:36 ` [PATCH 10/12] net: ti: am65-cpsw-nuss: Add a new compatible for AM64 Vignesh Raghavendra
` (3 subsequent siblings)
12 siblings, 1 reply; 17+ messages in thread
From: Vignesh Raghavendra @ 2021-05-10 14:36 UTC (permalink / raw)
To: u-boot
Currently driver may end up caching disabled port ID as active
interface. Fix this by bailing out earlier in case port is marked
disabled in the DT.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
drivers/net/ti/am65-cpsw-nuss.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index 9f11ce63b9..3534a6d807 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -719,11 +719,11 @@ static int am65_cpsw_probe_cpsw(struct udevice *dev)
if (!port_id)
continue;
- priv->port_id = port_id;
cpsw_common->ports[port_id].disabled = disabled;
if (disabled)
continue;
+ priv->port_id = port_id;
ret = am65_cpsw_ofdata_parse_phy(dev, node);
if (ret)
goto out;
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 09/12] net: ti: am65-cpsw-nuss: Don't cache disabled port ID
2021-05-10 14:36 ` [PATCH 09/12] net: ti: am65-cpsw-nuss: Don't cache disabled port ID Vignesh Raghavendra
@ 2021-05-15 19:50 ` Ramon Fried
0 siblings, 0 replies; 17+ messages in thread
From: Ramon Fried @ 2021-05-15 19:50 UTC (permalink / raw)
To: u-boot
On Mon, May 10, 2021 at 5:37 PM Vignesh Raghavendra <vigneshr@ti.com> wrote:
>
> Currently driver may end up caching disabled port ID as active
> interface. Fix this by bailing out earlier in case port is marked
> disabled in the DT.
>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> ---
> drivers/net/ti/am65-cpsw-nuss.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
> index 9f11ce63b9..3534a6d807 100644
> --- a/drivers/net/ti/am65-cpsw-nuss.c
> +++ b/drivers/net/ti/am65-cpsw-nuss.c
> @@ -719,11 +719,11 @@ static int am65_cpsw_probe_cpsw(struct udevice *dev)
> if (!port_id)
> continue;
>
> - priv->port_id = port_id;
> cpsw_common->ports[port_id].disabled = disabled;
> if (disabled)
> continue;
>
> + priv->port_id = port_id;
> ret = am65_cpsw_ofdata_parse_phy(dev, node);
> if (ret)
> goto out;
> --
> 2.31.1
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 10/12] net: ti: am65-cpsw-nuss: Add a new compatible for AM64
2021-05-10 14:36 [PATCH 00/12] AM64x: DMA and ethernet support Vignesh Raghavendra
` (8 preceding siblings ...)
2021-05-10 14:36 ` [PATCH 09/12] net: ti: am65-cpsw-nuss: Don't cache disabled port ID Vignesh Raghavendra
@ 2021-05-10 14:36 ` Vignesh Raghavendra
2021-05-15 19:50 ` Ramon Fried
2021-05-10 14:36 ` [PATCH 11/12] ARM: dts: k3-am64-main: Add CPSW DT nodes Vignesh Raghavendra
` (2 subsequent siblings)
12 siblings, 1 reply; 17+ messages in thread
From: Vignesh Raghavendra @ 2021-05-10 14:36 UTC (permalink / raw)
To: u-boot
Add a new compatible to support AM64 SoC
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
drivers/net/ti/am65-cpsw-nuss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index 3534a6d807..3ab6a30828 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -782,6 +782,7 @@ out:
static const struct udevice_id am65_cpsw_nuss_ids[] = {
{ .compatible = "ti,am654-cpsw-nuss" },
{ .compatible = "ti,j721e-cpsw-nuss" },
+ { .compatible = "ti,am642-cpsw-nuss" },
{ }
};
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 10/12] net: ti: am65-cpsw-nuss: Add a new compatible for AM64
2021-05-10 14:36 ` [PATCH 10/12] net: ti: am65-cpsw-nuss: Add a new compatible for AM64 Vignesh Raghavendra
@ 2021-05-15 19:50 ` Ramon Fried
0 siblings, 0 replies; 17+ messages in thread
From: Ramon Fried @ 2021-05-15 19:50 UTC (permalink / raw)
To: u-boot
On Mon, May 10, 2021 at 5:37 PM Vignesh Raghavendra <vigneshr@ti.com> wrote:
>
> Add a new compatible to support AM64 SoC
>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> ---
> drivers/net/ti/am65-cpsw-nuss.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
> index 3534a6d807..3ab6a30828 100644
> --- a/drivers/net/ti/am65-cpsw-nuss.c
> +++ b/drivers/net/ti/am65-cpsw-nuss.c
> @@ -782,6 +782,7 @@ out:
> static const struct udevice_id am65_cpsw_nuss_ids[] = {
> { .compatible = "ti,am654-cpsw-nuss" },
> { .compatible = "ti,j721e-cpsw-nuss" },
> + { .compatible = "ti,am642-cpsw-nuss" },
> { }
> };
>
> --
> 2.31.1
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 11/12] ARM: dts: k3-am64-main: Add CPSW DT nodes
2021-05-10 14:36 [PATCH 00/12] AM64x: DMA and ethernet support Vignesh Raghavendra
` (9 preceding siblings ...)
2021-05-10 14:36 ` [PATCH 10/12] net: ti: am65-cpsw-nuss: Add a new compatible for AM64 Vignesh Raghavendra
@ 2021-05-10 14:36 ` Vignesh Raghavendra
2021-05-10 14:36 ` [PATCH 12/12] ARM: dts: k3-am642-sk: Add ethernet related " Vignesh Raghavendra
2021-05-12 14:00 ` [PATCH 00/12] AM64x: DMA and ethernet support Lokesh Vutla
12 siblings, 0 replies; 17+ messages in thread
From: Vignesh Raghavendra @ 2021-05-10 14:36 UTC (permalink / raw)
To: u-boot
AM64 as CPSW3G IP with 2 external ports. Add DT entries for the same
(based on kernel DT).
Disable second port as its by default set to ICSS usage on EVM.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
arch/arm/dts/k3-am64-main.dtsi | 74 +++++++++++++++++++++
arch/arm/dts/k3-am64.dtsi | 2 +
arch/arm/dts/k3-am642-evm-u-boot.dtsi | 16 +++++
arch/arm/dts/k3-am642-evm.dts | 93 +++++++++++++++++++++++++++
4 files changed, 185 insertions(+)
diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi
index 4b6cd6cc90..a65011b396 100644
--- a/arch/arm/dts/k3-am64-main.dtsi
+++ b/arch/arm/dts/k3-am64-main.dtsi
@@ -178,6 +178,12 @@
compatible = "ti,am654-chipid";
reg = <0x00000014 0x4>;
};
+
+ phy_gmii_sel: phy at 4044 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x4044 0x8>;
+ #phy-cells = <1>;
+ };
};
main_uart0: serial at 2800000 {
@@ -403,6 +409,74 @@
ti,clkbuf-sel = <0x7>;
};
+ cpsw3g: ethernet at 8000000 {
+ compatible = "ti,am642-cpsw-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x8000000 0x0 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
+ clocks = <&k3_clks 13 0>;
+ assigned-clocks = <&k3_clks 13 1>;
+ assigned-clock-parents = <&k3_clks 13 9>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&main_pktdma 0xC500 15>,
+ <&main_pktdma 0xC501 15>,
+ <&main_pktdma 0xC502 15>,
+ <&main_pktdma 0xC503 15>,
+ <&main_pktdma 0xC504 15>,
+ <&main_pktdma 0xC505 15>,
+ <&main_pktdma 0xC506 15>,
+ <&main_pktdma 0xC507 15>,
+ <&main_pktdma 0x4500 15>;
+ dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
+ "tx7", "rx";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw_port1: port at 1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ phys = <&phy_gmii_sel 1>;
+ mac-address = [00 00 de ad be ef];
+ };
+
+ cpsw_port2: port at 2 {
+ reg = <2>;
+ ti,mac-only;
+ label = "port2";
+ phys = <&phy_gmii_sel 2>;
+ mac-address = [00 01 de ad be ef];
+ };
+ };
+
+ cpsw3g_mdio: mdio at f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x0 0xf00 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 13 0>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ };
+
+ cpts at 3d000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x0 0x3d000 0x0 0x400>;
+ clocks = <&k3_clks 13 1>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
main_gpio0: gpio at 600000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00600000 0x00 0x100>;
diff --git a/arch/arm/dts/k3-am64.dtsi b/arch/arm/dts/k3-am64.dtsi
index fde63463ca..6b2d0803b4 100644
--- a/arch/arm/dts/k3-am64.dtsi
+++ b/arch/arm/dts/k3-am64.dtsi
@@ -30,6 +30,8 @@
serial8 = &main_uart6;
i2c0 = &main_i2c0;
i2c1 = &main_i2c1;
+ ethernet0 = &cpsw_port1;
+ ethernet1 = &cpsw_port2;
};
chosen { };
diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
index 3bab736a18..5e0e41567f 100644
--- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
@@ -81,3 +81,19 @@
&sdhci1 {
u-boot,dm-spl;
};
+
+&cpsw3g {
+ reg = <0x0 0x8000000 0x0 0x200000>,
+ <0x0 0x43000200 0x0 0x8>;
+ reg-names = "cpsw_nuss", "mac_efuse";
+ /delete-property/ ranges;
+
+ cpsw-phy-sel at 04044 {
+ compatible = "ti,am64-phy-gmii-sel";
+ reg = <0x0 0x43004044 0x0 0x8>;
+ };
+};
+
+&cpsw_port2 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/k3-am642-evm.dts b/arch/arm/dts/k3-am642-evm.dts
index 1f1787750f..dc3482bea4 100644
--- a/arch/arm/dts/k3-am642-evm.dts
+++ b/arch/arm/dts/k3-am642-evm.dts
@@ -6,6 +6,8 @@
/dts-v1/;
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
/ {
@@ -101,6 +103,31 @@
default-state = "off";
};
};
+
+ mdio_mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ mdio-mux-1 {
+ compatible = "mdio-mux-multiplexer";
+ mux-controls = <&mdio_mux>;
+ mdio-parent-bus = <&cpsw3g_mdio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio at 1 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw3g_phy3: ethernet-phy at 3 {
+ reg = <3>;
+ };
+ };
+ };
};
&main_pmx0 {
@@ -133,6 +160,47 @@
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
>;
};
+
+ mdio1_pins_default: mdio1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
+ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
+ >;
+ };
+
+ rgmii1_pins_default: rgmii1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
+ AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
+ AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
+ AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
+ AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
+ AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
+ AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
+ AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
+ AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
+ AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
+ AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
+ AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
+ >;
+ };
+
+ rgmii2_pins_default: rgmii2-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
+ AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
+ AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
+ AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
+ AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
+ AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
+ AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
+ AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
+ AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
+ AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
+ AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
+ AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
+ >;
+ };
};
&main_uart0 {
@@ -227,6 +295,31 @@
status = "disabled";
};
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio1_pins_default
+ &rgmii1_pins_default
+ &rgmii2_pins_default>;
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw_port2 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy3>;
+};
+
+&cpsw3g_mdio {
+ cpsw3g_phy0: ethernet-phy at 0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
&sdhci0 {
/* emmc */
bus-width = <8>;
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 12/12] ARM: dts: k3-am642-sk: Add ethernet related DT nodes
2021-05-10 14:36 [PATCH 00/12] AM64x: DMA and ethernet support Vignesh Raghavendra
` (10 preceding siblings ...)
2021-05-10 14:36 ` [PATCH 11/12] ARM: dts: k3-am64-main: Add CPSW DT nodes Vignesh Raghavendra
@ 2021-05-10 14:36 ` Vignesh Raghavendra
2021-05-12 14:00 ` [PATCH 00/12] AM64x: DMA and ethernet support Lokesh Vutla
12 siblings, 0 replies; 17+ messages in thread
From: Vignesh Raghavendra @ 2021-05-10 14:36 UTC (permalink / raw)
To: u-boot
Add CPSW related nodes for AM642 SK. There are two CPSW ports on the
board but U-Boot supports only the first port.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
arch/arm/dts/k3-am642-sk-u-boot.dtsi | 16 +++++++
arch/arm/dts/k3-am642-sk.dts | 62 ++++++++++++++++++++++++++++
2 files changed, 78 insertions(+)
diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
index 8a987f1421..700a55b420 100644
--- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
@@ -85,3 +85,19 @@
&main_mmc1_pins_default {
u-boot,dm-spl;
};
+
+&cpsw3g {
+ reg = <0x0 0x8000000 0x0 0x200000>,
+ <0x0 0x43000200 0x0 0x8>;
+ reg-names = "cpsw_nuss", "mac_efuse";
+ /delete-property/ ranges;
+
+ cpsw-phy-sel at 04044 {
+ compatible = "ti,am64-phy-gmii-sel";
+ reg = <0x0 0x43004044 0x0 0x8>;
+ };
+};
+
+&cpsw_port2 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/k3-am642-sk.dts b/arch/arm/dts/k3-am642-sk.dts
index d557c49d16..df76c6e0b9 100644
--- a/arch/arm/dts/k3-am642-sk.dts
+++ b/arch/arm/dts/k3-am642-sk.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
/ {
@@ -57,6 +58,47 @@
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
>;
};
+
+ mdio1_pins_default: mdio1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
+ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
+ >;
+ };
+
+ rgmii1_pins_default: rgmii1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
+ AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
+ AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
+ AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
+ AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
+ AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
+ AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
+ AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
+ AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
+ AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
+ AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
+ AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
+ >;
+ };
+
+ rgmii2_pins_default: rgmii2-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
+ AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
+ AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
+ AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
+ AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
+ AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
+ AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
+ AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
+ AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
+ AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
+ AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
+ AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
+ >;
+ };
};
&main_uart1 {
@@ -92,3 +134,23 @@
ti,driver-strength-ohm = <50>;
disable-wp;
};
+
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio1_pins_default
+ &rgmii1_pins_default
+ &rgmii2_pins_default>;
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw3g_mdio {
+ cpsw3g_phy0: ethernet-phy at 0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 00/12] AM64x: DMA and ethernet support
2021-05-10 14:36 [PATCH 00/12] AM64x: DMA and ethernet support Vignesh Raghavendra
` (11 preceding siblings ...)
2021-05-10 14:36 ` [PATCH 12/12] ARM: dts: k3-am642-sk: Add ethernet related " Vignesh Raghavendra
@ 2021-05-12 14:00 ` Lokesh Vutla
12 siblings, 0 replies; 17+ messages in thread
From: Lokesh Vutla @ 2021-05-12 14:00 UTC (permalink / raw)
To: u-boot
On 10/05/21 8:06 pm, Vignesh Raghavendra wrote:
> This series add ethernet and DMA support for AM64x SoC.
Applied to u-boot-ti/for-rc
Thanks and regards,
Lokesh
^ permalink raw reply [flat|nested] 17+ messages in thread