From: Mark Rutland <mark.rutland@arm.com> To: Peter Collingbourne <pcc@google.com> Cc: Catalin Marinas <catalin.marinas@arm.com>, Vincenzo Frascino <vincenzo.frascino@arm.com>, Will Deacon <will@kernel.org>, Evgenii Stepanov <eugenis@google.com>, Andrey Konovalov <andreyknvl@gmail.com>, linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org Subject: Re: [PATCH v2] arm64: mte: initialize RGSR_EL1.SEED in __cpu_setup Date: Mon, 10 May 2021 16:31:44 +0100 [thread overview] Message-ID: <20210510153144.GC92897@C02TD0UTHF1T.local> (raw) In-Reply-To: <20210507185905.1745402-1-pcc@google.com> On Fri, May 07, 2021 at 11:59:05AM -0700, Peter Collingbourne wrote: > A valid implementation choice for the ChooseRandomNonExcludedTag() > pseudocode function used by IRG is to behave in the same way as with > GCR_EL1.RRND=0. This would mean that RGSR_EL1.SEED is used as an LFSR > which must have a non-zero value in order for IRG to properly produce > pseudorandom numbers. However, RGSR_EL1 is reset to an UNKNOWN value > on soft reset and thus may reset to 0. Therefore we must initialize > RGSR_EL1.SEED to a non-zero value in order to ensure that IRG behaves > as expected. > > Signed-off-by: Peter Collingbourne <pcc@google.com> > Fixes: 3b714d24ef17 ("arm64: mte: CPU feature detection and initial sysreg configuration") > Cc: <stable@vger.kernel.org> # 5.10 > Link: https://linux-review.googlesource.com/id/I2b089b6c7d6f17ee37e2f0db7df5ad5bcc04526c FWIW: Acked-by: Mark Rutland <mark.rutland@arm.com> Mark. > --- > arch/arm64/mm/proc.S | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > index 0a48191534ff..97d7bcd8d4f2 100644 > --- a/arch/arm64/mm/proc.S > +++ b/arch/arm64/mm/proc.S > @@ -447,6 +447,18 @@ SYM_FUNC_START(__cpu_setup) > mov x10, #(SYS_GCR_EL1_RRND | SYS_GCR_EL1_EXCL_MASK) > msr_s SYS_GCR_EL1, x10 > > + /* > + * If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then > + * RGSR_EL1.SEED must be non-zero for IRG to produce > + * pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we > + * must initialize it. > + */ > + mrs x10, CNTVCT_EL0 > + ands x10, x10, #SYS_RGSR_EL1_SEED_MASK > + csinc x10, x10, xzr, ne > + lsl x10, x10, #SYS_RGSR_EL1_SEED_SHIFT > + msr_s SYS_RGSR_EL1, x10 > + > /* clear any pending tag check faults in TFSR*_EL1 */ > msr_s SYS_TFSR_EL1, xzr > msr_s SYS_TFSRE0_EL1, xzr > -- > 2.31.1.607.g51e8a6a459-goog >
WARNING: multiple messages have this Message-ID (diff)
From: Mark Rutland <mark.rutland@arm.com> To: Peter Collingbourne <pcc@google.com> Cc: Catalin Marinas <catalin.marinas@arm.com>, Vincenzo Frascino <vincenzo.frascino@arm.com>, Will Deacon <will@kernel.org>, Evgenii Stepanov <eugenis@google.com>, Andrey Konovalov <andreyknvl@gmail.com>, linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org Subject: Re: [PATCH v2] arm64: mte: initialize RGSR_EL1.SEED in __cpu_setup Date: Mon, 10 May 2021 16:31:44 +0100 [thread overview] Message-ID: <20210510153144.GC92897@C02TD0UTHF1T.local> (raw) In-Reply-To: <20210507185905.1745402-1-pcc@google.com> On Fri, May 07, 2021 at 11:59:05AM -0700, Peter Collingbourne wrote: > A valid implementation choice for the ChooseRandomNonExcludedTag() > pseudocode function used by IRG is to behave in the same way as with > GCR_EL1.RRND=0. This would mean that RGSR_EL1.SEED is used as an LFSR > which must have a non-zero value in order for IRG to properly produce > pseudorandom numbers. However, RGSR_EL1 is reset to an UNKNOWN value > on soft reset and thus may reset to 0. Therefore we must initialize > RGSR_EL1.SEED to a non-zero value in order to ensure that IRG behaves > as expected. > > Signed-off-by: Peter Collingbourne <pcc@google.com> > Fixes: 3b714d24ef17 ("arm64: mte: CPU feature detection and initial sysreg configuration") > Cc: <stable@vger.kernel.org> # 5.10 > Link: https://linux-review.googlesource.com/id/I2b089b6c7d6f17ee37e2f0db7df5ad5bcc04526c FWIW: Acked-by: Mark Rutland <mark.rutland@arm.com> Mark. > --- > arch/arm64/mm/proc.S | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > index 0a48191534ff..97d7bcd8d4f2 100644 > --- a/arch/arm64/mm/proc.S > +++ b/arch/arm64/mm/proc.S > @@ -447,6 +447,18 @@ SYM_FUNC_START(__cpu_setup) > mov x10, #(SYS_GCR_EL1_RRND | SYS_GCR_EL1_EXCL_MASK) > msr_s SYS_GCR_EL1, x10 > > + /* > + * If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then > + * RGSR_EL1.SEED must be non-zero for IRG to produce > + * pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we > + * must initialize it. > + */ > + mrs x10, CNTVCT_EL0 > + ands x10, x10, #SYS_RGSR_EL1_SEED_MASK > + csinc x10, x10, xzr, ne > + lsl x10, x10, #SYS_RGSR_EL1_SEED_SHIFT > + msr_s SYS_RGSR_EL1, x10 > + > /* clear any pending tag check faults in TFSR*_EL1 */ > msr_s SYS_TFSR_EL1, xzr > msr_s SYS_TFSRE0_EL1, xzr > -- > 2.31.1.607.g51e8a6a459-goog > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-05-10 15:31 UTC|newest] Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-07 18:59 [PATCH v2] arm64: mte: initialize RGSR_EL1.SEED in __cpu_setup Peter Collingbourne 2021-05-07 18:59 ` Peter Collingbourne 2021-05-10 15:31 ` Mark Rutland [this message] 2021-05-10 15:31 ` Mark Rutland 2021-05-10 18:00 ` Catalin Marinas 2021-05-10 18:00 ` Catalin Marinas
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