From: Mathieu Poirier <mathieu.poirier@linaro.org> To: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Cc: Linux Doc Mailing List <linux-doc@vger.kernel.org>, Jonathan Corbet <corbet@lwn.net>, Leo Yan <leo.yan@linaro.org>, Mike Leach <mike.leach@linaro.org>, Suzuki K Poulose <suzuki.poulose@arm.com>, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 11/53] docs: trace: coresight: coresight-etm4x-reference.rst: avoid using UTF-8 chars Date: Mon, 10 May 2021 13:28:30 -0600 [thread overview] Message-ID: <20210510192830.GA7232@xps15> (raw) In-Reply-To: <859218d35d495d5d2c2893bf8e6e087394a107a7.1620641727.git.mchehab+huawei@kernel.org> On Mon, May 10, 2021 at 12:26:23PM +0200, Mauro Carvalho Chehab wrote: > While UTF-8 characters can be used at the Linux documentation, > the best is to use them only when ASCII doesn't offer a good replacement. > So, replace the occurences of the following UTF-8 characters: > > - U+00a0 (' '): NO-BREAK SPACE > - U+2018 ('‘'): LEFT SINGLE QUOTATION MARK > - U+2019 ('’'): RIGHT SINGLE QUOTATION MARK > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> > --- > .../coresight/coresight-etm4x-reference.rst | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.rst b/Documentation/trace/coresight/coresight-etm4x-reference.rst > index b64d9a9c79df..e8ddfc144d9a 100644 > --- a/Documentation/trace/coresight/coresight-etm4x-reference.rst > +++ b/Documentation/trace/coresight/coresight-etm4x-reference.rst > @@ -15,14 +15,14 @@ Root: ``/sys/bus/coresight/devices/etm<N>`` > > The following paragraphs explain the association between sysfs files and the > ETMv4 registers that they effect. Note the register names are given without > -the ‘TRC’ prefix. > +the 'TRC' prefix. > > ---- > > :File: ``mode`` (rw) > :Trace Registers: {CONFIGR + others} > :Notes: > - Bit select trace features. See ‘mode’ section below. Bits > + Bit select trace features. See 'mode' section below. Bits > in this will cause equivalent programming of trace config and > other registers to enable the features requested. > > @@ -89,7 +89,7 @@ the ‘TRC’ prefix. > :Notes: > Pair of addresses for a range selected by addr_idx. Include > / exclude according to the optional parameter, or if omitted > - uses the current ‘mode’ setting. Select comparator range in > + uses the current 'mode' setting. Select comparator range in > control register. Error if index is odd value. > > :Depends: ``mode, addr_idx`` > @@ -277,7 +277,7 @@ the ‘TRC’ prefix. > :Trace Registers: VICTLR{23:20} > :Notes: > Program non-secure exception level filters. Set / clear NS > - exception filter bits. Setting ‘1’ excludes trace from the > + exception filter bits. Setting '1' excludes trace from the > exception level. > > :Syntax: > @@ -427,7 +427,7 @@ the ‘TRC’ prefix. > :Syntax: > ``echo idx > vmid_idx`` > > - Where idx < numvmidc > + Where idx < numvmidc > > ---- > > @@ -628,7 +628,7 @@ the reset parameter:: > > > > -The ‘mode’ sysfs parameter. > +The 'mode' sysfs parameter. > --------------------------- > > This is a bitfield selection parameter that sets the overall trace mode for the > @@ -696,7 +696,7 @@ Bit assignments shown below:- > ETM_MODE_QELEM(val) > > **description:** > - ‘val’ determines level of Q element support enabled if > + 'val' determines level of Q element support enabled if > implemented by the ETM [IDR0] > > > @@ -780,7 +780,7 @@ Bit assignments shown below:- > ---- > > *Note a)* On startup the ETM is programmed to trace the complete address space > -using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to > +using address range comparator 0. 'mode' bits 30 / 31 modify this setting to > set EL exclude bits for NS state in either user space (EL0) or kernel space > (EL1) in the address range comparator. (the default setting excludes all > secure EL, and NS EL2) > -- > 2.30.2 >
WARNING: multiple messages have this Message-ID (diff)
From: Mathieu Poirier <mathieu.poirier@linaro.org> To: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Cc: Linux Doc Mailing List <linux-doc@vger.kernel.org>, Jonathan Corbet <corbet@lwn.net>, Leo Yan <leo.yan@linaro.org>, Mike Leach <mike.leach@linaro.org>, Suzuki K Poulose <suzuki.poulose@arm.com>, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 11/53] docs: trace: coresight: coresight-etm4x-reference.rst: avoid using UTF-8 chars Date: Mon, 10 May 2021 13:28:30 -0600 [thread overview] Message-ID: <20210510192830.GA7232@xps15> (raw) In-Reply-To: <859218d35d495d5d2c2893bf8e6e087394a107a7.1620641727.git.mchehab+huawei@kernel.org> On Mon, May 10, 2021 at 12:26:23PM +0200, Mauro Carvalho Chehab wrote: > While UTF-8 characters can be used at the Linux documentation, > the best is to use them only when ASCII doesn't offer a good replacement. > So, replace the occurences of the following UTF-8 characters: > > - U+00a0 (' '): NO-BREAK SPACE > - U+2018 ('‘'): LEFT SINGLE QUOTATION MARK > - U+2019 ('’'): RIGHT SINGLE QUOTATION MARK > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> > --- > .../coresight/coresight-etm4x-reference.rst | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.rst b/Documentation/trace/coresight/coresight-etm4x-reference.rst > index b64d9a9c79df..e8ddfc144d9a 100644 > --- a/Documentation/trace/coresight/coresight-etm4x-reference.rst > +++ b/Documentation/trace/coresight/coresight-etm4x-reference.rst > @@ -15,14 +15,14 @@ Root: ``/sys/bus/coresight/devices/etm<N>`` > > The following paragraphs explain the association between sysfs files and the > ETMv4 registers that they effect. Note the register names are given without > -the ‘TRC’ prefix. > +the 'TRC' prefix. > > ---- > > :File: ``mode`` (rw) > :Trace Registers: {CONFIGR + others} > :Notes: > - Bit select trace features. See ‘mode’ section below. Bits > + Bit select trace features. See 'mode' section below. Bits > in this will cause equivalent programming of trace config and > other registers to enable the features requested. > > @@ -89,7 +89,7 @@ the ‘TRC’ prefix. > :Notes: > Pair of addresses for a range selected by addr_idx. Include > / exclude according to the optional parameter, or if omitted > - uses the current ‘mode’ setting. Select comparator range in > + uses the current 'mode' setting. Select comparator range in > control register. Error if index is odd value. > > :Depends: ``mode, addr_idx`` > @@ -277,7 +277,7 @@ the ‘TRC’ prefix. > :Trace Registers: VICTLR{23:20} > :Notes: > Program non-secure exception level filters. Set / clear NS > - exception filter bits. Setting ‘1’ excludes trace from the > + exception filter bits. Setting '1' excludes trace from the > exception level. > > :Syntax: > @@ -427,7 +427,7 @@ the ‘TRC’ prefix. > :Syntax: > ``echo idx > vmid_idx`` > > - Where idx < numvmidc > + Where idx < numvmidc > > ---- > > @@ -628,7 +628,7 @@ the reset parameter:: > > > > -The ‘mode’ sysfs parameter. > +The 'mode' sysfs parameter. > --------------------------- > > This is a bitfield selection parameter that sets the overall trace mode for the > @@ -696,7 +696,7 @@ Bit assignments shown below:- > ETM_MODE_QELEM(val) > > **description:** > - ‘val’ determines level of Q element support enabled if > + 'val' determines level of Q element support enabled if > implemented by the ETM [IDR0] > > > @@ -780,7 +780,7 @@ Bit assignments shown below:- > ---- > > *Note a)* On startup the ETM is programmed to trace the complete address space > -using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to > +using address range comparator 0. 'mode' bits 30 / 31 modify this setting to > set EL exclude bits for NS state in either user space (EL0) or kernel space > (EL1) in the address range comparator. (the default setting excludes all > secure EL, and NS EL2) > -- > 2.30.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-05-10 19:28 UTC|newest] Thread overview: 219+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-10 10:26 [PATCH 00/53] Get rid of UTF-8 chars that can be mapped as ASCII Mauro Carvalho Chehab 2021-05-10 10:26 ` [Intel-wired-lan] " Mauro Carvalho Chehab 2021-05-10 10:26 ` [Intel-gfx] " Mauro Carvalho Chehab 2021-05-10 10:26 ` Mauro Carvalho Chehab 2021-05-10 10:26 ` Mauro Carvalho Chehab 2021-05-10 10:26 ` [f2fs-dev] " Mauro Carvalho Chehab 2021-05-10 10:26 ` Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 01/53] docs: cdrom-standard.rst: get rid of uneeded UTF-8 chars Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 02/53] docs: ABI: remove a meaningless UTF-8 character Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 03/53] docs: ABI: remove some spurious characters Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 04/53] docs: index.rst: avoid using UTF-8 chars Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 05/53] docs: hwmon: " Mauro Carvalho Chehab 2021-05-10 13:30 ` Guenter Roeck 2021-05-10 10:26 ` [PATCH 06/53] docs: admin-guide: " Mauro Carvalho Chehab 2021-05-10 18:40 ` Gabriel Krisman Bertazi 2021-05-12 8:44 ` Mauro Carvalho Chehab 2021-05-12 9:25 ` David Woodhouse 2021-05-12 10:22 ` Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 07/53] docs: admin-guide: media: ipu3.rst: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 08/53] docs: admin-guide: sysctl: kernel.rst: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 09/53] docs: admin-guide: perf: imx-ddr.rst: " Mauro Carvalho Chehab 2021-05-10 10:26 ` Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 10/53] docs: admin-guide: pm: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 11/53] docs: trace: coresight: coresight-etm4x-reference.rst: " Mauro Carvalho Chehab 2021-05-10 10:26 ` Mauro Carvalho Chehab 2021-05-10 19:28 ` Mathieu Poirier [this message] 2021-05-10 19:28 ` Mathieu Poirier 2021-05-10 10:26 ` [PATCH 12/53] docs: driver-api: " Mauro Carvalho Chehab [not found] ` <CAHp75Vegsb-+fVppv3C7Jp0a=mEGAh2pchX=Cr5ZvOMFt+G73Q@mail.gmail.com> 2021-05-12 8:49 ` Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 13/53] docs: driver-api: fpga: " Mauro Carvalho Chehab 2021-05-10 17:48 ` Moritz Fischer 2021-05-10 10:26 ` [PATCH 14/53] docs: driver-api: iio: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 15/53] docs: driver-api: thermal: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 16/53] docs: driver-api: media: drivers: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 17/53] docs: driver-api: firmware: other_interfaces.rst: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 18/53] docs: driver-api: nvdimm: btt.rst: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 19/53] docs: fault-injection: nvme-fault-injection.rst: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 20/53] docs: usb: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 21/53] docs: process: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 22/53] docs: block: data-integrity.rst: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 23/53] docs: userspace-api: media: fdl-appendix.rst: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 24/53] docs: userspace-api: media: v4l: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 25/53] docs: userspace-api: media: dvb: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 26/53] docs: vm: zswap.rst: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 27/53] docs: filesystems: f2fs.rst: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [f2fs-dev] " Mauro Carvalho Chehab 2021-05-11 3:16 ` Chao Yu 2021-05-11 3:16 ` Chao Yu 2021-05-10 10:26 ` [PATCH 28/53] docs: filesystems: ext4: " Mauro Carvalho Chehab 2021-05-10 19:23 ` Theodore Ts'o 2021-05-10 10:26 ` [PATCH 29/53] docs: kernel-hacking: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 30/53] docs: hid: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 31/53] docs: security: tpm: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 32/53] docs: security: keys: trusted-encrypted.rst: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 33/53] docs: riscv: vm-layout.rst: " Mauro Carvalho Chehab 2021-05-10 10:26 ` Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 34/53] docs: networking: scaling.rst: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 35/53] docs: networking: devlink: devlink-dpipe.rst: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 36/53] docs: networking: device_drivers: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [Intel-wired-lan] " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 37/53] docs: x86: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 38/53] docs: scheduler: sched-deadline.rst: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 39/53] docs: dev-tools: testing-overview.rst: " Mauro Carvalho Chehab 2021-05-10 10:48 ` Marco Elver 2021-05-12 8:52 ` Mauro Carvalho Chehab 2021-05-10 23:35 ` David Gow 2021-05-12 8:14 ` Mauro Carvalho Chehab 2021-05-12 8:29 ` Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 40/53] docs: power: powercap: powercap.rst: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 41/53] docs: ABI: " Mauro Carvalho Chehab 2021-05-10 13:53 ` Guenter Roeck 2021-05-10 10:26 ` [PATCH 42/53] docs: doc-guide: contributing.rst: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 43/53] docs: PCI: acpi-info.rst: " Mauro Carvalho Chehab 2021-05-10 10:37 ` Krzysztof Wilczyński 2021-05-10 10:26 ` [PATCH 44/53] docs: gpu: " Mauro Carvalho Chehab 2021-05-10 10:26 ` [Intel-gfx] " Mauro Carvalho Chehab 2021-05-10 10:26 ` Mauro Carvalho Chehab 2021-05-10 11:16 ` Jani Nikula 2021-05-10 11:16 ` [Intel-gfx] " Jani Nikula 2021-05-10 11:16 ` Jani Nikula 2021-05-10 12:36 ` Liviu Dudau 2021-05-10 12:36 ` [Intel-gfx] " Liviu Dudau 2021-05-10 12:36 ` Liviu Dudau 2021-05-10 10:26 ` [PATCH 45/53] docs: sound: kernel-api: writing-an-alsa-driver.rst: " Mauro Carvalho Chehab 2021-05-10 10:26 ` Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 46/53] docs: arm64: arm-acpi.rst: " Mauro Carvalho Chehab 2021-05-10 10:26 ` Mauro Carvalho Chehab 2021-05-10 10:26 ` [PATCH 47/53] docs: infiniband: tag_matching.rst: " Mauro Carvalho Chehab 2021-05-10 10:27 ` [PATCH 48/53] docs: timers: no_hz.rst: " Mauro Carvalho Chehab 2021-05-10 10:27 ` [PATCH 49/53] docs: misc-devices: ibmvmc.rst: " Mauro Carvalho Chehab 2021-05-10 10:27 ` [PATCH 50/53] docs: firmware-guide: acpi: lpit.rst: " Mauro Carvalho Chehab 2021-05-10 10:27 ` [PATCH 51/53] docs: firmware-guide: acpi: dsd: graph.rst: " Mauro Carvalho Chehab 2021-05-10 10:27 ` [PATCH 52/53] docs: virt: kvm: " Mauro Carvalho Chehab 2021-05-10 10:27 ` [PATCH 53/53] docs: RCU: " Mauro Carvalho Chehab 2021-05-11 0:05 ` Paul E. McKenney 2021-05-10 10:52 ` [PATCH 00/53] Get rid of UTF-8 chars that can be mapped as ASCII Thorsten Leemhuis 2021-05-10 10:52 ` [Intel-wired-lan] " Thorsten Leemhuis 2021-05-10 10:52 ` [Intel-gfx] " Thorsten Leemhuis 2021-05-10 10:52 ` Thorsten Leemhuis 2021-05-10 10:52 ` Thorsten Leemhuis 2021-05-10 10:52 ` [f2fs-dev] " Thorsten Leemhuis 2021-05-10 10:52 ` Thorsten Leemhuis 2021-05-10 11:19 ` Mauro Carvalho Chehab 2021-05-10 11:19 ` [Intel-wired-lan] " Mauro Carvalho Chehab 2021-05-10 11:19 ` [Intel-gfx] " Mauro Carvalho Chehab 2021-05-10 11:19 ` Mauro Carvalho Chehab 2021-05-10 11:19 ` Mauro Carvalho Chehab 2021-05-10 11:19 ` [f2fs-dev] " Mauro Carvalho Chehab 2021-05-10 11:19 ` Mauro Carvalho Chehab 2021-05-10 12:27 ` Mauro Carvalho Chehab 2021-05-10 12:27 ` [Intel-wired-lan] " Mauro Carvalho Chehab 2021-05-10 12:27 ` [Intel-gfx] " Mauro Carvalho Chehab 2021-05-10 12:27 ` Mauro Carvalho Chehab 2021-05-10 12:27 ` Mauro Carvalho Chehab 2021-05-10 12:27 ` [f2fs-dev] " Mauro Carvalho Chehab 2021-05-10 12:27 ` Mauro Carvalho Chehab 2021-05-10 10:54 ` David Woodhouse 2021-05-10 10:54 ` [Intel-wired-lan] " David Woodhouse 2021-05-10 10:54 ` [Intel-gfx] " David Woodhouse 2021-05-10 10:54 ` David Woodhouse 2021-05-10 10:54 ` David Woodhouse 2021-05-10 10:54 ` David Woodhouse 2021-05-10 11:55 ` Mauro Carvalho Chehab 2021-05-10 11:55 ` [Intel-wired-lan] " Mauro Carvalho Chehab 2021-05-10 11:55 ` [Intel-gfx] " Mauro Carvalho Chehab 2021-05-10 11:55 ` Mauro Carvalho Chehab 2021-05-10 11:55 ` Mauro Carvalho Chehab 2021-05-10 11:55 ` [f2fs-dev] " Mauro Carvalho Chehab 2021-05-10 11:55 ` Mauro Carvalho Chehab 2021-05-10 12:29 ` [f2fs-dev] " beroal 2021-05-10 13:16 ` Edward Cree 2021-05-10 13:16 ` [Intel-wired-lan] " Edward Cree 2021-05-10 13:16 ` [Intel-gfx] " Edward Cree 2021-05-10 13:16 ` Edward Cree 2021-05-10 13:16 ` Edward Cree 2021-05-10 13:16 ` [f2fs-dev] " Edward Cree 2021-05-10 13:16 ` Edward Cree 2021-05-10 13:38 ` Mauro Carvalho Chehab 2021-05-10 13:38 ` [Intel-wired-lan] " Mauro Carvalho Chehab 2021-05-10 13:38 ` [Intel-gfx] " Mauro Carvalho Chehab 2021-05-10 13:38 ` Mauro Carvalho Chehab 2021-05-10 13:38 ` Mauro Carvalho Chehab 2021-05-10 13:38 ` [f2fs-dev] " Mauro Carvalho Chehab 2021-05-10 13:38 ` Mauro Carvalho Chehab 2021-05-10 13:58 ` Edward Cree 2021-05-10 13:58 ` [Intel-wired-lan] " Edward Cree 2021-05-10 13:58 ` [Intel-gfx] " Edward Cree 2021-05-10 13:58 ` Edward Cree 2021-05-10 13:58 ` Edward Cree 2021-05-10 13:58 ` [f2fs-dev] " Edward Cree 2021-05-10 13:58 ` Edward Cree 2021-05-10 13:59 ` Matthew Wilcox 2021-05-10 13:59 ` [Intel-wired-lan] " Matthew Wilcox 2021-05-10 13:59 ` [Intel-gfx] " Matthew Wilcox 2021-05-10 13:59 ` Matthew Wilcox 2021-05-10 13:59 ` Matthew Wilcox 2021-05-10 13:59 ` [f2fs-dev] " Matthew Wilcox 2021-05-10 13:59 ` Matthew Wilcox 2021-05-10 14:33 ` Edward Cree 2021-05-10 14:33 ` [Intel-wired-lan] " Edward Cree 2021-05-10 14:33 ` [Intel-gfx] " Edward Cree 2021-05-10 14:33 ` Edward Cree 2021-05-10 14:33 ` Edward Cree 2021-05-10 14:33 ` [f2fs-dev] " Edward Cree 2021-05-10 14:33 ` Edward Cree 2021-05-11 9:00 ` Mauro Carvalho Chehab 2021-05-11 9:00 ` [Intel-wired-lan] " Mauro Carvalho Chehab 2021-05-11 9:00 ` [Intel-gfx] " Mauro Carvalho Chehab 2021-05-11 9:00 ` Mauro Carvalho Chehab 2021-05-11 9:00 ` Mauro Carvalho Chehab 2021-05-11 9:00 ` [f2fs-dev] " Mauro Carvalho Chehab 2021-05-11 9:00 ` Mauro Carvalho Chehab 2021-05-11 9:19 ` David Woodhouse 2021-05-11 9:19 ` [Intel-wired-lan] " David Woodhouse 2021-05-11 9:19 ` [Intel-gfx] " David Woodhouse 2021-05-11 9:19 ` David Woodhouse 2021-05-11 9:19 ` David Woodhouse 2021-05-11 9:19 ` David Woodhouse 2021-05-10 13:49 ` David Woodhouse 2021-05-10 13:49 ` [Intel-wired-lan] " David Woodhouse 2021-05-10 13:49 ` [Intel-gfx] " David Woodhouse 2021-05-10 13:49 ` David Woodhouse 2021-05-10 13:49 ` David Woodhouse 2021-05-10 13:49 ` David Woodhouse 2021-05-10 19:22 ` Theodore Ts'o 2021-05-10 19:22 ` [Intel-wired-lan] " Theodore Ts'o 2021-05-10 19:22 ` [Intel-gfx] " Theodore Ts'o 2021-05-10 19:22 ` Theodore Ts'o 2021-05-10 19:22 ` Theodore Ts'o 2021-05-10 19:22 ` [f2fs-dev] " Theodore Ts'o 2021-05-10 19:22 ` Theodore Ts'o 2021-05-11 9:37 ` Mauro Carvalho Chehab 2021-05-11 9:37 ` [Intel-wired-lan] " Mauro Carvalho Chehab 2021-05-11 9:37 ` [Intel-gfx] " Mauro Carvalho Chehab 2021-05-11 9:37 ` Mauro Carvalho Chehab 2021-05-11 9:37 ` Mauro Carvalho Chehab 2021-05-11 9:37 ` [f2fs-dev] " Mauro Carvalho Chehab 2021-05-11 9:37 ` Mauro Carvalho Chehab 2021-05-11 9:25 ` Mauro Carvalho Chehab 2021-05-11 9:25 ` [Intel-wired-lan] " Mauro Carvalho Chehab 2021-05-11 9:25 ` [Intel-gfx] " Mauro Carvalho Chehab 2021-05-11 9:25 ` Mauro Carvalho Chehab 2021-05-11 9:25 ` Mauro Carvalho Chehab 2021-05-11 9:25 ` [f2fs-dev] " Mauro Carvalho Chehab 2021-05-11 9:25 ` Mauro Carvalho Chehab 2021-05-10 14:00 ` Ben Boeckel 2021-05-10 14:00 ` [Intel-wired-lan] " Ben Boeckel 2021-05-10 14:00 ` [Intel-gfx] " Ben Boeckel 2021-05-10 14:00 ` Ben Boeckel 2021-05-10 14:00 ` Ben Boeckel 2021-05-10 14:00 ` [f2fs-dev] " Ben Boeckel 2021-05-10 14:00 ` Ben Boeckel 2021-05-10 21:57 ` Adam Borowski 2021-05-10 21:57 ` [Intel-wired-lan] " Adam Borowski 2021-05-10 21:57 ` [Intel-gfx] " Adam Borowski 2021-05-10 21:57 ` Adam Borowski 2021-05-10 21:57 ` Adam Borowski 2021-05-10 21:57 ` [f2fs-dev] " Adam Borowski 2021-05-10 21:57 ` Adam Borowski
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