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* [Intel-gfx] [PATCH v2 1/4] drm/i915/display: Fix fastsets involving PSR
@ 2021-05-14 23:22 José Roberto de Souza
  2021-05-14 23:22 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/display: Allow fastsets when DP_SDP_VSC infoframe do not match with PSR enabled José Roberto de Souza
                   ` (10 more replies)
  0 siblings, 11 replies; 24+ messages in thread
From: José Roberto de Souza @ 2021-05-14 23:22 UTC (permalink / raw)
  To: intel-gfx

Commit 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware
configuration read out") is not allowing fastsets to happen when PSR
states changes but PSR is a feature that can be enabled and disabled
during fastsets.

So here moving the PSR pipe conf checks to a block that is only
executed when checking if HW state matches with requested state, not
during the phase where it checks if fastset is possible or not.

There still a state mismatch not allowing fastsets between states
turning off or on PSR because of crtc_state->infoframes.enable
BIT(DP_SDP_VSC) but at least for now it will allow a fastset between
PSR1 <-> PSR2, that is a case heavilly used by CI due to pipe CRC not
work with PSR2, but the remaning issue will be fixed in a future patch.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fixes: 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware configuration read out")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0c2b194006f8..51f499271cc8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8548,6 +8548,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
 		if (bp_gamma)
 			PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
+
+		PIPE_CONF_CHECK_BOOL(has_psr);
+		PIPE_CONF_CHECK_BOOL(has_psr2);
+		PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
+		PIPE_CONF_CHECK_I(dc3co_exitline);
 	}
 
 	PIPE_CONF_CHECK_BOOL(double_wide);
@@ -8631,11 +8636,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_I(vrr.flipline);
 	PIPE_CONF_CHECK_I(vrr.pipeline_full);
 
-	PIPE_CONF_CHECK_BOOL(has_psr);
-	PIPE_CONF_CHECK_BOOL(has_psr2);
-	PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
-	PIPE_CONF_CHECK_I(dc3co_exitline);
-
 #undef PIPE_CONF_CHECK_X
 #undef PIPE_CONF_CHECK_I
 #undef PIPE_CONF_CHECK_BOOL
-- 
2.31.1

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^ permalink raw reply related	[flat|nested] 24+ messages in thread

end of thread, other threads:[~2021-06-11 18:15 UTC | newest]

Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-14 23:22 [Intel-gfx] [PATCH v2 1/4] drm/i915/display: Fix fastsets involving PSR José Roberto de Souza
2021-05-14 23:22 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/display: Allow fastsets when DP_SDP_VSC infoframe do not match with PSR enabled José Roberto de Souza
2021-06-07 11:44   ` Gwan-gyeong Mun
2021-05-14 23:22 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/display: Nuke has_infoframe José Roberto de Souza
2021-05-21 15:27   ` Mun, Gwan-gyeong
2021-05-21 19:58     ` Souza, Jose
2021-06-07 12:49       ` Gwan-gyeong Mun
2021-06-07 23:16         ` Souza, Jose
2021-05-14 23:22 ` [Intel-gfx] [PATCH v2 4/4] drm/i915/display: Drop FIXME about turn off infoframes José Roberto de Souza
2021-06-01 22:41   ` Sripada, Radhakrishna
2021-06-08  7:26   ` Ville Syrjälä
2021-06-09 19:25     ` Souza, Jose
2021-06-10 12:18       ` Ville Syrjälä
2021-06-10 17:44         ` Souza, Jose
2021-06-11 18:15           ` Ville Syrjälä
2021-05-14 23:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/4] drm/i915/display: Fix fastsets involving PSR Patchwork
2021-05-14 23:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-15  0:11 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-05-15  0:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/4] drm/i915/display: Fix fastsets involving PSR (rev2) Patchwork
2021-05-15  0:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-15  1:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-15 13:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-06-07 17:51   ` Souza, Jose
2021-06-07 11:19 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/display: Fix fastsets involving PSR Gwan-gyeong Mun

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