From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: mturquette@baylibre.com, sboyd@kernel.org,
narmstrong@baylibre.com, jbrunet@baylibre.com,
linux-clk@vger.kernel.org
Cc: khilman@baylibre.com, linux-kernel@vger.kernel.org,
linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: [PATCH RFC v1 0/3] clk: meson: rounding for fast clocks on 32-bit SoCs
Date: Mon, 17 May 2021 22:37:21 +0200 [thread overview]
Message-ID: <20210517203724.1006254-1-martin.blumenstingl@googlemail.com> (raw)
On the 32-bit Amlogic Meson8/8b/8m2 SoCs we run into a problem with the
fast HDMI PLL and it's OD (post-dividers). This clock tree can run at
up to approx. 3GHz.
This however causes a problem, because these rates require BIT(31) to
be usable. Unfortunately this is not the case with clk_ops.round_rate
on 32-bit systems. BIT(31) is reserved for the sign (+ or -).
clk_ops.determine_rate does not suffer from this limitation. It uses
an int to signal any errors and can then take all availble 32 bits for
the clock rate.
I am sending this as RFC to start a discussion whether:
- this is a good way to solve it?
- what are the alternatives?
- getting some feedback on areas that need to be improved
As always: any feedback is welcome!
Thank you!
Martin
Martin Blumenstingl (3):
clk: divider: Add re-usable determine_rate implementations
clk: meson: regmap: switch to determine_rate for the dividers
clk: meson: pll: switch to determine_rate for the PLL ops
drivers/clk/clk-divider.c | 39 +++++++++++++++++++++++++++++++++-
drivers/clk/meson/clk-pll.c | 26 +++++++++++++----------
drivers/clk/meson/clk-regmap.c | 19 ++++++++---------
include/linux/clk-provider.h | 6 ++++++
4 files changed, 68 insertions(+), 22 deletions(-)
--
2.31.1
WARNING: multiple messages have this Message-ID (diff)
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: mturquette@baylibre.com, sboyd@kernel.org,
narmstrong@baylibre.com, jbrunet@baylibre.com,
linux-clk@vger.kernel.org
Cc: khilman@baylibre.com, linux-kernel@vger.kernel.org,
linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: [PATCH RFC v1 0/3] clk: meson: rounding for fast clocks on 32-bit SoCs
Date: Mon, 17 May 2021 22:37:21 +0200 [thread overview]
Message-ID: <20210517203724.1006254-1-martin.blumenstingl@googlemail.com> (raw)
On the 32-bit Amlogic Meson8/8b/8m2 SoCs we run into a problem with the
fast HDMI PLL and it's OD (post-dividers). This clock tree can run at
up to approx. 3GHz.
This however causes a problem, because these rates require BIT(31) to
be usable. Unfortunately this is not the case with clk_ops.round_rate
on 32-bit systems. BIT(31) is reserved for the sign (+ or -).
clk_ops.determine_rate does not suffer from this limitation. It uses
an int to signal any errors and can then take all availble 32 bits for
the clock rate.
I am sending this as RFC to start a discussion whether:
- this is a good way to solve it?
- what are the alternatives?
- getting some feedback on areas that need to be improved
As always: any feedback is welcome!
Thank you!
Martin
Martin Blumenstingl (3):
clk: divider: Add re-usable determine_rate implementations
clk: meson: regmap: switch to determine_rate for the dividers
clk: meson: pll: switch to determine_rate for the PLL ops
drivers/clk/clk-divider.c | 39 +++++++++++++++++++++++++++++++++-
drivers/clk/meson/clk-pll.c | 26 +++++++++++++----------
drivers/clk/meson/clk-regmap.c | 19 ++++++++---------
include/linux/clk-provider.h | 6 ++++++
4 files changed, 68 insertions(+), 22 deletions(-)
--
2.31.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: mturquette@baylibre.com, sboyd@kernel.org,
narmstrong@baylibre.com, jbrunet@baylibre.com,
linux-clk@vger.kernel.org
Cc: khilman@baylibre.com, linux-kernel@vger.kernel.org,
linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: [PATCH RFC v1 0/3] clk: meson: rounding for fast clocks on 32-bit SoCs
Date: Mon, 17 May 2021 22:37:21 +0200 [thread overview]
Message-ID: <20210517203724.1006254-1-martin.blumenstingl@googlemail.com> (raw)
On the 32-bit Amlogic Meson8/8b/8m2 SoCs we run into a problem with the
fast HDMI PLL and it's OD (post-dividers). This clock tree can run at
up to approx. 3GHz.
This however causes a problem, because these rates require BIT(31) to
be usable. Unfortunately this is not the case with clk_ops.round_rate
on 32-bit systems. BIT(31) is reserved for the sign (+ or -).
clk_ops.determine_rate does not suffer from this limitation. It uses
an int to signal any errors and can then take all availble 32 bits for
the clock rate.
I am sending this as RFC to start a discussion whether:
- this is a good way to solve it?
- what are the alternatives?
- getting some feedback on areas that need to be improved
As always: any feedback is welcome!
Thank you!
Martin
Martin Blumenstingl (3):
clk: divider: Add re-usable determine_rate implementations
clk: meson: regmap: switch to determine_rate for the dividers
clk: meson: pll: switch to determine_rate for the PLL ops
drivers/clk/clk-divider.c | 39 +++++++++++++++++++++++++++++++++-
drivers/clk/meson/clk-pll.c | 26 +++++++++++++----------
drivers/clk/meson/clk-regmap.c | 19 ++++++++---------
include/linux/clk-provider.h | 6 ++++++
4 files changed, 68 insertions(+), 22 deletions(-)
--
2.31.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
next reply other threads:[~2021-05-17 20:37 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-17 20:37 Martin Blumenstingl [this message]
2021-05-17 20:37 ` [PATCH RFC v1 0/3] clk: meson: rounding for fast clocks on 32-bit SoCs Martin Blumenstingl
2021-05-17 20:37 ` Martin Blumenstingl
2021-05-17 20:37 ` [PATCH RFC v1 1/3] clk: divider: Add re-usable determine_rate implementations Martin Blumenstingl
2021-05-17 20:37 ` Martin Blumenstingl
2021-05-17 20:37 ` Martin Blumenstingl
2021-05-18 7:44 ` Jerome Brunet
2021-05-18 7:44 ` Jerome Brunet
2021-05-18 7:44 ` Jerome Brunet
2021-05-18 20:33 ` Martin Blumenstingl
2021-05-18 20:33 ` Martin Blumenstingl
2021-05-18 20:33 ` Martin Blumenstingl
2021-05-19 12:31 ` Jerome Brunet
2021-05-19 12:31 ` Jerome Brunet
2021-05-19 12:31 ` Jerome Brunet
2021-05-17 20:37 ` [PATCH RFC v1 2/3] clk: meson: regmap: switch to determine_rate for the dividers Martin Blumenstingl
2021-05-17 20:37 ` Martin Blumenstingl
2021-05-17 20:37 ` Martin Blumenstingl
2021-05-18 7:47 ` Jerome Brunet
2021-05-18 7:47 ` Jerome Brunet
2021-05-18 7:47 ` Jerome Brunet
2021-05-17 20:37 ` [PATCH RFC v1 3/3] clk: meson: pll: switch to determine_rate for the PLL ops Martin Blumenstingl
2021-05-17 20:37 ` Martin Blumenstingl
2021-05-17 20:37 ` Martin Blumenstingl
2021-05-18 7:50 ` Jerome Brunet
2021-05-18 7:50 ` Jerome Brunet
2021-05-18 7:50 ` Jerome Brunet
2021-05-18 20:17 ` Martin Blumenstingl
2021-05-18 20:17 ` Martin Blumenstingl
2021-05-18 20:17 ` Martin Blumenstingl
2021-05-19 15:10 ` Jerome Brunet
2021-05-19 15:10 ` Jerome Brunet
2021-05-19 15:10 ` Jerome Brunet
2021-05-18 7:37 ` [PATCH RFC v1 0/3] clk: meson: rounding for fast clocks on 32-bit SoCs Jerome Brunet
2021-05-18 7:37 ` Jerome Brunet
2021-05-18 7:37 ` Jerome Brunet
2021-05-18 20:20 ` Martin Blumenstingl
2021-05-18 20:20 ` Martin Blumenstingl
2021-05-18 20:20 ` Martin Blumenstingl
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