[igt-dev] [PATCH i-g-t 00/17] Introduce PXP Test

[igt-dev] [PATCH i-g-t 00/17] Introduce PXP Test

[Alan Previn]

This series adds gem_pxp tests for the new PXP subsystem currently
being reviewed at https://patchwork.freedesktop.org/series/86798/ .
This series currently includes 4 groups of tests addressing the
features and restrictions described by Daniele's series :
   1. test i915 interfaces for allocation of protected bo's
      and contexts and enforcement of UAPI rule disallowing the
      modification of parameters after it's been created.
   2. verify PXP subsystem protected sessions generate encrypted
      content on protected output buffers and decrypt protected
      inputs buffers.
   3. verify i915 PXP auto-teardown succeeds on suspend-resume
      cycles and gem-exec of stale protected assets fail. Ensure
      protected-contexts adhere to stricter invalidation
      enforcement upon teardown event.
   4. Ensure that display plane decryption works as expected with
      protected buffers with and without HDCP.

NOTE: Although this series is on a fifth revision, this feature
has not been merged into the kernel yet. One final revision may
be necesssary depending on whether additional UAPI changes are
made on the kernel series. Additionally, if ioctl wrapper for
GEM_CREATE_EXT is merged in first, it would be dropped from this
series first.

Changes from prior rev1 to now:
   v5:
      - Addressed all rev4 review comments. No changes to
        overall flow and logic compared to the last rev.
   v4:
      - Addressed all rev3 review comments. NOTE: that all
        test cases and code logic are the same but a decent
        amount of refactoring has occured due to address
        v3 comments to break out subtests into separate
        functions while combining certain checks into the same
        function to reduce test time by minimizing number of
        suspend-resume power cycles.
   v3:
      - Addressed all rev2 review comments.
      - In line with one of the rev2 comments, a thorough fixup
        of all line-breaks in function calls was made for a more
        consistent styling.
      - Rebased on igt upstream repo and updated to latest kernel
        UAPI that added GEM_CREATE_EXT.
   v2: 
      - Addressed all rev1 review comments except these:
           1.Chris Wilson : "...have the caller do 1-3 once for its protected
             context. Call it something like intel_bb_enable_pxp(),
             intel_bb_set_pxp if it should be reversible.".
             -  This couldn't be implemented because [1] HW needs different
             instruction sequences for enabling/disabling PXP depending
             on the engine class and [2] the pair of "pxp-enable" and "pxp-
             disable" instructions need to be contained within the same batch
             that is dispatched to the hardware. That said, implementing
             internal intel_batchbuffer funtionality for this would conflict
             with how rendercopy_gen9 uses batch buffer memory by repositioing
             the pointer and consuming unused portions of the batch buffer as
             3d state offsets that batchbuffer has no visibility.
         
      - Added these additional subtests:
           1. verify that buffer sharing works across testing pxp context.
           2. verify teardown bans contexts via DRM_IOCTL_I915_GET_RESET_STAT.
           3. verify display plane decryption of protected buffers.

Alan Previn (16):
  Sync i915_drm.h UAPI from kernel
  Add PXP UAPI support in i915_drm.h
  Update IOCTL wrapper with DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT
  Add basic PXP testing of buffer and context alloc
  Perform a regular 3d copy as a control checkpoint
  Add PXP attribute support in batchbuffer and buffer_ops libs
  Add MI_SET_APPID instruction definition
  Enable protected session cmd in gen12_render_copyfunc
  Add subtest to copy raw source to protected dest
  Add test where both src and dest are protected
  Verify PXP teardown occurred through suspend-resume
  Verify execbuf fails with stale PXP context after teardown
  Verify execbuf fails with stale PXP buffer after teardown
  Verify execbuf ok with stale prot-buff and regular context
  Ensure RESET_STATS reports invalidated protected context
  Verify protected surfaces are dma buffer sharable

Karthik B S (1):
  tests/i915_pxp: CRC validation for display tests.

 include/drm-uapi/i915_drm.h |  448 +++++++++++-
 lib/intel_batchbuffer.c     |   23 +-
 lib/intel_batchbuffer.h     |   31 +
 lib/intel_bufops.h          |   15 +
 lib/intel_reg.h             |    9 +
 lib/ioctl_wrappers.c        |   34 +
 lib/ioctl_wrappers.h        |    2 +
 lib/rendercopy_gen9.c       |   72 +-
 tests/i915/gem_pxp.c        | 1318 +++++++++++++++++++++++++++++++++++
 tests/meson.build           |    1 +
 10 files changed, 1910 insertions(+), 43 deletions(-)
 create mode 100644 tests/i915/gem_pxp.c

-- 
2.25.1

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[igt-dev] [PATCH i-g-t 01/17] Sync i915_drm.h UAPI from kernel

[Alan Previn]

Sync i915_drm.h UAPI from drm-tip kernel baselined on following tag:
"drm-tip: 2021y-05m-12d-18h-04m-49s UTC integration manifest"

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 include/drm-uapi/i915_drm.h | 396 ++++++++++++++++++++++++++++++++----
 1 file changed, 361 insertions(+), 35 deletions(-)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index bf9ea471..d9fbf218 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -62,8 +62,8 @@ extern "C" {
 #define I915_ERROR_UEVENT		"ERROR"
 #define I915_RESET_UEVENT		"RESET"
 
-/*
- * i915_user_extension: Base class for defining a chain of extensions
+/**
+ * struct i915_user_extension - Base class for defining a chain of extensions
  *
  * Many interfaces need to grow over time. In most cases we can simply
  * extend the struct and have userspace pass in more data. Another option,
@@ -76,12 +76,58 @@ extern "C" {
  * increasing complexity, and for large parts of that interface to be
  * entirely optional. The downside is more pointer chasing; chasing across
  * the boundary with pointers encapsulated inside u64.
+ *
+ * Example chaining:
+ *
+ * .. code-block:: C
+ *
+ *	struct i915_user_extension ext3 {
+ *		.next_extension = 0, // end
+ *		.name = ...,
+ *	};
+ *	struct i915_user_extension ext2 {
+ *		.next_extension = (uintptr_t)&ext3,
+ *		.name = ...,
+ *	};
+ *	struct i915_user_extension ext1 {
+ *		.next_extension = (uintptr_t)&ext2,
+ *		.name = ...,
+ *	};
+ *
+ * Typically the struct i915_user_extension would be embedded in some uAPI
+ * struct, and in this case we would feed it the head of the chain(i.e ext1),
+ * which would then apply all of the above extensions.
+ *
  */
 struct i915_user_extension {
+	/**
+	 * @next_extension:
+	 *
+	 * Pointer to the next struct i915_user_extension, or zero if the end.
+	 */
 	__u64 next_extension;
+	/**
+	 * @name: Name of the extension.
+	 *
+	 * Note that the name here is just some integer.
+	 *
+	 * Also note that the name space for this is not global for the whole
+	 * driver, but rather its scope/meaning is limited to the specific piece
+	 * of uAPI which has embedded the struct i915_user_extension.
+	 */
 	__u32 name;
-	__u32 flags; /* All undefined bits must be zero. */
-	__u32 rsvd[4]; /* Reserved for future use; must be zero. */
+	/**
+	 * @flags: MBZ
+	 *
+	 * All undefined bits must be zero.
+	 */
+	__u32 flags;
+	/**
+	 * @rsvd: MBZ
+	 *
+	 * Reserved for future use; must be zero.
+	 */
+	__u32 rsvd[4];
 };
 
 /*
@@ -360,6 +406,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_QUERY			0x39
 #define DRM_I915_GEM_VM_CREATE		0x3a
 #define DRM_I915_GEM_VM_DESTROY		0x3b
+#define DRM_I915_GEM_CREATE_EXT		0x3c
 /* Must be kept compact -- no holes */
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
@@ -392,6 +439,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_GEM_ENTERVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
 #define DRM_IOCTL_I915_GEM_LEAVEVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
 #define DRM_IOCTL_I915_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext)
 #define DRM_IOCTL_I915_GEM_PREAD	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
 #define DRM_IOCTL_I915_GEM_PWRITE	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
 #define DRM_IOCTL_I915_GEM_MMAP		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -943,6 +991,7 @@ struct drm_i915_gem_exec_object {
 	__u64 offset;
 };
 
+/* DRM_IOCTL_I915_GEM_EXECBUFFER was removed in Linux 5.13 */
 struct drm_i915_gem_execbuffer {
 	/**
 	 * List of buffers to be validated with their relocations to be
@@ -1053,12 +1102,12 @@ struct drm_i915_gem_exec_fence {
 	__u32 flags;
 };
 
-/**
+/*
  * See drm_i915_gem_execbuffer_ext_timeline_fences.
  */
 #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0
 
-/**
+/*
  * This structure describes an array of drm_syncobj and associated points for
  * timeline variants of drm_syncobj. It is invalid to append this structure to
  * the execbuf if I915_EXEC_FENCE_ARRAY is set.
@@ -1699,7 +1748,7 @@ struct drm_i915_gem_context_param {
 	__u64 value;
 };
 
-/**
+/*
  * Context SSEU programming
  *
  * It may be necessary for either functional or performance reason to configure
@@ -2066,7 +2115,7 @@ struct drm_i915_perf_open_param {
 	__u64 properties_ptr;
 };
 
-/**
+/*
  * Enable data capture for a stream that was either opened in a disabled state
  * via I915_PERF_FLAG_DISABLED or was later disabled via
  * I915_PERF_IOCTL_DISABLE.
@@ -2080,7 +2129,7 @@ struct drm_i915_perf_open_param {
  */
 #define I915_PERF_IOCTL_ENABLE	_IO('i', 0x0)
 
-/**
+/*
  * Disable data capture for a stream.
  *
  * It is an error to try and read a stream that is disabled.
@@ -2089,11 +2138,11 @@ struct drm_i915_perf_open_param {
  */
 #define I915_PERF_IOCTL_DISABLE	_IO('i', 0x1)
 
-/**
+/*
  * Change metrics_set captured by a stream.
  *
  * If the stream is bound to a specific context, the configuration change
- * will performed __inline__ with that context such that it takes effect before
+ * will performed inline with that context such that it takes effect before
  * the next execbuf submission.
  *
  * Returns the previously bound metrics set id, or a negative error code.
@@ -2102,7 +2151,7 @@ struct drm_i915_perf_open_param {
  */
 #define I915_PERF_IOCTL_CONFIG	_IO('i', 0x2)
 
-/**
+/*
  * Common to all i915 perf records
  */
 struct drm_i915_perf_record_header {
@@ -2150,7 +2199,7 @@ enum drm_i915_perf_record_type {
 	DRM_I915_PERF_RECORD_MAX /* non-ABI */
 };
 
-/**
+/*
  * Structure to upload perf dynamic configuration into the kernel.
  */
 struct drm_i915_perf_oa_config {
@@ -2171,53 +2220,95 @@ struct drm_i915_perf_oa_config {
 	__u64 flex_regs_ptr;
 };
 
+/**
+ * struct drm_i915_query_item - An individual query for the kernel to process.
+ *
+ * The behaviour is determined by the @query_id. Note that exactly what
+ * @data_ptr is also depends on the specific @query_id.
+ */
 struct drm_i915_query_item {
+	/** @query_id: The id for this query */
 	__u64 query_id;
 #define DRM_I915_QUERY_TOPOLOGY_INFO    1
 #define DRM_I915_QUERY_ENGINE_INFO	2
 #define DRM_I915_QUERY_PERF_CONFIG      3
+#define DRM_I915_QUERY_MEMORY_REGIONS   4
 /* Must be kept compact -- no holes and well documented */
 
-	/*
+	/**
+	 * @length:
+	 *
 	 * When set to zero by userspace, this is filled with the size of the
-	 * data to be written at the data_ptr pointer. The kernel sets this
+	 * data to be written at the @data_ptr pointer. The kernel sets this
 	 * value to a negative value to signal an error on a particular query
 	 * item.
 	 */
 	__s32 length;
 
-	/*
+	/**
+	 * @flags:
+	 *
 	 * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
 	 *
 	 * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
-	 * following :
-	 *         - DRM_I915_QUERY_PERF_CONFIG_LIST
-	 *         - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
-	 *         - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
+	 * following:
+	 *
+	 *	- DRM_I915_QUERY_PERF_CONFIG_LIST
+	 *      - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
+	 *      - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
 	 */
 	__u32 flags;
 #define DRM_I915_QUERY_PERF_CONFIG_LIST          1
 #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2
 #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID   3
 
-	/*
-	 * Data will be written at the location pointed by data_ptr when the
-	 * value of length matches the length of the data to be written by the
+	/**
+	 * @data_ptr:
+	 *
+	 * Data will be written at the location pointed by @data_ptr when the
+	 * value of @length matches the length of the data to be written by the
 	 * kernel.
 	 */
 	__u64 data_ptr;
 };
 
+/**
+ * struct drm_i915_query - Supply an array of struct drm_i915_query_item for the
+ * kernel to fill out.
+ *
+ * Note that this is generally a two step process for each struct
+ * drm_i915_query_item in the array:
+ *
+ * 1. Call the DRM_IOCTL_I915_QUERY, giving it our array of struct
+ *    drm_i915_query_item, with &drm_i915_query_item.length set to zero. The
+ *    kernel will then fill in the size, in bytes, which tells userspace how
+ *    memory it needs to allocate for the blob(say for an array of properties).
+ *
+ * 2. Next we call DRM_IOCTL_I915_QUERY again, this time with the
+ *    &drm_i915_query_item.data_ptr equal to our newly allocated blob. Note that
+ *    the &drm_i915_query_item.length should still be the same as what the
+ *    kernel previously set. At this point the kernel can fill in the blob.
+ *
+ * Note that for some query items it can make sense for userspace to just pass
+ * in a buffer/blob equal to or larger than the required size. In this case only
+ * a single ioctl call is needed. For some smaller query items this can work
+ * quite well.
+ *
+ */
 struct drm_i915_query {
+	/** @num_items: The number of elements in the @items_ptr array */
 	__u32 num_items;
 
-	/*
-	 * Unused for now. Must be cleared to zero.
+	/**
+	 * @flags: Unused for now. Must be cleared to zero.
 	 */
 	__u32 flags;
 
-	/*
-	 * This points to an array of num_items drm_i915_query_item structures.
+	/**
+	 * @items_ptr:
+	 *
+	 * Pointer to an array of struct drm_i915_query_item. The number of
+	 * array elements is @num_items.
 	 */
 	__u64 items_ptr;
 };
@@ -2291,21 +2382,21 @@ struct drm_i915_query_topology_info {
  * Describes one engine and it's capabilities as known to the driver.
  */
 struct drm_i915_engine_info {
-	/** Engine class and instance. */
+	/** @engine: Engine class and instance. */
 	struct i915_engine_class_instance engine;
 
-	/** Reserved field. */
+	/** @rsvd0: Reserved field. */
 	__u32 rsvd0;
 
-	/** Engine flags. */
+	/** @flags: Engine flags. */
 	__u64 flags;
 
-	/** Capabilities of this engine. */
+	/** @capabilities: Capabilities of this engine. */
 	__u64 capabilities;
 #define I915_VIDEO_CLASS_CAPABILITY_HEVC		(1 << 0)
 #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC	(1 << 1)
 
-	/** Reserved fields. */
+	/** @rsvd1: Reserved fields. */
 	__u64 rsvd1[4];
 };
 
@@ -2316,13 +2407,13 @@ struct drm_i915_engine_info {
  * an array of struct drm_i915_engine_info structures.
  */
 struct drm_i915_query_engine_info {
-	/** Number of struct drm_i915_engine_info structs following. */
+	/** @num_engines: Number of struct drm_i915_engine_info structs following. */
 	__u32 num_engines;
 
-	/** MBZ */
+	/** @rsvd: MBZ */
 	__u32 rsvd[3];
 
-	/** Marker for drm_i915_engine_info structures. */
+	/** @engines: Marker for drm_i915_engine_info structures. */
 	struct drm_i915_engine_info engines[];
 };
 
@@ -2376,6 +2467,241 @@ struct drm_i915_query_perf_config {
 	__u8 data[];
 };
 
+/**
+ * enum drm_i915_gem_memory_class - Supported memory classes
+ */
+enum drm_i915_gem_memory_class {
+	/** @I915_MEMORY_CLASS_SYSTEM: System memory */
+	I915_MEMORY_CLASS_SYSTEM = 0,
+	/** @I915_MEMORY_CLASS_DEVICE: Device local-memory */
+	I915_MEMORY_CLASS_DEVICE,
+};
+
+/**
+ * struct drm_i915_gem_memory_class_instance - Identify particular memory region
+ */
+struct drm_i915_gem_memory_class_instance {
+	/** @memory_class: See enum drm_i915_gem_memory_class */
+	__u16 memory_class;
+
+	/** @memory_instance: Which instance */
+	__u16 memory_instance;
+};
+
+/**
+ * struct drm_i915_memory_region_info - Describes one region as known to the
+ * driver.
+ *
+ * Note that we reserve some stuff here for potential future work. As an example
+ * we might want expose the capabilities for a given region, which could include
+ * things like if the region is CPU mappable/accessible, what are the supported
+ * mapping types etc.
+ *
+ * Note that to extend struct drm_i915_memory_region_info and struct
+ * drm_i915_query_memory_regions in the future the plan is to do the following:
+ *
+ * .. code-block:: C
+ *
+ *	struct drm_i915_memory_region_info {
+ *		struct drm_i915_gem_memory_class_instance region;
+ *		union {
+ *			__u32 rsvd0;
+ *			__u32 new_thing1;
+ *		};
+ *		...
+ *		union {
+ *			__u64 rsvd1[8];
+ *			struct {
+ *				__u64 new_thing2;
+ *				__u64 new_thing3;
+ *				...
+ *			};
+ *		};
+ *	};
+ *
+ * With this things should remain source compatible between versions for
+ * userspace, even as we add new fields.
+ *
+ * Note this is using both struct drm_i915_query_item and struct drm_i915_query.
+ * For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS
+ * at &drm_i915_query_item.query_id.
+ */
+struct drm_i915_memory_region_info {
+	/** @region: The class:instance pair encoding */
+	struct drm_i915_gem_memory_class_instance region;
+
+	/** @rsvd0: MBZ */
+	__u32 rsvd0;
+
+	/** @probed_size: Memory probed by the driver (-1 = unknown) */
+	__u64 probed_size;
+
+	/** @unallocated_size: Estimate of memory remaining (-1 = unknown) */
+	__u64 unallocated_size;
+
+	/** @rsvd1: MBZ */
+	__u64 rsvd1[8];
+};
+
+/**
+ * struct drm_i915_query_memory_regions
+ *
+ * The region info query enumerates all regions known to the driver by filling
+ * in an array of struct drm_i915_memory_region_info structures.
+ *
+ * Example for getting the list of supported regions:
+ *
+ * .. code-block:: C
+ *
+ *	struct drm_i915_query_memory_regions *info;
+ *	struct drm_i915_query_item item = {
+ *		.query_id = DRM_I915_QUERY_MEMORY_REGIONS;
+ *	};
+ *	struct drm_i915_query query = {
+ *		.num_items = 1,
+ *		.items_ptr = (uintptr_t)&item,
+ *	};
+ *	int err, i;
+ *
+ *	// First query the size of the blob we need, this needs to be large
+ *	// enough to hold our array of regions. The kernel will fill out the
+ *	// item.length for us, which is the number of bytes we need.
+ *	err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
+ *	if (err) ...
+ *
+ *	info = calloc(1, item.length);
+ *	// Now that we allocated the required number of bytes, we call the ioctl
+ *	// again, this time with the data_ptr pointing to our newly allocated
+ *	// blob, which the kernel can then populate with the all the region info.
+ *	item.data_ptr = (uintptr_t)&info,
+ *
+ *	err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
+ *	if (err) ...
+ *
+ *	// We can now access each region in the array
+ *	for (i = 0; i < info->num_regions; i++) {
+ *		struct drm_i915_memory_region_info mr = info->regions[i];
+ *		u16 class = mr.region.class;
+ *		u16 instance = mr.region.instance;
+ *
+ *		....
+ *	}
+ *
+ *	free(info);
+ */
+struct drm_i915_query_memory_regions {
+	/** @num_regions: Number of supported regions */
+	__u32 num_regions;
+
+	/** @rsvd: MBZ */
+	__u32 rsvd[3];
+
+	/** @regions: Info about each supported region */
+	struct drm_i915_memory_region_info regions[];
+};
+
+/**
+ * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
+ * extension support using struct i915_user_extension.
+ *
+ * Note that in the future we want to have our buffer flags here, at least for
+ * the stuff that is immutable. Previously we would have two ioctls, one to
+ * create the object with gem_create, and another to apply various parameters,
+ * however this creates some ambiguity for the params which are considered
+ * immutable. Also in general we're phasing out the various SET/GET ioctls.
+ */
+struct drm_i915_gem_create_ext {
+	/**
+	 * @size: Requested size for the object.
+	 *
+	 * The (page-aligned) allocated size for the object will be returned.
+	 *
+	 * Note that for some devices we have might have further minimum
+	 * page-size restrictions(larger than 4K), like for device local-memory.
+	 * However in general the final size here should always reflect any
+	 * rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS
+	 * extension to place the object in device local-memory.
+	 */
+	__u64 size;
+	/**
+	 * @handle: Returned handle for the object.
+	 *
+	 * Object handles are nonzero.
+	 */
+	__u32 handle;
+	/** @flags: MBZ */
+	__u32 flags;
+	/**
+	 * @extensions: The chain of extensions to apply to this object.
+	 *
+	 * This will be useful in the future when we need to support several
+	 * different extensions, and we need to apply more than one when
+	 * creating the object. See struct i915_user_extension.
+	 *
+	 * If we don't supply any extensions then we get the same old gem_create
+	 * behaviour.
+	 *
+	 * For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see
+	 * struct drm_i915_gem_create_ext_memory_regions.
+	 */
+#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
+	__u64 extensions;
+};
+
+/**
+ * struct drm_i915_gem_create_ext_memory_regions - The
+ * I915_GEM_CREATE_EXT_MEMORY_REGIONS extension.
+ *
+ * Set the object with the desired set of placements/regions in priority
+ * order. Each entry must be unique and supported by the device.
+ *
+ * This is provided as an array of struct drm_i915_gem_memory_class_instance, or
+ * an equivalent layout of class:instance pair encodings. See struct
+ * drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to
+ * query the supported regions for a device.
+ *
+ * As an example, on discrete devices, if we wish to set the placement as
+ * device local-memory we can do something like:
+ *
+ * .. code-block:: C
+ *
+ *	struct drm_i915_gem_memory_class_instance region_lmem = {
+ *              .memory_class = I915_MEMORY_CLASS_DEVICE,
+ *              .memory_instance = 0,
+ *      };
+ *      struct drm_i915_gem_create_ext_memory_regions regions = {
+ *              .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS },
+ *              .regions = (uintptr_t)&region_lmem,
+ *              .num_regions = 1,
+ *      };
+ *      struct drm_i915_gem_create_ext create_ext = {
+ *              .size = 16 * PAGE_SIZE,
+ *              .extensions = (uintptr_t)&regions,
+ *      };
+ *
+ *      int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
+ *      if (err) ...
+ *
+ * At which point we get the object handle in &drm_i915_gem_create_ext.handle,
+ * along with the final object size in &drm_i915_gem_create_ext.size, which
+ * should account for any rounding up, if required.
+ */
+struct drm_i915_gem_create_ext_memory_regions {
+	/** @base: Extension link. See struct i915_user_extension. */
+	struct i915_user_extension base;
+
+	/** @pad: MBZ */
+	__u32 pad;
+	/** @num_regions: Number of elements in the @regions array. */
+	__u32 num_regions;
+	/**
+	 * @regions: The regions/placements array.
+	 *
+	 * An array of struct drm_i915_gem_memory_class_instance.
+	 */
+	__u64 regions;
+};
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.25.1

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[igt-dev] [PATCH i-g-t 02/17] Add PXP UAPI support in i915_drm.h

[Alan Previn]

At the time of this commit, PXP hasnt been merged into
upstream kernel so this has no kernel tag reference yet

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 include/drm-uapi/i915_drm.h | 52 +++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index d9fbf218..e67e3e5c 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -1743,6 +1743,26 @@ struct drm_i915_gem_context_param {
  * Default is 16 KiB.
  */
 #define I915_CONTEXT_PARAM_RINGSIZE	0xc
+
+/*
+ * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ *
+ * Mark that the context makes use of protected content, which will result
+ * in the context being invalidated when the protected content session is.
+ * This flag can only be set at context creation time and, when set to true,
+ * must be preceded by an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE
+ * to false. This flag can't be set to true in conjunction with setting the
+ * I915_CONTEXT_PARAM_BANNABLE flag to false.
+ *
+ * Given the numerous restriction on this flag, there are several unique
+ * failure cases:
+ *
+ * -ENODEV: feature not available
+ * -EEXIST: trying to modify an existing context
+ * -EPERM: trying to mark a recoverable or not bannable context as protected
+ * -EACCES: submitting an invalidated context for execution
+ */
+#define I915_CONTEXT_PARAM_PROTECTED_CONTENT    0xd
 /* Must be kept compact -- no holes and well documented */
 
 	__u64 value;
@@ -1973,6 +1993,12 @@ struct drm_i915_reg_read {
 struct drm_i915_reset_stats {
 	__u32 ctx_id;
 	__u32 flags;
+	/*
+	 * contexts marked as using protected content are invalidated when the
+	 * protected content session dies. Submission of invalidated contexts
+	 * is rejected with -EACCES.
+	 */
+#define I915_CONTEXT_INVALIDATED 0x1
 
 	/* All resets since boot/module reload, for all contexts */
 	__u32 reset_count;
@@ -2645,6 +2671,7 @@ struct drm_i915_gem_create_ext {
 	 * struct drm_i915_gem_create_ext_memory_regions.
 	 */
 #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
+#define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1
 	__u64 extensions;
 };
 
@@ -2702,6 +2729,31 @@ struct drm_i915_gem_create_ext_memory_regions {
 	__u64 regions;
 };
 
+/*
+ * I915_OBJECT_PARAM_PROTECTED_CONTENT:
+ *
+ * If set to true, buffer contents is expected to be protected by PXP
+ * encryption and requires decryption for scan out and processing. This is
+ * only possible on platforms that have PXP enabled, on all other scenarios
+ * setting this flag will cause the ioctl to fail and return -ENODEV.
+ *
+ * The buffer contents are considered invalid after a PXP session teardown.
+ * It is recommended to use protected buffers only with contexts created
+ * using the I915_CONTEXT_PARAM_PROTECTED_CONTENT flag, as that will enable
+ * extra checks at submission time on the validity of the objects involved,
+ * which can lead to the following errors:
+ *
+ * -ENODEV: PXP session not currently active
+ * -EIO: buffer has become invalid after a teardown event
+ */
+struct drm_i915_gem_create_ext_protected_content {
+	struct i915_user_extension base;
+	__u32 flags;
+};
+
+/* ID of the protected content session managed by i915 when PXP is active */
+#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.25.1

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[igt-dev] [PATCH i-g-t 03/17] Update IOCTL wrapper with DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT

[Alan Previn]

Update IOCTL wrapper with DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 lib/ioctl_wrappers.c | 34 ++++++++++++++++++++++++++++++++++
 lib/ioctl_wrappers.h |  2 ++
 2 files changed, 36 insertions(+)

diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 4440004c..c8e01911 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -657,6 +657,40 @@ void gem_execbuf_wr(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
 	igt_assert_eq(__gem_execbuf_wr(fd, execbuf), 0);
 }
 
+/**
+ * __gem_ctx_create_ext:
+ * @fd: open i915 drm file descriptor
+ * @ctx_ext: context_create_ext data structure
+ *
+ * This wraps the GEM_CONTEXT_CREATE_EXT ioctl, which allocates gem context based on
+ * additional drm_i915_gem_context_create_ext_setparam input extensions. This is
+ * allowed to fail, with -errno returned
+ */
+int __gem_ctx_create_ext(int fd, struct drm_i915_gem_context_create_ext *ctx_ext)
+{
+	int err = 0;
+
+	if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, ctx_ext)) {
+		err = -errno;
+		igt_assume(err != 0);
+	}
+	errno = 0;
+	return err;
+}
+
+/**
+ * gem_ctx_create_ext:
+ * @fd: open i915 drm file descriptor
+ * @ctx_ext: context_create_ext data structure
+ *
+ * This wraps the GEM_CONTEXT_CREATE_EXT ioctl, which allocates gem context based on
+ * additional drm_i915_gem_context_create_ext_setparam input extensions.
+ */
+void gem_ctx_create_ext(int fd, struct drm_i915_gem_context_create_ext *ctx_ext)
+{
+	igt_assert_eq(__gem_ctx_create_ext(fd, ctx_ext), 0);
+}
+
 /**
  * gem_madvise:
  * @fd: open i915 drm file descriptor
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index 9ea67365..8288c8d7 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -82,6 +82,8 @@ void gem_execbuf_wr(int fd, struct drm_i915_gem_execbuffer2 *execbuf);
 int __gem_execbuf_wr(int fd, struct drm_i915_gem_execbuffer2 *execbuf);
 void gem_execbuf(int fd, struct drm_i915_gem_execbuffer2 *execbuf);
 int __gem_execbuf(int fd, struct drm_i915_gem_execbuffer2 *execbuf);
+int __gem_ctx_create_ext(int fd, struct drm_i915_gem_context_create_ext *ctx_ext);
+void gem_ctx_create_ext(int fd, struct drm_i915_gem_context_create_ext *ctx_ext);
 
 #ifndef I915_GEM_DOMAIN_WC
 #define I915_GEM_DOMAIN_WC 0x80
-- 
2.25.1

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[igt-dev] [PATCH i-g-t 04/17] Add basic PXP testing of buffer and context alloc

[Alan Previn]

Test PXP capability support as well as the allocation of protected
buffers and protected contexts.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 tests/i915/gem_pxp.c | 353 +++++++++++++++++++++++++++++++++++++++++++
 tests/meson.build    |   1 +
 2 files changed, 354 insertions(+)
 create mode 100644 tests/i915/gem_pxp.c

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
new file mode 100644
index 00000000..8779dddc
--- /dev/null
+++ b/tests/i915/gem_pxp.c
@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include "igt.h"
+#include "i915/gem.h"
+
+IGT_TEST_DESCRIPTION("Test PXP that manages protected content through arbitrated HW-PXP-session");
+/* Note: PXP = "Protected Xe Path" */
+
+static bool is_pxp_hw_supported(int i915)
+{
+	uint32_t devid = intel_get_drm_devid(i915);
+
+	if (IS_TIGERLAKE(devid) || IS_ROCKETLAKE(devid) || IS_ALDERLAKE_S(devid))
+		return true;
+
+	return false;
+}
+
+static int create_bo_ext(int i915, uint32_t size, bool protected_is_true, uint32_t *bo_out)
+{
+	int ret;
+
+	struct drm_i915_gem_create_ext_protected_content protected_ext = {
+		.base = { .name = I915_GEM_CREATE_EXT_PROTECTED_CONTENT },
+		.flags = 0,
+	};
+
+	struct drm_i915_gem_create_ext create_ext = {
+		.size = size,
+		.extensions = 0,
+	};
+
+	if (protected_is_true)
+		create_ext.extensions = (uintptr_t)&protected_ext;
+
+	ret = igt_ioctl(i915, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
+	if (!ret)
+		*bo_out = create_ext.handle;
+
+	return ret;
+}
+
+static void test_bo_alloc_pxp_nohw(int i915)
+{
+	int ret;
+	uint32_t bo;
+
+	ret = create_bo_ext(i915, 4096, false, &bo);
+	igt_assert_eq(ret, 0);
+	gem_close(i915, bo);
+
+	ret = create_bo_ext(i915, 4096, true, &bo);
+	igt_assert_eq(ret, -ENODEV);
+	igt_assert_eq(bo, 0);
+}
+
+static void test_bo_alloc_pxp_off(int i915)
+{
+	int ret;
+	uint32_t bo;
+
+	ret = create_bo_ext(i915, 4096, false, &bo);
+	igt_assert_eq(ret, 0);
+	gem_close(i915, bo);
+}
+
+static void test_bo_alloc_pxp_on(int i915)
+{
+	int ret;
+	uint32_t bo;
+
+	ret = create_bo_ext(i915, 4096, true, &bo);
+	igt_assert_eq(ret, 0);
+	gem_close(i915, bo);
+}
+
+static int create_ctx_with_params(int i915, bool with_protected_param, bool protected_is_true,
+				  bool with_recoverable_param, bool recoverable_is_true,
+				  uint32_t *ctx_out)
+{
+	int ret;
+
+	struct drm_i915_gem_context_create_ext_setparam p_prot = {
+		.base = {
+			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+			.next_extension = 0,
+		},
+		.param = {
+			.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
+			.value = 0,
+		}
+	};
+	struct drm_i915_gem_context_create_ext_setparam p_norecover = {
+		.base = {
+			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+			.next_extension = 0,
+		},
+		.param = {
+			.param = I915_CONTEXT_PARAM_RECOVERABLE,
+			.value = 0,
+		}
+	};
+	struct drm_i915_gem_context_create_ext create = {
+		.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
+		.extensions = 0,
+	};
+
+	p_prot.param.value = protected_is_true;
+	p_norecover.param.value = recoverable_is_true;
+
+	if (with_protected_param && with_recoverable_param) {
+		create.extensions = to_user_pointer(&(p_norecover.base));
+		p_norecover.base.next_extension = to_user_pointer(&(p_prot.base));
+	} else if (!with_protected_param && with_recoverable_param) {
+		create.extensions = to_user_pointer(&(p_norecover.base));
+		p_norecover.base.next_extension = 0;
+	} else if (with_protected_param && !with_recoverable_param) {
+		create.extensions = to_user_pointer(&(p_prot.base));
+		p_prot.base.next_extension = 0;
+	} else if (!with_protected_param && !with_recoverable_param) {
+		create.flags = 0;
+	}
+
+	ret = __gem_ctx_create_ext(i915, &create);
+	if (!ret)
+		*ctx_out = create.ctx_id;
+
+	return ret;
+}
+
+#define CHANGE_PARAM_PROTECTED 0x0001
+#define CHANGE_PARAM_RECOVERY 0x0002
+
+static int modify_ctx_param(int i915, uint32_t ctx_id, uint32_t param_mask, bool param_value)
+{
+	int ret;
+
+	struct drm_i915_gem_context_param ctx_param = {
+		.ctx_id = ctx_id,
+		.param = 0,
+		.value = 0,
+	};
+
+	if (param_mask == CHANGE_PARAM_PROTECTED) {
+		ctx_param.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT;
+		ctx_param.value = (int)param_value;
+	} else if (param_mask == CHANGE_PARAM_RECOVERY) {
+		ctx_param.param = I915_CONTEXT_PARAM_RECOVERABLE;
+		ctx_param.value = (int)param_value;
+	}
+
+	ret = igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &ctx_param);
+
+	return ret;
+}
+
+static int get_ctx_protected_param(int i915, uint32_t ctx_id)
+{
+	int ret;
+
+	struct drm_i915_gem_context_param ctx_param = {
+		.ctx_id = ctx_id,
+		.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
+	};
+
+	ret = igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &ctx_param);
+	igt_assert_eq(ret, 0);
+
+	return ctx_param.value;
+}
+
+static int get_ctx_recovery_param(int i915, uint32_t ctx_id)
+{
+	int ret;
+
+	struct drm_i915_gem_context_param ctx_param = {
+		.ctx_id = ctx_id,
+		.param = I915_CONTEXT_PARAM_RECOVERABLE,
+	};
+
+	ret = igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &ctx_param);
+	igt_assert_eq(ret, 0);
+
+	return ctx_param.value;
+}
+
+static void test_ctx_alloc_pxp_nohw(int i915)
+{
+	uint32_t ctx;
+
+	igt_assert_eq(create_ctx_with_params(i915, true, true, true, false, &ctx), -ENODEV);
+	igt_assert_eq(create_ctx_with_params(i915, true, false, true, false, &ctx), 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	gem_context_destroy(i915, ctx);
+}
+
+static void test_ctx_alloc_recover_off_protect_off(int i915)
+{
+	uint32_t ctx;
+
+	igt_assert_eq(create_ctx_with_params(i915, true, false, true, false, &ctx), 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	gem_context_destroy(i915, ctx);
+}
+
+static void test_ctx_alloc_recover_off_protect_on(int i915)
+{
+	uint32_t ctx;
+
+	igt_assert_eq(create_ctx_with_params(i915, true, true, true, false, &ctx), 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	gem_context_destroy(i915, ctx);
+}
+
+static void test_ctx_alloc_recover_on_protect_off(int i915)
+{
+	uint32_t ctx;
+
+	igt_assert_eq(create_ctx_with_params(i915, true, false, true, true, &ctx), 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 1);
+	gem_context_destroy(i915, ctx);
+}
+
+static void test_ctx_alloc_recover_on_protect_on(int i915)
+{
+	uint32_t ctx;
+
+	igt_assert_eq(create_ctx_with_params(i915, true, true, true, true, &ctx), -EPERM);
+	igt_assert_eq(create_ctx_with_params(i915, true, true, false, false, &ctx), -EPERM);
+}
+
+static void test_ctx_mod_recover_off_to_on(int i915)
+{
+	uint32_t ctx;
+
+	igt_assert_eq(create_ctx_with_params(i915, true, true, true, false, &ctx), 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_RECOVERY, true), -EPERM);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	gem_context_destroy(i915, ctx);
+}
+
+static void test_ctx_mod_protected_on_to_off(int i915)
+{
+	uint32_t ctx;
+
+	igt_assert_eq(create_ctx_with_params(i915, true, true, true, false, &ctx), 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_PROTECTED, false), -EPERM);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	gem_context_destroy(i915, ctx);
+}
+
+static void test_ctx_mod_protected_to_all_invalid(int i915)
+{
+	uint32_t ctx;
+
+	igt_assert_eq(create_ctx_with_params(i915, true, true, true, false, &ctx), 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_RECOVERY, true), -EPERM);
+	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_PROTECTED, false), -EPERM);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	gem_context_destroy(i915, ctx);
+}
+
+static void test_ctx_mod_regular_to_all_valid(int i915)
+{
+	uint32_t ctx;
+
+	igt_assert_eq(create_ctx_with_params(i915, false, false, false, false, &ctx), 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 1);
+	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_RECOVERY, false), 0);
+	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_PROTECTED, true), -EPERM);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	gem_context_destroy(i915, ctx);
+}
+
+igt_main
+{
+	int i915 = -1;
+	bool pxp_supported = false;
+
+	igt_fixture
+	{
+		i915 = drm_open_driver(DRIVER_INTEL);
+		igt_require(i915);
+		igt_require_gem(i915);
+		pxp_supported = is_pxp_hw_supported(i915);
+	}
+
+	igt_subtest_group {
+		igt_fixture {
+			igt_require((pxp_supported == 0));
+		}
+
+		igt_describe("Verify protected buffer on unsupported hw:");
+		igt_subtest("hw-rejects-pxp-buffer")
+			test_bo_alloc_pxp_nohw(i915);
+		igt_describe("Verify protected context on unsupported hw:");
+		igt_subtest("hw-rejects-pxp-context")
+			test_ctx_alloc_pxp_nohw(i915);
+	}
+
+	igt_subtest_group {
+		igt_fixture {
+			igt_require(pxp_supported);
+		}
+
+		igt_describe("Verify protected buffer on supported hw:");
+		igt_subtest("create-regular-buffer")
+			test_bo_alloc_pxp_off(i915);
+		igt_subtest("create-protected-buffer")
+			test_bo_alloc_pxp_on(i915);
+
+		igt_describe("Verify protected context on supported hw:");
+		igt_subtest("create-regular-context-1")
+			test_ctx_alloc_recover_off_protect_off(i915);
+		igt_subtest("create-regular-context-2")
+			test_ctx_alloc_recover_on_protect_off(i915);
+		igt_subtest("fail-invalid-protected-context")
+			test_ctx_alloc_recover_on_protect_on(i915);
+		igt_subtest("create-valid-protected-context")
+			test_ctx_alloc_recover_off_protect_on(i915);
+
+		igt_describe("Verify protected context integrity:");
+		igt_subtest("reject-modify-context-protection-on")
+			test_ctx_mod_regular_to_all_valid(i915);
+		igt_subtest("reject-modify-context-protection-off-1")
+			test_ctx_mod_recover_off_to_on(i915);
+		igt_subtest("reject-modify-context-protection-off-2")
+			test_ctx_mod_protected_on_to_off(i915);
+		igt_subtest("reject-modify-context-protection-off-3")
+			test_ctx_mod_protected_to_all_invalid(i915);
+	}
+
+	igt_fixture {
+		close(i915);
+	}
+}
diff --git a/tests/meson.build b/tests/meson.build
index 19cc4ebe..e0bff4d1 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -187,6 +187,7 @@ i915_progs = [
 	'gem_pread_after_blit',
 	'gem_pwrite',
 	'gem_pwrite_snooped',
+	'gem_pxp',
 	'gem_read_read_speed',
 	'gem_readwrite',
 	'gem_reg_read',
-- 
2.25.1

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[igt-dev] [PATCH i-g-t 05/17] Perform a regular 3d copy as a control checkpoint

[Alan Previn]

As a control checkpoint, allocate buffers to be used
as texture and render target in the 3d engine for a
regular src to dest copy blit and verify buffer pixels.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 tests/i915/gem_pxp.c | 166 ++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 157 insertions(+), 9 deletions(-)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 8779dddc..b1415efc 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -236,6 +236,20 @@ static void test_ctx_alloc_recover_on_protect_on(int i915)
 	igt_assert_eq(create_ctx_with_params(i915, true, true, false, false, &ctx), -EPERM);
 }
 
+static void test_ctx_mod_regular_to_all_valid(int i915)
+{
+	uint32_t ctx;
+
+	igt_assert_eq(create_ctx_with_params(i915, false, false, false, false, &ctx), 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 1);
+	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_RECOVERY, false), 0);
+	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_PROTECTED, true), -EPERM);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	gem_context_destroy(i915, ctx);
+}
+
 static void test_ctx_mod_recover_off_to_on(int i915)
 {
 	uint32_t ctx;
@@ -275,24 +289,145 @@ static void test_ctx_mod_protected_to_all_invalid(int i915)
 	gem_context_destroy(i915, ctx);
 }
 
-static void test_ctx_mod_regular_to_all_valid(int i915)
+static void fill_bo_content(int i915, uint32_t bo, uint32_t size, uint32_t initcolor)
 {
-	uint32_t ctx;
+	uint32_t *ptr, *ptrtmp;
+	int loop = 0;
 
-	igt_assert_eq(create_ctx_with_params(i915, false, false, false, false, &ctx), 0);
-	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
-	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 1);
-	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_RECOVERY, false), 0);
-	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_PROTECTED, true), -EPERM);
-	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
-	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	ptr = gem_mmap__device_coherent(i915, bo, 0, size, PROT_WRITE);
+	ptrtmp = ptr;
+
+	/* read and count all dword matches till size */
+	while (loop++ < (size/4)) {
+		*ptrtmp = initcolor;
+		++ptrtmp;
+	}
+
+	igt_assert(gem_munmap(ptr, size) == 0);
+}
+
+#define COMPARE_COLOR_READIBLE     1
+#define COMPARE_COLOR_UNREADIBLE   2
+#define COMPARE_N_PIXELS_VERBOSELY 0
+
+static void assert_bo_content_check(int i915, uint32_t bo, int compare_op,
+				    uint32_t size, uint32_t color)
+{
+	uint32_t *ptr, *ptrtmp;
+	int loop = 0, num_matches = 0;
+	uint32_t value;
+	bool op_readible = (compare_op == COMPARE_COLOR_READIBLE);
+
+	ptr = gem_mmap__device_coherent(i915, bo, 0, size, PROT_READ);
+	ptrtmp = ptr;
+
+	if (COMPARE_N_PIXELS_VERBOSELY) {
+		igt_info("--------->>>\n");
+		while (loop < COMPARE_N_PIXELS_VERBOSELY && loop < (size/4)) {
+			value = *ptrtmp;
+			igt_info("Color read = 0x%08x ", value);
+			igt_info("expected %c= 0x%08x)\n", op_readible?'=':'!', color);
+			++ptrtmp;
+			++loop;
+		}
+		igt_info("<<<---------\n");
+		ptrtmp = ptr;
+		loop = 0;
+	}
+
+	/* count all pixels for matches */
+	while (loop++ < (size/4)) {
+		value = *ptrtmp;
+		if (value == color)
+			++num_matches;
+		++ptrtmp;
+	}
+
+	if (op_readible)
+		igt_assert_eq(num_matches, (size/4));
+	else
+		igt_assert_eq(num_matches, 0);
+
+	igt_assert(gem_munmap(ptr, size) == 0);
+}
+
+static uint32_t alloc_and_fill_dest_buff(int i915, bool protected, uint32_t size,
+					 uint32_t init_color)
+{
+	uint32_t bo;
+	int ret;
+
+	ret = create_bo_ext(i915, size, protected, &bo);
+	igt_assert_eq(ret, 0);
+	igt_assert(bo);
+	fill_bo_content(i915, bo, size, init_color);
+	assert_bo_content_check(i915, bo, COMPARE_COLOR_READIBLE, size, init_color);
+
+	return bo;
+}
+
+/*
+ * Rendering tests surface attributes, keep it simple:
+ * page aligned width==stride, thus, and size
+ */
+#define TSTSURF_WIDTH       1024
+#define TSTSURF_HEIGHT      128
+#define TSTSURF_BYTESPP     4
+#define TSTSURF_STRIDE      (TSTSURF_WIDTH*TSTSURF_BYTESPP)
+#define TSTSURF_SIZE        (TSTSURF_STRIDE*TSTSURF_HEIGHT)
+#define TSTSURF_FILLCOLOR1  0xfaceface
+#define TSTSURF_INITCOLOR1  0x12341234
+
+static void test_render_baseline(int i915)
+{
+	uint32_t ctx, srcbo, dstbo;
+	struct intel_buf *srcbuf, *dstbuf;
+	struct buf_ops *bops;
+	struct intel_bb *ibb;
+	uint32_t devid;
+	int ret;
+
+	devid = intel_get_drm_devid(i915);
+	igt_assert(devid);
+
+	bops = buf_ops_create(i915);
+	igt_assert(bops);
+
+	/* Perform a regular 3d copy as a control checkpoint */
+	ret = create_ctx_with_params(i915, false, false, false, false, &ctx);
+	igt_assert_eq(ret, 0);
+	ibb = intel_bb_create_with_context(i915, ctx, 4096);
+	igt_assert(ibb);
+
+	dstbo = alloc_and_fill_dest_buff(i915, false, TSTSURF_SIZE, TSTSURF_INITCOLOR1);
+	dstbuf = intel_buf_create_using_handle(bops, dstbo, TSTSURF_WIDTH, TSTSURF_HEIGHT,
+					       TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+
+	srcbo = alloc_and_fill_dest_buff(i915, false, TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
+	srcbuf = intel_buf_create_using_handle(bops, srcbo, TSTSURF_WIDTH, TSTSURF_HEIGHT,
+					       TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+
+	gen12_render_copyfunc(ibb, srcbuf, 0, 0, TSTSURF_WIDTH, TSTSURF_HEIGHT, dstbuf, 0, 0);
+	gem_sync(i915, dstbo);
+
+	assert_bo_content_check(i915, dstbo, COMPARE_COLOR_READIBLE,
+				TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
+
+	intel_bb_destroy(ibb);
+	intel_buf_destroy(srcbuf);
+	gem_close(i915, srcbo);
+	intel_buf_destroy(dstbuf);
+	gem_close(i915, dstbo);
 	gem_context_destroy(i915, ctx);
+	buf_ops_destroy(bops);
 }
 
 igt_main
 {
 	int i915 = -1;
 	bool pxp_supported = false;
+	igt_render_copyfunc_t rendercopy = NULL;
+	uint32_t devid = 0;
 
 	igt_fixture
 	{
@@ -346,6 +481,19 @@ igt_main
 		igt_subtest("reject-modify-context-protection-off-3")
 			test_ctx_mod_protected_to_all_invalid(i915);
 	}
+	igt_subtest_group {
+		igt_fixture {
+			igt_require(pxp_supported);
+			devid = intel_get_drm_devid(i915);
+			igt_assert(devid);
+			rendercopy = igt_get_render_copyfunc(devid);
+			igt_require(rendercopy);
+		}
+
+		igt_describe("Verify protected render operations:");
+		igt_subtest("regular-baseline-src-copy-readible")
+			test_render_baseline(i915);
+	}
 
 	igt_fixture {
 		close(i915);
-- 
2.25.1

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[igt-dev] [PATCH i-g-t 06/17] Add PXP attribute support in batchbuffer and buffer_ops libs

[Alan Previn]

Eventually when we get to testing PXP rendering capability,
we shall reuse lib's rendercopy feature. Rendercopy libraries
shall retrieve information about PXP-session-enablement and
which buffers are protected from these new flags.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 lib/intel_batchbuffer.c | 21 +++++++++++++++++++++
 lib/intel_batchbuffer.h | 28 ++++++++++++++++++++++++++++
 lib/intel_bufops.h      | 15 +++++++++++++++
 3 files changed, 64 insertions(+)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 0b2c5b21..23957109 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -2357,6 +2357,27 @@ uint64_t intel_bb_offset_reloc_to_object(struct intel_bb *ibb,
 				  delta, offset, presumed_offset);
 }
 
+/*
+ * @intel_bb_set_pxp:
+ * @ibb: pointer to intel_bb
+ * @new_state: enable or disable pxp session
+ * @apptype: pxp session input identifies what type of session to enable
+ * @appid: pxp session input provides which appid to use
+ *
+ * This function merely stores the pxp state and session information to
+ * be retrieved and programmed later by supporting libraries such as
+ * gen12_render_copy that must program the HW within the same dispatch
+ */
+void intel_bb_set_pxp(struct intel_bb *ibb, bool new_state,
+		      uint32_t apptype, uint32_t appid)
+{
+	igt_assert(ibb);
+
+	ibb->pxp.enabled = new_state;
+	ibb->pxp.apptype = new_state ? apptype : 0;
+	ibb->pxp.appid   = new_state ? appid : 0;
+}
+
 static void intel_bb_dump_execbuf(struct intel_bb *ibb,
 				  struct drm_i915_gem_execbuffer2 *execbuf)
 {
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 6f148713..389da7b2 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -438,6 +438,11 @@ typedef void (*igt_media_spinfunc_t)(int i915,
 
 igt_media_spinfunc_t igt_get_media_spinfunc(int devid);
 
+struct igt_pxp {
+	bool     enabled;
+	uint32_t apptype;
+	uint32_t appid;
+};
 
 /*
  * Batchbuffer without libdrm dependency
@@ -464,6 +469,7 @@ struct intel_bb {
 	bool supports_48b_address;
 	bool uses_full_ppgtt;
 
+	struct igt_pxp pxp;
 	uint32_t ctx;
 	uint32_t vm_id;
 
@@ -578,6 +584,27 @@ static inline void intel_bb_out(struct intel_bb *ibb, uint32_t dword)
 	igt_assert(intel_bb_offset(ibb) <= ibb->size);
 }
 
+void intel_bb_set_pxp(struct intel_bb *ibb, bool new_state,
+		      uint32_t apptype, uint32_t appid);
+
+static inline bool intel_bb_pxp_enabled(struct intel_bb *ibb)
+{
+	igt_assert(ibb);
+	return ibb->pxp.enabled;
+}
+
+static inline uint32_t intel_bb_pxp_apptype(struct intel_bb *ibb)
+{
+	igt_assert(ibb);
+	return ibb->pxp.apptype;
+}
+
+static inline uint32_t intel_bb_pxp_appid(struct intel_bb *ibb)
+{
+	igt_assert(ibb);
+	return ibb->pxp.appid;
+}
+
 struct drm_i915_gem_exec_object2 *
 intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
 		    uint64_t offset, uint64_t alignment, bool write);
@@ -691,3 +718,4 @@ typedef void (*igt_huc_copyfunc_t)(int fd,
 
 igt_huc_copyfunc_t	igt_get_huc_copyfunc(int devid);
 #endif
+
diff --git a/lib/intel_bufops.h b/lib/intel_bufops.h
index 9e57d53e..bffeb1b0 100644
--- a/lib/intel_bufops.h
+++ b/lib/intel_bufops.h
@@ -50,6 +50,9 @@ struct intel_buf {
 	uint32_t *ptr;
 	bool cpu_write;
 
+	/* Content Protection*/
+	bool is_protected;
+
 	/* For debugging purposes */
 	char name[INTEL_BUF_NAME_MAXSIZE + 1];
 };
@@ -155,6 +158,18 @@ struct intel_buf *intel_buf_create_using_handle_and_size(struct buf_ops *bops,
 							 int stride);
 void intel_buf_destroy(struct intel_buf *buf);
 
+static inline void intel_buf_set_pxp(struct intel_buf *buf, bool new_pxp_state)
+{
+	igt_assert(buf);
+	buf->is_protected = new_pxp_state;
+}
+
+static inline bool intel_buf_pxp(const struct intel_buf *buf)
+{
+	igt_assert(buf);
+	return buf->is_protected;
+}
+
 void *intel_buf_cpu_map(struct intel_buf *buf, bool write);
 void *intel_buf_device_map(struct intel_buf *buf, bool write);
 void intel_buf_unmap(struct intel_buf *buf);
-- 
2.25.1

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[igt-dev] [PATCH i-g-t 07/17] Add MI_SET_APPID instruction definition

[Alan Previn]

Add MI_SET_APPID instruction and param definitions

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 lib/intel_reg.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index ac1fc6cb..46b5da20 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2546,6 +2546,15 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define CTXT_PALETTE_SAVE_DISABLE	(1<<3)
 #define CTXT_PALETTE_RESTORE_DISABLE	(1<<2)
 
+#define MI_SET_APPID                    (0x0E << 23)
+#define APPID_CTXSAVE_INHIBIT           (1 << 8)
+#define APPID_CTXREST_INHIBIT           (1 << 9)
+#define DISPLAY_APPTYPE                 (0)
+#define TRANSCODE_APPTYPE               (1)
+#define APPTYPE(n)                      (n << 7)
+#define APPID(n)                        (n & 0x7f)
+
+
 /* Dword 0 */
 #define MI_VERTEX_BUFFER		(0x17<<23)
 #define MI_VERTEX_BUFFER_IDX(x)		(x<<20)
-- 
2.25.1

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[igt-dev] [PATCH i-g-t 08/17] Enable protected session cmd in gen12_render_copyfunc

[Alan Previn]

1. In _gen9_render_op, check if the incoming batchbuffer
   is marked with pxp enabled. If so, insert MI_SET_APPID
   along with PIPE_CONTROL instructions at the start and
   end of the rendering operation in the command buffer.

2. The two PIPE_CONTROLs will enable protected memory
   at the start of the batch and disabling protected
   memory at the end of it. These PIPE_CONTROLs require a
   Post-Sync operation with a write to memory for hardware
   to accept.

3. In order to satisfy #2, _gen9_render_op uses unused
   regions of the ibb buffer for the PIPE_CONTROL PostSync
   write to memory (no different from how other 3d states
   are being referenced).

4. _gen9_render_op shall check the incoming surface
   buffers for "is_protected" flag and if its set, it
   will mark the SURFACE_STATE's MOCS field accordingly.

NOTE: _gen9_render_op needs to program the HW to enable
the PXP session as part of the rendering batch buffer
because the HW requires that enabling/disabling protected
memory access must be programmed in pairs within the same
"dispatch of rendering commands" to HW.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 lib/rendercopy_gen9.c | 72 ++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 65 insertions(+), 7 deletions(-)

diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index eecf73d3..bfcf311b 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -19,7 +19,8 @@
 #include "intel_bufops.h"
 #include "intel_batchbuffer.h"
 #include "intel_io.h"
-#include "rendercopy.h"
+#include "igt.h"
+#include "i915/gem.h"
 #include "gen9_render.h"
 #include "intel_reg.h"
 #include "igt_aux.h"
@@ -152,6 +153,8 @@ gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst) {
 		ss->ss0.tiled_mode = 3;
 
 	ss->ss1.memory_object_control = I915_MOCS_PTE << 1;
+	if (intel_buf_pxp(buf))
+		ss->ss1.memory_object_control |= 1;
 
 	if (buf->tiling == I915_TILING_Yf)
 		ss->ss5.trmode = 1;
@@ -873,6 +876,53 @@ static void gen8_emit_primitive(struct intel_bb *ibb, uint32_t offset)
 	intel_bb_out(ibb, 0);	/* index buffer offset, ignored */
 }
 
+#define GFX_OP_PIPE_CONTROL    ((3 << 29) | (3 << 27) | (2 << 24))
+#define PIPE_CONTROL_CS_STALL	            (1 << 20)
+#define PIPE_CONTROL_RENDER_TARGET_FLUSH    (1 << 12)
+#define PIPE_CONTROL_FLUSH_ENABLE           (1 << 7)
+#define PIPE_CONTROL_DATA_CACHE_INVALIDATE  (1 << 5)
+#define PIPE_CONTROL_PROTECTEDPATH_DISABLE  (1 << 27)
+#define PIPE_CONTROL_PROTECTEDPATH_ENABLE   (1 << 22)
+#define PIPE_CONTROL_POST_SYNC_OP           (1 << 14)
+#define PIPE_CONTROL_POST_SYNC_OP_STORE_DW_IDX (1 << 21)
+#define PS_OP_TAG_START                     0x1234fed0
+#define PS_OP_TAG_END                       0x5678cbaf
+static void gen12_emit_pxp_state(struct intel_bb *ibb, bool enable,
+		 uint32_t pxp_write_op_offset)
+{
+	uint32_t pipe_ctl_flags;
+	uint32_t set_app_id, ps_op_id;
+
+	if (enable) {
+		pipe_ctl_flags = PIPE_CONTROL_FLUSH_ENABLE;
+		intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
+		intel_bb_out(ibb, pipe_ctl_flags);
+
+		set_app_id =  MI_SET_APPID |
+			      APPTYPE(intel_bb_pxp_apptype(ibb)) |
+			      APPID(intel_bb_pxp_appid(ibb));
+		intel_bb_out(ibb, set_app_id);
+
+		pipe_ctl_flags = PIPE_CONTROL_PROTECTEDPATH_ENABLE;
+		ps_op_id = PS_OP_TAG_START;
+	} else {
+		pipe_ctl_flags = PIPE_CONTROL_PROTECTEDPATH_DISABLE;
+		ps_op_id = PS_OP_TAG_END;
+	}
+
+	pipe_ctl_flags |= (PIPE_CONTROL_CS_STALL |
+			   PIPE_CONTROL_RENDER_TARGET_FLUSH |
+			   PIPE_CONTROL_DATA_CACHE_INVALIDATE |
+			   PIPE_CONTROL_POST_SYNC_OP);
+	intel_bb_out(ibb, GFX_OP_PIPE_CONTROL | 4);
+	intel_bb_out(ibb, pipe_ctl_flags);
+	intel_bb_emit_reloc(ibb, ibb->handle, 0, I915_GEM_DOMAIN_COMMAND,
+			    (enable ? pxp_write_op_offset : (pxp_write_op_offset+8)),
+			    ibb->batch_offset);
+	intel_bb_out(ibb, ps_op_id);
+	intel_bb_out(ibb, ps_op_id);
+}
+
 /* The general rule is if it's named gen6 it is directly copied from
  * gen6_render_copyfunc.
  *
@@ -922,6 +972,7 @@ void _gen9_render_op(struct intel_bb *ibb,
 	uint32_t vertex_buffer;
 	uint32_t aux_pgtable_state;
 	bool fast_clear = !src;
+	uint32_t pxp_scratch_offset;
 
 	if (!fast_clear)
 		igt_assert(src->bpp == dst->bpp);
@@ -950,8 +1001,12 @@ void _gen9_render_op(struct intel_bb *ibb,
 	aux_pgtable_state = gen12_create_aux_pgtable_state(ibb, aux_pgtable_buf);
 
 	/* TODO: there is other state which isn't setup */
+	pxp_scratch_offset = intel_bb_offset(ibb);
 	intel_bb_ptr_set(ibb, 0);
 
+	if (intel_bb_pxp_enabled(ibb))
+		gen12_emit_pxp_state(ibb, true, pxp_scratch_offset);
+
 	/* Start emitting the commands. The order roughly follows the mesa blorp
 	 * order */
 	intel_bb_out(ibb, G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D |
@@ -963,13 +1018,12 @@ void _gen9_render_op(struct intel_bb *ibb,
 		for (int i = 0; i < 4; i++) {
 			intel_bb_out(ibb, MI_STORE_DWORD_IMM);
 			intel_bb_emit_reloc(ibb, dst->handle,
-					    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-                                            dst->cc.offset + i*sizeof(float),
-					    dst->addr.offset);
+					I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+					dst->cc.offset + i*sizeof(float),
+					dst->addr.offset);
 			intel_bb_out(ibb, *(uint32_t*)&clear_color[i]);
-               }
-       }
-
+		}
+	}
 
 	gen8_emit_sip(ibb);
 
@@ -1023,10 +1077,14 @@ void _gen9_render_op(struct intel_bb *ibb,
 	gen8_emit_vf_topology(ibb);
 	gen8_emit_primitive(ibb, vertex_buffer);
 
+	if (intel_bb_pxp_enabled(ibb))
+		gen12_emit_pxp_state(ibb, false, pxp_scratch_offset);
+
 	intel_bb_emit_bbe(ibb);
 	intel_bb_exec(ibb, intel_bb_offset(ibb),
 		      I915_EXEC_RENDER | I915_EXEC_NO_RELOC, false);
 	dump_batch(ibb);
+
 	intel_bb_reset(ibb, false);
 }
 
-- 
2.25.1

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[igt-dev] [PATCH i-g-t 09/17] Add subtest to copy raw source to protected dest

[Alan Previn]

Add subtest to 3d-copy raw source buffer (with
known readible content) to a destination buffer
marked as protected with a protected session using
default session keys. The destination buffer is
verified to be different from the source (when
read via CPU) because its encrypted.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 tests/i915/gem_pxp.c | 55 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index b1415efc..5a29024a 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -376,7 +376,9 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected, uint32_t size
 #define TSTSURF_STRIDE      (TSTSURF_WIDTH*TSTSURF_BYTESPP)
 #define TSTSURF_SIZE        (TSTSURF_STRIDE*TSTSURF_HEIGHT)
 #define TSTSURF_FILLCOLOR1  0xfaceface
+#define TSTSURF_FILLCOLOR2  0xdeaddead
 #define TSTSURF_INITCOLOR1  0x12341234
+#define TSTSURF_INITCOLOR2  0x56785678
 
 static void test_render_baseline(int i915)
 {
@@ -422,6 +424,57 @@ static void test_render_baseline(int i915)
 	buf_ops_destroy(bops);
 }
 
+static void test_render_pxp_src_to_protdest(int i915)
+{
+	uint32_t ctx, srcbo, dstbo;
+	struct intel_buf *srcbuf, *dstbuf;
+	struct buf_ops *bops;
+	struct intel_bb *ibb;
+	uint32_t devid;
+	int ret;
+
+	devid = intel_get_drm_devid(i915);
+	igt_assert(devid);
+
+	bops = buf_ops_create(i915);
+	igt_assert(bops);
+
+	/*
+	 * Perform a protected render operation but only label
+	 * the dest as protected. After rendering, the content
+	 * should be encrypted
+	 */
+	ret = create_ctx_with_params(i915, true, true, true, false, &ctx);
+	igt_assert_eq(ret, 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
+	ibb = intel_bb_create_with_context(i915, ctx, 4096);
+	igt_assert(ibb);
+	intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, I915_PROTECTED_CONTENT_DEFAULT_SESSION);
+
+	dstbo = alloc_and_fill_dest_buff(i915, true, TSTSURF_SIZE, TSTSURF_INITCOLOR2);
+	dstbuf = intel_buf_create_using_handle(bops, dstbo, TSTSURF_WIDTH, TSTSURF_HEIGHT,
+						TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+	intel_buf_set_pxp(dstbuf, true);
+
+	srcbo = alloc_and_fill_dest_buff(i915, false, TSTSURF_SIZE, TSTSURF_FILLCOLOR2);
+	srcbuf = intel_buf_create_using_handle(bops, srcbo, TSTSURF_WIDTH, TSTSURF_HEIGHT,
+						TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+
+	gen12_render_copyfunc(ibb, srcbuf, 0, 0, TSTSURF_WIDTH, TSTSURF_HEIGHT, dstbuf, 0, 0);
+	gem_sync(i915, dstbo);
+
+	assert_bo_content_check(i915, dstbo, COMPARE_COLOR_UNREADIBLE,
+				TSTSURF_SIZE, TSTSURF_FILLCOLOR2);
+
+	intel_bb_destroy(ibb);
+	intel_buf_destroy(srcbuf);
+	gem_close(i915, srcbo);
+	intel_buf_destroy(dstbuf);
+	gem_close(i915, dstbo);
+	gem_context_destroy(i915, ctx);
+	buf_ops_destroy(bops);
+}
+
 igt_main
 {
 	int i915 = -1;
@@ -493,6 +546,8 @@ igt_main
 		igt_describe("Verify protected render operations:");
 		igt_subtest("regular-baseline-src-copy-readible")
 			test_render_baseline(i915);
+		igt_subtest("protected-raw-src-copy-not-readible")
+			test_render_pxp_src_to_protdest(i915);
 	}
 
 	igt_fixture {
-- 
2.25.1

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[igt-dev] [PATCH i-g-t 10/17] Add test where both src and dest are protected

[Alan Previn]

When both the source and destination surfaces are
protected, the destination pixel result of the 3d
copy operation would be the same as the source. By
appending this test case to the end of the prior
test (raw-src to protected-dest) and reusing the
previous' test destination as the current source,
we can prove that new-source was decrypted properly
as we would see the difference in results: repeating
the same render operation but with a src buffer
that is protected in this case yields matching
(but still encrypted) output rendered pixels.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 tests/i915/gem_pxp.c | 144 +++++++++++++++++++++++++++++++++++++++----
 1 file changed, 133 insertions(+), 11 deletions(-)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 5a29024a..2f2d2716 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -308,29 +308,51 @@ static void fill_bo_content(int i915, uint32_t bo, uint32_t size, uint32_t initc
 
 #define COMPARE_COLOR_READIBLE     1
 #define COMPARE_COLOR_UNREADIBLE   2
+#define COMPARE_BUFFER_READIBLE    3
+#define COMPARE_BUFFER_UNREADIBLE  4
+#define COPY_BUFFER                5
 #define COMPARE_N_PIXELS_VERBOSELY 0
 
-static void assert_bo_content_check(int i915, uint32_t bo, int compare_op,
-				    uint32_t size, uint32_t color)
+static void assert_bo_content_check(int i915, uint32_t bo, int compare_op, uint32_t size,
+				    uint32_t color, uint32_t *auxptr, int auxsize)
 {
-	uint32_t *ptr, *ptrtmp;
+	uint32_t *ptr, *ptrtmp, *auxtmp;
 	int loop = 0, num_matches = 0;
 	uint32_t value;
-	bool op_readible = (compare_op == COMPARE_COLOR_READIBLE);
+	bool op_readible = ((compare_op == COMPARE_COLOR_READIBLE) ||
+		 (compare_op == COMPARE_BUFFER_READIBLE));
+	bool chk_buff = ((compare_op == COMPARE_BUFFER_READIBLE) ||
+		 (compare_op == COMPARE_BUFFER_UNREADIBLE));
+	bool copy_buff = (compare_op == COPY_BUFFER);
 
 	ptr = gem_mmap__device_coherent(i915, bo, 0, size, PROT_READ);
 	ptrtmp = ptr;
 
+	if (chk_buff || copy_buff) {
+		if (auxsize < size)
+			auxptr = NULL;
+		igt_assert(auxptr);
+		auxtmp = auxptr;
+	}
+
 	if (COMPARE_N_PIXELS_VERBOSELY) {
 		igt_info("--------->>>\n");
 		while (loop < COMPARE_N_PIXELS_VERBOSELY && loop < (size/4)) {
 			value = *ptrtmp;
-			igt_info("Color read = 0x%08x ", value);
-			igt_info("expected %c= 0x%08x)\n", op_readible?'=':'!', color);
+			if (chk_buff)
+				color = *auxtmp;
+			if (copy_buff)
+				igt_info("Color copy = 0x%08x\n", value);
+			else {
+				igt_info("Color read = 0x%08x ", value);
+				igt_info("expected %c= 0x%08x)\n", op_readible?'=':'!', color);
+			}
+			++auxtmp;
 			++ptrtmp;
 			++loop;
 		}
 		igt_info("<<<---------\n");
+		auxtmp = auxptr;
 		ptrtmp = ptr;
 		loop = 0;
 	}
@@ -338,8 +360,25 @@ static void assert_bo_content_check(int i915, uint32_t bo, int compare_op,
 	/* count all pixels for matches */
 	while (loop++ < (size/4)) {
 		value = *ptrtmp;
-		if (value == color)
-			++num_matches;
+		switch (compare_op) {
+		case COMPARE_COLOR_READIBLE:
+		case COMPARE_COLOR_UNREADIBLE:
+			if (value == color)
+				++num_matches;
+			break;
+		case COMPARE_BUFFER_READIBLE:
+		case COMPARE_BUFFER_UNREADIBLE:
+			if (value == (*auxtmp))
+				++num_matches;
+			++auxtmp;
+			break;
+		case COPY_BUFFER:
+			*auxtmp = value;
+			++auxtmp;
+			break;
+		default:
+			break;
+		}
 		++ptrtmp;
 	}
 
@@ -361,7 +400,8 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected, uint32_t size
 	igt_assert_eq(ret, 0);
 	igt_assert(bo);
 	fill_bo_content(i915, bo, size, init_color);
-	assert_bo_content_check(i915, bo, COMPARE_COLOR_READIBLE, size, init_color);
+	assert_bo_content_check(i915, bo, COMPARE_COLOR_READIBLE,
+				size, init_color, NULL, 0);
 
 	return bo;
 }
@@ -379,6 +419,7 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected, uint32_t size
 #define TSTSURF_FILLCOLOR2  0xdeaddead
 #define TSTSURF_INITCOLOR1  0x12341234
 #define TSTSURF_INITCOLOR2  0x56785678
+#define TSTSURF_INITCOLOR3  0xabcdabcd
 
 static void test_render_baseline(int i915)
 {
@@ -413,7 +454,7 @@ static void test_render_baseline(int i915)
 	gem_sync(i915, dstbo);
 
 	assert_bo_content_check(i915, dstbo, COMPARE_COLOR_READIBLE,
-				TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
+				TSTSURF_SIZE, TSTSURF_FILLCOLOR1, NULL, 0);
 
 	intel_bb_destroy(ibb);
 	intel_buf_destroy(srcbuf);
@@ -464,13 +505,92 @@ static void test_render_pxp_src_to_protdest(int i915)
 	gem_sync(i915, dstbo);
 
 	assert_bo_content_check(i915, dstbo, COMPARE_COLOR_UNREADIBLE,
-				TSTSURF_SIZE, TSTSURF_FILLCOLOR2);
+				TSTSURF_SIZE, TSTSURF_FILLCOLOR2, NULL, 0);
+
+	intel_bb_destroy(ibb);
+	intel_buf_destroy(srcbuf);
+	gem_close(i915, srcbo);
+	intel_buf_destroy(dstbuf);
+	gem_close(i915, dstbo);
+	gem_context_destroy(i915, ctx);
+	buf_ops_destroy(bops);
+}
+
+static void test_render_pxp_protsrc_to_protdest(int i915)
+{
+	uint32_t ctx, srcbo, dstbo, dstbo2;
+	struct intel_buf *srcbuf, *dstbuf, *dstbuf2;
+	struct buf_ops *bops;
+	struct intel_bb *ibb;
+	uint32_t devid;
+	int ret;
+	uint32_t encrypted[TSTSURF_SIZE/TSTSURF_BYTESPP];
+
+	devid = intel_get_drm_devid(i915);
+	igt_assert(devid);
+
+	bops = buf_ops_create(i915);
+	igt_assert(bops);
+
+	/*
+	 * Perform a protected render operation but only label
+	 * the dest as protected. After rendering, the content
+	 * should be encrypted
+	 */
+	ret = create_ctx_with_params(i915, true, true, true, false, &ctx);
+	igt_assert_eq(ret, 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
+	ibb = intel_bb_create_with_context(i915, ctx, 4096);
+	igt_assert(ibb);
+	intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, I915_PROTECTED_CONTENT_DEFAULT_SESSION);
+
+	dstbo = alloc_and_fill_dest_buff(i915, true, TSTSURF_SIZE, TSTSURF_INITCOLOR2);
+	dstbuf = intel_buf_create_using_handle(bops, dstbo, TSTSURF_WIDTH, TSTSURF_HEIGHT,
+						TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+	intel_buf_set_pxp(dstbuf, true);
+
+	srcbo = alloc_and_fill_dest_buff(i915, false, TSTSURF_SIZE, TSTSURF_FILLCOLOR2);
+	srcbuf = intel_buf_create_using_handle(bops, srcbo, TSTSURF_WIDTH, TSTSURF_HEIGHT,
+						TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+
+	gen12_render_copyfunc(ibb, srcbuf, 0, 0, TSTSURF_WIDTH, TSTSURF_HEIGHT, dstbuf, 0, 0);
+	gem_sync(i915, dstbo);
+
+	assert_bo_content_check(i915, dstbo, COMPARE_COLOR_UNREADIBLE,
+				TSTSURF_SIZE, TSTSURF_FILLCOLOR2, NULL, 0);
+
+	/*
+	 * Reuse prior dst as the new-src and create dst2 as the new-dest.
+	 * Take a copy of encrypted content from new-src for comparison after render
+	 * operation. After the rendering, we should find no difference in content
+	 * since both new-src and new-dest are labelled as encrypted. HW should read
+	 * and decrypt new-src, perform the render and re-encrypt when going into
+	 * new-dest
+	 */
+	assert_bo_content_check(i915, dstbo, COPY_BUFFER,
+				TSTSURF_SIZE, 0, encrypted, TSTSURF_SIZE);
+
+	dstbo2 = alloc_and_fill_dest_buff(i915, false, TSTSURF_SIZE, TSTSURF_INITCOLOR3);
+	dstbuf2 = intel_buf_create_using_handle(bops, dstbo2, TSTSURF_WIDTH, TSTSURF_HEIGHT,
+						TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+	intel_buf_set_pxp(dstbuf2, true);
+	intel_buf_set_pxp(dstbuf, true);/*this time, src is protected*/
+
+	intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, I915_PROTECTED_CONTENT_DEFAULT_SESSION);
+
+	gen12_render_copyfunc(ibb, dstbuf, 0, 0, TSTSURF_WIDTH, TSTSURF_HEIGHT, dstbuf2, 0, 0);
+	gem_sync(i915, dstbo2);
+
+	assert_bo_content_check(i915, dstbo2, COMPARE_BUFFER_READIBLE,
+				TSTSURF_SIZE, 0, encrypted, TSTSURF_SIZE);
 
 	intel_bb_destroy(ibb);
 	intel_buf_destroy(srcbuf);
 	gem_close(i915, srcbo);
 	intel_buf_destroy(dstbuf);
 	gem_close(i915, dstbo);
+	intel_buf_destroy(dstbuf2);
+	gem_close(i915, dstbo2);
 	gem_context_destroy(i915, ctx);
 	buf_ops_destroy(bops);
 }
@@ -548,6 +668,8 @@ igt_main
 			test_render_baseline(i915);
 		igt_subtest("protected-raw-src-copy-not-readible")
 			test_render_pxp_src_to_protdest(i915);
+		igt_subtest("protected-encrypted-src-copy-not-readible")
+			test_render_pxp_protsrc_to_protdest(i915);
 	}
 
 	igt_fixture {
-- 
2.25.1

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[igt-dev] [PATCH i-g-t 11/17] Verify PXP teardown occurred through suspend-resume

[Alan Previn]

During a suspend-resume cycle, the hardware and driver shall
ensure the PXP session and keys are torn down and re-
established. Verify that key change did occur by repeating
the 3d rendercopy operation before and after a suspend cycle
and ensuring that the encrypted output is different.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 tests/i915/gem_pxp.c | 67 +++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 66 insertions(+), 1 deletion(-)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 2f2d2716..10134604 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -9,6 +9,12 @@
 IGT_TEST_DESCRIPTION("Test PXP that manages protected content through arbitrated HW-PXP-session");
 /* Note: PXP = "Protected Xe Path" */
 
+/* Struct and definitions for power management. */
+struct powermgt_data {
+	int debugfsdir;
+	bool has_runtime_pm;
+};
+
 static bool is_pxp_hw_supported(int i915)
 {
 	uint32_t devid = intel_get_drm_devid(i915);
@@ -465,7 +471,7 @@ static void test_render_baseline(int i915)
 	buf_ops_destroy(bops);
 }
 
-static void test_render_pxp_src_to_protdest(int i915)
+static void __test_render_pxp_src_to_protdest(int i915, uint32_t *outpixels, int outsize)
 {
 	uint32_t ctx, srcbo, dstbo;
 	struct intel_buf *srcbuf, *dstbuf;
@@ -507,6 +513,10 @@ static void test_render_pxp_src_to_protdest(int i915)
 	assert_bo_content_check(i915, dstbo, COMPARE_COLOR_UNREADIBLE,
 				TSTSURF_SIZE, TSTSURF_FILLCOLOR2, NULL, 0);
 
+	if (outpixels)
+		assert_bo_content_check(i915, dstbo, COPY_BUFFER,
+					TSTSURF_SIZE, 0, outpixels, outsize);
+
 	intel_bb_destroy(ibb);
 	intel_buf_destroy(srcbuf);
 	gem_close(i915, srcbo);
@@ -516,6 +526,11 @@ static void test_render_pxp_src_to_protdest(int i915)
 	buf_ops_destroy(bops);
 }
 
+static void test_render_pxp_src_to_protdest(int i915)
+{
+	__test_render_pxp_src_to_protdest(i915, NULL, 0);
+}
+
 static void test_render_pxp_protsrc_to_protdest(int i915)
 {
 	uint32_t ctx, srcbo, dstbo, dstbo2;
@@ -595,10 +610,47 @@ static void test_render_pxp_protsrc_to_protdest(int i915)
 	buf_ops_destroy(bops);
 }
 
+static void init_powermgt_resources(int i915, struct powermgt_data *pm)
+{
+	pm->debugfsdir = igt_debugfs_dir(i915);
+	igt_require(pm->debugfsdir != -1);
+	pm->has_runtime_pm = igt_setup_runtime_pm(i915);
+	igt_require(pm->has_runtime_pm);
+}
+
+static void trigger_powermgt_suspend_cycle(int i915,
+	struct powermgt_data *pm)
+{
+	igt_pm_enable_sata_link_power_management();
+	igt_system_suspend_autoresume(SUSPEND_STATE_MEM, SUSPEND_TEST_DEVICES);
+	igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_SUSPENDED);
+}
+
+static void test_pxp_pwrcycle_teardown_keychange(int i915, struct powermgt_data *pm)
+{
+	uint32_t encrypted_pixels_b4[TSTSURF_SIZE/TSTSURF_BYTESPP];
+	uint32_t encrypted_pixels_aft[TSTSURF_SIZE/TSTSURF_BYTESPP];
+	int matched_after_keychange = 0, loop = 0;
+
+	__test_render_pxp_src_to_protdest(i915, encrypted_pixels_b4, TSTSURF_SIZE);
+
+	trigger_powermgt_suspend_cycle(i915, pm);
+
+	__test_render_pxp_src_to_protdest(i915, encrypted_pixels_aft, TSTSURF_SIZE);
+
+	while (loop < (TSTSURF_SIZE/TSTSURF_BYTESPP)) {
+		if (encrypted_pixels_b4[loop] == encrypted_pixels_aft[loop])
+			++matched_after_keychange;
+		++loop;
+	}
+	igt_assert_eq(matched_after_keychange, 0);
+}
+
 igt_main
 {
 	int i915 = -1;
 	bool pxp_supported = false;
+	struct powermgt_data pm = {0};
 	igt_render_copyfunc_t rendercopy = NULL;
 	uint32_t devid = 0;
 
@@ -671,6 +723,19 @@ igt_main
 		igt_subtest("protected-encrypted-src-copy-not-readible")
 			test_render_pxp_protsrc_to_protdest(i915);
 	}
+	igt_subtest_group {
+		igt_fixture {
+			igt_require(pxp_supported);
+			devid = intel_get_drm_devid(i915);
+			igt_assert(devid);
+			rendercopy = igt_get_render_copyfunc(devid);
+			igt_require(rendercopy);
+			init_powermgt_resources(i915, &pm);
+		}
+		igt_describe("Verify suspend-resume teardown management:");
+		igt_subtest("verify-pxp-key-change-after-suspend-resume")
+			test_pxp_pwrcycle_teardown_keychange(i915, &pm);
+	}
 
 	igt_fixture {
 		close(i915);
-- 
2.25.1

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[igt-dev] [PATCH i-g-t 12/17] Verify execbuf fails with stale PXP context after teardown

[Alan Previn]

Add a subtest to verify that reusing a stale protected context
in a gem_execbuff after a teardown (triggered by suspend-resume
cycle) shall fail with -EACCES error.

NOTE: The end-to-end architecture requirement includes that
any break in the links of the PXP sessions needs to trigger a
full teardown and the application needs to be made aware of that
allowing it to re-establish the end-to-end pipeline of buffers,
contexts and renders again if it chooses to. This stricter
behavior targets only contexts created with PXP enabled.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 lib/intel_batchbuffer.c |   2 +-
 lib/intel_batchbuffer.h |   3 +
 tests/i915/gem_pxp.c    | 135 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 139 insertions(+), 1 deletion(-)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 23957109..e16ab056 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -2536,7 +2536,7 @@ static void update_offsets(struct intel_bb *ibb,
  * Note: In this step execobj for bb is allocated and inserted to the objects
  * array.
 */
-static int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
+int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 			   uint64_t flags, bool sync)
 {
 	struct drm_i915_gem_execbuffer2 execbuf;
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 389da7b2..b16ae00f 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -664,6 +664,9 @@ uint64_t intel_bb_offset_reloc_to_object(struct intel_bb *ibb,
 					 uint32_t offset,
 					 uint64_t presumed_offset);
 
+int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
+			uint64_t flags, bool sync);
+
 void intel_bb_dump_cache(struct intel_bb *ibb);
 
 void intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 10134604..f1ef0a24 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -15,6 +15,14 @@ struct powermgt_data {
 	bool has_runtime_pm;
 };
 
+struct simple_exec_assets {
+	uint32_t ctx;
+	uint32_t fencebo;
+	struct intel_buf *fencebuf;
+	struct buf_ops *bops;
+	struct intel_bb *ibb;
+};
+
 static bool is_pxp_hw_supported(int i915)
 {
 	uint32_t devid = intel_get_drm_devid(i915);
@@ -646,6 +654,131 @@ static void test_pxp_pwrcycle_teardown_keychange(int i915, struct powermgt_data
 	igt_assert_eq(matched_after_keychange, 0);
 }
 
+#define GFX_OP_PIPE_CONTROL    ((3 << 29) | (3 << 27) | (2 << 24))
+#define PIPE_CONTROL_CS_STALL	            (1 << 20)
+#define PIPE_CONTROL_RENDER_TARGET_FLUSH    (1 << 12)
+#define PIPE_CONTROL_FLUSH_ENABLE           (1 << 7)
+#define PIPE_CONTROL_DATA_CACHE_INVALIDATE  (1 << 5)
+#define PIPE_CONTROL_PROTECTEDPATH_DISABLE  (1 << 27)
+#define PIPE_CONTROL_PROTECTEDPATH_ENABLE   (1 << 22)
+#define PIPE_CONTROL_POST_SYNC_OP           (1 << 14)
+#define PIPE_CONTROL_POST_SYNC_OP_STORE_DW_IDX (1 << 21)
+#define PS_OP_TAG_BEFORE                    0x1234fed0
+#define PS_OP_TAG_AFTER                     0x5678cbaf
+
+static void emit_pipectrl(struct intel_bb *ibb, struct intel_buf *fenceb, bool before)
+{
+	uint32_t pipe_ctl_flags = 0;
+	uint32_t ps_op_id;
+
+	intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
+	intel_bb_out(ibb, pipe_ctl_flags);
+
+	if (before)
+		ps_op_id = PS_OP_TAG_BEFORE;
+	else
+		ps_op_id = PS_OP_TAG_AFTER;
+
+	pipe_ctl_flags = (PIPE_CONTROL_FLUSH_ENABLE |
+			  PIPE_CONTROL_CS_STALL |
+			  PIPE_CONTROL_POST_SYNC_OP);
+	intel_bb_out(ibb, GFX_OP_PIPE_CONTROL | 4);
+	intel_bb_out(ibb, pipe_ctl_flags);
+	intel_bb_emit_reloc(ibb, fenceb->handle, 0, I915_GEM_DOMAIN_COMMAND, (before?0:8),
+			    fenceb->addr.offset);
+	intel_bb_out(ibb, ps_op_id);
+	intel_bb_out(ibb, ps_op_id);
+	intel_bb_out(ibb, MI_NOOP);
+	intel_bb_out(ibb, MI_NOOP);
+}
+
+static void assert_pipectl_storedw_done(int i915, uint32_t bo)
+{
+	uint32_t *ptr;
+	uint32_t success_mask = 0x0;
+
+	ptr = gem_mmap__device_coherent(i915, bo, 0, 4096, PROT_READ);
+
+	if (ptr[0] == PS_OP_TAG_BEFORE && ptr[1] == PS_OP_TAG_BEFORE)
+		success_mask |= 0x1;
+
+	igt_assert_eq(success_mask, 0x1);
+	igt_assert(gem_munmap(ptr, 4096) == 0);
+}
+
+static int gem_execbuf_flush_store_dw(int i915, struct intel_bb *ibb, uint32_t ctx,
+				      struct intel_buf *fence)
+{
+	int ret;
+
+	intel_bb_ptr_set(ibb, 0);
+	intel_bb_add_intel_buf(ibb, fence, true);
+	emit_pipectrl(ibb, fence, true);
+	intel_bb_emit_bbe(ibb);
+	ret = __intel_bb_exec(ibb, intel_bb_offset(ibb),
+				  I915_EXEC_RENDER | I915_EXEC_NO_RELOC, false);
+	if (ret == 0) {
+		gem_sync(ibb->i915, fence->handle);
+		assert_pipectl_storedw_done(i915, fence->handle);
+	}
+	return ret;
+}
+
+static void prepare_exec_assets(int i915, struct simple_exec_assets *data, bool ctx_pxp,
+				bool buf_pxp)
+{
+	int ret;
+
+	if (ctx_pxp)
+		ret = create_ctx_with_params(i915, true, true, true, false, &(data->ctx));
+	else
+		ret = create_ctx_with_params(i915, false, false, false, false, &(data->ctx));
+	igt_assert_eq(ret, 0);
+	igt_assert_eq(get_ctx_protected_param(i915, data->ctx), ctx_pxp);
+	data->ibb = intel_bb_create_with_context(i915, data->ctx, 4096);
+	igt_assert(data->ibb);
+
+	data->fencebo = alloc_and_fill_dest_buff(i915, buf_pxp, 4096, 0);
+
+	data->bops = buf_ops_create(i915);
+	igt_assert(data->bops);
+
+	data->fencebuf = intel_buf_create_using_handle(data->bops, data->fencebo, 256, 4,
+						       32, 0, I915_TILING_NONE, 0);
+	intel_bb_add_intel_buf(data->ibb, data->fencebuf, true);
+}
+
+static void free_exec_assets(int i915, struct simple_exec_assets *data)
+{
+	intel_bb_destroy(data->ibb);
+	gem_close(i915, data->fencebo);
+	intel_buf_destroy(data->fencebuf);
+	gem_context_destroy(i915, data->ctx);
+	buf_ops_destroy(data->bops);
+}
+
+static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_data *pm)
+{
+	int ret;
+	struct simple_exec_assets data = {0};
+
+	/*
+	 * Use normal buffers for testing for invalidation
+	 * of protected contexts to ensure kernel is catching
+	 * the invalidated context (not buffer)
+	 */
+	prepare_exec_assets(i915, &data, true, false);
+	ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf);
+	igt_assert(ret == 0);
+
+	trigger_powermgt_suspend_cycle(i915, pm);
+
+	ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf);
+	igt_assert_f((ret == -EACCES), "Executing stale pxp context didn't fail with -EACCES\n");
+
+	free_exec_assets(i915, &data);
+}
+
 igt_main
 {
 	int i915 = -1;
@@ -735,6 +868,8 @@ igt_main
 		igt_describe("Verify suspend-resume teardown management:");
 		igt_subtest("verify-pxp-key-change-after-suspend-resume")
 			test_pxp_pwrcycle_teardown_keychange(i915, &pm);
+		igt_subtest("verify-pxp-execution-behavior-after-suspend-resume")
+			test_pxp_pwrcycle_staleasset_execution(i915, &pm);
 	}
 
 	igt_fixture {
-- 
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[igt-dev] [PATCH i-g-t 13/17] Verify execbuf fails with stale PXP buffer after teardown

[Alan Previn]

Add a check to verify that reusing a stale protected buffer
in a gem_execbuff (with a protected context) after a teardown
(triggered by suspend-resume cycle) shall fail with -ENOEXEC error.
Reuse the existing subtest function to with separate assets
to minimize the number of suspend-resume cycles we take.

NOTE: The end-to-end architecture requirement includes that
any break in the links of the PXP sessions needs to trigger a
full teardown and the application needs to be made aware of that
allowing it to re-establish the end-to-end pipeline of buffers,
contexts and renders again if it chooses to. This stricter
behavior targets only contexts created with PXP enabled.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 tests/i915/gem_pxp.c | 34 ++++++++++++++++++++++++++++------
 1 file changed, 28 insertions(+), 6 deletions(-)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index f1ef0a24..b4f369ae 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -760,23 +760,45 @@ static void free_exec_assets(int i915, struct simple_exec_assets *data)
 static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_data *pm)
 {
 	int ret;
-	struct simple_exec_assets data = {0};
+	struct simple_exec_assets data[2] = {{0}, {0}};
+	uint32_t ctx2;
+	struct intel_bb *ibb2;
 
 	/*
-	 * Use normal buffers for testing for invalidation
+	 * For data[0]: Use normal buffers for testing for invalidation
 	 * of protected contexts to ensure kernel is catching
 	 * the invalidated context (not buffer)
 	 */
-	prepare_exec_assets(i915, &data, true, false);
-	ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf);
+	prepare_exec_assets(i915, &data[0], true, false);
+	ret = gem_execbuf_flush_store_dw(i915, data[0].ibb, data[0].ctx, data[0].fencebuf);
+	igt_assert(ret == 0);
+
+	prepare_exec_assets(i915, &data[1], true, true);
+	ret = gem_execbuf_flush_store_dw(i915, data[1].ibb, data[1].ctx, data[1].fencebuf);
 	igt_assert(ret == 0);
 
 	trigger_powermgt_suspend_cycle(i915, pm);
 
-	ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf);
+	ret = gem_execbuf_flush_store_dw(i915, data[0].ibb, data[0].ctx, data[0].fencebuf);
 	igt_assert_f((ret == -EACCES), "Executing stale pxp context didn't fail with -EACCES\n");
 
-	free_exec_assets(i915, &data);
+	/*
+	 * For data[1]: after teardown, alloc new assets for context but
+	 * reuse the bo to ensure the kernel is catching the
+	 * invalidated bo (not context)
+	 */
+	ret = create_ctx_with_params(i915, true, true, true, false, &ctx2);
+	igt_assert_eq(ret, 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx2), 1);
+	ibb2 = intel_bb_create_with_context(i915, ctx2, 4096);
+	igt_assert(ibb2);
+	intel_bb_detach_intel_buf(data[1].ibb, data[1].fencebuf);
+	intel_bb_add_intel_buf(ibb2, data[1].fencebuf, true);
+	ret = gem_execbuf_flush_store_dw(i915, ibb2, ctx2, data[1].fencebuf);
+	igt_assert_f((ret == -ENOEXEC), "Executing stale pxp buffer didn't fail with -ENOEXEC\n");
+
+	free_exec_assets(i915, &data[0]);
+	free_exec_assets(i915, &data[1]);
 }
 
 igt_main
-- 
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[igt-dev] [PATCH i-g-t 14/17] Verify execbuf ok with stale prot-buff and regular context

[Alan Previn]

Add a check to verify that reusing a stale protected
buffer in a gem_execbuff call, but using a regular (not-
protcted) context will succeed despite after a teardown
(triggered by suspend-resume cycle).

This ensures that user space applications that choose
not to opt-in for strict PXP teardown awareness (by
using a regular context) won't suffer gem_execbuff
failures if a protected buffer was among the assets
used in any of its rendering operations.

Reuse the existing subtest to minimize the number
of suspend resume cycles we take.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 tests/i915/gem_pxp.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index b4f369ae..e3c21c70 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -760,7 +760,7 @@ static void free_exec_assets(int i915, struct simple_exec_assets *data)
 static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_data *pm)
 {
 	int ret;
-	struct simple_exec_assets data[2] = {{0}, {0}};
+	struct simple_exec_assets data[3] = {{0}, {0}, {0}};
 	uint32_t ctx2;
 	struct intel_bb *ibb2;
 
@@ -777,6 +777,15 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
 	ret = gem_execbuf_flush_store_dw(i915, data[1].ibb, data[1].ctx, data[1].fencebuf);
 	igt_assert(ret == 0);
 
+	/*
+	 * For data[2]: Use non-pxp contexts but with protected buffers
+	 * to verify the "pxp-execution-opt-in" expectation where
+	 * execution will run without error (not buffer)
+	 */
+	prepare_exec_assets(i915, &data[2], false, true);
+	ret = gem_execbuf_flush_store_dw(i915, data[2].ibb, data[2].ctx, data[2].fencebuf);
+	igt_assert(ret == 0);
+
 	trigger_powermgt_suspend_cycle(i915, pm);
 
 	ret = gem_execbuf_flush_store_dw(i915, data[0].ibb, data[0].ctx, data[0].fencebuf);
@@ -797,8 +806,12 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
 	ret = gem_execbuf_flush_store_dw(i915, ibb2, ctx2, data[1].fencebuf);
 	igt_assert_f((ret == -ENOEXEC), "Executing stale pxp buffer didn't fail with -ENOEXEC\n");
 
+	ret = gem_execbuf_flush_store_dw(i915, data[2].ibb, data[2].ctx, data[2].fencebuf);
+	igt_assert_f((ret == 0), "Opt-out-execution with stale pxp buffer didn't succeed\n");
+
 	free_exec_assets(i915, &data[0]);
 	free_exec_assets(i915, &data[1]);
+	free_exec_assets(i915, &data[2]);
 }
 
 igt_main
-- 
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[igt-dev] [PATCH i-g-t 15/17] Ensure RESET_STATS reports invalidated protected context

[Alan Previn]

When protected contexts are created but get invalidated
due to PXP session teardown (such as after a suspend-resume
cycle), RESET_STATS ioctl for said context will report it
as I915_CONTEXT_INVALIDATED.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 tests/i915/gem_pxp.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index e3c21c70..69a3143a 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -757,6 +757,22 @@ static void free_exec_assets(int i915, struct simple_exec_assets *data)
 	buf_ops_destroy(data->bops);
 }
 
+static bool is_context_valid(int i915, uint32_t ctx)
+{
+	struct drm_i915_reset_stats rs;
+	int ret;
+
+	memset(&rs, 0, sizeof(rs));
+	rs.ctx_id = ctx;
+	ret = drmIoctl(i915, DRM_IOCTL_I915_GET_RESET_STATS, &rs);
+	igt_assert(ret == 0);
+
+	if (rs.flags & I915_CONTEXT_INVALIDATED)
+		return false;
+
+	return true;
+}
+
 static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_data *pm)
 {
 	int ret;
@@ -788,6 +804,8 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
 
 	trigger_powermgt_suspend_cycle(i915, pm);
 
+	igt_assert_f(!is_context_valid(i915, data[0].ctx),
+				       "RESET_STATS missed INVAL bit on stale pxp context\n");
 	ret = gem_execbuf_flush_store_dw(i915, data[0].ibb, data[0].ctx, data[0].fencebuf);
 	igt_assert_f((ret == -EACCES), "Executing stale pxp context didn't fail with -EACCES\n");
 
@@ -796,6 +814,8 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
 	 * reuse the bo to ensure the kernel is catching the
 	 * invalidated bo (not context)
 	 */
+	igt_assert_f(!is_context_valid(i915, data[1].ctx),
+				       "RESET_STATS missed INVAL bit on stale pxp context\n");
 	ret = create_ctx_with_params(i915, true, true, true, false, &ctx2);
 	igt_assert_eq(ret, 0);
 	igt_assert_eq(get_ctx_protected_param(i915, ctx2), 1);
@@ -806,6 +826,8 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
 	ret = gem_execbuf_flush_store_dw(i915, ibb2, ctx2, data[1].fencebuf);
 	igt_assert_f((ret == -ENOEXEC), "Executing stale pxp buffer didn't fail with -ENOEXEC\n");
 
+	igt_assert_f(is_context_valid(i915, data[2].ctx),
+				       "RESET_STATS false-hit on opt-out context\n");
 	ret = gem_execbuf_flush_store_dw(i915, data[2].ibb, data[2].ctx, data[2].fencebuf);
 	igt_assert_f((ret == 0), "Opt-out-execution with stale pxp buffer didn't succeed\n");
 
-- 
2.25.1

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[igt-dev] [PATCH i-g-t 16/17] Verify protected surfaces are dma buffer sharable

[Alan Previn]

Verify we can export a protected surface from
protected context A into protected context B (with
different client driver handles) and protected
rendering is successful even after prior file
handle is closed (i.e. pxp specific refcounting
works).

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 tests/i915/gem_pxp.c | 103 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 103 insertions(+)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 69a3143a..179fb742 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -3,6 +3,7 @@
  * Copyright © 2021 Intel Corporation
  */
 
+#include <fcntl.h>
 #include "igt.h"
 #include "i915/gem.h"
 
@@ -618,6 +619,106 @@ static void test_render_pxp_protsrc_to_protdest(int i915)
 	buf_ops_destroy(bops);
 }
 
+static int export_handle(int fd, uint32_t handle, int *outfd)
+{
+	struct drm_prime_handle args;
+	int ret;
+
+	args.handle = handle;
+	args.flags = DRM_CLOEXEC;
+	args.fd = -1;
+
+	ret = drmIoctl(fd, DRM_IOCTL_PRIME_HANDLE_TO_FD, &args);
+	if (ret)
+		ret = errno;
+	*outfd = args.fd;
+
+	return ret;
+}
+
+static void test_pxp_dmabuffshare_refcnt(void)
+{
+	uint32_t ctx[2], sbo[2], dbo[2];
+	struct intel_buf *sbuf[2], *dbuf[2];
+	struct buf_ops *bops[2];
+	struct intel_bb *ibb[2];
+	int fd[2], dmabuf_fd = 0, ret, n, num_matches = 0;
+	uint32_t encrypted[2][TSTSURF_SIZE/TSTSURF_BYTESPP];
+
+	/* First, create the client driver handles and
+	 * protected dest buffer (is exported via dma-buff
+	 * from first handle and imported to the second).
+	 */
+	for (n = 0; n < 2; ++n) {
+		fd[n] = drm_open_driver(DRIVER_INTEL);
+		igt_require(fd[n]);
+		if (n == 0) {
+			dbo[0] = alloc_and_fill_dest_buff(fd[0], true, TSTSURF_SIZE,
+							  TSTSURF_INITCOLOR1);
+		} else {
+			ret = export_handle(fd[0], dbo[0], &dmabuf_fd);
+			igt_assert(ret == 0);
+			dbo[1] = prime_fd_to_handle(fd[1], dmabuf_fd);
+			igt_assert(dbo[1]);
+		}
+	}
+	/* Repeat twice: Create a full set of assets to perform
+	 * a protected 3D session but using the same dest buffer
+	 * from above.
+	 */
+	for (n = 0; n < 2; ++n) {
+		ret = create_ctx_with_params(fd[n], true, true, true, false, &ctx[n]);
+		igt_assert_eq(ret, 0);
+		igt_assert_eq(get_ctx_protected_param(fd[n], ctx[n]), 1);
+		ibb[n] = intel_bb_create_with_context(fd[n], ctx[n], 4096);
+		intel_bb_set_pxp(ibb[n], true, DISPLAY_APPTYPE,
+				 I915_PROTECTED_CONTENT_DEFAULT_SESSION);
+
+		bops[n] = buf_ops_create(fd[n]);
+		if (n == 1)
+			fill_bo_content(fd[1], dbo[1], TSTSURF_SIZE, TSTSURF_INITCOLOR2);
+
+		dbuf[n] = intel_buf_create_using_handle(bops[n], dbo[n], TSTSURF_WIDTH,
+							TSTSURF_HEIGHT,	TSTSURF_BYTESPP*8, 0,
+							I915_TILING_NONE, 0);
+		intel_buf_set_pxp(dbuf[n], true);
+
+		sbo[n] = alloc_and_fill_dest_buff(fd[n], false, TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
+		sbuf[n] = intel_buf_create_using_handle(bops[n], sbo[n], TSTSURF_WIDTH,
+							TSTSURF_HEIGHT, TSTSURF_BYTESPP*8, 0,
+							I915_TILING_NONE, 0);
+
+		gen12_render_copyfunc(ibb[n], sbuf[n], 0, 0, TSTSURF_WIDTH, TSTSURF_HEIGHT,
+				      dbuf[n], 0, 0);
+		gem_sync(fd[n], dbo[n]);
+
+		assert_bo_content_check(fd[n], dbo[n], COMPARE_COLOR_UNREADIBLE, TSTSURF_SIZE,
+					TSTSURF_FILLCOLOR1, NULL, 0);
+		assert_bo_content_check(fd[n], dbo[n], COPY_BUFFER, TSTSURF_SIZE, 0, encrypted[n],
+					TSTSURF_SIZE);
+
+		/* free up all assets except the dest buffer to
+		 * verify dma buff refcounting is performed on
+		 * the protected dest buffer on the 2nd loop with
+		 * successful reuse in another protected render.
+		 */
+		intel_bb_destroy(ibb[n]);
+		intel_buf_destroy(sbuf[n]);
+		intel_buf_destroy(dbuf[n]);
+		gem_close(fd[n], sbo[n]);
+		gem_close(fd[n], dbo[n]);
+		gem_context_destroy(fd[n], ctx[n]);
+		close(fd[n]);
+	}
+
+	/* Verify that encrypted output across loops were equal */
+	for (n = 0; n < (TSTSURF_SIZE/4); ++n)
+		if (encrypted[0][n] == encrypted[1][n])
+			++num_matches;
+	igt_assert(num_matches == (TSTSURF_SIZE/4));
+}
+
+
 static void init_powermgt_resources(int i915, struct powermgt_data *pm)
 {
 	pm->debugfsdir = igt_debugfs_dir(i915);
@@ -912,6 +1013,8 @@ igt_main
 			test_render_pxp_src_to_protdest(i915);
 		igt_subtest("protected-encrypted-src-copy-not-readible")
 			test_render_pxp_protsrc_to_protdest(i915);
+		igt_subtest("dmabuf-shared-protected-dst-is-context-refcounted")
+			test_pxp_dmabuffshare_refcnt();
 	}
 	igt_subtest_group {
 		igt_fixture {
-- 
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[igt-dev] [PATCH i-g-t 17/17] tests/i915_pxp: CRC validation for display tests.

[Alan Previn]

From: Karthik B S <karthik.b.s@intel.com>

Added subtests to validate pxp using CRC validation.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
---
 tests/i915/gem_pxp.c | 286 ++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 283 insertions(+), 3 deletions(-)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 179fb742..728c925a 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -435,6 +435,7 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected, uint32_t size
 #define TSTSURF_INITCOLOR1  0x12341234
 #define TSTSURF_INITCOLOR2  0x56785678
 #define TSTSURF_INITCOLOR3  0xabcdabcd
+#define TSTSURF_GREENCOLOR  0xFF00FF00
 
 static void test_render_baseline(int i915)
 {
@@ -906,7 +907,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
 	trigger_powermgt_suspend_cycle(i915, pm);
 
 	igt_assert_f(!is_context_valid(i915, data[0].ctx),
-				       "RESET_STATS missed INVAL bit on stale pxp context\n");
+		     "RESET_STATS missed INVAL bit on stale pxp context\n");
 	ret = gem_execbuf_flush_store_dw(i915, data[0].ibb, data[0].ctx, data[0].fencebuf);
 	igt_assert_f((ret == -EACCES), "Executing stale pxp context didn't fail with -EACCES\n");
 
@@ -916,7 +917,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
 	 * invalidated bo (not context)
 	 */
 	igt_assert_f(!is_context_valid(i915, data[1].ctx),
-				       "RESET_STATS missed INVAL bit on stale pxp context\n");
+		     "RESET_STATS missed INVAL bit on stale pxp context\n");
 	ret = create_ctx_with_params(i915, true, true, true, false, &ctx2);
 	igt_assert_eq(ret, 0);
 	igt_assert_eq(get_ctx_protected_param(i915, ctx2), 1);
@@ -928,7 +929,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
 	igt_assert_f((ret == -ENOEXEC), "Executing stale pxp buffer didn't fail with -ENOEXEC\n");
 
 	igt_assert_f(is_context_valid(i915, data[2].ctx),
-				       "RESET_STATS false-hit on opt-out context\n");
+		     "RESET_STATS false-hit on opt-out context\n");
 	ret = gem_execbuf_flush_store_dw(i915, data[2].ibb, data[2].ctx, data[2].fencebuf);
 	igt_assert_f((ret == 0), "Opt-out-execution with stale pxp buffer didn't succeed\n");
 
@@ -937,6 +938,266 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
 	free_exec_assets(i915, &data[2]);
 }
 
+static void setup_protected_fb(int i915, int width, int height, igt_fb_t *fb, uint32_t ctx)
+{
+	int err;
+	uint32_t srcbo;
+	struct intel_buf *srcbuf, *dstbuf;
+	struct buf_ops *bops;
+	struct intel_bb *ibb;
+	uint32_t devid;
+	igt_render_copyfunc_t rendercopy;
+
+	devid = intel_get_drm_devid(i915);
+	igt_assert(devid);
+
+	rendercopy = igt_get_render_copyfunc(devid);
+	igt_assert(rendercopy);
+
+	bops = buf_ops_create(i915);
+	igt_assert(bops);
+
+	igt_init_fb(fb, i915, width, height, DRM_FORMAT_XRGB8888, LOCAL_DRM_FORMAT_MOD_NONE,
+		    IGT_COLOR_YCBCR_BT709, IGT_COLOR_YCBCR_LIMITED_RANGE);
+
+	igt_calc_fb_size(i915, width, height, DRM_FORMAT_XRGB8888, LOCAL_DRM_FORMAT_MOD_NONE,
+			 &fb->size, &fb->strides[0]);
+
+	err = create_bo_ext(i915, fb->size, true, &(fb->gem_handle));
+	igt_assert_eq(err, 0);
+	igt_assert(fb->gem_handle);
+
+	err = __gem_set_tiling(i915, fb->gem_handle, igt_fb_mod_to_tiling(fb->modifier),
+			       fb->strides[0]);
+	igt_assert(err == 0 || err == -EOPNOTSUPP);
+
+	do_or_die(__kms_addfb(fb->fd, fb->gem_handle, fb->width, fb->height, fb->drm_format,
+			      fb->modifier, fb->strides, fb->offsets, fb->num_planes,
+			      LOCAL_DRM_MODE_FB_MODIFIERS, &fb->fb_id));
+
+	dstbuf = intel_buf_create_using_handle(bops, fb->gem_handle, fb->width, fb->height,
+					       fb->plane_bpp[0], 0,
+					       igt_fb_mod_to_tiling(fb->modifier), 0);
+	dstbuf->is_protected = true;
+
+	srcbo = alloc_and_fill_dest_buff(i915, false, fb->size, TSTSURF_GREENCOLOR);
+	srcbuf = intel_buf_create_using_handle(bops, srcbo, fb->width, fb->height,
+					       fb->plane_bpp[0], 0,
+					       igt_fb_mod_to_tiling(fb->modifier), 0);
+
+	ibb = intel_bb_create_with_context(i915, ctx, 4096);
+	igt_assert(ibb);
+
+	ibb->pxp.enabled = true;
+	ibb->pxp.apptype = DISPLAY_APPTYPE;
+	ibb->pxp.appid = I915_PROTECTED_CONTENT_DEFAULT_SESSION;
+
+	gen12_render_copyfunc(ibb, srcbuf, 0, 0, fb->width, fb->height, dstbuf, 0, 0);
+
+	gem_sync(i915, fb->gem_handle);
+	assert_bo_content_check(i915, fb->gem_handle, COMPARE_COLOR_UNREADIBLE, fb->size,
+				TSTSURF_GREENCOLOR, NULL, 0);
+
+	intel_bb_destroy(ibb);
+	intel_buf_destroy(srcbuf);
+	gem_close(i915, srcbo);
+}
+
+static void __debugfs_read(int fd, const char *param, char *buf, int len)
+{
+	len = igt_debugfs_simple_read(fd, param, buf, len);
+	if (len < 0)
+		igt_assert_eq(len, -ENODEV);
+}
+
+#define debugfs_read(fd, p, arr) __debugfs_read(fd, p, arr, sizeof(arr))
+#define MAX_SINK_HDCP_CAP_BUF_LEN	5000
+
+#define CP_UNDESIRED				0
+#define CP_DESIRED				1
+#define CP_ENABLED				2
+
+#define KERNEL_AUTH_TIME_ALLOWED_MSEC		(3 *  6 * 1000)
+#define KERNEL_DISABLE_TIME_ALLOWED_MSEC	(1 * 1000)
+
+static bool
+wait_for_prop_value(igt_output_t *output, uint64_t expected,
+		    uint32_t timeout_mSec)
+{
+	uint64_t val;
+	int i;
+
+	for (i = 0; i < timeout_mSec; i++) {
+		val = igt_output_get_prop(output, IGT_CONNECTOR_CONTENT_PROTECTION);
+		if (val == expected)
+			return true;
+		usleep(1000);
+	}
+
+	igt_info("prop_value mismatch %" PRId64 " != %" PRId64 "\n", val, expected);
+
+	return false;
+}
+
+static bool sink_hdcp_capable(int i915, igt_output_t *output)
+{
+	char buf[MAX_SINK_HDCP_CAP_BUF_LEN];
+	int fd;
+
+	fd = igt_debugfs_connector_dir(i915, output->name, O_RDONLY);
+	if (fd < 0)
+		return false;
+
+	if (is_i915_device(i915))
+		debugfs_read(fd, "i915_hdcp_sink_capability", buf);
+	else
+		debugfs_read(fd, "hdcp_sink_capability", buf);
+
+	close(fd);
+
+	igt_debug("Sink capability: %s\n", buf);
+
+	return strstr(buf, "HDCP1.4");
+}
+
+static bool output_hdcp_capable(int i915, igt_output_t *output, bool content_type)
+{
+	if (!output->props[IGT_CONNECTOR_CONTENT_PROTECTION])
+		return false;
+	if (!output->props[IGT_CONNECTOR_HDCP_CONTENT_TYPE] && content_type)
+		return false;
+	if (!sink_hdcp_capable(i915, output))
+		return false;
+
+	return true;
+}
+
+static void test_display_protected_crc(int i915, igt_display_t *display, bool hdcp)
+{
+	igt_output_t *output;
+	drmModeModeInfo *mode;
+	igt_fb_t ref_fb, protected_fb;
+	igt_plane_t *plane;
+	igt_pipe_t *pipe;
+	igt_pipe_crc_t *pipe_crc;
+	igt_crc_t ref_crc, new_crc;
+	int width = 0, height = 0, i = 0, ret, count, valid_outputs = 0;
+	uint32_t ctx;
+	igt_output_t *hdcp_output[IGT_MAX_PIPES];
+
+	ret = create_ctx_with_params(i915, true, true, true, false, &ctx);
+	igt_assert_eq(ret, 0);
+
+	for_each_connected_output(display, output) {
+		mode = igt_output_get_mode(output);
+
+		width = max(width, mode->hdisplay);
+		height = max(height, mode->vdisplay);
+
+		if (!output_hdcp_capable(i915, output, 0))
+			continue;
+
+		hdcp_output[valid_outputs++] = output;
+	}
+
+	if (hdcp)
+		igt_require_f(valid_outputs > 0, "No HDCP capable connector found\n");
+
+	igt_create_color_fb(i915, width, height, DRM_FORMAT_XRGB8888, LOCAL_DRM_FORMAT_MOD_NONE,
+			    0, 1, 0, &ref_fb);
+
+	/* Do a modeset on all outputs */
+	for_each_connected_output(display, output) {
+		mode = igt_output_get_mode(output);
+		pipe = &display->pipes[i];
+		plane = igt_pipe_get_plane_type(pipe, DRM_PLANE_TYPE_PRIMARY);
+		igt_require(igt_pipe_connector_valid(i, output));
+		igt_output_set_pipe(output, i);
+
+		igt_plane_set_fb(plane, &ref_fb);
+		igt_fb_set_size(&ref_fb, plane, mode->hdisplay, mode->vdisplay);
+		igt_plane_set_size(plane, mode->hdisplay, mode->vdisplay);
+
+		igt_display_commit2(display, COMMIT_ATOMIC);
+		i++;
+	}
+
+	if (hdcp) {
+		/* Enable HDCP on all the valid connectors */
+		for (count = 0; count < valid_outputs; count++) {
+			igt_output_set_prop_value(hdcp_output[count],
+						  IGT_CONNECTOR_CONTENT_PROTECTION, CP_DESIRED);
+			if (output->props[IGT_CONNECTOR_HDCP_CONTENT_TYPE])
+				igt_output_set_prop_value(hdcp_output[count],
+							  IGT_CONNECTOR_HDCP_CONTENT_TYPE, 0);
+		}
+
+		igt_display_commit2(display, COMMIT_ATOMIC);
+
+		/*Verify that HDCP is enabled on all valid connectors */
+		for (count = 0; count < valid_outputs; count++) {
+			ret = wait_for_prop_value(hdcp_output[count], CP_ENABLED,
+						  KERNEL_AUTH_TIME_ALLOWED_MSEC);
+			igt_assert_f(ret, "Content Protection not enabled on %s\n",
+				     hdcp_output[count]->name);
+		}
+	}
+
+	setup_protected_fb(i915, width, height, &protected_fb, ctx);
+
+	for_each_connected_output(display, output) {
+		mode = igt_output_get_mode(output);
+		pipe = &display->pipes[output->pending_pipe];
+		pipe_crc = igt_pipe_crc_new(i915, pipe->pipe, INTEL_PIPE_CRC_SOURCE_AUTO);
+		plane = igt_pipe_get_plane_type(pipe, DRM_PLANE_TYPE_PRIMARY);
+		igt_require(igt_pipe_connector_valid(pipe->pipe, output));
+		igt_output_set_pipe(output, pipe->pipe);
+
+		igt_plane_set_fb(plane, &ref_fb);
+		igt_fb_set_size(&ref_fb, plane, mode->hdisplay, mode->vdisplay);
+		igt_plane_set_size(plane, mode->hdisplay, mode->vdisplay);
+
+		igt_display_commit2(display, COMMIT_ATOMIC);
+		igt_pipe_crc_collect_crc(pipe_crc, &ref_crc);
+
+		igt_plane_set_fb(plane, &protected_fb);
+		igt_fb_set_size(&protected_fb, plane, mode->hdisplay, mode->vdisplay);
+		igt_plane_set_size(plane, mode->hdisplay, mode->vdisplay);
+
+		igt_display_commit2(display, COMMIT_ATOMIC);
+		igt_pipe_crc_collect_crc(pipe_crc, &new_crc);
+		igt_assert_crc_equal(&ref_crc, &new_crc);
+
+		if (hdcp) {
+			/* Disable HDCP and collect CRC */
+			igt_output_set_prop_value(hdcp_output[0], IGT_CONNECTOR_CONTENT_PROTECTION,
+						  CP_UNDESIRED);
+			igt_display_commit2(display, COMMIT_ATOMIC);
+			ret = wait_for_prop_value(hdcp_output[0], CP_UNDESIRED,
+						  KERNEL_DISABLE_TIME_ALLOWED_MSEC);
+			igt_assert_f(ret, "Content Protection not cleared\n");
+
+			igt_plane_set_fb(plane, &protected_fb);
+			igt_fb_set_size(&protected_fb, plane, mode->hdisplay, mode->vdisplay);
+			igt_plane_set_size(plane, mode->hdisplay, mode->vdisplay);
+
+			igt_display_commit2(display, COMMIT_ATOMIC);
+			igt_pipe_crc_collect_crc(pipe_crc, &new_crc);
+			igt_assert_f(!igt_check_crc_equal(&ref_crc, &new_crc),
+				    "CRC's expected to be different after HDCP is disabled\n");
+		}
+		/*
+		 * Testing with one pipe-output combination is sufficient.
+		 * So break the loop.
+		 */
+		break;
+	}
+
+	gem_context_destroy(i915, ctx);
+	igt_remove_fb(i915, &ref_fb);
+	igt_remove_fb(i915, &protected_fb);
+}
+
 igt_main
 {
 	int i915 = -1;
@@ -944,6 +1205,7 @@ igt_main
 	struct powermgt_data pm = {0};
 	igt_render_copyfunc_t rendercopy = NULL;
 	uint32_t devid = 0;
+	igt_display_t display;
 
 	igt_fixture
 	{
@@ -1031,6 +1293,24 @@ igt_main
 		igt_subtest("verify-pxp-execution-behavior-after-suspend-resume")
 			test_pxp_pwrcycle_staleasset_execution(i915, &pm);
 	}
+	igt_subtest_group {
+		igt_fixture {
+			igt_require(pxp_supported);
+			devid = intel_get_drm_devid(i915);
+			igt_assert(devid);
+			rendercopy = igt_get_render_copyfunc(devid);
+			igt_require(rendercopy);
+
+			igt_require_pipe_crc(i915);
+			igt_display_require(&display, i915);
+		}
+		igt_describe("Test the display CRC");
+		igt_subtest("display-protected-crc-without-hdcp")
+			test_display_protected_crc(i915, &display, 0);
+		igt_subtest("display-protected-crc-with-hdcp")
+			test_display_protected_crc(i915, &display, 1);
+	}
+
 
 	igt_fixture {
 		close(i915);
-- 
2.25.1

_______________________________________________
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[igt-dev] ✓ Fi.CI.BAT: success for Introduce PXP Test (rev5)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 12697 bytes --]

== Series Details ==

Series: Introduce PXP Test (rev5)
URL   : https://patchwork.freedesktop.org/series/87570/
State : success

== Summary ==

CI Bug Log - changes from IGT_6087 -> IGTPW_5817
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/index.html

Known issues
------------

  Here are the changes found in IGTPW_5817 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_cs_nop@nop-compute0:
    - fi-ilk-650:         NOTRUN -> [SKIP][1] ([fdo#109271]) +30 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-ilk-650/igt@amdgpu/amd_cs_nop@nop-compute0.html

  * igt@gem_exec_fence@basic-await@rcs0:
    - fi-elk-e7500:       [PASS][2] -> [FAIL][3] ([i915#3457])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-elk-e7500/igt@gem_exec_fence@basic-await@rcs0.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-elk-e7500/igt@gem_exec_fence@basic-await@rcs0.html
    - fi-glk-dsi:         [PASS][4] -> [FAIL][5] ([i915#3457])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-glk-dsi/igt@gem_exec_fence@basic-await@rcs0.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-glk-dsi/igt@gem_exec_fence@basic-await@rcs0.html

  * igt@gem_exec_fence@nb-await@vecs0:
    - fi-bsw-kefka:       [PASS][6] -> [FAIL][7] ([i915#3457]) +1 similar issue
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-bsw-kefka/igt@gem_exec_fence@nb-await@vecs0.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-bsw-kefka/igt@gem_exec_fence@nb-await@vecs0.html

  * igt@gem_wait@busy@all:
    - fi-bsw-nick:        [PASS][8] -> [FAIL][9] ([i915#3177] / [i915#3457])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-bsw-nick/igt@gem_wait@busy@all.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-bsw-nick/igt@gem_wait@busy@all.html

  * igt@gem_wait@wait@all:
    - fi-pnv-d510:        [PASS][10] -> [FAIL][11] ([i915#3457])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-pnv-d510/igt@gem_wait@wait@all.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-pnv-d510/igt@gem_wait@wait@all.html
    - fi-bsw-nick:        [PASS][12] -> [FAIL][13] ([i915#3457]) +1 similar issue
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-bsw-nick/igt@gem_wait@wait@all.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-bsw-nick/igt@gem_wait@wait@all.html

  * igt@i915_module_load@reload:
    - fi-ilk-650:         NOTRUN -> [DMESG-FAIL][14] ([i915#3457]) +1 similar issue
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-ilk-650/igt@i915_module_load@reload.html

  * igt@kms_chamelium@dp-hpd-fast:
    - fi-ilk-650:         NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-ilk-650/igt@kms_chamelium@dp-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-ilk-650:         NOTRUN -> [FAIL][16] ([i915#3457]) +1 similar issue
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-ilk-650/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
    - fi-elk-e7500:       [PASS][17] -> [FAIL][18] ([i915#53]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-elk-e7500/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-elk-e7500/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
    - fi-ilk-650:         NOTRUN -> [FAIL][19] ([i915#53]) +8 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-ilk-650/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-a:
    - fi-pnv-d510:        [PASS][20] -> [FAIL][21] ([i915#53])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-pnv-d510/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-pnv-d510/igt@kms_pipe_crc_basic@read-crc-pipe-a.html

  
#### Possible fixes ####

  * igt@gem_exec_fence@basic-await@bcs0:
    - fi-bsw-n3050:       [FAIL][22] ([i915#3457]) -> [PASS][23] +1 similar issue
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-bsw-n3050/igt@gem_exec_fence@basic-await@bcs0.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-bsw-n3050/igt@gem_exec_fence@basic-await@bcs0.html

  * igt@gem_exec_fence@basic-await@vecs0:
    - fi-bsw-kefka:       [FAIL][24] ([i915#3457]) -> [PASS][25] +2 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-bsw-kefka/igt@gem_exec_fence@basic-await@vecs0.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-bsw-kefka/igt@gem_exec_fence@basic-await@vecs0.html

  * igt@gem_exec_fence@nb-await@vcs0:
    - fi-bsw-nick:        [FAIL][26] ([i915#3457]) -> [PASS][27] +1 similar issue
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-bsw-nick/igt@gem_exec_fence@nb-await@vcs0.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-bsw-nick/igt@gem_exec_fence@nb-await@vcs0.html

  * igt@gem_wait@busy@all:
    - fi-glk-dsi:         [FAIL][28] ([i915#3457]) -> [PASS][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-glk-dsi/igt@gem_wait@busy@all.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-glk-dsi/igt@gem_wait@busy@all.html
    - fi-bsw-kefka:       [FAIL][30] ([i915#3177] / [i915#3457]) -> [PASS][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-bsw-kefka/igt@gem_wait@busy@all.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-bsw-kefka/igt@gem_wait@busy@all.html

  * igt@gem_wait@wait@all:
    - fi-bwr-2160:        [FAIL][32] ([i915#3457]) -> [PASS][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-bwr-2160/igt@gem_wait@wait@all.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-bwr-2160/igt@gem_wait@wait@all.html

  * igt@kms_busy@basic@modeset:
    - fi-ilk-650:         [INCOMPLETE][34] ([i915#3457]) -> [PASS][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-ilk-650/igt@kms_busy@basic@modeset.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-ilk-650/igt@kms_busy@basic@modeset.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
    - fi-elk-e7500:       [FAIL][36] ([i915#53]) -> [PASS][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-elk-e7500/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-elk-e7500/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
    - fi-bwr-2160:        [FAIL][38] ([i915#53]) -> [PASS][39] +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-bwr-2160/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-bwr-2160/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html

  
#### Warnings ####

  * igt@gem_exec_gttfill@basic:
    - fi-pnv-d510:        [FAIL][40] ([i915#3457] / [i915#3472]) -> [FAIL][41] ([i915#3472])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
    - fi-ilk-650:         [FAIL][42] ([i915#3457] / [i915#3472]) -> [FAIL][43] ([i915#3472])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-ilk-650/igt@gem_exec_gttfill@basic.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-ilk-650/igt@gem_exec_gttfill@basic.html

  * igt@i915_module_load@reload:
    - fi-kbl-r:           [DMESG-WARN][44] ([i915#3457]) -> [DMESG-WARN][45] ([i915#3457] / [i915#92])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-kbl-r/igt@i915_module_load@reload.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-kbl-r/igt@i915_module_load@reload.html
    - fi-bsw-kefka:       [DMESG-FAIL][46] ([i915#1982] / [i915#3457]) -> [DMESG-WARN][47] ([i915#1982] / [i915#3457])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-bsw-kefka/igt@i915_module_load@reload.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-bsw-kefka/igt@i915_module_load@reload.html

  * igt@runner@aborted:
    - fi-glk-dsi:         [FAIL][48] ([i915#3363] / [k.org#202321]) -> [FAIL][49] ([i915#2426] / [i915#3363] / [k.org#202321])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-glk-dsi/igt@runner@aborted.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-glk-dsi/igt@runner@aborted.html
    - fi-kbl-soraka:      [FAIL][50] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][51] ([i915#1436] / [i915#3363])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-kbl-soraka/igt@runner@aborted.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-kbl-soraka/igt@runner@aborted.html
    - fi-cfl-guc:         [FAIL][52] ([i915#2426] / [i915#3363]) -> [FAIL][53] ([i915#3363])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-cfl-guc/igt@runner@aborted.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-cfl-guc/igt@runner@aborted.html
    - fi-kbl-7567u:       [FAIL][54] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][55] ([i915#1436] / [i915#3363])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-kbl-7567u/igt@runner@aborted.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-kbl-7567u/igt@runner@aborted.html
    - fi-skl-guc:         [FAIL][56] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][57] ([i915#1436] / [i915#3363])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/fi-skl-guc/igt@runner@aborted.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/fi-skl-guc/igt@runner@aborted.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#3177]: https://gitlab.freedesktop.org/drm/intel/issues/3177
  [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
  [i915#3457]: https://gitlab.freedesktop.org/drm/intel/issues/3457
  [i915#3472]: https://gitlab.freedesktop.org/drm/intel/issues/3472
  [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321


Participating hosts (39 -> 35)
------------------------------

  Missing    (4): fi-dg1-1 fi-bsw-cyan fi-bdw-samus fi-kbl-7500u 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6087 -> IGTPW_5817

  CI-20190529: 20190529
  CI_DRM_10095: a0301381199253bca72b57df9b8162bf483dbea4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_5817: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/index.html
  IGT_6087: a1772be7dede83a4f65e5986fd7083a9c8f89083 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@gem_pxp@create-protected-buffer
+igt@gem_pxp@create-regular-buffer
+igt@gem_pxp@create-regular-context-1
+igt@gem_pxp@create-regular-context-2
+igt@gem_pxp@create-valid-protected-context
+igt@gem_pxp@display-protected-crc-without-hdcp
+igt@gem_pxp@display-protected-crc-with-hdcp
+igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted
+igt@gem_pxp@fail-invalid-protected-context
+igt@gem_pxp@hw-rejects-pxp-buffer
+igt@gem_pxp@hw-rejects-pxp-context
+igt@gem_pxp@protected-encrypted-src-copy-not-readible
+igt@gem_pxp@protected-raw-src-copy-not-readible
+igt@gem_pxp@regular-baseline-src-copy-readible
+igt@gem_pxp@reject-modify-context-protection-off-1
+igt@gem_pxp@reject-modify-context-protection-off-2
+igt@gem_pxp@reject-modify-context-protection-off-3
+igt@gem_pxp@reject-modify-context-protection-on
+igt@gem_pxp@verify-pxp-execution-behavior-after-suspend-resume
+igt@gem_pxp@verify-pxp-key-change-after-suspend-resume

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/index.html

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_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] ✗ Fi.CI.IGT: failure for Introduce PXP Test (rev5)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 30243 bytes --]

== Series Details ==

Series: Introduce PXP Test (rev5)
URL   : https://patchwork.freedesktop.org/series/87570/
State : failure

== Summary ==

CI Bug Log - changes from IGT_6087_full -> IGTPW_5817_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_5817_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_5817_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_5817_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_mmap_gtt@cpuset-basic-small-copy-xy:
    - shard-snb:          NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb5/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html

  * igt@gem_ppgtt@blt-vs-render-ctx0:
    - shard-apl:          [PASS][2] -> [FAIL][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-apl7/igt@gem_ppgtt@blt-vs-render-ctx0.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@gem_ppgtt@blt-vs-render-ctx0.html

  * {igt@gem_pxp@create-regular-context-1} (NEW):
    - shard-iclb:         NOTRUN -> [SKIP][4] +12 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb3/igt@gem_pxp@create-regular-context-1.html

  * {igt@gem_pxp@hw-rejects-pxp-context} (NEW):
    - shard-glk:          NOTRUN -> [FAIL][5]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk6/igt@gem_pxp@hw-rejects-pxp-context.html
    - shard-iclb:         NOTRUN -> [FAIL][6]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb5/igt@gem_pxp@hw-rejects-pxp-context.html
    - shard-snb:          NOTRUN -> [FAIL][7]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb6/igt@gem_pxp@hw-rejects-pxp-context.html
    - shard-kbl:          NOTRUN -> [FAIL][8]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl1/igt@gem_pxp@hw-rejects-pxp-context.html

  * {igt@gem_pxp@protected-encrypted-src-copy-not-readible} (NEW):
    - shard-tglb:         NOTRUN -> [FAIL][9] +10 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html

  * igt@i915_selftest@perf@request:
    - shard-tglb:         [PASS][10] -> [DMESG-FAIL][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-tglb3/igt@i915_selftest@perf@request.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb6/igt@i915_selftest@perf@request.html

  * igt@kms_flip_tiling@flip-changes-tiling-y@hdmi-a-2-pipe-a:
    - shard-glk:          [PASS][12] -> [FAIL][13] +5 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk6/igt@kms_flip_tiling@flip-changes-tiling-y@hdmi-a-2-pipe-a.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk3/igt@kms_flip_tiling@flip-changes-tiling-y@hdmi-a-2-pipe-a.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes}:
    - shard-glk:          [PASS][14] -> [FAIL][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html

  
New tests
---------

  New tests have been introduced between IGT_6087_full and IGTPW_5817_full:

### New IGT tests (20) ###

  * igt@gem_pxp@create-protected-buffer:
    - Statuses : 1 fail(s) 4 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@gem_pxp@create-regular-buffer:
    - Statuses :
    - Exec time: [None] s

  * igt@gem_pxp@create-regular-context-1:
    - Statuses : 1 fail(s) 4 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@gem_pxp@create-regular-context-2:
    - Statuses : 1 fail(s) 4 skip(s)
    - Exec time: [0.0, 0.02] s

  * igt@gem_pxp@create-valid-protected-context:
    - Statuses : 1 fail(s) 4 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@gem_pxp@display-protected-crc-with-hdcp:
    - Statuses : 1 fail(s) 4 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@gem_pxp@display-protected-crc-without-hdcp:
    - Statuses : 1 fail(s) 2 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
    - Statuses : 1 fail(s) 4 skip(s)
    - Exec time: [0.0, 0.03] s

  * igt@gem_pxp@fail-invalid-protected-context:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@hw-rejects-pxp-buffer:
    - Statuses :
    - Exec time: [None] s

  * igt@gem_pxp@hw-rejects-pxp-context:
    - Statuses : 4 fail(s)
    - Exec time: [0.01, 0.02] s

  * igt@gem_pxp@protected-encrypted-src-copy-not-readible:
    - Statuses : 1 fail(s) 5 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@gem_pxp@protected-raw-src-copy-not-readible:
    - Statuses : 1 fail(s) 3 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@gem_pxp@regular-baseline-src-copy-readible:
    - Statuses : 1 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@gem_pxp@reject-modify-context-protection-off-1:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@reject-modify-context-protection-off-2:
    - Statuses :
    - Exec time: [None] s

  * igt@gem_pxp@reject-modify-context-protection-off-3:
    - Statuses : 3 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@reject-modify-context-protection-on:
    - Statuses : 1 fail(s) 5 skip(s)
    - Exec time: [0.0, 0.00] s

  * igt@gem_pxp@verify-pxp-execution-behavior-after-suspend-resume:
    - Statuses :
    - Exec time: [None] s

  * igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
    - Statuses : 1 fail(s) 5 skip(s)
    - Exec time: [0.0, 0.01] s

  

Known issues
------------

  Here are the changes found in IGTPW_5817_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-noreloc-purge-cache:
    - shard-iclb:         NOTRUN -> [DMESG-WARN][16] ([i915#3457]) +3 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb7/igt@api_intel_bb@blit-noreloc-purge-cache.html
    - shard-glk:          NOTRUN -> [DMESG-FAIL][17] ([i915#3457]) +2 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk3/igt@api_intel_bb@blit-noreloc-purge-cache.html

  * igt@api_intel_bb@offset-control:
    - shard-apl:          NOTRUN -> [DMESG-WARN][18] ([i915#3457]) +1 similar issue
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@api_intel_bb@offset-control.html
    - shard-glk:          NOTRUN -> [DMESG-WARN][19] ([i915#3457])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk1/igt@api_intel_bb@offset-control.html

  * igt@feature_discovery@chamelium:
    - shard-tglb:         NOTRUN -> [SKIP][20] ([fdo#111827])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb2/igt@feature_discovery@chamelium.html
    - shard-iclb:         NOTRUN -> [SKIP][21] ([fdo#111827])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@feature_discovery@chamelium.html

  * igt@gem_create@create-massive:
    - shard-iclb:         NOTRUN -> [DMESG-WARN][22] ([i915#3002])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb6/igt@gem_create@create-massive.html
    - shard-kbl:          NOTRUN -> [DMESG-WARN][23] ([i915#3002])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@gem_create@create-massive.html
    - shard-tglb:         NOTRUN -> [DMESG-WARN][24] ([i915#3002])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@gem_create@create-massive.html
    - shard-glk:          NOTRUN -> [DMESG-WARN][25] ([i915#3002])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@gem_create@create-massive.html

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][26] ([i915#180] / [i915#3457]) +4 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html

  * igt@gem_ctx_persistence@legacy-engines-hostile:
    - shard-snb:          NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#1099]) +2 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb7/igt@gem_ctx_persistence@legacy-engines-hostile.html

  * igt@gem_ctx_persistence@many-contexts:
    - shard-glk:          [PASS][28] -> [DMESG-WARN][29] ([i915#118] / [i915#3457] / [i915#95])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk5/igt@gem_ctx_persistence@many-contexts.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@gem_ctx_persistence@many-contexts.html

  * igt@gem_eio@unwedge-stress:
    - shard-apl:          NOTRUN -> [FAIL][30] ([i915#3457]) +10 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@gem_eio@unwedge-stress.html
    - shard-snb:          NOTRUN -> [FAIL][31] ([i915#3354] / [i915#3457])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb5/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_endless@dispatch@vecs0:
    - shard-apl:          NOTRUN -> [INCOMPLETE][32] ([i915#2502] / [i915#3457])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl6/igt@gem_exec_endless@dispatch@vecs0.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-iclb:         NOTRUN -> [FAIL][33] ([i915#2842] / [i915#3457]) +5 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@gem_exec_fair@basic-none-rrul@rcs0.html
    - shard-glk:          NOTRUN -> [INCOMPLETE][34] ([i915#3457]) +1 similar issue
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk2/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-tglb:         NOTRUN -> [FAIL][35] ([i915#2842] / [i915#3457]) +5 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
    - shard-kbl:          NOTRUN -> [FAIL][36] ([i915#2842] / [i915#3457])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl3/igt@gem_exec_fair@basic-none@vcs1.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-tglb:         [PASS][37] -> [FAIL][38] ([i915#2842] / [i915#3457])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-tglb2/igt@gem_exec_fair@basic-pace@rcs0.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb6/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
    - shard-iclb:         [PASS][39] -> [FAIL][40] ([i915#2842] / [i915#3457])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-iclb8/igt@gem_exec_fair@basic-pace@vcs0.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@gem_exec_fair@basic-pace@vcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-kbl:          [PASS][41] -> [FAIL][42] ([i915#2842] / [i915#3457])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_exec_schedule@preempt-hang@vcs0:
    - shard-glk:          [PASS][43] -> [FAIL][44] ([i915#3457]) +28 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk2/igt@gem_exec_schedule@preempt-hang@vcs0.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk8/igt@gem_exec_schedule@preempt-hang@vcs0.html

  * igt@gem_exec_schedule@submit-early-slice@vecs0:
    - shard-glk:          NOTRUN -> [FAIL][45] ([i915#3457]) +50 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@gem_exec_schedule@submit-early-slice@vecs0.html

  * igt@gem_exec_whisper@basic-contexts-all:
    - shard-glk:          NOTRUN -> [DMESG-WARN][46] ([i915#118] / [i915#95])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@gem_exec_whisper@basic-contexts-all.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [PASS][47] -> [SKIP][48] ([i915#2190])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-tglb2/igt@gem_huc_copy@huc-copy.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb6/igt@gem_huc_copy@huc-copy.html

  * igt@gem_mmap_gtt@cpuset-basic-small-copy:
    - shard-snb:          NOTRUN -> [INCOMPLETE][49] ([i915#3468]) +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb7/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
    - shard-kbl:          [PASS][50] -> [INCOMPLETE][51] ([i915#3468])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-kbl1/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl4/igt@gem_mmap_gtt@cpuset-basic-small-copy.html

  * igt@gem_mmap_gtt@cpuset-basic-small-copy-xy:
    - shard-tglb:         NOTRUN -> [INCOMPLETE][52] ([i915#3468]) +2 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb2/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
    - shard-kbl:          NOTRUN -> [INCOMPLETE][53] ([i915#3468]) +3 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl6/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html

  * igt@gem_mmap_offset@clear:
    - shard-glk:          NOTRUN -> [FAIL][54] ([i915#1888] / [i915#3160])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@gem_mmap_offset@clear.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-apl:          NOTRUN -> [WARN][55] ([i915#2658])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl6/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
    - shard-apl:          NOTRUN -> [INCOMPLETE][56] ([i915#3468])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl6/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled:
    - shard-iclb:         NOTRUN -> [SKIP][57] ([i915#768]) +4 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html

  * igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled:
    - shard-iclb:         NOTRUN -> [INCOMPLETE][58] ([i915#3468]) +2 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb1/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled.html
    - shard-glk:          NOTRUN -> [INCOMPLETE][59] ([i915#3468]) +2 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk5/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled.html
    - shard-tglb:         NOTRUN -> [INCOMPLETE][60] ([i915#3457] / [i915#3468])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled.html

  * igt@gem_softpin@evict-snoop-interruptible:
    - shard-tglb:         NOTRUN -> [SKIP][61] ([fdo#109312])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb6/igt@gem_softpin@evict-snoop-interruptible.html
    - shard-iclb:         NOTRUN -> [SKIP][62] ([fdo#109312])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb6/igt@gem_softpin@evict-snoop-interruptible.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-apl:          NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#3323])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-tglb:         NOTRUN -> [SKIP][64] ([i915#3297]) +2 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@gem_userptr_blits@dmabuf-unsync.html
    - shard-iclb:         NOTRUN -> [SKIP][65] ([i915#3297]) +3 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb4/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_wait@await@bcs0:
    - shard-apl:          [PASS][66] -> [FAIL][67] ([i915#3457]) +1 similar issue
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-apl7/igt@gem_wait@await@bcs0.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@gem_wait@await@bcs0.html

  * igt@gen3_render_linear_blits:
    - shard-tglb:         NOTRUN -> [SKIP][68] ([fdo#109289]) +4 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb2/igt@gen3_render_linear_blits.html
    - shard-iclb:         NOTRUN -> [SKIP][69] ([fdo#109289]) +3 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb7/igt@gen3_render_linear_blits.html

  * igt@gen7_exec_parse@basic-offset:
    - shard-apl:          NOTRUN -> [SKIP][70] ([fdo#109271]) +171 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@gen7_exec_parse@basic-offset.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-iclb:         NOTRUN -> [SKIP][71] ([fdo#112306]) +4 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@bb-start-out:
    - shard-tglb:         NOTRUN -> [SKIP][72] ([fdo#112306]) +3 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@gen9_exec_parse@bb-start-out.html

  * igt@i915_hangman@error-state-capture@bcs0:
    - shard-snb:          NOTRUN -> [DMESG-WARN][73] ([i915#3457]) +2 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb7/igt@i915_hangman@error-state-capture@bcs0.html

  * igt@i915_module_load@reload:
    - shard-tglb:         NOTRUN -> [DMESG-WARN][74] ([i915#3457]) +3 similar issues
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb2/igt@i915_module_load@reload.html
    - shard-kbl:          NOTRUN -> [DMESG-WARN][75] ([i915#3457]) +5 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@i915_module_load@reload.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-tglb:         NOTRUN -> [SKIP][76] ([i915#3288])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@i915_pm_dc@dc9-dpms.html
    - shard-iclb:         NOTRUN -> [FAIL][77] ([i915#3343])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb1/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_pm_rpm@cursor:
    - shard-tglb:         [PASS][78] -> [DMESG-WARN][79] ([i915#2411] / [i915#3457]) +1 similar issue
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-tglb6/igt@i915_pm_rpm@cursor.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb6/igt@i915_pm_rpm@cursor.html
    - shard-kbl:          [PASS][80] -> [DMESG-WARN][81] ([i915#3457])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-kbl2/igt@i915_pm_rpm@cursor.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl3/igt@i915_pm_rpm@cursor.html
    - shard-glk:          [PASS][82] -> [DMESG-WARN][83] ([i915#3457])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk7/igt@i915_pm_rpm@cursor.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk2/igt@i915_pm_rpm@cursor.html

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-iclb:         NOTRUN -> [SKIP][84] ([fdo#110892]) +1 similar issue
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb5/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@i915_pm_rps@reset:
    - shard-apl:          NOTRUN -> [DMESG-FAIL][85] ([i915#3457]) +2 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@i915_pm_rps@reset.html

  * igt@kms_atomic@plane-immutable-zpos:
    - shard-glk:          [PASS][86] -> [FAIL][87] ([i915#2657] / [i915#3457])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk3/igt@kms_atomic@plane-immutable-zpos.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk8/igt@kms_atomic@plane-immutable-zpos.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][88] ([fdo#110725] / [fdo#111614]) +6 similar issues
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb5/igt@kms_big_fb@linear-16bpp-rotate-90.html
    - shard-tglb:         NOTRUN -> [SKIP][89] ([fdo#111614]) +6 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
    - shard-tglb:         NOTRUN -> [SKIP][90] ([fdo#111615]) +3 similar issues
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
    - shard-iclb:         NOTRUN -> [SKIP][91] ([fdo#110723])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb1/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html

  * igt@kms_big_joiner@invalid-modeset:
    - shard-iclb:         NOTRUN -> [SKIP][92] ([i915#2705])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb3/igt@kms_big_joiner@invalid-modeset.html
    - shard-kbl:          NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#2705])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@kms_big_joiner@invalid-modeset.html
    - shard-apl:          NOTRUN -> [SKIP][94] ([fdo#109271] / [i915#2705])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@kms_big_joiner@invalid-modeset.html
    - shard-glk:          NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#2705])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@kms_big_joiner@invalid-modeset.html
    - shard-tglb:         NOTRUN -> [SKIP][96] ([i915#2705])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@kms_big_joiner@invalid-modeset.html

  * igt@kms_chamelium@dp-hpd-storm-disable:
    - shard-glk:          NOTRUN -> [SKIP][97] ([fdo#109271] / [fdo#111827]) +19 similar issues
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk3/igt@kms_chamelium@dp-hpd-storm-disable.html

  * igt@kms_chamelium@dp-mode-timings:
    - shard-apl:          NOTRUN -> [SKIP][98] ([fdo#109271] / [fdo#111827]) +15 similar issues
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl6/igt@kms_chamelium@dp-mode-timings.html

  * igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
    - shard-snb:          NOTRUN -> [SKIP][99] ([fdo#109271] / [fdo#111827]) +16 similar issues
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb6/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html

  * igt@kms_chamelium@hdmi-hpd-storm:
    - shard-kbl:          NOTRUN -> [SKIP][100] ([fdo#109271] / [fdo#111827]) +30 similar issues
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@kms_chamelium@hdmi-hpd-storm.html

  * igt@kms_color@pipe-b-degamma:
    - shard-tglb:         NOTRUN -> [FAIL][101] ([i915#1149])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@kms_color@pipe-b-degamma.html
    - shard-glk:          NOTRUN -> [FAIL][102] ([i915#71])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk3/igt@kms_color@pipe-b-degamma.html
    - shard-iclb:         NOTRUN -> [FAIL][103] ([i915#1149])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb5/igt@kms_color@pipe-b-degamma.html

  * igt@kms_color@pipe-c-degamma:
    - shard-glk:          [PASS][104] -> [FAIL][105] ([i915#71]) +1 similar issue
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk5/igt@kms_color@pipe-c-degamma.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk6/igt@kms_color@pipe-c-degamma.html

  * igt@kms_color@pipe-d-ctm-0-25:
    - shard-iclb:         NOTRUN -> [SKIP][106] ([fdo#109278] / [i915#1149]) +2 similar issues
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb5/igt@kms_color@pipe-d-ctm-0-25.html

  * igt@kms_color_chamelium@pipe-b-ctm-0-75:
    - shard-tglb:         NOTRUN -> [SKIP][107] ([fdo#109284] / [fdo#111827]) +21 similar issues
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@kms_color_chamelium@pipe-b-ctm-0-75.html

  * igt@kms_color_chamelium@pipe-b-ctm-red-to-blue:
    - shard-iclb:         NOTRUN -> [SKIP][108] ([fdo#109284] / [fdo#111827]) +19 similar issues
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@kms_color_chamelium@pipe-b-ctm-red-to-blue.html

  * igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
    - shard-iclb:         NOTRUN -> [SKIP][109] ([fdo#109278] / [fdo#109284] / [fdo#111827]) +1 similar issue
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb7/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-kbl:          NOTRUN -> [TIMEOUT][110] ([i915#1319])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-iclb:         NOTRUN -> [SKIP][111] ([i915#3116])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb7/igt@kms_content_protection@dp-mst-lic-type-1.html
    - shard-tglb:         NOTRUN -> [SKIP][112] ([i915#3116])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb2/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@uevent:
    - shard-kbl:          NOTRUN -> [FAIL][113] ([i915#2105])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@kms_content_protection@uevent.html
    - shard-tglb:         NOTRUN -> [SKIP][114] ([fdo#111828])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@kms_content_protection@uevent.html
    - shard-iclb:         NOTRUN -> [SKIP][115] ([fdo#109300] / [fdo#111066])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb1/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen:
    - shard-snb:          NOTRUN -> [FAIL][116] ([i915#3457]) +4 similar issues
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb5/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html

  * igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding:
    - shard-tglb:         NOTRUN -> [SKIP][117] ([i915#3319] / [i915#3457]) +6 similar issues
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding.html

  * igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen:
    - shard-kbl:          NOTRUN -> [FAIL][118] ([i915#3444] / [i915#3457]) +16 similar issues
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html

  * igt@kms_cursor_crc@pipe-a-cursor-dpms:
    - shard-apl:          [PASS][119] -> [FAIL][120] ([i915#3444] / [i915#3457])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-dpms.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-dpms.html

  * igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen:
    - shard-iclb:         NOTRUN -> [SKIP][121] ([fdo#109278] / [fdo#109279] / [i915#3457]) +6 similar issues
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb6/igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-64x21-random:
    - shard-apl:          NOTRUN -> [FAIL][122] ([i915#3444] / [i915#3457]) +3 similar issues
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@kms_cursor_crc@pipe-b-cursor-64x21-random.html

  * igt@kms_cursor_crc@pipe-b-cursor-64x64-random:
    - shard-iclb:         NOTRUN -> [FAIL][123] ([i915#3457]) +13 similar issues
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb7/igt@kms_cursor_crc@pipe-b-cursor-64x64-random.html
    - shard-glk:          NOTRUN -> [FAIL][124] ([i915#3444] / [i915#3457]) +11 similar issues
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk1/igt@kms_cursor_crc@pipe-b-cursor-64x64-random.html

  * igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque:
    - shard-glk:          [PASS][125] -> [FAIL][126] ([i915#3444] / [i915#3457]) +4 similar issues
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk8/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk3/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
    - shard-kbl:          [PASS][127] -> [FAIL][128] ([i915#3444] / [i915#3457])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html

  * igt@kms_cursor_crc@pipe-b-cursor-dpms:
    - shard-iclb:         [PASS][129] -> [FAIL][130] ([i915#3457]) +1 similar issue
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-iclb5/igt@kms_cursor_crc@pipe-b-cursor-dpms.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb1/igt@kms_cursor_crc@pipe-b-cursor-dpms.html

  * igt@kms_cursor_crc@pi

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/index.html

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_______________________________________________
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Re: [igt-dev] [PATCH i-g-t 01/17] Sync i915_drm.h UAPI from kernel

[Rodrigo Vivi]

On Tue, May 18, 2021 at 03:33:28AM -0700, Alan Previn wrote:
> Sync i915_drm.h UAPI from drm-tip kernel baselined on following tag:
> "drm-tip: 2021y-05m-12d-18h-04m-49s UTC integration manifest"

drm-tip integration manifest is a weak ref hard to find.

better to 
drm-tip$ git log include/uapi/drm/i915_drm.h
then mention the last commit touching this file.

check the other commits changing this patch.

Anyway, this approach is correct. And you will have to sync it again
before merge so if you follow the same:

Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
>  include/drm-uapi/i915_drm.h | 396 ++++++++++++++++++++++++++++++++----
>  1 file changed, 361 insertions(+), 35 deletions(-)
> 
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index bf9ea471..d9fbf218 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -62,8 +62,8 @@ extern "C" {
>  #define I915_ERROR_UEVENT		"ERROR"
>  #define I915_RESET_UEVENT		"RESET"
>  
> -/*
> - * i915_user_extension: Base class for defining a chain of extensions
> +/**
> + * struct i915_user_extension - Base class for defining a chain of extensions
>   *
>   * Many interfaces need to grow over time. In most cases we can simply
>   * extend the struct and have userspace pass in more data. Another option,
> @@ -76,12 +76,58 @@ extern "C" {
>   * increasing complexity, and for large parts of that interface to be
>   * entirely optional. The downside is more pointer chasing; chasing across
>   * the boundary with pointers encapsulated inside u64.
> + *
> + * Example chaining:
> + *
> + * .. code-block:: C
> + *
> + *	struct i915_user_extension ext3 {
> + *		.next_extension = 0, // end
> + *		.name = ...,
> + *	};
> + *	struct i915_user_extension ext2 {
> + *		.next_extension = (uintptr_t)&ext3,
> + *		.name = ...,
> + *	};
> + *	struct i915_user_extension ext1 {
> + *		.next_extension = (uintptr_t)&ext2,
> + *		.name = ...,
> + *	};
> + *
> + * Typically the struct i915_user_extension would be embedded in some uAPI
> + * struct, and in this case we would feed it the head of the chain(i.e ext1),
> + * which would then apply all of the above extensions.
> + *
>   */
>  struct i915_user_extension {
> +	/**
> +	 * @next_extension:
> +	 *
> +	 * Pointer to the next struct i915_user_extension, or zero if the end.
> +	 */
>  	__u64 next_extension;
> +	/**
> +	 * @name: Name of the extension.
> +	 *
> +	 * Note that the name here is just some integer.
> +	 *
> +	 * Also note that the name space for this is not global for the whole
> +	 * driver, but rather its scope/meaning is limited to the specific piece
> +	 * of uAPI which has embedded the struct i915_user_extension.
> +	 */
>  	__u32 name;
> -	__u32 flags; /* All undefined bits must be zero. */
> -	__u32 rsvd[4]; /* Reserved for future use; must be zero. */
> +	/**
> +	 * @flags: MBZ
> +	 *
> +	 * All undefined bits must be zero.
> +	 */
> +	__u32 flags;
> +	/**
> +	 * @rsvd: MBZ
> +	 *
> +	 * Reserved for future use; must be zero.
> +	 */
> +	__u32 rsvd[4];
>  };
>  
>  /*
> @@ -360,6 +406,7 @@ typedef struct _drm_i915_sarea {
>  #define DRM_I915_QUERY			0x39
>  #define DRM_I915_GEM_VM_CREATE		0x3a
>  #define DRM_I915_GEM_VM_DESTROY		0x3b
> +#define DRM_I915_GEM_CREATE_EXT		0x3c
>  /* Must be kept compact -- no holes */
>  
>  #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
> @@ -392,6 +439,7 @@ typedef struct _drm_i915_sarea {
>  #define DRM_IOCTL_I915_GEM_ENTERVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
>  #define DRM_IOCTL_I915_GEM_LEAVEVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
>  #define DRM_IOCTL_I915_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
> +#define DRM_IOCTL_I915_GEM_CREATE_EXT	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext)
>  #define DRM_IOCTL_I915_GEM_PREAD	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
>  #define DRM_IOCTL_I915_GEM_PWRITE	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
>  #define DRM_IOCTL_I915_GEM_MMAP		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
> @@ -943,6 +991,7 @@ struct drm_i915_gem_exec_object {
>  	__u64 offset;
>  };
>  
> +/* DRM_IOCTL_I915_GEM_EXECBUFFER was removed in Linux 5.13 */
>  struct drm_i915_gem_execbuffer {
>  	/**
>  	 * List of buffers to be validated with their relocations to be
> @@ -1053,12 +1102,12 @@ struct drm_i915_gem_exec_fence {
>  	__u32 flags;
>  };
>  
> -/**
> +/*
>   * See drm_i915_gem_execbuffer_ext_timeline_fences.
>   */
>  #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0
>  
> -/**
> +/*
>   * This structure describes an array of drm_syncobj and associated points for
>   * timeline variants of drm_syncobj. It is invalid to append this structure to
>   * the execbuf if I915_EXEC_FENCE_ARRAY is set.
> @@ -1699,7 +1748,7 @@ struct drm_i915_gem_context_param {
>  	__u64 value;
>  };
>  
> -/**
> +/*
>   * Context SSEU programming
>   *
>   * It may be necessary for either functional or performance reason to configure
> @@ -2066,7 +2115,7 @@ struct drm_i915_perf_open_param {
>  	__u64 properties_ptr;
>  };
>  
> -/**
> +/*
>   * Enable data capture for a stream that was either opened in a disabled state
>   * via I915_PERF_FLAG_DISABLED or was later disabled via
>   * I915_PERF_IOCTL_DISABLE.
> @@ -2080,7 +2129,7 @@ struct drm_i915_perf_open_param {
>   */
>  #define I915_PERF_IOCTL_ENABLE	_IO('i', 0x0)
>  
> -/**
> +/*
>   * Disable data capture for a stream.
>   *
>   * It is an error to try and read a stream that is disabled.
> @@ -2089,11 +2138,11 @@ struct drm_i915_perf_open_param {
>   */
>  #define I915_PERF_IOCTL_DISABLE	_IO('i', 0x1)
>  
> -/**
> +/*
>   * Change metrics_set captured by a stream.
>   *
>   * If the stream is bound to a specific context, the configuration change
> - * will performed __inline__ with that context such that it takes effect before
> + * will performed inline with that context such that it takes effect before
>   * the next execbuf submission.
>   *
>   * Returns the previously bound metrics set id, or a negative error code.
> @@ -2102,7 +2151,7 @@ struct drm_i915_perf_open_param {
>   */
>  #define I915_PERF_IOCTL_CONFIG	_IO('i', 0x2)
>  
> -/**
> +/*
>   * Common to all i915 perf records
>   */
>  struct drm_i915_perf_record_header {
> @@ -2150,7 +2199,7 @@ enum drm_i915_perf_record_type {
>  	DRM_I915_PERF_RECORD_MAX /* non-ABI */
>  };
>  
> -/**
> +/*
>   * Structure to upload perf dynamic configuration into the kernel.
>   */
>  struct drm_i915_perf_oa_config {
> @@ -2171,53 +2220,95 @@ struct drm_i915_perf_oa_config {
>  	__u64 flex_regs_ptr;
>  };
>  
> +/**
> + * struct drm_i915_query_item - An individual query for the kernel to process.
> + *
> + * The behaviour is determined by the @query_id. Note that exactly what
> + * @data_ptr is also depends on the specific @query_id.
> + */
>  struct drm_i915_query_item {
> +	/** @query_id: The id for this query */
>  	__u64 query_id;
>  #define DRM_I915_QUERY_TOPOLOGY_INFO    1
>  #define DRM_I915_QUERY_ENGINE_INFO	2
>  #define DRM_I915_QUERY_PERF_CONFIG      3
> +#define DRM_I915_QUERY_MEMORY_REGIONS   4
>  /* Must be kept compact -- no holes and well documented */
>  
> -	/*
> +	/**
> +	 * @length:
> +	 *
>  	 * When set to zero by userspace, this is filled with the size of the
> -	 * data to be written at the data_ptr pointer. The kernel sets this
> +	 * data to be written at the @data_ptr pointer. The kernel sets this
>  	 * value to a negative value to signal an error on a particular query
>  	 * item.
>  	 */
>  	__s32 length;
>  
> -	/*
> +	/**
> +	 * @flags:
> +	 *
>  	 * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
>  	 *
>  	 * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
> -	 * following :
> -	 *         - DRM_I915_QUERY_PERF_CONFIG_LIST
> -	 *         - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
> -	 *         - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
> +	 * following:
> +	 *
> +	 *	- DRM_I915_QUERY_PERF_CONFIG_LIST
> +	 *      - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
> +	 *      - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
>  	 */
>  	__u32 flags;
>  #define DRM_I915_QUERY_PERF_CONFIG_LIST          1
>  #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2
>  #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID   3
>  
> -	/*
> -	 * Data will be written at the location pointed by data_ptr when the
> -	 * value of length matches the length of the data to be written by the
> +	/**
> +	 * @data_ptr:
> +	 *
> +	 * Data will be written at the location pointed by @data_ptr when the
> +	 * value of @length matches the length of the data to be written by the
>  	 * kernel.
>  	 */
>  	__u64 data_ptr;
>  };
>  
> +/**
> + * struct drm_i915_query - Supply an array of struct drm_i915_query_item for the
> + * kernel to fill out.
> + *
> + * Note that this is generally a two step process for each struct
> + * drm_i915_query_item in the array:
> + *
> + * 1. Call the DRM_IOCTL_I915_QUERY, giving it our array of struct
> + *    drm_i915_query_item, with &drm_i915_query_item.length set to zero. The
> + *    kernel will then fill in the size, in bytes, which tells userspace how
> + *    memory it needs to allocate for the blob(say for an array of properties).
> + *
> + * 2. Next we call DRM_IOCTL_I915_QUERY again, this time with the
> + *    &drm_i915_query_item.data_ptr equal to our newly allocated blob. Note that
> + *    the &drm_i915_query_item.length should still be the same as what the
> + *    kernel previously set. At this point the kernel can fill in the blob.
> + *
> + * Note that for some query items it can make sense for userspace to just pass
> + * in a buffer/blob equal to or larger than the required size. In this case only
> + * a single ioctl call is needed. For some smaller query items this can work
> + * quite well.
> + *
> + */
>  struct drm_i915_query {
> +	/** @num_items: The number of elements in the @items_ptr array */
>  	__u32 num_items;
>  
> -	/*
> -	 * Unused for now. Must be cleared to zero.
> +	/**
> +	 * @flags: Unused for now. Must be cleared to zero.
>  	 */
>  	__u32 flags;
>  
> -	/*
> -	 * This points to an array of num_items drm_i915_query_item structures.
> +	/**
> +	 * @items_ptr:
> +	 *
> +	 * Pointer to an array of struct drm_i915_query_item. The number of
> +	 * array elements is @num_items.
>  	 */
>  	__u64 items_ptr;
>  };
> @@ -2291,21 +2382,21 @@ struct drm_i915_query_topology_info {
>   * Describes one engine and it's capabilities as known to the driver.
>   */
>  struct drm_i915_engine_info {
> -	/** Engine class and instance. */
> +	/** @engine: Engine class and instance. */
>  	struct i915_engine_class_instance engine;
>  
> -	/** Reserved field. */
> +	/** @rsvd0: Reserved field. */
>  	__u32 rsvd0;
>  
> -	/** Engine flags. */
> +	/** @flags: Engine flags. */
>  	__u64 flags;
>  
> -	/** Capabilities of this engine. */
> +	/** @capabilities: Capabilities of this engine. */
>  	__u64 capabilities;
>  #define I915_VIDEO_CLASS_CAPABILITY_HEVC		(1 << 0)
>  #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC	(1 << 1)
>  
> -	/** Reserved fields. */
> +	/** @rsvd1: Reserved fields. */
>  	__u64 rsvd1[4];
>  };
>  
> @@ -2316,13 +2407,13 @@ struct drm_i915_engine_info {
>   * an array of struct drm_i915_engine_info structures.
>   */
>  struct drm_i915_query_engine_info {
> -	/** Number of struct drm_i915_engine_info structs following. */
> +	/** @num_engines: Number of struct drm_i915_engine_info structs following. */
>  	__u32 num_engines;
>  
> -	/** MBZ */
> +	/** @rsvd: MBZ */
>  	__u32 rsvd[3];
>  
> -	/** Marker for drm_i915_engine_info structures. */
> +	/** @engines: Marker for drm_i915_engine_info structures. */
>  	struct drm_i915_engine_info engines[];
>  };
>  
> @@ -2376,6 +2467,241 @@ struct drm_i915_query_perf_config {
>  	__u8 data[];
>  };
>  
> +/**
> + * enum drm_i915_gem_memory_class - Supported memory classes
> + */
> +enum drm_i915_gem_memory_class {
> +	/** @I915_MEMORY_CLASS_SYSTEM: System memory */
> +	I915_MEMORY_CLASS_SYSTEM = 0,
> +	/** @I915_MEMORY_CLASS_DEVICE: Device local-memory */
> +	I915_MEMORY_CLASS_DEVICE,
> +};
> +
> +/**
> + * struct drm_i915_gem_memory_class_instance - Identify particular memory region
> + */
> +struct drm_i915_gem_memory_class_instance {
> +	/** @memory_class: See enum drm_i915_gem_memory_class */
> +	__u16 memory_class;
> +
> +	/** @memory_instance: Which instance */
> +	__u16 memory_instance;
> +};
> +
> +/**
> + * struct drm_i915_memory_region_info - Describes one region as known to the
> + * driver.
> + *
> + * Note that we reserve some stuff here for potential future work. As an example
> + * we might want expose the capabilities for a given region, which could include
> + * things like if the region is CPU mappable/accessible, what are the supported
> + * mapping types etc.
> + *
> + * Note that to extend struct drm_i915_memory_region_info and struct
> + * drm_i915_query_memory_regions in the future the plan is to do the following:
> + *
> + * .. code-block:: C
> + *
> + *	struct drm_i915_memory_region_info {
> + *		struct drm_i915_gem_memory_class_instance region;
> + *		union {
> + *			__u32 rsvd0;
> + *			__u32 new_thing1;
> + *		};
> + *		...
> + *		union {
> + *			__u64 rsvd1[8];
> + *			struct {
> + *				__u64 new_thing2;
> + *				__u64 new_thing3;
> + *				...
> + *			};
> + *		};
> + *	};
> + *
> + * With this things should remain source compatible between versions for
> + * userspace, even as we add new fields.
> + *
> + * Note this is using both struct drm_i915_query_item and struct drm_i915_query.
> + * For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS
> + * at &drm_i915_query_item.query_id.
> + */
> +struct drm_i915_memory_region_info {
> +	/** @region: The class:instance pair encoding */
> +	struct drm_i915_gem_memory_class_instance region;
> +
> +	/** @rsvd0: MBZ */
> +	__u32 rsvd0;
> +
> +	/** @probed_size: Memory probed by the driver (-1 = unknown) */
> +	__u64 probed_size;
> +
> +	/** @unallocated_size: Estimate of memory remaining (-1 = unknown) */
> +	__u64 unallocated_size;
> +
> +	/** @rsvd1: MBZ */
> +	__u64 rsvd1[8];
> +};
> +
> +/**
> + * struct drm_i915_query_memory_regions
> + *
> + * The region info query enumerates all regions known to the driver by filling
> + * in an array of struct drm_i915_memory_region_info structures.
> + *
> + * Example for getting the list of supported regions:
> + *
> + * .. code-block:: C
> + *
> + *	struct drm_i915_query_memory_regions *info;
> + *	struct drm_i915_query_item item = {
> + *		.query_id = DRM_I915_QUERY_MEMORY_REGIONS;
> + *	};
> + *	struct drm_i915_query query = {
> + *		.num_items = 1,
> + *		.items_ptr = (uintptr_t)&item,
> + *	};
> + *	int err, i;
> + *
> + *	// First query the size of the blob we need, this needs to be large
> + *	// enough to hold our array of regions. The kernel will fill out the
> + *	// item.length for us, which is the number of bytes we need.
> + *	err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
> + *	if (err) ...
> + *
> + *	info = calloc(1, item.length);
> + *	// Now that we allocated the required number of bytes, we call the ioctl
> + *	// again, this time with the data_ptr pointing to our newly allocated
> + *	// blob, which the kernel can then populate with the all the region info.
> + *	item.data_ptr = (uintptr_t)&info,
> + *
> + *	err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
> + *	if (err) ...
> + *
> + *	// We can now access each region in the array
> + *	for (i = 0; i < info->num_regions; i++) {
> + *		struct drm_i915_memory_region_info mr = info->regions[i];
> + *		u16 class = mr.region.class;
> + *		u16 instance = mr.region.instance;
> + *
> + *		....
> + *	}
> + *
> + *	free(info);
> + */
> +struct drm_i915_query_memory_regions {
> +	/** @num_regions: Number of supported regions */
> +	__u32 num_regions;
> +
> +	/** @rsvd: MBZ */
> +	__u32 rsvd[3];
> +
> +	/** @regions: Info about each supported region */
> +	struct drm_i915_memory_region_info regions[];
> +};
> +
> +/**
> + * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
> + * extension support using struct i915_user_extension.
> + *
> + * Note that in the future we want to have our buffer flags here, at least for
> + * the stuff that is immutable. Previously we would have two ioctls, one to
> + * create the object with gem_create, and another to apply various parameters,
> + * however this creates some ambiguity for the params which are considered
> + * immutable. Also in general we're phasing out the various SET/GET ioctls.
> + */
> +struct drm_i915_gem_create_ext {
> +	/**
> +	 * @size: Requested size for the object.
> +	 *
> +	 * The (page-aligned) allocated size for the object will be returned.
> +	 *
> +	 * Note that for some devices we have might have further minimum
> +	 * page-size restrictions(larger than 4K), like for device local-memory.
> +	 * However in general the final size here should always reflect any
> +	 * rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS
> +	 * extension to place the object in device local-memory.
> +	 */
> +	__u64 size;
> +	/**
> +	 * @handle: Returned handle for the object.
> +	 *
> +	 * Object handles are nonzero.
> +	 */
> +	__u32 handle;
> +	/** @flags: MBZ */
> +	__u32 flags;
> +	/**
> +	 * @extensions: The chain of extensions to apply to this object.
> +	 *
> +	 * This will be useful in the future when we need to support several
> +	 * different extensions, and we need to apply more than one when
> +	 * creating the object. See struct i915_user_extension.
> +	 *
> +	 * If we don't supply any extensions then we get the same old gem_create
> +	 * behaviour.
> +	 *
> +	 * For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see
> +	 * struct drm_i915_gem_create_ext_memory_regions.
> +	 */
> +#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
> +	__u64 extensions;
> +};
> +
> +/**
> + * struct drm_i915_gem_create_ext_memory_regions - The
> + * I915_GEM_CREATE_EXT_MEMORY_REGIONS extension.
> + *
> + * Set the object with the desired set of placements/regions in priority
> + * order. Each entry must be unique and supported by the device.
> + *
> + * This is provided as an array of struct drm_i915_gem_memory_class_instance, or
> + * an equivalent layout of class:instance pair encodings. See struct
> + * drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to
> + * query the supported regions for a device.
> + *
> + * As an example, on discrete devices, if we wish to set the placement as
> + * device local-memory we can do something like:
> + *
> + * .. code-block:: C
> + *
> + *	struct drm_i915_gem_memory_class_instance region_lmem = {
> + *              .memory_class = I915_MEMORY_CLASS_DEVICE,
> + *              .memory_instance = 0,
> + *      };
> + *      struct drm_i915_gem_create_ext_memory_regions regions = {
> + *              .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS },
> + *              .regions = (uintptr_t)&region_lmem,
> + *              .num_regions = 1,
> + *      };
> + *      struct drm_i915_gem_create_ext create_ext = {
> + *              .size = 16 * PAGE_SIZE,
> + *              .extensions = (uintptr_t)&regions,
> + *      };
> + *
> + *      int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
> + *      if (err) ...
> + *
> + * At which point we get the object handle in &drm_i915_gem_create_ext.handle,
> + * along with the final object size in &drm_i915_gem_create_ext.size, which
> + * should account for any rounding up, if required.
> + */
> +struct drm_i915_gem_create_ext_memory_regions {
> +	/** @base: Extension link. See struct i915_user_extension. */
> +	struct i915_user_extension base;
> +
> +	/** @pad: MBZ */
> +	__u32 pad;
> +	/** @num_regions: Number of elements in the @regions array. */
> +	__u32 num_regions;
> +	/**
> +	 * @regions: The regions/placements array.
> +	 *
> +	 * An array of struct drm_i915_gem_memory_class_instance.
> +	 */
> +	__u64 regions;
> +};
> +
>  #if defined(__cplusplus)
>  }
>  #endif
> -- 
> 2.25.1
> 
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Re: [igt-dev] [PATCH i-g-t 03/17] Update IOCTL wrapper with DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT

[Rodrigo Vivi]

On Tue, May 18, 2021 at 03:33:30AM -0700, Alan Previn wrote:
> Update IOCTL wrapper with DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT

assuming nothing will change there

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
>  lib/ioctl_wrappers.c | 34 ++++++++++++++++++++++++++++++++++
>  lib/ioctl_wrappers.h |  2 ++
>  2 files changed, 36 insertions(+)
> 
> diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
> index 4440004c..c8e01911 100644
> --- a/lib/ioctl_wrappers.c
> +++ b/lib/ioctl_wrappers.c
> @@ -657,6 +657,40 @@ void gem_execbuf_wr(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
>  	igt_assert_eq(__gem_execbuf_wr(fd, execbuf), 0);
>  }
>  
> +/**
> + * __gem_ctx_create_ext:
> + * @fd: open i915 drm file descriptor
> + * @ctx_ext: context_create_ext data structure
> + *
> + * This wraps the GEM_CONTEXT_CREATE_EXT ioctl, which allocates gem context based on
> + * additional drm_i915_gem_context_create_ext_setparam input extensions. This is
> + * allowed to fail, with -errno returned
> + */
> +int __gem_ctx_create_ext(int fd, struct drm_i915_gem_context_create_ext *ctx_ext)
> +{
> +	int err = 0;
> +
> +	if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, ctx_ext)) {
> +		err = -errno;
> +		igt_assume(err != 0);
> +	}
> +	errno = 0;
> +	return err;
> +}
> +
> +/**
> + * gem_ctx_create_ext:
> + * @fd: open i915 drm file descriptor
> + * @ctx_ext: context_create_ext data structure
> + *
> + * This wraps the GEM_CONTEXT_CREATE_EXT ioctl, which allocates gem context based on
> + * additional drm_i915_gem_context_create_ext_setparam input extensions.
> + */
> +void gem_ctx_create_ext(int fd, struct drm_i915_gem_context_create_ext *ctx_ext)
> +{
> +	igt_assert_eq(__gem_ctx_create_ext(fd, ctx_ext), 0);
> +}
> +
>  /**
>   * gem_madvise:
>   * @fd: open i915 drm file descriptor
> diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
> index 9ea67365..8288c8d7 100644
> --- a/lib/ioctl_wrappers.h
> +++ b/lib/ioctl_wrappers.h
> @@ -82,6 +82,8 @@ void gem_execbuf_wr(int fd, struct drm_i915_gem_execbuffer2 *execbuf);
>  int __gem_execbuf_wr(int fd, struct drm_i915_gem_execbuffer2 *execbuf);
>  void gem_execbuf(int fd, struct drm_i915_gem_execbuffer2 *execbuf);
>  int __gem_execbuf(int fd, struct drm_i915_gem_execbuffer2 *execbuf);
> +int __gem_ctx_create_ext(int fd, struct drm_i915_gem_context_create_ext *ctx_ext);
> +void gem_ctx_create_ext(int fd, struct drm_i915_gem_context_create_ext *ctx_ext);
>  
>  #ifndef I915_GEM_DOMAIN_WC
>  #define I915_GEM_DOMAIN_WC 0x80
> -- 
> 2.25.1
> 
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Re: [igt-dev] [PATCH i-g-t 02/17] Add PXP UAPI support in i915_drm.h

[Rodrigo Vivi]

On Tue, May 18, 2021 at 03:33:29AM -0700, Alan Previn wrote:
> At the time of this commit, PXP hasnt been merged into
> upstream kernel so this has no kernel tag reference yet

chicken egg issue right, but probably better to kill this patch
and sync directly when merging, right after the kernel merged.

> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
>  include/drm-uapi/i915_drm.h | 52 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 52 insertions(+)
> 
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index d9fbf218..e67e3e5c 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -1743,6 +1743,26 @@ struct drm_i915_gem_context_param {
>   * Default is 16 KiB.
>   */
>  #define I915_CONTEXT_PARAM_RINGSIZE	0xc
> +
> +/*
> + * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + *
> + * Mark that the context makes use of protected content, which will result
> + * in the context being invalidated when the protected content session is.
> + * This flag can only be set at context creation time and, when set to true,
> + * must be preceded by an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE
> + * to false. This flag can't be set to true in conjunction with setting the
> + * I915_CONTEXT_PARAM_BANNABLE flag to false.
> + *
> + * Given the numerous restriction on this flag, there are several unique
> + * failure cases:
> + *
> + * -ENODEV: feature not available
> + * -EEXIST: trying to modify an existing context
> + * -EPERM: trying to mark a recoverable or not bannable context as protected
> + * -EACCES: submitting an invalidated context for execution
> + */
> +#define I915_CONTEXT_PARAM_PROTECTED_CONTENT    0xd
>  /* Must be kept compact -- no holes and well documented */
>  
>  	__u64 value;
> @@ -1973,6 +1993,12 @@ struct drm_i915_reg_read {
>  struct drm_i915_reset_stats {
>  	__u32 ctx_id;
>  	__u32 flags;
> +	/*
> +	 * contexts marked as using protected content are invalidated when the
> +	 * protected content session dies. Submission of invalidated contexts
> +	 * is rejected with -EACCES.
> +	 */
> +#define I915_CONTEXT_INVALIDATED 0x1
>  
>  	/* All resets since boot/module reload, for all contexts */
>  	__u32 reset_count;
> @@ -2645,6 +2671,7 @@ struct drm_i915_gem_create_ext {
>  	 * struct drm_i915_gem_create_ext_memory_regions.
>  	 */
>  #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
> +#define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1
>  	__u64 extensions;
>  };
>  
> @@ -2702,6 +2729,31 @@ struct drm_i915_gem_create_ext_memory_regions {
>  	__u64 regions;
>  };
>  
> +/*
> + * I915_OBJECT_PARAM_PROTECTED_CONTENT:
> + *
> + * If set to true, buffer contents is expected to be protected by PXP
> + * encryption and requires decryption for scan out and processing. This is
> + * only possible on platforms that have PXP enabled, on all other scenarios
> + * setting this flag will cause the ioctl to fail and return -ENODEV.
> + *
> + * The buffer contents are considered invalid after a PXP session teardown.
> + * It is recommended to use protected buffers only with contexts created
> + * using the I915_CONTEXT_PARAM_PROTECTED_CONTENT flag, as that will enable
> + * extra checks at submission time on the validity of the objects involved,
> + * which can lead to the following errors:
> + *
> + * -ENODEV: PXP session not currently active
> + * -EIO: buffer has become invalid after a teardown event
> + */
> +struct drm_i915_gem_create_ext_protected_content {
> +	struct i915_user_extension base;
> +	__u32 flags;
> +};
> +
> +/* ID of the protected content session managed by i915 when PXP is active */
> +#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
> +
>  #if defined(__cplusplus)
>  }
>  #endif
> -- 
> 2.25.1
> 
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Re: [igt-dev] [PATCH i-g-t 04/17] Add basic PXP testing of buffer and context alloc

[Rodrigo Vivi]

On Tue, May 18, 2021 at 03:33:31AM -0700, Alan Previn wrote:
> Test PXP capability support as well as the allocation of protected
> buffers and protected contexts.
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
>  tests/i915/gem_pxp.c | 353 +++++++++++++++++++++++++++++++++++++++++++
>  tests/meson.build    |   1 +
>  2 files changed, 354 insertions(+)
>  create mode 100644 tests/i915/gem_pxp.c

I'm not sure gem_pxp is the best name for this. Specially when we start
adding display cases.

Could we go with pxp.c only?

anyway, the content is great.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
> new file mode 100644
> index 00000000..8779dddc
> --- /dev/null
> +++ b/tests/i915/gem_pxp.c
> @@ -0,0 +1,353 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#include "igt.h"
> +#include "i915/gem.h"
> +
> +IGT_TEST_DESCRIPTION("Test PXP that manages protected content through arbitrated HW-PXP-session");
> +/* Note: PXP = "Protected Xe Path" */
> +
> +static bool is_pxp_hw_supported(int i915)
> +{
> +	uint32_t devid = intel_get_drm_devid(i915);
> +
> +	if (IS_TIGERLAKE(devid) || IS_ROCKETLAKE(devid) || IS_ALDERLAKE_S(devid))
> +		return true;
> +
> +	return false;
> +}
> +
> +static int create_bo_ext(int i915, uint32_t size, bool protected_is_true, uint32_t *bo_out)
> +{
> +	int ret;
> +
> +	struct drm_i915_gem_create_ext_protected_content protected_ext = {
> +		.base = { .name = I915_GEM_CREATE_EXT_PROTECTED_CONTENT },
> +		.flags = 0,
> +	};
> +
> +	struct drm_i915_gem_create_ext create_ext = {
> +		.size = size,
> +		.extensions = 0,
> +	};
> +
> +	if (protected_is_true)
> +		create_ext.extensions = (uintptr_t)&protected_ext;
> +
> +	ret = igt_ioctl(i915, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
> +	if (!ret)
> +		*bo_out = create_ext.handle;
> +
> +	return ret;
> +}
> +
> +static void test_bo_alloc_pxp_nohw(int i915)
> +{
> +	int ret;
> +	uint32_t bo;
> +
> +	ret = create_bo_ext(i915, 4096, false, &bo);
> +	igt_assert_eq(ret, 0);
> +	gem_close(i915, bo);
> +
> +	ret = create_bo_ext(i915, 4096, true, &bo);
> +	igt_assert_eq(ret, -ENODEV);
> +	igt_assert_eq(bo, 0);
> +}
> +
> +static void test_bo_alloc_pxp_off(int i915)
> +{
> +	int ret;
> +	uint32_t bo;
> +
> +	ret = create_bo_ext(i915, 4096, false, &bo);
> +	igt_assert_eq(ret, 0);
> +	gem_close(i915, bo);
> +}
> +
> +static void test_bo_alloc_pxp_on(int i915)
> +{
> +	int ret;
> +	uint32_t bo;
> +
> +	ret = create_bo_ext(i915, 4096, true, &bo);
> +	igt_assert_eq(ret, 0);
> +	gem_close(i915, bo);
> +}
> +
> +static int create_ctx_with_params(int i915, bool with_protected_param, bool protected_is_true,
> +				  bool with_recoverable_param, bool recoverable_is_true,
> +				  uint32_t *ctx_out)
> +{
> +	int ret;
> +
> +	struct drm_i915_gem_context_create_ext_setparam p_prot = {
> +		.base = {
> +			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
> +			.next_extension = 0,
> +		},
> +		.param = {
> +			.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
> +			.value = 0,
> +		}
> +	};
> +	struct drm_i915_gem_context_create_ext_setparam p_norecover = {
> +		.base = {
> +			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
> +			.next_extension = 0,
> +		},
> +		.param = {
> +			.param = I915_CONTEXT_PARAM_RECOVERABLE,
> +			.value = 0,
> +		}
> +	};
> +	struct drm_i915_gem_context_create_ext create = {
> +		.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
> +		.extensions = 0,
> +	};
> +
> +	p_prot.param.value = protected_is_true;
> +	p_norecover.param.value = recoverable_is_true;
> +
> +	if (with_protected_param && with_recoverable_param) {
> +		create.extensions = to_user_pointer(&(p_norecover.base));
> +		p_norecover.base.next_extension = to_user_pointer(&(p_prot.base));
> +	} else if (!with_protected_param && with_recoverable_param) {
> +		create.extensions = to_user_pointer(&(p_norecover.base));
> +		p_norecover.base.next_extension = 0;
> +	} else if (with_protected_param && !with_recoverable_param) {
> +		create.extensions = to_user_pointer(&(p_prot.base));
> +		p_prot.base.next_extension = 0;
> +	} else if (!with_protected_param && !with_recoverable_param) {
> +		create.flags = 0;
> +	}
> +
> +	ret = __gem_ctx_create_ext(i915, &create);
> +	if (!ret)
> +		*ctx_out = create.ctx_id;
> +
> +	return ret;
> +}
> +
> +#define CHANGE_PARAM_PROTECTED 0x0001
> +#define CHANGE_PARAM_RECOVERY 0x0002
> +
> +static int modify_ctx_param(int i915, uint32_t ctx_id, uint32_t param_mask, bool param_value)
> +{
> +	int ret;
> +
> +	struct drm_i915_gem_context_param ctx_param = {
> +		.ctx_id = ctx_id,
> +		.param = 0,
> +		.value = 0,
> +	};
> +
> +	if (param_mask == CHANGE_PARAM_PROTECTED) {
> +		ctx_param.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT;
> +		ctx_param.value = (int)param_value;
> +	} else if (param_mask == CHANGE_PARAM_RECOVERY) {
> +		ctx_param.param = I915_CONTEXT_PARAM_RECOVERABLE;
> +		ctx_param.value = (int)param_value;
> +	}
> +
> +	ret = igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &ctx_param);
> +
> +	return ret;
> +}
> +
> +static int get_ctx_protected_param(int i915, uint32_t ctx_id)
> +{
> +	int ret;
> +
> +	struct drm_i915_gem_context_param ctx_param = {
> +		.ctx_id = ctx_id,
> +		.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
> +	};
> +
> +	ret = igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &ctx_param);
> +	igt_assert_eq(ret, 0);
> +
> +	return ctx_param.value;
> +}
> +
> +static int get_ctx_recovery_param(int i915, uint32_t ctx_id)
> +{
> +	int ret;
> +
> +	struct drm_i915_gem_context_param ctx_param = {
> +		.ctx_id = ctx_id,
> +		.param = I915_CONTEXT_PARAM_RECOVERABLE,
> +	};
> +
> +	ret = igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &ctx_param);
> +	igt_assert_eq(ret, 0);
> +
> +	return ctx_param.value;
> +}
> +
> +static void test_ctx_alloc_pxp_nohw(int i915)
> +{
> +	uint32_t ctx;
> +
> +	igt_assert_eq(create_ctx_with_params(i915, true, true, true, false, &ctx), -ENODEV);
> +	igt_assert_eq(create_ctx_with_params(i915, true, false, true, false, &ctx), 0);
> +	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
> +	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
> +	gem_context_destroy(i915, ctx);
> +}
> +
> +static void test_ctx_alloc_recover_off_protect_off(int i915)
> +{
> +	uint32_t ctx;
> +
> +	igt_assert_eq(create_ctx_with_params(i915, true, false, true, false, &ctx), 0);
> +	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
> +	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
> +	gem_context_destroy(i915, ctx);
> +}
> +
> +static void test_ctx_alloc_recover_off_protect_on(int i915)
> +{
> +	uint32_t ctx;
> +
> +	igt_assert_eq(create_ctx_with_params(i915, true, true, true, false, &ctx), 0);
> +	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
> +	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
> +	gem_context_destroy(i915, ctx);
> +}
> +
> +static void test_ctx_alloc_recover_on_protect_off(int i915)
> +{
> +	uint32_t ctx;
> +
> +	igt_assert_eq(create_ctx_with_params(i915, true, false, true, true, &ctx), 0);
> +	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
> +	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 1);
> +	gem_context_destroy(i915, ctx);
> +}
> +
> +static void test_ctx_alloc_recover_on_protect_on(int i915)
> +{
> +	uint32_t ctx;
> +
> +	igt_assert_eq(create_ctx_with_params(i915, true, true, true, true, &ctx), -EPERM);
> +	igt_assert_eq(create_ctx_with_params(i915, true, true, false, false, &ctx), -EPERM);
> +}
> +
> +static void test_ctx_mod_recover_off_to_on(int i915)
> +{
> +	uint32_t ctx;
> +
> +	igt_assert_eq(create_ctx_with_params(i915, true, true, true, false, &ctx), 0);
> +	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
> +	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
> +	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_RECOVERY, true), -EPERM);
> +	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
> +	gem_context_destroy(i915, ctx);
> +}
> +
> +static void test_ctx_mod_protected_on_to_off(int i915)
> +{
> +	uint32_t ctx;
> +
> +	igt_assert_eq(create_ctx_with_params(i915, true, true, true, false, &ctx), 0);
> +	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
> +	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
> +	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_PROTECTED, false), -EPERM);
> +	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
> +	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
> +	gem_context_destroy(i915, ctx);
> +}
> +
> +static void test_ctx_mod_protected_to_all_invalid(int i915)
> +{
> +	uint32_t ctx;
> +
> +	igt_assert_eq(create_ctx_with_params(i915, true, true, true, false, &ctx), 0);
> +	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
> +	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
> +	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_RECOVERY, true), -EPERM);
> +	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_PROTECTED, false), -EPERM);
> +	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
> +	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
> +	gem_context_destroy(i915, ctx);
> +}
> +
> +static void test_ctx_mod_regular_to_all_valid(int i915)
> +{
> +	uint32_t ctx;
> +
> +	igt_assert_eq(create_ctx_with_params(i915, false, false, false, false, &ctx), 0);
> +	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
> +	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 1);
> +	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_RECOVERY, false), 0);
> +	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_PROTECTED, true), -EPERM);
> +	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
> +	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
> +	gem_context_destroy(i915, ctx);
> +}
> +
> +igt_main
> +{
> +	int i915 = -1;
> +	bool pxp_supported = false;
> +
> +	igt_fixture
> +	{
> +		i915 = drm_open_driver(DRIVER_INTEL);
> +		igt_require(i915);
> +		igt_require_gem(i915);
> +		pxp_supported = is_pxp_hw_supported(i915);
> +	}
> +
> +	igt_subtest_group {
> +		igt_fixture {
> +			igt_require((pxp_supported == 0));
> +		}
> +
> +		igt_describe("Verify protected buffer on unsupported hw:");
> +		igt_subtest("hw-rejects-pxp-buffer")
> +			test_bo_alloc_pxp_nohw(i915);
> +		igt_describe("Verify protected context on unsupported hw:");
> +		igt_subtest("hw-rejects-pxp-context")
> +			test_ctx_alloc_pxp_nohw(i915);
> +	}
> +
> +	igt_subtest_group {
> +		igt_fixture {
> +			igt_require(pxp_supported);
> +		}
> +
> +		igt_describe("Verify protected buffer on supported hw:");
> +		igt_subtest("create-regular-buffer")
> +			test_bo_alloc_pxp_off(i915);
> +		igt_subtest("create-protected-buffer")
> +			test_bo_alloc_pxp_on(i915);
> +
> +		igt_describe("Verify protected context on supported hw:");
> +		igt_subtest("create-regular-context-1")
> +			test_ctx_alloc_recover_off_protect_off(i915);
> +		igt_subtest("create-regular-context-2")
> +			test_ctx_alloc_recover_on_protect_off(i915);
> +		igt_subtest("fail-invalid-protected-context")
> +			test_ctx_alloc_recover_on_protect_on(i915);
> +		igt_subtest("create-valid-protected-context")
> +			test_ctx_alloc_recover_off_protect_on(i915);
> +
> +		igt_describe("Verify protected context integrity:");
> +		igt_subtest("reject-modify-context-protection-on")
> +			test_ctx_mod_regular_to_all_valid(i915);
> +		igt_subtest("reject-modify-context-protection-off-1")
> +			test_ctx_mod_recover_off_to_on(i915);
> +		igt_subtest("reject-modify-context-protection-off-2")
> +			test_ctx_mod_protected_on_to_off(i915);
> +		igt_subtest("reject-modify-context-protection-off-3")
> +			test_ctx_mod_protected_to_all_invalid(i915);
> +	}
> +
> +	igt_fixture {
> +		close(i915);
> +	}
> +}
> diff --git a/tests/meson.build b/tests/meson.build
> index 19cc4ebe..e0bff4d1 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -187,6 +187,7 @@ i915_progs = [
>  	'gem_pread_after_blit',
>  	'gem_pwrite',
>  	'gem_pwrite_snooped',
> +	'gem_pxp',
>  	'gem_read_read_speed',
>  	'gem_readwrite',
>  	'gem_reg_read',
> -- 
> 2.25.1
> 
> _______________________________________________
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> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t 05/17] Perform a regular 3d copy as a control checkpoint

[Rodrigo Vivi]

On Tue, May 18, 2021 at 03:33:32AM -0700, Alan Previn wrote:
> As a control checkpoint, allocate buffers to be used
> as texture and render target in the 3d engine for a
> regular src to dest copy blit and verify buffer pixels.
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  tests/i915/gem_pxp.c | 166 ++++++++++++++++++++++++++++++++++++++++---
>  1 file changed, 157 insertions(+), 9 deletions(-)
> 
> diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
> index 8779dddc..b1415efc 100644
> --- a/tests/i915/gem_pxp.c
> +++ b/tests/i915/gem_pxp.c
> @@ -236,6 +236,20 @@ static void test_ctx_alloc_recover_on_protect_on(int i915)
>  	igt_assert_eq(create_ctx_with_params(i915, true, true, false, false, &ctx), -EPERM);
>  }
>  
> +static void test_ctx_mod_regular_to_all_valid(int i915)
> +{
> +	uint32_t ctx;
> +
> +	igt_assert_eq(create_ctx_with_params(i915, false, false, false, false, &ctx), 0);
> +	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
> +	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 1);
> +	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_RECOVERY, false), 0);
> +	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_PROTECTED, true), -EPERM);
> +	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
> +	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
> +	gem_context_destroy(i915, ctx);
> +}
> +
>  static void test_ctx_mod_recover_off_to_on(int i915)
>  {
>  	uint32_t ctx;
> @@ -275,24 +289,145 @@ static void test_ctx_mod_protected_to_all_invalid(int i915)
>  	gem_context_destroy(i915, ctx);
>  }
>  
> -static void test_ctx_mod_regular_to_all_valid(int i915)
> +static void fill_bo_content(int i915, uint32_t bo, uint32_t size, uint32_t initcolor)
>  {
> -	uint32_t ctx;
> +	uint32_t *ptr, *ptrtmp;
> +	int loop = 0;
>  
> -	igt_assert_eq(create_ctx_with_params(i915, false, false, false, false, &ctx), 0);
> -	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
> -	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 1);
> -	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_RECOVERY, false), 0);
> -	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_PROTECTED, true), -EPERM);
> -	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
> -	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
> +	ptr = gem_mmap__device_coherent(i915, bo, 0, size, PROT_WRITE);
> +	ptrtmp = ptr;
> +
> +	/* read and count all dword matches till size */
> +	while (loop++ < (size/4)) {
> +		*ptrtmp = initcolor;
> +		++ptrtmp;
> +	}
> +
> +	igt_assert(gem_munmap(ptr, size) == 0);
> +}
> +
> +#define COMPARE_COLOR_READIBLE     1
> +#define COMPARE_COLOR_UNREADIBLE   2
> +#define COMPARE_N_PIXELS_VERBOSELY 0
> +
> +static void assert_bo_content_check(int i915, uint32_t bo, int compare_op,
> +				    uint32_t size, uint32_t color)
> +{
> +	uint32_t *ptr, *ptrtmp;
> +	int loop = 0, num_matches = 0;
> +	uint32_t value;
> +	bool op_readible = (compare_op == COMPARE_COLOR_READIBLE);
> +
> +	ptr = gem_mmap__device_coherent(i915, bo, 0, size, PROT_READ);
> +	ptrtmp = ptr;
> +
> +	if (COMPARE_N_PIXELS_VERBOSELY) {
> +		igt_info("--------->>>\n");
> +		while (loop < COMPARE_N_PIXELS_VERBOSELY && loop < (size/4)) {
> +			value = *ptrtmp;
> +			igt_info("Color read = 0x%08x ", value);
> +			igt_info("expected %c= 0x%08x)\n", op_readible?'=':'!', color);
> +			++ptrtmp;
> +			++loop;
> +		}
> +		igt_info("<<<---------\n");
> +		ptrtmp = ptr;
> +		loop = 0;
> +	}
> +
> +	/* count all pixels for matches */
> +	while (loop++ < (size/4)) {
> +		value = *ptrtmp;
> +		if (value == color)
> +			++num_matches;
> +		++ptrtmp;
> +	}
> +
> +	if (op_readible)
> +		igt_assert_eq(num_matches, (size/4));
> +	else
> +		igt_assert_eq(num_matches, 0);
> +
> +	igt_assert(gem_munmap(ptr, size) == 0);
> +}
> +
> +static uint32_t alloc_and_fill_dest_buff(int i915, bool protected, uint32_t size,
> +					 uint32_t init_color)
> +{
> +	uint32_t bo;
> +	int ret;
> +
> +	ret = create_bo_ext(i915, size, protected, &bo);
> +	igt_assert_eq(ret, 0);
> +	igt_assert(bo);
> +	fill_bo_content(i915, bo, size, init_color);
> +	assert_bo_content_check(i915, bo, COMPARE_COLOR_READIBLE, size, init_color);
> +
> +	return bo;
> +}
> +
> +/*
> + * Rendering tests surface attributes, keep it simple:
> + * page aligned width==stride, thus, and size
> + */
> +#define TSTSURF_WIDTH       1024
> +#define TSTSURF_HEIGHT      128
> +#define TSTSURF_BYTESPP     4
> +#define TSTSURF_STRIDE      (TSTSURF_WIDTH*TSTSURF_BYTESPP)
> +#define TSTSURF_SIZE        (TSTSURF_STRIDE*TSTSURF_HEIGHT)
> +#define TSTSURF_FILLCOLOR1  0xfaceface
> +#define TSTSURF_INITCOLOR1  0x12341234
> +
> +static void test_render_baseline(int i915)
> +{
> +	uint32_t ctx, srcbo, dstbo;
> +	struct intel_buf *srcbuf, *dstbuf;
> +	struct buf_ops *bops;
> +	struct intel_bb *ibb;
> +	uint32_t devid;
> +	int ret;
> +
> +	devid = intel_get_drm_devid(i915);
> +	igt_assert(devid);
> +
> +	bops = buf_ops_create(i915);
> +	igt_assert(bops);
> +
> +	/* Perform a regular 3d copy as a control checkpoint */
> +	ret = create_ctx_with_params(i915, false, false, false, false, &ctx);
> +	igt_assert_eq(ret, 0);
> +	ibb = intel_bb_create_with_context(i915, ctx, 4096);
> +	igt_assert(ibb);
> +
> +	dstbo = alloc_and_fill_dest_buff(i915, false, TSTSURF_SIZE, TSTSURF_INITCOLOR1);
> +	dstbuf = intel_buf_create_using_handle(bops, dstbo, TSTSURF_WIDTH, TSTSURF_HEIGHT,
> +					       TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
> +
> +	srcbo = alloc_and_fill_dest_buff(i915, false, TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
> +	srcbuf = intel_buf_create_using_handle(bops, srcbo, TSTSURF_WIDTH, TSTSURF_HEIGHT,
> +					       TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
> +
> +	gen12_render_copyfunc(ibb, srcbuf, 0, 0, TSTSURF_WIDTH, TSTSURF_HEIGHT, dstbuf, 0, 0);
> +	gem_sync(i915, dstbo);
> +
> +	assert_bo_content_check(i915, dstbo, COMPARE_COLOR_READIBLE,
> +				TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
> +
> +	intel_bb_destroy(ibb);
> +	intel_buf_destroy(srcbuf);
> +	gem_close(i915, srcbo);
> +	intel_buf_destroy(dstbuf);
> +	gem_close(i915, dstbo);
>  	gem_context_destroy(i915, ctx);
> +	buf_ops_destroy(bops);
>  }
>  
>  igt_main
>  {
>  	int i915 = -1;
>  	bool pxp_supported = false;
> +	igt_render_copyfunc_t rendercopy = NULL;
> +	uint32_t devid = 0;
>  
>  	igt_fixture
>  	{
> @@ -346,6 +481,19 @@ igt_main
>  		igt_subtest("reject-modify-context-protection-off-3")
>  			test_ctx_mod_protected_to_all_invalid(i915);
>  	}
> +	igt_subtest_group {
> +		igt_fixture {
> +			igt_require(pxp_supported);
> +			devid = intel_get_drm_devid(i915);
> +			igt_assert(devid);
> +			rendercopy = igt_get_render_copyfunc(devid);
> +			igt_require(rendercopy);
> +		}
> +
> +		igt_describe("Verify protected render operations:");
> +		igt_subtest("regular-baseline-src-copy-readible")
> +			test_render_baseline(i915);
> +	}
>  
>  	igt_fixture {
>  		close(i915);
> -- 
> 2.25.1
> 
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t 07/17] Add MI_SET_APPID instruction definition

[Rodrigo Vivi]

On Tue, May 18, 2021 at 03:33:34AM -0700, Alan Previn wrote:
> Add MI_SET_APPID instruction and param definitions
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
>  lib/intel_reg.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> index ac1fc6cb..46b5da20 100644
> --- a/lib/intel_reg.h
> +++ b/lib/intel_reg.h
> @@ -2546,6 +2546,15 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>  #define CTXT_PALETTE_SAVE_DISABLE	(1<<3)
>  #define CTXT_PALETTE_RESTORE_DISABLE	(1<<2)
>  
> +#define MI_SET_APPID                    (0x0E << 23)
> +#define APPID_CTXSAVE_INHIBIT           (1 << 8)
> +#define APPID_CTXREST_INHIBIT           (1 << 9)
> +#define DISPLAY_APPTYPE                 (0)
> +#define TRANSCODE_APPTYPE               (1)
> +#define APPTYPE(n)                      (n << 7)
> +#define APPID(n)                        (n & 0x7f)

What about sorting the bits?

anyway
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


> +
> +
>  /* Dword 0 */
>  #define MI_VERTEX_BUFFER		(0x17<<23)
>  #define MI_VERTEX_BUFFER_IDX(x)		(x<<20)
> -- 
> 2.25.1
> 
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Re: [igt-dev] ✗ Fi.CI.IGT: failure for Introduce PXP Test (rev5)

[Rodrigo Vivi]

On Tue, May 18, 2021 at 06:19:48PM -0000, Patchwork wrote:
>    Patch Details
> 
>    Series:  Introduce PXP Test (rev5)
>    URL:     [1]https://patchwork.freedesktop.org/series/87570/
>    State:   failure
>    Details:
>    [2]https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/index.html
> 
>            CI Bug Log - changes from IGT_6087_full -> IGTPW_5817_full
> 
> Summary
> 
>    FAILURE
> 
>    Serious unknown changes coming with IGTPW_5817_full absolutely need to
>    be
>    verified manually.
> 
>    If you think the reported changes have nothing to do with the changes
>    introduced in IGTPW_5817_full, please notify your bug team to allow
>    them
>    to document this new failure mode, which will reduce false positives in
>    CI.
> 
>    External URL:
>    https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/index.html
> 
> Possible new issues
> 
>    Here are the unknown changes that may have been introduced in
>    IGTPW_5817_full:
> 
>   IGT changes
> 
>     Possible regressions
> 
>      * igt@gem_mmap_gtt@cpuset-basic-small-copy-xy:
>           + shard-snb: NOTRUN -> [3]INCOMPLETE
>      * igt@gem_ppgtt@blt-vs-render-ctx0:
>           + shard-apl: [4]PASS -> [5]FAIL

since we are touching the render path for gen9+ we need to pay attention
to cases like this...

>      * {igt@gem_pxp@create-regular-context-1} (NEW):
>           + shard-iclb: NOTRUN -> [6]SKIP +12 similar issues
>      * {igt@gem_pxp@hw-rejects-pxp-context} (NEW):
>           + shard-glk: NOTRUN -> [7]FAIL
>           + shard-iclb: NOTRUN -> [8]FAIL
>           + shard-snb: NOTRUN -> [9]FAIL
>           + shard-kbl: NOTRUN -> [10]FAIL
>      * {igt@gem_pxp@protected-encrypted-src-copy-not-readible} (NEW):
>           + shard-tglb: NOTRUN -> [11]FAIL +10 similar issues
>      * igt@i915_selftest@perf@request:
>           + shard-tglb: [12]PASS -> [13]DMESG-FAIL
>      * igt@kms_flip_tiling@flip-changes-tiling-y@hdmi-a-2-pipe-a:
>           + shard-glk: [14]PASS -> [15]FAIL +5 similar issues
> 
>     Suppressed
> 
>    The following results come from untrusted machines, tests, or statuses.
>    They do not affect the overall result.
>      * {igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes}:
>           + shard-glk: [16]PASS -> [17]FAIL
> 
> New tests
> 
>    New tests have been introduced between IGT_6087_full and
>    IGTPW_5817_full:
> 
>   New IGT tests (20)
> 
>      * igt@gem_pxp@create-protected-buffer:
>           + Statuses : 1 fail(s) 4 skip(s)
>           + Exec time: [0.0, 0.01] s
>      * igt@gem_pxp@create-regular-buffer:
>           + Statuses :
>           + Exec time: [None] s
>      * igt@gem_pxp@create-regular-context-1:
>           + Statuses : 1 fail(s) 4 skip(s)
>           + Exec time: [0.0, 0.01] s
>      * igt@gem_pxp@create-regular-context-2:
>           + Statuses : 1 fail(s) 4 skip(s)
>           + Exec time: [0.0, 0.02] s
>      * igt@gem_pxp@create-valid-protected-context:
>           + Statuses : 1 fail(s) 4 skip(s)
>           + Exec time: [0.0, 0.01] s
>      * igt@gem_pxp@display-protected-crc-with-hdcp:
>           + Statuses : 1 fail(s) 4 skip(s)
>           + Exec time: [0.0, 0.01] s
>      * igt@gem_pxp@display-protected-crc-without-hdcp:
>           + Statuses : 1 fail(s) 2 skip(s)
>           + Exec time: [0.0, 0.01] s
>      * igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
>           + Statuses : 1 fail(s) 4 skip(s)
>           + Exec time: [0.0, 0.03] s
>      * igt@gem_pxp@fail-invalid-protected-context:
>           + Statuses : 1 skip(s)
>           + Exec time: [0.0] s
>      * igt@gem_pxp@hw-rejects-pxp-buffer:
>           + Statuses :
>           + Exec time: [None] s
>      * igt@gem_pxp@hw-rejects-pxp-context:
>           + Statuses : 4 fail(s)
>           + Exec time: [0.01, 0.02] s
>      * igt@gem_pxp@protected-encrypted-src-copy-not-readible:
>           + Statuses : 1 fail(s) 5 skip(s)
>           + Exec time: [0.0, 0.01] s
>      * igt@gem_pxp@protected-raw-src-copy-not-readible:
>           + Statuses : 1 fail(s) 3 skip(s)
>           + Exec time: [0.0, 0.01] s
>      * igt@gem_pxp@regular-baseline-src-copy-readible:
>           + Statuses : 1 pass(s) 2 skip(s)
>           + Exec time: [0.0, 0.01] s
>      * igt@gem_pxp@reject-modify-context-protection-off-1:
>           + Statuses : 1 skip(s)
>           + Exec time: [0.0] s
>      * igt@gem_pxp@reject-modify-context-protection-off-2:
>           + Statuses :
>           + Exec time: [None] s
>      * igt@gem_pxp@reject-modify-context-protection-off-3:
>           + Statuses : 3 skip(s)
>           + Exec time: [0.0] s
>      * igt@gem_pxp@reject-modify-context-protection-on:
>           + Statuses : 1 fail(s) 5 skip(s)
>           + Exec time: [0.0, 0.00] s
>      * igt@gem_pxp@verify-pxp-execution-behavior-after-suspend-resume:
>           + Statuses :
>           + Exec time: [None] s
>      * igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
>           + Statuses : 1 fail(s) 5 skip(s)
>           + Exec time: [0.0, 0.01] s
> 
> Known issues
> 
>    Here are the changes found in IGTPW_5817_full that come from known
>    issues:
> 
>   IGT changes
> 
>     Issues hit
> 
>      * igt@api_intel_bb@blit-noreloc-purge-cache:
>           + shard-iclb: NOTRUN -> [18]DMESG-WARN ([i915#3457]) +3 similar
>             issues
>           + shard-glk: NOTRUN -> [19]DMESG-FAIL ([i915#3457]) +2 similar
>             issues
>      * igt@api_intel_bb@offset-control:
>           + shard-apl: NOTRUN -> [20]DMESG-WARN ([i915#3457]) +1 similar
>             issue
>           + shard-glk: NOTRUN -> [21]DMESG-WARN ([i915#3457])
>      * igt@feature_discovery@chamelium:
>           + shard-tglb: NOTRUN -> [22]SKIP ([fdo#111827])
>           + shard-iclb: NOTRUN -> [23]SKIP ([fdo#111827])
>      * igt@gem_create@create-massive:
>           + shard-iclb: NOTRUN -> [24]DMESG-WARN ([i915#3002])
>           + shard-kbl: NOTRUN -> [25]DMESG-WARN ([i915#3002])
>           + shard-tglb: NOTRUN -> [26]DMESG-WARN ([i915#3002])
>           + shard-glk: NOTRUN -> [27]DMESG-WARN ([i915#3002])
>      * igt@gem_ctx_isolation@preservation-s3@vcs0:
>           + shard-kbl: NOTRUN -> [28]DMESG-WARN ([i915#180] / [i915#3457])
>             +4 similar issues
>      * igt@gem_ctx_persistence@legacy-engines-hostile:
>           + shard-snb: NOTRUN -> [29]SKIP ([fdo#109271] / [i915#1099]) +2
>             similar issues
>      * igt@gem_ctx_persistence@many-contexts:
>           + shard-glk: [30]PASS -> [31]DMESG-WARN ([i915#118] /
>             [i915#3457] / [i915#95])
>      * igt@gem_eio@unwedge-stress:
>           + shard-apl: NOTRUN -> [32]FAIL ([i915#3457]) +10 similar issues
>           + shard-snb: NOTRUN -> [33]FAIL ([i915#3354] / [i915#3457])
>      * igt@gem_exec_endless@dispatch@vecs0:
>           + shard-apl: NOTRUN -> [34]INCOMPLETE ([i915#2502] /
>             [i915#3457])
>      * igt@gem_exec_fair@basic-none-rrul@rcs0:
>           + shard-iclb: NOTRUN -> [35]FAIL ([i915#2842] / [i915#3457]) +5
>             similar issues
>           + shard-glk: NOTRUN -> [36]INCOMPLETE ([i915#3457]) +1 similar
>             issue
>      * igt@gem_exec_fair@basic-none@vcs0:
>           + shard-tglb: NOTRUN -> [37]FAIL ([i915#2842] / [i915#3457]) +5
>             similar issues
>      * igt@gem_exec_fair@basic-none@vcs1:
>           + shard-kbl: NOTRUN -> [38]FAIL ([i915#2842] / [i915#3457])
>      * igt@gem_exec_fair@basic-pace@rcs0:
>           + shard-tglb: [39]PASS -> [40]FAIL ([i915#2842] / [i915#3457])
>      * igt@gem_exec_fair@basic-pace@vcs0:
>           + shard-iclb: [41]PASS -> [42]FAIL ([i915#2842] / [i915#3457])
>      * igt@gem_exec_fair@basic-pace@vcs1:
>           + shard-kbl: [43]PASS -> [44]FAIL ([i915#2842] / [i915#3457])
>      * igt@gem_exec_schedule@preempt-hang@vcs0:
>           + shard-glk: [45]PASS -> [46]FAIL ([i915#3457]) +28 similar
>             issues
>      * igt@gem_exec_schedule@submit-early-slice@vecs0:
>           + shard-glk: NOTRUN -> [47]FAIL ([i915#3457]) +50 similar issues
>      * igt@gem_exec_whisper@basic-contexts-all:
>           + shard-glk: NOTRUN -> [48]DMESG-WARN ([i915#118] / [i915#95])
>      * igt@gem_huc_copy@huc-copy:
>           + shard-tglb: [49]PASS -> [50]SKIP ([i915#2190])
>      * igt@gem_mmap_gtt@cpuset-basic-small-copy:
>           + shard-snb: NOTRUN -> [51]INCOMPLETE ([i915#3468]) +1 similar
>             issue
>           + shard-kbl: [52]PASS -> [53]INCOMPLETE ([i915#3468])
>      * igt@gem_mmap_gtt@cpuset-basic-small-copy-xy:
>           + shard-tglb: NOTRUN -> [54]INCOMPLETE ([i915#3468]) +2 similar
>             issues
>           + shard-kbl: NOTRUN -> [55]INCOMPLETE ([i915#3468]) +3 similar
>             issues
>      * igt@gem_mmap_offset@clear:
>           + shard-glk: NOTRUN -> [56]FAIL ([i915#1888] / [i915#3160])
>      * igt@gem_pwrite@basic-exhaustion:
>           + shard-apl: NOTRUN -> [57]WARN ([i915#2658])
>      * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
>           + shard-apl: NOTRUN -> [58]INCOMPLETE ([i915#3468])
>      * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled:
>           + shard-iclb: NOTRUN -> [59]SKIP ([i915#768]) +4 similar issues
>      * igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled:
>           + shard-iclb: NOTRUN -> [60]INCOMPLETE ([i915#3468]) +2 similar
>             issues
>           + shard-glk: NOTRUN -> [61]INCOMPLETE ([i915#3468]) +2 similar
>             issues
>           + shard-tglb: NOTRUN -> [62]INCOMPLETE ([i915#3457] /
>             [i915#3468])
>      * igt@gem_softpin@evict-snoop-interruptible:
>           + shard-tglb: NOTRUN -> [63]SKIP ([fdo#109312])
>           + shard-iclb: NOTRUN -> [64]SKIP ([fdo#109312])
>      * igt@gem_userptr_blits@dmabuf-sync:
>           + shard-apl: NOTRUN -> [65]SKIP ([fdo#109271] / [i915#3323])
>      * igt@gem_userptr_blits@dmabuf-unsync:
>           + shard-tglb: NOTRUN -> [66]SKIP ([i915#3297]) +2 similar issues
>           + shard-iclb: NOTRUN -> [67]SKIP ([i915#3297]) +3 similar issues
>      * igt@gem_wait@await@bcs0:
>           + shard-apl: [68]PASS -> [69]FAIL ([i915#3457]) +1 similar issue
>      * igt@gen3_render_linear_blits:
>           + shard-tglb: NOTRUN -> [70]SKIP ([fdo#109289]) +4 similar
>             issues
>           + shard-iclb: NOTRUN -> [71]SKIP ([fdo#109289]) +3 similar
>             issues
>      * igt@gen7_exec_parse@basic-offset:
>           + shard-apl: NOTRUN -> [72]SKIP ([fdo#109271]) +171 similar
>             issues
>      * igt@gen9_exec_parse@allowed-all:
>           + shard-iclb: NOTRUN -> [73]SKIP ([fdo#112306]) +4 similar
>             issues
>      * igt@gen9_exec_parse@bb-start-out:
>           + shard-tglb: NOTRUN -> [74]SKIP ([fdo#112306]) +3 similar
>             issues
>      * igt@i915_hangman@error-state-capture@bcs0:
>           + shard-snb: NOTRUN -> [75]DMESG-WARN ([i915#3457]) +2 similar
>             issues
>      * igt@i915_module_load@reload:
>           + shard-tglb: NOTRUN -> [76]DMESG-WARN ([i915#3457]) +3 similar
>             issues
>           + shard-kbl: NOTRUN -> [77]DMESG-WARN ([i915#3457]) +5 similar
>             issues
>      * igt@i915_pm_dc@dc9-dpms:
>           + shard-tglb: NOTRUN -> [78]SKIP ([i915#3288])
>           + shard-iclb: NOTRUN -> [79]FAIL ([i915#3343])
>      * igt@i915_pm_rpm@cursor:
>           + shard-tglb: [80]PASS -> [81]DMESG-WARN ([i915#2411] /
>             [i915#3457]) +1 similar issue
>           + shard-kbl: [82]PASS -> [83]DMESG-WARN ([i915#3457])
>           + shard-glk: [84]PASS -> [85]DMESG-WARN ([i915#3457])
>      * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
>           + shard-iclb: NOTRUN -> [86]SKIP ([fdo#110892]) +1 similar issue
>      * igt@i915_pm_rps@reset:
>           + shard-apl: NOTRUN -> [87]DMESG-FAIL ([i915#3457]) +2 similar
>             issues
>      * igt@kms_atomic@plane-immutable-zpos:
>           + shard-glk: [88]PASS -> [89]FAIL ([i915#2657] / [i915#3457])
>      * igt@kms_big_fb@linear-16bpp-rotate-90:
>           + shard-iclb: NOTRUN -> [90]SKIP ([fdo#110725] / [fdo#111614])
>             +6 similar issues
>           + shard-tglb: NOTRUN -> [91]SKIP ([fdo#111614]) +6 similar
>             issues
>      * igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
>           + shard-tglb: NOTRUN -> [92]SKIP ([fdo#111615]) +3 similar
>             issues
>      * igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
>           + shard-iclb: NOTRUN -> [93]SKIP ([fdo#110723])
>      * igt@kms_big_joiner@invalid-modeset:
>           + shard-iclb: NOTRUN -> [94]SKIP ([i915#2705])
>           + shard-kbl: NOTRUN -> [95]SKIP ([fdo#109271] / [i915#2705])
>           + shard-apl: NOTRUN -> [96]SKIP ([fdo#109271] / [i915#2705])
>           + shard-glk: NOTRUN -> [97]SKIP ([fdo#109271] / [i915#2705])
>           + shard-tglb: NOTRUN -> [98]SKIP ([i915#2705])
>      * igt@kms_chamelium@dp-hpd-storm-disable:
>           + shard-glk: NOTRUN -> [99]SKIP ([fdo#109271] / [fdo#111827])
>             +19 similar issues
>      * igt@kms_chamelium@dp-mode-timings:
>           + shard-apl: NOTRUN -> [100]SKIP ([fdo#109271] / [fdo#111827])
>             +15 similar issues
>      * igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
>           + shard-snb: NOTRUN -> [101]SKIP ([fdo#109271] / [fdo#111827])
>             +16 similar issues
>      * igt@kms_chamelium@hdmi-hpd-storm:
>           + shard-kbl: NOTRUN -> [102]SKIP ([fdo#109271] / [fdo#111827])
>             +30 similar issues
>      * igt@kms_color@pipe-b-degamma:
>           + shard-tglb: NOTRUN -> [103]FAIL ([i915#1149])
>           + shard-glk: NOTRUN -> [104]FAIL ([i915#71])
>           + shard-iclb: NOTRUN -> [105]FAIL ([i915#1149])
>      * igt@kms_color@pipe-c-degamma:
>           + shard-glk: [106]PASS -> [107]FAIL ([i915#71]) +1 similar issue
>      * igt@kms_color@pipe-d-ctm-0-25:
>           + shard-iclb: NOTRUN -> [108]SKIP ([fdo#109278] / [i915#1149])
>             +2 similar issues
>      * igt@kms_color_chamelium@pipe-b-ctm-0-75:
>           + shard-tglb: NOTRUN -> [109]SKIP ([fdo#109284] / [fdo#111827])
>             +21 similar issues
>      * igt@kms_color_chamelium@pipe-b-ctm-red-to-blue:
>           + shard-iclb: NOTRUN -> [110]SKIP ([fdo#109284] / [fdo#111827])
>             +19 similar issues
>      * igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
>           + shard-iclb: NOTRUN -> [111]SKIP ([fdo#109278] / [fdo#109284] /
>             [fdo#111827]) +1 similar issue
>      * igt@kms_content_protection@atomic-dpms:
>           + shard-kbl: NOTRUN -> [112]TIMEOUT ([i915#1319])
>      * igt@kms_content_protection@dp-mst-lic-type-1:
>           + shard-iclb: NOTRUN -> [113]SKIP ([i915#3116])
>           + shard-tglb: NOTRUN -> [114]SKIP ([i915#3116])
>      * igt@kms_content_protection@uevent:
>           + shard-kbl: NOTRUN -> [115]FAIL ([i915#2105])
>           + shard-tglb: NOTRUN -> [116]SKIP ([fdo#111828])
>           + shard-iclb: NOTRUN -> [117]SKIP ([fdo#109300] / [fdo#111066])
>      * igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen:
>           + shard-snb: NOTRUN -> [118]FAIL ([i915#3457]) +4 similar issues
>      * igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding:
>           + shard-tglb: NOTRUN -> [119]SKIP ([i915#3319] / [i915#3457]) +6
>             similar issues
>      * igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen:
>           + shard-kbl: NOTRUN -> [120]FAIL ([i915#3444] / [i915#3457]) +16
>             similar issues
>      * igt@kms_cursor_crc@pipe-a-cursor-dpms:
>           + shard-apl: [121]PASS -> [122]FAIL ([i915#3444] / [i915#3457])
>      * igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen:
>           + shard-iclb: NOTRUN -> [123]SKIP ([fdo#109278] / [fdo#109279] /
>             [i915#3457]) +6 similar issues
>      * igt@kms_cursor_crc@pipe-b-cursor-64x21-random:
>           + shard-apl: NOTRUN -> [124]FAIL ([i915#3444] / [i915#3457]) +3
>             similar issues
>      * igt@kms_cursor_crc@pipe-b-cursor-64x64-random:
>           + shard-iclb: NOTRUN -> [125]FAIL ([i915#3457]) +13 similar
>             issues
>           + shard-glk: NOTRUN -> [126]FAIL ([i915#3444] / [i915#3457]) +11
>             similar issues
>      * igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque:
>           + shard-glk: [127]PASS -> [128]FAIL ([i915#3444] / [i915#3457])
>             +4 similar issues
>           + shard-kbl: [129]PASS -> [130]FAIL ([i915#3444] / [i915#3457])
>      * igt@kms_cursor_crc@pipe-b-cursor-dpms:
>           + shard-iclb: [131]PASS -> [132]FAIL ([i915#3457]) +1 similar
>             issue
>      * igt@kms_cursor_crc@pi
> 
> References
> 
>    1. https://patchwork.freedesktop.org/series/87570/
>    2. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/index.html
>    3. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb5/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
>    4. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-apl7/igt@gem_ppgtt@blt-vs-render-ctx0.html
>    5. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@gem_ppgtt@blt-vs-render-ctx0.html
>    6. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb3/igt@gem_pxp@create-regular-context-1.html
>    7. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk6/igt@gem_pxp@hw-rejects-pxp-context.html
>    8. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb5/igt@gem_pxp@hw-rejects-pxp-context.html
>    9. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb6/igt@gem_pxp@hw-rejects-pxp-context.html
>   10. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl1/igt@gem_pxp@hw-rejects-pxp-context.html
>   11. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
>   12. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-tglb3/igt@i915_selftest@perf@request.html
>   13. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb6/igt@i915_selftest@perf@request.html
>   14. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk6/igt@kms_flip_tiling@flip-changes-tiling-y@hdmi-a-2-pipe-a.html
>   15. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk3/igt@kms_flip_tiling@flip-changes-tiling-y@hdmi-a-2-pipe-a.html
>   16. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
>   17. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
>   18. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb7/igt@api_intel_bb@blit-noreloc-purge-cache.html
>   19. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk3/igt@api_intel_bb@blit-noreloc-purge-cache.html
>   20. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@api_intel_bb@offset-control.html
>   21. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk1/igt@api_intel_bb@offset-control.html
>   22. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb2/igt@feature_discovery@chamelium.html
>   23. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@feature_discovery@chamelium.html
>   24. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb6/igt@gem_create@create-massive.html
>   25. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@gem_create@create-massive.html
>   26. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@gem_create@create-massive.html
>   27. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@gem_create@create-massive.html
>   28. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html
>   29. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb7/igt@gem_ctx_persistence@legacy-engines-hostile.html
>   30. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk5/igt@gem_ctx_persistence@many-contexts.html
>   31. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@gem_ctx_persistence@many-contexts.html
>   32. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@gem_eio@unwedge-stress.html
>   33. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb5/igt@gem_eio@unwedge-stress.html
>   34. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl6/igt@gem_exec_endless@dispatch@vecs0.html
>   35. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@gem_exec_fair@basic-none-rrul@rcs0.html
>   36. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
>   37. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@gem_exec_fair@basic-none@vcs0.html
>   38. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl3/igt@gem_exec_fair@basic-none@vcs1.html
>   39. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-tglb2/igt@gem_exec_fair@basic-pace@rcs0.html
>   40. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb6/igt@gem_exec_fair@basic-pace@rcs0.html
>   41. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-iclb8/igt@gem_exec_fair@basic-pace@vcs0.html
>   42. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@gem_exec_fair@basic-pace@vcs0.html
>   43. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html
>   44. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
>   45. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk2/igt@gem_exec_schedule@preempt-hang@vcs0.html
>   46. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk8/igt@gem_exec_schedule@preempt-hang@vcs0.html
>   47. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@gem_exec_schedule@submit-early-slice@vecs0.html
>   48. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@gem_exec_whisper@basic-contexts-all.html
>   49. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-tglb2/igt@gem_huc_copy@huc-copy.html
>   50. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb6/igt@gem_huc_copy@huc-copy.html
>   51. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb7/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
>   52. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-kbl1/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
>   53. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl4/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
>   54. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb2/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
>   55. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl6/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
>   56. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@gem_mmap_offset@clear.html
>   57. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl6/igt@gem_pwrite@basic-exhaustion.html
>   58. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl6/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html
>   59. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
>   60. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb1/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled.html
>   61. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk5/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled.html
>   62. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled.html
>   63. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb6/igt@gem_softpin@evict-snoop-interruptible.html
>   64. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb6/igt@gem_softpin@evict-snoop-interruptible.html
>   65. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@gem_userptr_blits@dmabuf-sync.html
>   66. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@gem_userptr_blits@dmabuf-unsync.html
>   67. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb4/igt@gem_userptr_blits@dmabuf-unsync.html
>   68. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-apl7/igt@gem_wait@await@bcs0.html
>   69. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@gem_wait@await@bcs0.html
>   70. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb2/igt@gen3_render_linear_blits.html
>   71. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb7/igt@gen3_render_linear_blits.html
>   72. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@gen7_exec_parse@basic-offset.html
>   73. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@gen9_exec_parse@allowed-all.html
>   74. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@gen9_exec_parse@bb-start-out.html
>   75. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb7/igt@i915_hangman@error-state-capture@bcs0.html
>   76. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb2/igt@i915_module_load@reload.html
>   77. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@i915_module_load@reload.html
>   78. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@i915_pm_dc@dc9-dpms.html
>   79. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb1/igt@i915_pm_dc@dc9-dpms.html
>   80. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-tglb6/igt@i915_pm_rpm@cursor.html
>   81. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb6/igt@i915_pm_rpm@cursor.html
>   82. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-kbl2/igt@i915_pm_rpm@cursor.html
>   83. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl3/igt@i915_pm_rpm@cursor.html
>   84. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk7/igt@i915_pm_rpm@cursor.html
>   85. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk2/igt@i915_pm_rpm@cursor.html
>   86. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb5/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
>   87. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@i915_pm_rps@reset.html
>   88. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk3/igt@kms_atomic@plane-immutable-zpos.html
>   89. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk8/igt@kms_atomic@plane-immutable-zpos.html
>   90. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb5/igt@kms_big_fb@linear-16bpp-rotate-90.html
>   91. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@kms_big_fb@linear-16bpp-rotate-90.html
>   92. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html
>   93. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb1/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
>   94. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb3/igt@kms_big_joiner@invalid-modeset.html
>   95. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@kms_big_joiner@invalid-modeset.html
>   96. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@kms_big_joiner@invalid-modeset.html
>   97. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@kms_big_joiner@invalid-modeset.html
>   98. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@kms_big_joiner@invalid-modeset.html
>   99. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk3/igt@kms_chamelium@dp-hpd-storm-disable.html
>  100. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl6/igt@kms_chamelium@dp-mode-timings.html
>  101. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb6/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
>  102. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@kms_chamelium@hdmi-hpd-storm.html
>  103. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@kms_color@pipe-b-degamma.html
>  104. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk3/igt@kms_color@pipe-b-degamma.html
>  105. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb5/igt@kms_color@pipe-b-degamma.html
>  106. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk5/igt@kms_color@pipe-c-degamma.html
>  107. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk6/igt@kms_color@pipe-c-degamma.html
>  108. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb5/igt@kms_color@pipe-d-ctm-0-25.html
>  109. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@kms_color_chamelium@pipe-b-ctm-0-75.html
>  110. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@kms_color_chamelium@pipe-b-ctm-red-to-blue.html
>  111. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb7/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
>  112. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@kms_content_protection@atomic-dpms.html
>  113. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb7/igt@kms_content_protection@dp-mst-lic-type-1.html
>  114. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb2/igt@kms_content_protection@dp-mst-lic-type-1.html
>  115. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@kms_content_protection@uevent.html
>  116. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@kms_content_protection@uevent.html
>  117. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb1/igt@kms_content_protection@uevent.html
>  118. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb5/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html
>  119. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding.html
>  120. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html
>  121. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-dpms.html
>  122. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-dpms.html
>  123. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb6/igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen.html
>  124. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@kms_cursor_crc@pipe-b-cursor-64x21-random.html
>  125. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb7/igt@kms_cursor_crc@pipe-b-cursor-64x64-random.html
>  126. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk1/igt@kms_cursor_crc@pipe-b-cursor-64x64-random.html
>  127. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk8/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
>  128. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk3/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
>  129. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
>  130. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
>  131. https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-iclb5/igt@kms_cursor_crc@pipe-b-cursor-dpms.html
>  132. https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb1/igt@kms_cursor_crc@pipe-b-cursor-dpms.html

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Re: [igt-dev] [PATCH i-g-t 01/17] Sync i915_drm.h UAPI from kernel

[Teres Alexis, Alan Previn]

Got it - will fix this accordingly.
However, I will wait for another kernel rev before i sync and push the
next rev of this series. (due to new issues being resolved on recent
kernel patches)

On Wed, 2021-06-02 at 16:07 -0400, Rodrigo Vivi wrote:
> On Tue, May 18, 2021 at 03:33:28AM -0700, Alan Previn wrote:
> > Sync i915_drm.h UAPI from drm-tip kernel baselined on following
> > tag:
> > "drm-tip: 2021y-05m-12d-18h-04m-49s UTC integration manifest"
> 
> drm-tip integration manifest is a weak ref hard to find.
> 
> better to 
> drm-tip$ git log include/uapi/drm/i915_drm.h
> then mention the last commit touching this file.
> 
> check the other commits changing this patch.
> 
> Anyway, this approach is correct. And you will have to sync it again
> before merge so if you follow the same:
> 
> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> > Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> > ---
> >  include/drm-uapi/i915_drm.h | 396
> > ++++++++++++++++++++++++++++++++----
> >  1 file changed, 361 insertions(+), 35 deletions(-)
> > 
> > diff --git a/include/drm-uapi/i915_drm.h b/include/drm-
> > uapi/i915_drm.h
> > index bf9ea471..d9fbf218 100644
> > --- a/include/drm-uapi/i915_drm.h
> > +++ b/include/drm-uapi/i915_drm.h
> > @@ -62,8 +62,8 @@ extern "C" {
> >  #define I915_ERROR_UEVENT		"ERROR"
> >  #define I915_RESET_UEVENT		"RESET"
> >  
> > -/*
> > - * i915_user_extension: Base class for defining a chain of
> > extensions
> > +/**
> > + * struct i915_user_extension - Base class for defining a chain of
> > extensions
> >   *
> >   * Many interfaces need to grow over time. In most cases we can
> > simply
> >   * extend the struct and have userspace pass in more data. Another
> > option,
> > @@ -76,12 +76,58 @@ extern "C" {
> >   * increasing complexity, and for large parts of that interface to
> > be
> >   * entirely optional. The downside is more pointer chasing;
> > chasing across
> >   * the boundary with pointers encapsulated inside u64.
> > + *
> > + * Example chaining:
> > + *
> > + * .. code-block:: C
> > + *
> > + *	struct i915_user_extension ext3 {
> > + *		.next_extension = 0, // end
> > + *		.name = ...,
> > + *	};
> > + *	struct i915_user_extension ext2 {
> > + *		.next_extension = (uintptr_t)&ext3,
> > + *		.name = ...,
> > + *	};
> > + *	struct i915_user_extension ext1 {
> > + *		.next_extension = (uintptr_t)&ext2,
> > + *		.name = ...,
> > + *	};
> > + *
> > + * Typically the struct i915_user_extension would be embedded in
> > some uAPI
> > + * struct, and in this case we would feed it the head of the
> > chain(i.e ext1),
> > + * which would then apply all of the above extensions.
> > + *
> >   */
> >  struct i915_user_extension {
> > +	/**
> > +	 * @next_extension:
> > +	 *
> > +	 * Pointer to the next struct i915_user_extension, or zero if
> > the end.
> > +	 */
> >  	__u64 next_extension;
> > +	/**
> > +	 * @name: Name of the extension.
> > +	 *
> > +	 * Note that the name here is just some integer.
> > +	 *
> > +	 * Also note that the name space for this is not global for the
> > whole
> > +	 * driver, but rather its scope/meaning is limited to the
> > specific piece
> > +	 * of uAPI which has embedded the struct i915_user_extension.
> > +	 */
> >  	__u32 name;
> > -	__u32 flags; /* All undefined bits must be zero. */
> > -	__u32 rsvd[4]; /* Reserved for future use; must be zero. */
> > +	/**
> > +	 * @flags: MBZ
> > +	 *
> > +	 * All undefined bits must be zero.
> > +	 */
> > +	__u32 flags;
> > +	/**
> > +	 * @rsvd: MBZ
> > +	 *
> > +	 * Reserved for future use; must be zero.
> > +	 */
> > +	__u32 rsvd[4];
> >  };
> >  
> >  /*
> > @@ -360,6 +406,7 @@ typedef struct _drm_i915_sarea {
> >  #define DRM_I915_QUERY			0x39
> >  #define DRM_I915_GEM_VM_CREATE		0x3a
> >  #define DRM_I915_GEM_VM_DESTROY		0x3b
> > +#define DRM_I915_GEM_CREATE_EXT		0x3c
> >  /* Must be kept compact -- no holes */
> >  
> >  #define DRM_IOCTL_I915_INIT		DRM_IOW(
> > DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
> > @@ -392,6 +439,7 @@ typedef struct _drm_i915_sarea {
> >  #define DRM_IOCTL_I915_GEM_ENTERVT	DRM_IO(DRM_COMMAND_BASE +
> > DRM_I915_GEM_ENTERVT)
> >  #define DRM_IOCTL_I915_GEM_LEAVEVT	DRM_IO(DRM_COMMAND_BASE +
> > DRM_I915_GEM_LEAVEVT)
> >  #define DRM_IOCTL_I915_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE +
> > DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
> > +#define DRM_IOCTL_I915_GEM_CREATE_EXT	DRM_IOWR(DRM_COMMAND_BA
> > SE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext)
> >  #define DRM_IOCTL_I915_GEM_PREAD	DRM_IOW (DRM_COMMAND_BASE +
> > DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
> >  #define DRM_IOCTL_I915_GEM_PWRITE	DRM_IOW (DRM_COMMAND_BASE +
> > DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
> >  #define DRM_IOCTL_I915_GEM_MMAP		DRM_IOWR(DRM_COMMAND_BA
> > SE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
> > @@ -943,6 +991,7 @@ struct drm_i915_gem_exec_object {
> >  	__u64 offset;
> >  };
> >  
> > +/* DRM_IOCTL_I915_GEM_EXECBUFFER was removed in Linux 5.13 */
> >  struct drm_i915_gem_execbuffer {
> >  	/**
> >  	 * List of buffers to be validated with their relocations to be
> > @@ -1053,12 +1102,12 @@ struct drm_i915_gem_exec_fence {
> >  	__u32 flags;
> >  };
> >  
> > -/**
> > +/*
> >   * See drm_i915_gem_execbuffer_ext_timeline_fences.
> >   */
> >  #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0
> >  
> > -/**
> > +/*
> >   * This structure describes an array of drm_syncobj and associated
> > points for
> >   * timeline variants of drm_syncobj. It is invalid to append this
> > structure to
> >   * the execbuf if I915_EXEC_FENCE_ARRAY is set.
> > @@ -1699,7 +1748,7 @@ struct drm_i915_gem_context_param {
> >  	__u64 value;
> >  };
> >  
> > -/**
> > +/*
> >   * Context SSEU programming
> >   *
> >   * It may be necessary for either functional or performance reason
> > to configure
> > @@ -2066,7 +2115,7 @@ struct drm_i915_perf_open_param {
> >  	__u64 properties_ptr;
> >  };
> >  
> > -/**
> > +/*
> >   * Enable data capture for a stream that was either opened in a
> > disabled state
> >   * via I915_PERF_FLAG_DISABLED or was later disabled via
> >   * I915_PERF_IOCTL_DISABLE.
> > @@ -2080,7 +2129,7 @@ struct drm_i915_perf_open_param {
> >   */
> >  #define I915_PERF_IOCTL_ENABLE	_IO('i', 0x0)
> >  
> > -/**
> > +/*
> >   * Disable data capture for a stream.
> >   *
> >   * It is an error to try and read a stream that is disabled.
> > @@ -2089,11 +2138,11 @@ struct drm_i915_perf_open_param {
> >   */
> >  #define I915_PERF_IOCTL_DISABLE	_IO('i', 0x1)
> >  
> > -/**
> > +/*
> >   * Change metrics_set captured by a stream.
> >   *
> >   * If the stream is bound to a specific context, the configuration
> > change
> > - * will performed __inline__ with that context such that it takes
> > effect before
> > + * will performed inline with that context such that it takes
> > effect before
> >   * the next execbuf submission.
> >   *
> >   * Returns the previously bound metrics set id, or a negative
> > error code.
> > @@ -2102,7 +2151,7 @@ struct drm_i915_perf_open_param {
> >   */
> >  #define I915_PERF_IOCTL_CONFIG	_IO('i', 0x2)
> >  
> > -/**
> > +/*
> >   * Common to all i915 perf records
> >   */
> >  struct drm_i915_perf_record_header {
> > @@ -2150,7 +2199,7 @@ enum drm_i915_perf_record_type {
> >  	DRM_I915_PERF_RECORD_MAX /* non-ABI */
> >  };
> >  
> > -/**
> > +/*
> >   * Structure to upload perf dynamic configuration into the kernel.
> >   */
> >  struct drm_i915_perf_oa_config {
> > @@ -2171,53 +2220,95 @@ struct drm_i915_perf_oa_config {
> >  	__u64 flex_regs_ptr;
> >  };
> >  
> > +/**
> > + * struct drm_i915_query_item - An individual query for the kernel
> > to process.
> > + *
> > + * The behaviour is determined by the @query_id. Note that exactly
> > what
> > + * @data_ptr is also depends on the specific @query_id.
> > + */
> >  struct drm_i915_query_item {
> > +	/** @query_id: The id for this query */
> >  	__u64 query_id;
> >  #define DRM_I915_QUERY_TOPOLOGY_INFO    1
> >  #define DRM_I915_QUERY_ENGINE_INFO	2
> >  #define DRM_I915_QUERY_PERF_CONFIG      3
> > +#define DRM_I915_QUERY_MEMORY_REGIONS   4
> >  /* Must be kept compact -- no holes and well documented */
> >  
> > -	/*
> > +	/**
> > +	 * @length:
> > +	 *
> >  	 * When set to zero by userspace, this is filled with the size
> > of the
> > -	 * data to be written at the data_ptr pointer. The kernel sets
> > this
> > +	 * data to be written at the @data_ptr pointer. The kernel sets
> > this
> >  	 * value to a negative value to signal an error on a particular
> > query
> >  	 * item.
> >  	 */
> >  	__s32 length;
> >  
> > -	/*
> > +	/**
> > +	 * @flags:
> > +	 *
> >  	 * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
> >  	 *
> >  	 * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of
> > the
> > -	 * following :
> > -	 *         - DRM_I915_QUERY_PERF_CONFIG_LIST
> > -	 *         - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
> > -	 *         - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
> > +	 * following:
> > +	 *
> > +	 *	- DRM_I915_QUERY_PERF_CONFIG_LIST
> > +	 *      - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
> > +	 *      - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
> >  	 */
> >  	__u32 flags;
> >  #define DRM_I915_QUERY_PERF_CONFIG_LIST          1
> >  #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2
> >  #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID   3
> >  
> > -	/*
> > -	 * Data will be written at the location pointed by data_ptr
> > when the
> > -	 * value of length matches the length of the data to be written
> > by the
> > +	/**
> > +	 * @data_ptr:
> > +	 *
> > +	 * Data will be written at the location pointed by @data_ptr
> > when the
> > +	 * value of @length matches the length of the data to be
> > written by the
> >  	 * kernel.
> >  	 */
> >  	__u64 data_ptr;
> >  };
> >  
> > +/**
> > + * struct drm_i915_query - Supply an array of struct
> > drm_i915_query_item for the
> > + * kernel to fill out.
> > + *
> > + * Note that this is generally a two step process for each struct
> > + * drm_i915_query_item in the array:
> > + *
> > + * 1. Call the DRM_IOCTL_I915_QUERY, giving it our array of struct
> > + *    drm_i915_query_item, with &drm_i915_query_item.length set to
> > zero. The
> > + *    kernel will then fill in the size, in bytes, which tells
> > userspace how
> > + *    memory it needs to allocate for the blob(say for an array of
> > properties).
> > + *
> > + * 2. Next we call DRM_IOCTL_I915_QUERY again, this time with the
> > + *    &drm_i915_query_item.data_ptr equal to our newly allocated
> > blob. Note that
> > + *    the &drm_i915_query_item.length should still be the same as
> > what the
> > + *    kernel previously set. At this point the kernel can fill in
> > the blob.
> > + *
> > + * Note that for some query items it can make sense for userspace
> > to just pass
> > + * in a buffer/blob equal to or larger than the required size. In
> > this case only
> > + * a single ioctl call is needed. For some smaller query items
> > this can work
> > + * quite well.
> > + *
> > + */
> >  struct drm_i915_query {
> > +	/** @num_items: The number of elements in the @items_ptr array
> > */
> >  	__u32 num_items;
> >  
> > -	/*
> > -	 * Unused for now. Must be cleared to zero.
> > +	/**
> > +	 * @flags: Unused for now. Must be cleared to zero.
> >  	 */
> >  	__u32 flags;
> >  
> > -	/*
> > -	 * This points to an array of num_items drm_i915_query_item
> > structures.
> > +	/**
> > +	 * @items_ptr:
> > +	 *
> > +	 * Pointer to an array of struct drm_i915_query_item. The
> > number of
> > +	 * array elements is @num_items.
> >  	 */
> >  	__u64 items_ptr;
> >  };
> > @@ -2291,21 +2382,21 @@ struct drm_i915_query_topology_info {
> >   * Describes one engine and it's capabilities as known to the
> > driver.
> >   */
> >  struct drm_i915_engine_info {
> > -	/** Engine class and instance. */
> > +	/** @engine: Engine class and instance. */
> >  	struct i915_engine_class_instance engine;
> >  
> > -	/** Reserved field. */
> > +	/** @rsvd0: Reserved field. */
> >  	__u32 rsvd0;
> >  
> > -	/** Engine flags. */
> > +	/** @flags: Engine flags. */
> >  	__u64 flags;
> >  
> > -	/** Capabilities of this engine. */
> > +	/** @capabilities: Capabilities of this engine. */
> >  	__u64 capabilities;
> >  #define I915_VIDEO_CLASS_CAPABILITY_HEVC		(1 << 0)
> >  #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC	(1 <<
> > 1)
> >  
> > -	/** Reserved fields. */
> > +	/** @rsvd1: Reserved fields. */
> >  	__u64 rsvd1[4];
> >  };
> >  
> > @@ -2316,13 +2407,13 @@ struct drm_i915_engine_info {
> >   * an array of struct drm_i915_engine_info structures.
> >   */
> >  struct drm_i915_query_engine_info {
> > -	/** Number of struct drm_i915_engine_info structs following. */
> > +	/** @num_engines: Number of struct drm_i915_engine_info structs
> > following. */
> >  	__u32 num_engines;
> >  
> > -	/** MBZ */
> > +	/** @rsvd: MBZ */
> >  	__u32 rsvd[3];
> >  
> > -	/** Marker for drm_i915_engine_info structures. */
> > +	/** @engines: Marker for drm_i915_engine_info structures. */
> >  	struct drm_i915_engine_info engines[];
> >  };
> >  
> > @@ -2376,6 +2467,241 @@ struct drm_i915_query_perf_config {
> >  	__u8 data[];
> >  };
> >  
> > +/**
> > + * enum drm_i915_gem_memory_class - Supported memory classes
> > + */
> > +enum drm_i915_gem_memory_class {
> > +	/** @I915_MEMORY_CLASS_SYSTEM: System memory */
> > +	I915_MEMORY_CLASS_SYSTEM = 0,
> > +	/** @I915_MEMORY_CLASS_DEVICE: Device local-memory */
> > +	I915_MEMORY_CLASS_DEVICE,
> > +};
> > +
> > +/**
> > + * struct drm_i915_gem_memory_class_instance - Identify particular
> > memory region
> > + */
> > +struct drm_i915_gem_memory_class_instance {
> > +	/** @memory_class: See enum drm_i915_gem_memory_class */
> > +	__u16 memory_class;
> > +
> > +	/** @memory_instance: Which instance */
> > +	__u16 memory_instance;
> > +};
> > +
> > +/**
> > + * struct drm_i915_memory_region_info - Describes one region as
> > known to the
> > + * driver.
> > + *
> > + * Note that we reserve some stuff here for potential future work.
> > As an example
> > + * we might want expose the capabilities for a given region, which
> > could include
> > + * things like if the region is CPU mappable/accessible, what are
> > the supported
> > + * mapping types etc.
> > + *
> > + * Note that to extend struct drm_i915_memory_region_info and
> > struct
> > + * drm_i915_query_memory_regions in the future the plan is to do
> > the following:
> > + *
> > + * .. code-block:: C
> > + *
> > + *	struct drm_i915_memory_region_info {
> > + *		struct drm_i915_gem_memory_class_instance region;
> > + *		union {
> > + *			__u32 rsvd0;
> > + *			__u32 new_thing1;
> > + *		};
> > + *		...
> > + *		union {
> > + *			__u64 rsvd1[8];
> > + *			struct {
> > + *				__u64 new_thing2;
> > + *				__u64 new_thing3;
> > + *				...
> > + *			};
> > + *		};
> > + *	};
> > + *
> > + * With this things should remain source compatible between
> > versions for
> > + * userspace, even as we add new fields.
> > + *
> > + * Note this is using both struct drm_i915_query_item and struct
> > drm_i915_query.
> > + * For this new query we are adding the new query id
> > DRM_I915_QUERY_MEMORY_REGIONS
> > + * at &drm_i915_query_item.query_id.
> > + */
> > +struct drm_i915_memory_region_info {
> > +	/** @region: The class:instance pair encoding */
> > +	struct drm_i915_gem_memory_class_instance region;
> > +
> > +	/** @rsvd0: MBZ */
> > +	__u32 rsvd0;
> > +
> > +	/** @probed_size: Memory probed by the driver (-1 = unknown) */
> > +	__u64 probed_size;
> > +
> > +	/** @unallocated_size: Estimate of memory remaining (-1 =
> > unknown) */
> > +	__u64 unallocated_size;
> > +
> > +	/** @rsvd1: MBZ */
> > +	__u64 rsvd1[8];
> > +};
> > +
> > +/**
> > + * struct drm_i915_query_memory_regions
> > + *
> > + * The region info query enumerates all regions known to the
> > driver by filling
> > + * in an array of struct drm_i915_memory_region_info structures.
> > + *
> > + * Example for getting the list of supported regions:
> > + *
> > + * .. code-block:: C
> > + *
> > + *	struct drm_i915_query_memory_regions *info;
> > + *	struct drm_i915_query_item item = {
> > + *		.query_id = DRM_I915_QUERY_MEMORY_REGIONS;
> > + *	};
> > + *	struct drm_i915_query query = {
> > + *		.num_items = 1,
> > + *		.items_ptr = (uintptr_t)&item,
> > + *	};
> > + *	int err, i;
> > + *
> > + *	// First query the size of the blob we need, this needs to be
> > large
> > + *	// enough to hold our array of regions. The kernel will fill
> > out the
> > + *	// item.length for us, which is the number of bytes we need.
> > + *	err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
> > + *	if (err) ...
> > + *
> > + *	info = calloc(1, item.length);
> > + *	// Now that we allocated the required number of bytes, we call
> > the ioctl
> > + *	// again, this time with the data_ptr pointing to our newly
> > allocated
> > + *	// blob, which the kernel can then populate with the all the
> > region info.
> > + *	item.data_ptr = (uintptr_t)&info,
> > + *
> > + *	err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
> > + *	if (err) ...
> > + *
> > + *	// We can now access each region in the array
> > + *	for (i = 0; i < info->num_regions; i++) {
> > + *		struct drm_i915_memory_region_info mr = info-
> > >regions[i];
> > + *		u16 class = mr.region.class;
> > + *		u16 instance = mr.region.instance;
> > + *
> > + *		....
> > + *	}
> > + *
> > + *	free(info);
> > + */
> > +struct drm_i915_query_memory_regions {
> > +	/** @num_regions: Number of supported regions */
> > +	__u32 num_regions;
> > +
> > +	/** @rsvd: MBZ */
> > +	__u32 rsvd[3];
> > +
> > +	/** @regions: Info about each supported region */
> > +	struct drm_i915_memory_region_info regions[];
> > +};
> > +
> > +/**
> > + * struct drm_i915_gem_create_ext - Existing gem_create behaviour,
> > with added
> > + * extension support using struct i915_user_extension.
> > + *
> > + * Note that in the future we want to have our buffer flags here,
> > at least for
> > + * the stuff that is immutable. Previously we would have two
> > ioctls, one to
> > + * create the object with gem_create, and another to apply various
> > parameters,
> > + * however this creates some ambiguity for the params which are
> > considered
> > + * immutable. Also in general we're phasing out the various
> > SET/GET ioctls.
> > + */
> > +struct drm_i915_gem_create_ext {
> > +	/**
> > +	 * @size: Requested size for the object.
> > +	 *
> > +	 * The (page-aligned) allocated size for the object will be
> > returned.
> > +	 *
> > +	 * Note that for some devices we have might have further
> > minimum
> > +	 * page-size restrictions(larger than 4K), like for device
> > local-memory.
> > +	 * However in general the final size here should always reflect
> > any
> > +	 * rounding up, if for example using the
> > I915_GEM_CREATE_EXT_MEMORY_REGIONS
> > +	 * extension to place the object in device local-memory.
> > +	 */
> > +	__u64 size;
> > +	/**
> > +	 * @handle: Returned handle for the object.
> > +	 *
> > +	 * Object handles are nonzero.
> > +	 */
> > +	__u32 handle;
> > +	/** @flags: MBZ */
> > +	__u32 flags;
> > +	/**
> > +	 * @extensions: The chain of extensions to apply to this
> > object.
> > +	 *
> > +	 * This will be useful in the future when we need to support
> > several
> > +	 * different extensions, and we need to apply more than one
> > when
> > +	 * creating the object. See struct i915_user_extension.
> > +	 *
> > +	 * If we don't supply any extensions then we get the same old
> > gem_create
> > +	 * behaviour.
> > +	 *
> > +	 * For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see
> > +	 * struct drm_i915_gem_create_ext_memory_regions.
> > +	 */
> > +#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
> > +	__u64 extensions;
> > +};
> > +
> > +/**
> > + * struct drm_i915_gem_create_ext_memory_regions - The
> > + * I915_GEM_CREATE_EXT_MEMORY_REGIONS extension.
> > + *
> > + * Set the object with the desired set of placements/regions in
> > priority
> > + * order. Each entry must be unique and supported by the device.
> > + *
> > + * This is provided as an array of struct
> > drm_i915_gem_memory_class_instance, or
> > + * an equivalent layout of class:instance pair encodings. See
> > struct
> > + * drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS
> > for how to
> > + * query the supported regions for a device.
> > + *
> > + * As an example, on discrete devices, if we wish to set the
> > placement as
> > + * device local-memory we can do something like:
> > + *
> > + * .. code-block:: C
> > + *
> > + *	struct drm_i915_gem_memory_class_instance region_lmem = {
> > + *              .memory_class = I915_MEMORY_CLASS_DEVICE,
> > + *              .memory_instance = 0,
> > + *      };
> > + *      struct drm_i915_gem_create_ext_memory_regions regions = {
> > + *              .base = { .name =
> > I915_GEM_CREATE_EXT_MEMORY_REGIONS },
> > + *              .regions = (uintptr_t)&region_lmem,
> > + *              .num_regions = 1,
> > + *      };
> > + *      struct drm_i915_gem_create_ext create_ext = {
> > + *              .size = 16 * PAGE_SIZE,
> > + *              .extensions = (uintptr_t)&regions,
> > + *      };
> > + *
> > + *      int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT,
> > &create_ext);
> > + *      if (err) ...
> > + *
> > + * At which point we get the object handle in
> > &drm_i915_gem_create_ext.handle,
> > + * along with the final object size in
> > &drm_i915_gem_create_ext.size, which
> > + * should account for any rounding up, if required.
> > + */
> > +struct drm_i915_gem_create_ext_memory_regions {
> > +	/** @base: Extension link. See struct i915_user_extension. */
> > +	struct i915_user_extension base;
> > +
> > +	/** @pad: MBZ */
> > +	__u32 pad;
> > +	/** @num_regions: Number of elements in the @regions array. */
> > +	__u32 num_regions;
> > +	/**
> > +	 * @regions: The regions/placements array.
> > +	 *
> > +	 * An array of struct drm_i915_gem_memory_class_instance.
> > +	 */
> > +	__u64 regions;
> > +};
> > +
> >  #if defined(__cplusplus)
> >  }
> >  #endif
> > -- 
> > 2.25.1
> > 
> > _______________________________________________
> > igt-dev mailing list
> > igt-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t 02/17] Add PXP UAPI support in i915_drm.h

[Teres Alexis, Alan Previn]

Okay - will do. 

On Wed, 2021-06-02 at 16:10 -0400, Rodrigo Vivi wrote:
> On Tue, May 18, 2021 at 03:33:29AM -0700, Alan Previn wrote:
> > At the time of this commit, PXP hasnt been merged into
> > upstream kernel so this has no kernel tag reference yet
> 
> chicken egg issue right, but probably better to kill this patch
> and sync directly when merging, right after the kernel merged.
> 
> > Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> > ---
> >  include/drm-uapi/i915_drm.h | 52
> > +++++++++++++++++++++++++++++++++++++
> >  1 file changed, 52 insertions(+)
> > 
> > diff --git a/include/drm-uapi/i915_drm.h b/include/drm-
> > uapi/i915_drm.h
> > index d9fbf218..e67e3e5c 100644
> > --- a/include/drm-uapi/i915_drm.h
> > +++ b/include/drm-uapi/i915_drm.h
> > @@ -1743,6 +1743,26 @@ struct drm_i915_gem_context_param {
> >   * Default is 16 KiB.
> >   */
> >  #define I915_CONTEXT_PARAM_RINGSIZE	0xc
> > +
> > +/*
> > + * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> > + *
> > + * Mark that the context makes use of protected content, which
> > will result
> > + * in the context being invalidated when the protected content
> > session is.
> > + * This flag can only be set at context creation time and, when
> > set to true,
> > + * must be preceded by an explicit setting of
> > I915_CONTEXT_PARAM_RECOVERABLE
> > + * to false. This flag can't be set to true in conjunction with
> > setting the
> > + * I915_CONTEXT_PARAM_BANNABLE flag to false.
> > + *
> > + * Given the numerous restriction on this flag, there are several
> > unique
> > + * failure cases:
> > + *
> > + * -ENODEV: feature not available
> > + * -EEXIST: trying to modify an existing context
> > + * -EPERM: trying to mark a recoverable or not bannable context as
> > protected
> > + * -EACCES: submitting an invalidated context for execution
> > + */
> > +#define I915_CONTEXT_PARAM_PROTECTED_CONTENT    0xd
> >  /* Must be kept compact -- no holes and well documented */
> >  
> >  	__u64 value;
> > @@ -1973,6 +1993,12 @@ struct drm_i915_reg_read {
> >  struct drm_i915_reset_stats {
> >  	__u32 ctx_id;
> >  	__u32 flags;
> > +	/*
> > +	 * contexts marked as using protected content are invalidated
> > when the
> > +	 * protected content session dies. Submission of invalidated
> > contexts
> > +	 * is rejected with -EACCES.
> > +	 */
> > +#define I915_CONTEXT_INVALIDATED 0x1
> >  
> >  	/* All resets since boot/module reload, for all contexts */
> >  	__u32 reset_count;
> > @@ -2645,6 +2671,7 @@ struct drm_i915_gem_create_ext {
> >  	 * struct drm_i915_gem_create_ext_memory_regions.
> >  	 */
> >  #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
> > +#define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1
> >  	__u64 extensions;
> >  };
> >  
> > @@ -2702,6 +2729,31 @@ struct
> > drm_i915_gem_create_ext_memory_regions {
> >  	__u64 regions;
> >  };
> >  
> > +/*
> > + * I915_OBJECT_PARAM_PROTECTED_CONTENT:
> > + *
> > + * If set to true, buffer contents is expected to be protected by
> > PXP
> > + * encryption and requires decryption for scan out and processing.
> > This is
> > + * only possible on platforms that have PXP enabled, on all other
> > scenarios
> > + * setting this flag will cause the ioctl to fail and return
> > -ENODEV.
> > + *
> > + * The buffer contents are considered invalid after a PXP session
> > teardown.
> > + * It is recommended to use protected buffers only with contexts
> > created
> > + * using the I915_CONTEXT_PARAM_PROTECTED_CONTENT flag, as that
> > will enable
> > + * extra checks at submission time on the validity of the objects
> > involved,
> > + * which can lead to the following errors:
> > + *
> > + * -ENODEV: PXP session not currently active
> > + * -EIO: buffer has become invalid after a teardown event
> > + */
> > +struct drm_i915_gem_create_ext_protected_content {
> > +	struct i915_user_extension base;
> > +	__u32 flags;
> > +};
> > +
> > +/* ID of the protected content session managed by i915 when PXP is
> > active */
> > +#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
> > +
> >  #if defined(__cplusplus)
> >  }
> >  #endif
> > -- 
> > 2.25.1
> > 
> > _______________________________________________
> > igt-dev mailing list
> > igt-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t 07/17] Add MI_SET_APPID instruction definition

[Teres Alexis, Alan Previn]

On Wed, 2021-06-02 at 17:40 -0400, Rodrigo Vivi wrote:
> On Tue, May 18, 2021 at 03:33:34AM -0700, Alan Previn wrote:
> > Add MI_SET_APPID instruction and param definitions
> > 
> > Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> > ---
> >  lib/intel_reg.h | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> > 
> > diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> > index ac1fc6cb..46b5da20 100644
> > --- a/lib/intel_reg.h
> > +++ b/lib/intel_reg.h
> > @@ -2546,6 +2546,15 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> > SOFTWARE.
> >  #define CTXT_PALETTE_SAVE_DISABLE	(1<<3)
> >  #define CTXT_PALETTE_RESTORE_DISABLE	(1<<2)
> >  
> > +#define MI_SET_APPID                    (0x0E << 23)
> > +#define APPID_CTXSAVE_INHIBIT           (1 << 8)
> > +#define APPID_CTXREST_INHIBIT           (1 << 9)
> > +#define DISPLAY_APPTYPE                 (0)
> > +#define TRANSCODE_APPTYPE               (1)
> > +#define APPTYPE(n)                      (n << 7)
> > +#define APPID(n)                        (n & 0x7f)
> 
> What about sorting the bits?
> 
What do u mean by "sorting the bits"? if u mean swap
APP_CTXSAVE_INHIBIT with APP_CTXREST_INHIBIT so we work from MSB down,
then sure, i will fix that. If i have misunderstood, could u paste some
psuedocode? (so i understand correctly)

> anyway
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> 
> > +
> > +
> >  /* Dword 0 */
> >  #define MI_VERTEX_BUFFER		(0x17<<23)
> >  #define MI_VERTEX_BUFFER_IDX(x)		(x<<20)
> > -- 
> > 2.25.1
> > 
> > _______________________________________________
> > igt-dev mailing list
> > igt-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t 07/17] Add MI_SET_APPID instruction definition

[Michal Wajdeczko]

On 18.05.2021 12:33, Alan Previn wrote:
> Add MI_SET_APPID instruction and param definitions
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
>  lib/intel_reg.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> index ac1fc6cb..46b5da20 100644
> --- a/lib/intel_reg.h
> +++ b/lib/intel_reg.h
> @@ -2546,6 +2546,15 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>  #define CTXT_PALETTE_SAVE_DISABLE	(1<<3)
>  #define CTXT_PALETTE_RESTORE_DISABLE	(1<<2)
>  
> +#define MI_SET_APPID                    (0x0E << 23)
> +#define APPID_CTXSAVE_INHIBIT           (1 << 8)
> +#define APPID_CTXREST_INHIBIT           (1 << 9)
> +#define DISPLAY_APPTYPE                 (0)
> +#define TRANSCODE_APPTYPE               (1)
> +#define APPTYPE(n)                      (n << 7)
> +#define APPID(n)                        (n & 0x7f)

macro params shall be wrapped by ()

#define APPTYPE(n)                      ((n) << 7)
#define APPID(n)                        ((n) & 0x7f)

> +
> +
>  /* Dword 0 */
>  #define MI_VERTEX_BUFFER		(0x17<<23)
>  #define MI_VERTEX_BUFFER_IDX(x)		(x<<20)
> 
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Re: [igt-dev] [PATCH i-g-t 07/17] Add MI_SET_APPID instruction definition

[Rodrigo Vivi]

On Wed, Jun 02, 2021 at 08:54:06PM -0400, Teres Alexis, Alan Previn wrote:
> On Wed, 2021-06-02 at 17:40 -0400, Rodrigo Vivi wrote:
> > On Tue, May 18, 2021 at 03:33:34AM -0700, Alan Previn wrote:
> > > Add MI_SET_APPID instruction and param definitions
> > >
> > > Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> > > ---
> > >  lib/intel_reg.h | 9 +++++++++
> > >  1 file changed, 9 insertions(+)
> > >
> > > diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> > > index ac1fc6cb..46b5da20 100644
> > > --- a/lib/intel_reg.h
> > > +++ b/lib/intel_reg.h
> > > @@ -2546,6 +2546,15 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> > > SOFTWARE.
> > >  #define CTXT_PALETTE_SAVE_DISABLE  (1<<3)
> > >  #define CTXT_PALETTE_RESTORE_DISABLE       (1<<2)
> > >
> > > +#define MI_SET_APPID                    (0x0E << 23)
> > > +#define APPID_CTXSAVE_INHIBIT           (1 << 8)
> > > +#define APPID_CTXREST_INHIBIT           (1 << 9)
> > > +#define DISPLAY_APPTYPE                 (0)
> > > +#define TRANSCODE_APPTYPE               (1)
> > > +#define APPTYPE(n)                      (n << 7)
> > > +#define APPID(n)                        (n & 0x7f)
> >
> > What about sorting the bits?
> >
> What do u mean by "sorting the bits"? if u mean swap
> APP_CTXSAVE_INHIBIT with APP_CTXREST_INHIBIT so we work from MSB down,
> then sure, i will fix that. If i have misunderstood, could u paste some
> psuedocode? (so i understand correctly)

I meant something like this:

#define MI_SET_APPID                    (0x0E << 23)
#define APPID_CTXREST_INHIBIT           (1 << 9)
#define APPID_CTXSAVE_INHIBIT           (1 << 8)
#define APPTYPE(n)                      (n << 7)
#define  DISPLAY_APPTYPE                (0)
#define  TRANSCODE_APPTYPE              (1)
#define APPID(n)                        (n & 0x7f)

> 
> > anyway
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

but up to you, you have the rv-b already ;)

> >
> >
> > > +
> > > +
> > >  /* Dword 0 */
> > >  #define MI_VERTEX_BUFFER           (0x17<<23)
> > >  #define MI_VERTEX_BUFFER_IDX(x)            (x<<20)
> > > --
> > > 2.25.1
> > >
> > > _______________________________________________
> > > igt-dev mailing list
> > > igt-dev@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t 07/17] Add MI_SET_APPID instruction definition

[Teres Alexis, Alan Previn]

On Thu, 2021-06-03 at 10:52 +0200, Michal Wajdeczko wrote:
> 
> On 18.05.2021 12:33, Alan Previn wrote:
> > Add MI_SET_APPID instruction and param definitions
> > 
> > Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> > ---
> >  lib/intel_reg.h | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> > 
> > diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> > index ac1fc6cb..46b5da20 100644
> > --- a/lib/intel_reg.h
> > +++ b/lib/intel_reg.h
> > @@ -2546,6 +2546,15 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> > SOFTWARE.
> >  #define CTXT_PALETTE_SAVE_DISABLE	(1<<3)
> >  #define CTXT_PALETTE_RESTORE_DISABLE	(1<<2)
> >  
> > +#define MI_SET_APPID                    (0x0E << 23)
> > +#define APPID_CTXSAVE_INHIBIT           (1 << 8)
> > +#define APPID_CTXREST_INHIBIT           (1 << 9)
> > +#define DISPLAY_APPTYPE                 (0)
> > +#define TRANSCODE_APPTYPE               (1)
> > +#define APPTYPE(n)                      (n << 7)
> > +#define APPID(n)                        (n & 0x7f)
> 
> macro params shall be wrapped by ()

okay - i can see how it can be an issue without that additional () -
will fix it.

> 
> #define APPTYPE(n)                      ((n) << 7)
> #define APPID(n)                        ((n) & 0x7f)
> 
> > +
> > +
> >  /* Dword 0 */
> >  #define MI_VERTEX_BUFFER		(0x17<<23)
> >  #define MI_VERTEX_BUFFER_IDX(x)		(x<<20)
> > 

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Re: [igt-dev] ✗ Fi.CI.IGT: failure for Introduce PXP Test (rev5)

[Teres Alexis, Alan Previn]

On Wed, 2021-06-02 at 17:44 -0400, Rodrigo Vivi wrote:
> On Tue, May 18, 2021 at 06:19:48PM -0000, Patchwork wrote:
> >    Patch Details
> > 
> >    Series:  Introduce PXP Test (rev5)
> >    URL:     [1]https://patchwork.freedesktop.org/series/87570/
> >    State:   failure
> >    Details:
> >    [2]
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/index.html
> > 
> >            CI Bug Log - changes from IGT_6087_full ->
> > IGTPW_5817_full
> > 
> > Summary
> > 
> >    FAILURE
> > 
> >    Serious unknown changes coming with IGTPW_5817_full absolutely
> > need to
> >    be
> >    verified manually.
> > 
> >    If you think the reported changes have nothing to do with the
> > changes
> >    introduced in IGTPW_5817_full, please notify your bug team to
> > allow
> >    them
> >    to document this new failure mode, which will reduce false
> > positives in
> >    CI.
> > 
> >    External URL:
> >    https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/index.html
> > 
> > Possible new issues
> > 
> >    Here are the unknown changes that may have been introduced in
> >    IGTPW_5817_full:
> > 
> >   IGT changes
> > 
> >     Possible regressions
> > 
> >      * igt@gem_mmap_gtt@cpuset-basic-small-copy-xy:
> >           + shard-snb: NOTRUN -> [3]INCOMPLETE
> >      * igt@gem_ppgtt@blt-vs-render-ctx0:
> >           + shard-apl: [4]PASS -> [5]FAIL
> 
> since we are touching the render path for gen9+ we need to pay
> attention
> to cases like this...

In theory this doesnt make sense since I thought all changes I injected
into the render code paths was fenced by "if batchbuffer has pxp
enabled" or "if buffer has pxp enabled"- i will double check / trybot
before i push next rev.

Side note: wrt below results where pxp test is failing on legacy HW,
its due to kernel not yet supporting new PXP interface (where legacy HW
would reply with -ENODEV vs -EINVAL when IGT is allocating protected
buffers or contexts).

> 
> >      * {igt@gem_pxp@create-regular-context-1} (NEW):
> >           + shard-iclb: NOTRUN -> [6]SKIP +12 similar issues
> >      * {igt@gem_pxp@hw-rejects-pxp-context} (NEW):
> >           + shard-glk: NOTRUN -> [7]FAIL
> >           + shard-iclb: NOTRUN -> [8]FAIL
> >           + shard-snb: NOTRUN -> [9]FAIL
> >           + shard-kbl: NOTRUN -> [10]FAIL
> >      * {igt@gem_pxp@protected-encrypted-src-copy-not-readible}
> > (NEW):
> >           + shard-tglb: NOTRUN -> [11]FAIL +10 similar issues
> >      * igt@i915_selftest@perf@request:
> >           + shard-tglb: [12]PASS -> [13]DMESG-FAIL
> >      * igt@kms_flip_tiling@flip-changes-tiling-y@hdmi-a-2-pipe-a:
> >           + shard-glk: [14]PASS -> [15]FAIL +5 similar issues
> > 
> >     Suppressed
> > 
> >    The following results come from untrusted machines, tests, or
> > statuses.
> >    They do not affect the overall result.
> >      * {igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-
> > planes}:
> >           + shard-glk: [16]PASS -> [17]FAIL
> > 
> > New tests
> > 
> >    New tests have been introduced between IGT_6087_full and
> >    IGTPW_5817_full:
> > 
> >   New IGT tests (20)
> > 
> >      * igt@gem_pxp@create-protected-buffer:
> >           + Statuses : 1 fail(s) 4 skip(s)
> >           + Exec time: [0.0, 0.01] s
> >      * igt@gem_pxp@create-regular-buffer:
> >           + Statuses :
> >           + Exec time: [None] s
> >      * igt@gem_pxp@create-regular-context-1:
> >           + Statuses : 1 fail(s) 4 skip(s)
> >           + Exec time: [0.0, 0.01] s
> >      * igt@gem_pxp@create-regular-context-2:
> >           + Statuses : 1 fail(s) 4 skip(s)
> >           + Exec time: [0.0, 0.02] s
> >      * igt@gem_pxp@create-valid-protected-context:
> >           + Statuses : 1 fail(s) 4 skip(s)
> >           + Exec time: [0.0, 0.01] s
> >      * igt@gem_pxp@display-protected-crc-with-hdcp:
> >           + Statuses : 1 fail(s) 4 skip(s)
> >           + Exec time: [0.0, 0.01] s
> >      * igt@gem_pxp@display-protected-crc-without-hdcp:
> >           + Statuses : 1 fail(s) 2 skip(s)
> >           + Exec time: [0.0, 0.01] s
> >      * igt@gem
> > _pxp@dmabuf-shared-protected-dst-is-context-refcounted:
> >           + Statuses : 1 fail(s) 4 skip(s)
> >           + Exec time: [0.0, 0.03] s
> >      * igt@gem_pxp@fail-invalid-protected-context:
> >           + Statuses : 1 skip(s)
> >           + Exec time: [0.0] s
> >      * igt@gem_pxp@hw-rejects-pxp-buffer:
> >           + Statuses :
> >           + Exec time: [None] s
> >      * igt@gem_pxp@hw-rejects-pxp-context:
> >           + Statuses : 4 fail(s)
> >           + Exec time: [0.01, 0.02] s
> >      * igt@gem_pxp@protected-encrypted-src-copy-not-readible:
> >           + Statuses : 1 fail(s) 5 skip(s)
> >           + Exec time: [0.0, 0.01] s
> >      * igt@gem_pxp@protected-raw-src-copy-not-readible:
> >           + Statuses : 1 fail(s) 3 skip(s)
> >           + Exec time: [0.0, 0.01] s
> >      * igt@gem_pxp@regular-baseline-src-copy-readible:
> >           + Statuses : 1 pass(s) 2 skip(s)
> >           + Exec time: [0.0, 0.01] s
> >      * igt@gem_pxp@reject-modify-context-protection-off-1:
> >           + Statuses : 1 skip(s)
> >           + Exec time: [0.0] s
> >      * igt@gem_pxp@reject-modify-context-protection-off-2:
> >           + Statuses :
> >           + Exec time: [None] s
> >      * igt@gem_pxp@reject-modify-context-protection-off-3:
> >           + Statuses : 3 skip(s)
> >           + Exec time: [0.0] s
> >      * igt@gem_pxp@reject-modify-context-protection-on:
> >           + Statuses : 1 fail(s) 5 skip(s)
> >           + Exec time: [0.0, 0.00] s
> >      * igt@gem
> > _pxp@verify-pxp-execution-behavior-after-suspend-resume:
> >           + Statuses :
> >           + Exec time: [None] s
> >      * igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
> >           + Statuses : 1 fail(s) 5 skip(s)
> >           + Exec time: [0.0, 0.01] s
> > 
> > Known issues
> > 
> >    Here are the changes found in IGTPW_5817_full that come from
> > known
> >    issues:
> > 
> >   IGT changes
> > 
> >     Issues hit
> > 
> >      * igt@api_intel_bb@blit-noreloc-purge-cache:
> >           + shard-iclb: NOTRUN -> [18]DMESG-WARN ([i915#3457]) +3
> > similar
> >             issues
> >           + shard-glk: NOTRUN -> [19]DMESG-FAIL ([i915#3457]) +2
> > similar
> >             issues
> >      * igt@api_intel_bb@offset-control:
> >           + shard-apl: NOTRUN -> [20]DMESG-WARN ([i915#3457]) +1
> > similar
> >             issue
> >           + shard-glk: NOTRUN -> [21]DMESG-WARN ([i915#3457])
> >      * igt@feature_discovery@chamelium:
> >           + shard-tglb: NOTRUN -> [22]SKIP ([fdo#111827])
> >           + shard-iclb: NOTRUN -> [23]SKIP ([fdo#111827])
> >      * igt@gem_create@create-massive:
> >           + shard-iclb: NOTRUN -> [24]DMESG-WARN ([i915#3002])
> >           + shard-kbl: NOTRUN -> [25]DMESG-WARN ([i915#3002])
> >           + shard-tglb: NOTRUN -> [26]DMESG-WARN ([i915#3002])
> >           + shard-glk: NOTRUN -> [27]DMESG-WARN ([i915#3002])
> >      * igt@gem_ctx_isolation@preservation-s3@vcs0:
> >           + shard-kbl: NOTRUN -> [28]DMESG-WARN ([i915#180] /
> > [i915#3457])
> >             +4 similar issues
> >      * igt@gem_ctx_persistence@legacy-engines-hostile:
> >           + shard-snb: NOTRUN -> [29]SKIP ([fdo#109271] /
> > [i915#1099]) +2
> >             similar issues
> >      * igt@gem_ctx_persistence@many-contexts:
> >           + shard-glk: [30]PASS -> [31]DMESG-WARN ([i915#118] /
> >             [i915#3457] / [i915#95])
> >      * igt@gem_eio@unwedge-stress:
> >           + shard-apl: NOTRUN -> [32]FAIL ([i915#3457]) +10 similar
> > issues
> >           + shard-snb: NOTRUN -> [33]FAIL ([i915#3354] /
> > [i915#3457])
> >      * igt@gem_exec_endless@dispatch@vecs0:
> >           + shard-apl: NOTRUN -> [34]INCOMPLETE ([i915#2502] /
> >             [i915#3457])
> >      * igt@gem_exec_fair@basic-none-rrul@rcs0:
> >           + shard-iclb: NOTRUN -> [35]FAIL ([i915#2842] /
> > [i915#3457]) +5
> >             similar issues
> >           + shard-glk: NOTRUN -> [36]INCOMPLETE ([i915#3457]) +1
> > similar
> >             issue
> >      * igt@gem_exec_fair@basic-none@vcs0:
> >           + shard-tglb: NOTRUN -> [37]FAIL ([i915#2842] /
> > [i915#3457]) +5
> >             similar issues
> >      * igt@gem_exec_fair@basic-none@vcs1:
> >           + shard-kbl: NOTRUN -> [38]FAIL ([i915#2842] /
> > [i915#3457])
> >      * igt@gem_exec_fair@basic-pace@rcs0:
> >           + shard-tglb: [39]PASS -> [40]FAIL ([i915#2842] /
> > [i915#3457])
> >      * igt@gem_exec_fair@basic-pace@vcs0:
> >           + shard-iclb: [41]PASS -> [42]FAIL ([i915#2842] /
> > [i915#3457])
> >      * igt@gem_exec_fair@basic-pace@vcs1:
> >           + shard-kbl: [43]PASS -> [44]FAIL ([i915#2842] /
> > [i915#3457])
> >      * igt@gem_exec_schedule@preempt-hang@vcs0:
> >           + shard-glk: [45]PASS -> [46]FAIL ([i915#3457]) +28
> > similar
> >             issues
> >      * igt@gem_exec_schedule@submit-early-slice@vecs0:
> >           + shard-glk: NOTRUN -> [47]FAIL ([i915#3457]) +50 similar
> > issues
> >      * igt@gem_exec_whisper@basic-contexts-all:
> >           + shard-glk: NOTRUN -> [48]DMESG-WARN ([i915#118] /
> > [i915#95])
> >      * igt@gem_huc_copy@huc-copy:
> >           + shard-tglb: [49]PASS -> [50]SKIP ([i915#2190])
> >      * igt@gem_mmap_gtt@cpuset-basic-small-copy:
> >           + shard-snb: NOTRUN -> [51]INCOMPLETE ([i915#3468]) +1
> > similar
> >             issue
> >           + shard-kbl: [52]PASS -> [53]INCOMPLETE ([i915#3468])
> >      * igt@gem_mmap_gtt@cpuset-basic-small-copy-xy:
> >           + shard-tglb: NOTRUN -> [54]INCOMPLETE ([i915#3468]) +2
> > similar
> >             issues
> >           + shard-kbl: NOTRUN -> [55]INCOMPLETE ([i915#3468]) +3
> > similar
> >             issues
> >      * igt@gem_mmap_offset@clear:
> >           + shard-glk: NOTRUN -> [56]FAIL ([i915#1888] /
> > [i915#3160])
> >      * igt@gem_pwrite@basic-exhaustion:
> >           + shard-apl: NOTRUN -> [57]WARN ([i915#2658])
> >      * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
> >           + shard-apl: NOTRUN -> [58]INCOMPLETE ([i915#3468])
> >      * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled:
> >           + shard-iclb: NOTRUN -> [59]SKIP ([i915#768]) +4 similar
> > issues
> >      * igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled:
> >           + shard-iclb: NOTRUN -> [60]INCOMPLETE ([i915#3468]) +2
> > similar
> >             issues
> >           + shard-glk: NOTRUN -> [61]INCOMPLETE ([i915#3468]) +2
> > similar
> >             issues
> >           + shard-tglb: NOTRUN -> [62]INCOMPLETE ([i915#3457] /
> >             [i915#3468])
> >      * igt@gem_softpin@evict-snoop-interruptible:
> >           + shard-tglb: NOTRUN -> [63]SKIP ([fdo#109312])
> >           + shard-iclb: NOTRUN -> [64]SKIP ([fdo#109312])
> >      * igt@gem_userptr_blits@dmabuf-sync:
> >           + shard-apl: NOTRUN -> [65]SKIP ([fdo#109271] /
> > [i915#3323])
> >      * igt@gem_userptr_blits@dmabuf-unsync:
> >           + shard-tglb: NOTRUN -> [66]SKIP ([i915#3297]) +2 similar
> > issues
> >           + shard-iclb: NOTRUN -> [67]SKIP ([i915#3297]) +3 similar
> > issues
> >      * igt@gem_wait@await@bcs0:
> >           + shard-apl: [68]PASS -> [69]FAIL ([i915#3457]) +1
> > similar issue
> >      * igt@gen3_render_linear_blits:
> >           + shard-tglb: NOTRUN -> [70]SKIP ([fdo#109289]) +4
> > similar
> >             issues
> >           + shard-iclb: NOTRUN -> [71]SKIP ([fdo#109289]) +3
> > similar
> >             issues
> >      * igt@gen7_exec_parse@basic-offset:
> >           + shard-apl: NOTRUN -> [72]SKIP ([fdo#109271]) +171
> > similar
> >             issues
> >      * igt@gen9_exec_parse@allowed-all:
> >           + shard-iclb: NOTRUN -> [73]SKIP ([fdo#112306]) +4
> > similar
> >             issues
> >      * igt@gen9_exec_parse@bb-start-out:
> >           + shard-tglb: NOTRUN -> [74]SKIP ([fdo#112306]) +3
> > similar
> >             issues
> >      * igt@i915_hangman@error-state-capture@bcs0:
> >           + shard-snb: NOTRUN -> [75]DMESG-WARN ([i915#3457]) +2
> > similar
> >             issues
> >      * igt@i915_module_load@reload:
> >           + shard-tglb: NOTRUN -> [76]DMESG-WARN ([i915#3457]) +3
> > similar
> >             issues
> >           + shard-kbl: NOTRUN -> [77]DMESG-WARN ([i915#3457]) +5
> > similar
> >             issues
> >      * igt@i915_pm_dc@dc9-dpms:
> >           + shard-tglb: NOTRUN -> [78]SKIP ([i915#3288])
> >           + shard-iclb: NOTRUN -> [79]FAIL ([i915#3343])
> >      * igt@i915_pm_rpm@cursor:
> >           + shard-tglb: [80]PASS -> [81]DMESG-WARN ([i915#2411] /
> >             [i915#3457]) +1 similar issue
> >           + shard-kbl: [82]PASS -> [83]DMESG-WARN ([i915#3457])
> >           + shard-glk: [84]PASS -> [85]DMESG-WARN ([i915#3457])
> >      * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
> >           + shard-iclb: NOTRUN -> [86]SKIP ([fdo#110892]) +1
> > similar issue
> >      * igt@i915_pm_rps@reset:
> >           + shard-apl: NOTRUN -> [87]DMESG-FAIL ([i915#3457]) +2
> > similar
> >             issues
> >      * igt@kms_atomic@plane-immutable-zpos:
> >           + shard-glk: [88]PASS -> [89]FAIL ([i915#2657] /
> > [i915#3457])
> >      * igt@kms_big_fb@linear-16bpp-rotate-90:
> >           + shard-iclb: NOTRUN -> [90]SKIP ([fdo#110725] /
> > [fdo#111614])
> >             +6 similar issues
> >           + shard-tglb: NOTRUN -> [91]SKIP ([fdo#111614]) +6
> > similar
> >             issues
> >      * igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
> >           + shard-tglb: NOTRUN -> [92]SKIP ([fdo#111615]) +3
> > similar
> >             issues
> >      * igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
> >           + shard-iclb: NOTRUN -> [93]SKIP ([fdo#110723])
> >      * igt@kms_big_joiner@invalid-modeset:
> >           + shard-iclb: NOTRUN -> [94]SKIP ([i915#2705])
> >           + shard-kbl: NOTRUN -> [95]SKIP ([fdo#109271] /
> > [i915#2705])
> >           + shard-apl: NOTRUN -> [96]SKIP ([fdo#109271] /
> > [i915#2705])
> >           + shard-glk: NOTRUN -> [97]SKIP ([fdo#109271] /
> > [i915#2705])
> >           + shard-tglb: NOTRUN -> [98]SKIP ([i915#2705])
> >      * igt@kms_chamelium@dp-hpd-storm-disable:
> >           + shard-glk: NOTRUN -> [99]SKIP ([fdo#109271] /
> > [fdo#111827])
> >             +19 similar issues
> >      * igt@kms_chamelium@dp-mode-timings:
> >           + shard-apl: NOTRUN -> [100]SKIP ([fdo#109271] /
> > [fdo#111827])
> >             +15 similar issues
> >      * igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
> >           + shard-snb: NOTRUN -> [101]SKIP ([fdo#109271] /
> > [fdo#111827])
> >             +16 similar issues
> >      * igt@kms_chamelium@hdmi-hpd-storm:
> >           + shard-kbl: NOTRUN -> [102]SKIP ([fdo#109271] /
> > [fdo#111827])
> >             +30 similar issues
> >      * igt@kms_color@pipe-b-degamma:
> >           + shard-tglb: NOTRUN -> [103]FAIL ([i915#1149])
> >           + shard-glk: NOTRUN -> [104]FAIL ([i915#71])
> >           + shard-iclb: NOTRUN -> [105]FAIL ([i915#1149])
> >      * igt@kms_color@pipe-c-degamma:
> >           + shard-glk: [106]PASS -> [107]FAIL ([i915#71]) +1
> > similar issue
> >      * igt@kms_color@pipe-d-ctm-0-25:
> >           + shard-iclb: NOTRUN -> [108]SKIP ([fdo#109278] /
> > [i915#1149])
> >             +2 similar issues
> >      * igt@kms_color_chamelium@pipe-b-ctm-0-75:
> >           + shard-tglb: NOTRUN -> [109]SKIP ([fdo#109284] /
> > [fdo#111827])
> >             +21 similar issues
> >      * igt@kms_color_chamelium@pipe-b-ctm-red-to-blue:
> >           + shard-iclb: NOTRUN -> [110]SKIP ([fdo#109284] /
> > [fdo#111827])
> >             +19 similar issues
> >      * igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
> >           + shard-iclb: NOTRUN -> [111]SKIP ([fdo#109278] /
> > [fdo#109284] /
> >             [fdo#111827]) +1 similar issue
> >      * igt@kms_content_protection@atomic-dpms:
> >           + shard-kbl: NOTRUN -> [112]TIMEOUT ([i915#1319])
> >      * igt@kms_content_protection@dp-mst-lic-type-1:
> >           + shard-iclb: NOTRUN -> [113]SKIP ([i915#3116])
> >           + shard-tglb: NOTRUN -> [114]SKIP ([i915#3116])
> >      * igt@kms_content_protection@uevent:
> >           + shard-kbl: NOTRUN -> [115]FAIL ([i915#2105])
> >           + shard-tglb: NOTRUN -> [116]SKIP ([fdo#111828])
> >           + shard-iclb: NOTRUN -> [117]SKIP ([fdo#109300] /
> > [fdo#111066])
> >      * igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen:
> >           + shard-snb: NOTRUN -> [118]FAIL ([i915#3457]) +4 similar
> > issues
> >      * igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding:
> >           + shard-tglb: NOTRUN -> [119]SKIP ([i915#3319] /
> > [i915#3457]) +6
> >             similar issues
> >      * igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen:
> >           + shard-kbl: NOTRUN -> [120]FAIL ([i915#3444] /
> > [i915#3457]) +16
> >             similar issues
> >      * igt@kms_cursor_crc@pipe-a-cursor-dpms:
> >           + shard-apl: [121]PASS -> [122]FAIL ([i915#3444] /
> > [i915#3457])
> >      * igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen:
> >           + shard-iclb: NOTRUN -> [123]SKIP ([fdo#109278] /
> > [fdo#109279] /
> >             [i915#3457]) +6 similar issues
> >      * igt@kms_cursor_crc@pipe-b-cursor-64x21-random:
> >           + shard-apl: NOTRUN -> [124]FAIL ([i915#3444] /
> > [i915#3457]) +3
> >             similar issues
> >      * igt@kms_cursor_crc@pipe-b-cursor-64x64-random:
> >           + shard-iclb: NOTRUN -> [125]FAIL ([i915#3457]) +13
> > similar
> >             issues
> >           + shard-glk: NOTRUN -> [126]FAIL ([i915#3444] /
> > [i915#3457]) +11
> >             similar issues
> >      * igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque:
> >           + shard-glk: [127]PASS -> [128]FAIL ([i915#3444] /
> > [i915#3457])
> >             +4 similar issues
> >           + shard-kbl: [129]PASS -> [130]FAIL ([i915#3444] /
> > [i915#3457])
> >      * igt@kms_cursor_crc@pipe-b-cursor-dpms:
> >           + shard-iclb: [131]PASS -> [132]FAIL ([i915#3457]) +1
> > similar
> >             issue
> >      * igt@kms_cursor_crc@pi
> > 
> > References
> > 
> >    1. https://patchwork.freedesktop.org/series/87570/
> >    2. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/index.html
> >    3. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb5/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
> >    4. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-apl7/igt@gem_ppgtt@blt-vs-render-ctx0.html
> >    5. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@gem_ppgtt@blt-vs-render-ctx0.html
> >    6. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb3/igt@gem_pxp@create-regular-context-1.html
> >    7. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk6/igt@gem_pxp@hw-rejects-pxp-context.html
> >    8. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb5/igt@gem_pxp@hw-rejects-pxp-context.html
> >    9. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb6/igt@gem_pxp@hw-rejects-pxp-context.html
> >   10. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl1/igt@gem_pxp@hw-rejects-pxp-context.html
> >   11. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
> >   12. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-tglb3/igt@i915_selftest@perf@request.html
> >   13. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb6/igt@i915_selftest@perf@request.html
> >   14. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk6/igt@kms_flip_tiling@flip-changes-tiling-y@hdmi-a-2-pipe-a.html
> >   15. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk3/igt@kms_flip_tiling@flip-changes-tiling-y@hdmi-a-2-pipe-a.html
> >   16. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
> >   17. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
> >   18. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb7/igt@api_intel_bb@blit-noreloc-purge-cache.html
> >   19. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk3/igt@api_intel_bb@blit-noreloc-purge-cache.html
> >   20. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@api_intel_bb@offset-control.html
> >   21. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk1/igt@api_intel_bb@offset-control.html
> >   22. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb2/igt@feature_discovery@chamelium.html
> >   23. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@feature_discovery@chamelium.html
> >   24. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb6/igt@gem_create@create-massive.html
> >   25. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@gem_create@create-massive.html
> >   26. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@gem_create@create-massive.html
> >   27. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@gem_create@create-massive.html
> >   28. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html
> >   29. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb7/igt@gem_ctx_persistence@legacy-engines-hostile.html
> >   30. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk5/igt@gem_ctx_persistence@many-contexts.html
> >   31. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@gem_ctx_persistence@many-contexts.html
> >   32. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@gem_eio@unwedge-stress.html
> >   33. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb5/igt@gem_eio@unwedge-stress.html
> >   34. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl6/igt@gem_exec_endless@dispatch@vecs0.html
> >   35. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@gem_exec_fair@basic-none-rrul@rcs0.html
> >   36. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
> >   37. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@gem_exec_fair@basic-none@vcs0.html
> >   38. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl3/igt@gem_exec_fair@basic-none@vcs1.html
> >   39. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-tglb2/igt@gem_exec_fair@basic-pace@rcs0.html
> >   40. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb6/igt@gem_exec_fair@basic-pace@rcs0.html
> >   41. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-iclb8/igt@gem_exec_fair@basic-pace@vcs0.html
> >   42. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@gem_exec_fair@basic-pace@vcs0.html
> >   43. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html
> >   44. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
> >   45. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk2/igt@gem_exec_schedule@preempt-hang@vcs0.html
> >   46. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk8/igt@gem_exec_schedule@preempt-hang@vcs0.html
> >   47. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@gem_exec_schedule@submit-early-slice@vecs0.html
> >   48. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@gem_exec_whisper@basic-contexts-all.html
> >   49. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-tglb2/igt@gem_huc_copy@huc-copy.html
> >   50. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb6/igt@gem_huc_copy@huc-copy.html
> >   51. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb7/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
> >   52. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-kbl1/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
> >   53. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl4/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
> >   54. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb2/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
> >   55. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl6/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
> >   56. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@gem_mmap_offset@clear.html
> >   57. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl6/igt@gem_pwrite@basic-exhaustion.html
> >   58. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl6/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html
> >   59. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
> >   60. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb1/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled.html
> >   61. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk5/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled.html
> >   62. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled.html
> >   63. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb6/igt@gem_softpin@evict-snoop-interruptible.html
> >   64. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb6/igt@gem_softpin@evict-snoop-interruptible.html
> >   65. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@gem_userptr_blits@dmabuf-sync.html
> >   66. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@gem_userptr_blits@dmabuf-unsync.html
> >   67. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb4/igt@gem_userptr_blits@dmabuf-unsync.html
> >   68. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-apl7/igt@gem_wait@await@bcs0.html
> >   69. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@gem_wait@await@bcs0.html
> >   70. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb2/igt@gen3_render_linear_blits.html
> >   71. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb7/igt@gen3_render_linear_blits.html
> >   72. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@gen7_exec_parse@basic-offset.html
> >   73. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@gen9_exec_parse@allowed-all.html
> >   74. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@gen9_exec_parse@bb-start-out.html
> >   75. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb7/igt@i915_hangman@error-state-capture@bcs0.html
> >   76. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb2/igt@i915_module_load@reload.html
> >   77. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@i915_module_load@reload.html
> >   78. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@i915_pm_dc@dc9-dpms.html
> >   79. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb1/igt@i915_pm_dc@dc9-dpms.html
> >   80. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-tglb6/igt@i915_pm_rpm@cursor.html
> >   81. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb6/igt@i915_pm_rpm@cursor.html
> >   82. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-kbl2/igt@i915_pm_rpm@cursor.html
> >   83. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl3/igt@i915_pm_rpm@cursor.html
> >   84. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk7/igt@i915_pm_rpm@cursor.html
> >   85. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk2/igt@i915_pm_rpm@cursor.html
> >   86. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb5/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
> >   87. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@i915_pm_rps@reset.html
> >   88. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk3/igt@kms_atomic@plane-immutable-zpos.html
> >   89. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk8/igt@kms_atomic@plane-immutable-zpos.html
> >   90. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb5/igt@kms_big_fb@linear-16bpp-rotate-90.html
> >   91. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@kms_big_fb@linear-16bpp-rotate-90.html
> >   92. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html
> >   93. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb1/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
> >   94. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb3/igt@kms_big_joiner@invalid-modeset.html
> >   95. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@kms_big_joiner@invalid-modeset.html
> >   96. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@kms_big_joiner@invalid-modeset.html
> >   97. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@kms_big_joiner@invalid-modeset.html
> >   98. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@kms_big_joiner@invalid-modeset.html
> >   99. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk3/igt@kms_chamelium@dp-hpd-storm-disable.html
> >  100. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl6/igt@kms_chamelium@dp-mode-timings.html
> >  101. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb6/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
> >  102. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@kms_chamelium@hdmi-hpd-storm.html
> >  103. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@kms_color@pipe-b-degamma.html
> >  104. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk3/igt@kms_color@pipe-b-degamma.html
> >  105. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb5/igt@kms_color@pipe-b-degamma.html
> >  106. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk5/igt@kms_color@pipe-c-degamma.html
> >  107. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk6/igt@kms_color@pipe-c-degamma.html
> >  108. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb5/igt@kms_color@pipe-d-ctm-0-25.html
> >  109. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@kms_color_chamelium@pipe-b-ctm-0-75.html
> >  110. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@kms_color_chamelium@pipe-b-ctm-red-to-blue.html
> >  111. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb7/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
> >  112. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@kms_content_protection@atomic-dpms.html
> >  113. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb7/igt@kms_content_protection@dp-mst-lic-type-1.html
> >  114. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb2/igt@kms_content_protection@dp-mst-lic-type-1.html
> >  115. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@kms_content_protection@uevent.html
> >  116. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@kms_content_protection@uevent.html
> >  117. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb1/igt@kms_content_protection@uevent.html
> >  118. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb5/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html
> >  119. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding.html
> >  120. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html
> >  121. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-dpms.html
> >  122. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-dpms.html
> >  123. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb6/igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen.html
> >  124. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@kms_cursor_crc@pipe-b-cursor-64x21-random.html
> >  125. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb7/igt@kms_cursor_crc@pipe-b-cursor-64x64-random.html
> >  126. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk1/igt@kms_cursor_crc@pipe-b-cursor-64x64-random.html
> >  127. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk8/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
> >  128. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk3/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
> >  129. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
> >  130. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
> >  131. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-iclb5/igt@kms_cursor_crc@pipe-b-cursor-dpms.html
> >  132. 
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb1/igt@kms_cursor_crc@pipe-b-cursor-dpms.html
> > _______________________________________________
> > igt-dev mailing list
> > igt-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] ✗ Fi.CI.IGT: failure for Introduce PXP Test (rev5)

[Rodrigo Vivi]

On Thu, Jun 03, 2021 at 02:09:40PM -0400, Teres Alexis, Alan Previn wrote:
> On Wed, 2021-06-02 at 17:44 -0400, Rodrigo Vivi wrote:
> > On Tue, May 18, 2021 at 06:19:48PM -0000, Patchwork wrote:
> > >    Patch Details
> > >
> > >    Series:  Introduce PXP Test (rev5)
> > >    URL:     [1]https://patchwork.freedesktop.org/series/87570/
> > >    State:   failure
> > >    Details:
> > >    [2]
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/index.html
> > >
> > >            CI Bug Log - changes from IGT_6087_full ->
> > > IGTPW_5817_full
> > >
> > > Summary
> > >
> > >    FAILURE
> > >
> > >    Serious unknown changes coming with IGTPW_5817_full absolutely
> > > need to
> > >    be
> > >    verified manually.
> > >
> > >    If you think the reported changes have nothing to do with the
> > > changes
> > >    introduced in IGTPW_5817_full, please notify your bug team to
> > > allow
> > >    them
> > >    to document this new failure mode, which will reduce false
> > > positives in
> > >    CI.
> > >
> > >    External URL:
> > >    https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/index.html
> > >
> > > Possible new issues
> > >
> > >    Here are the unknown changes that may have been introduced in
> > >    IGTPW_5817_full:
> > >
> > >   IGT changes
> > >
> > >     Possible regressions
> > >
> > >      * igt@gem_mmap_gtt@cpuset-basic-small-copy-xy:
> > >           + shard-snb: NOTRUN -> [3]INCOMPLETE
> > >      * igt@gem_ppgtt@blt-vs-render-ctx0:
> > >           + shard-apl: [4]PASS -> [5]FAIL
> >
> > since we are touching the render path for gen9+ we need to pay
> > attention
> > to cases like this...
> 
> In theory this doesnt make sense since I thought all changes I injected
> into the render code paths was fenced by "if batchbuffer has pxp
> enabled" or "if buffer has pxp enabled"- i will double check / trybot
> before i push next rev.

yeap, fully agree... but we should pay attention at least.

> 
> Side note: wrt below results where pxp test is failing on legacy HW,
> its due to kernel not yet supporting new PXP interface (where legacy HW
> would reply with -ENODEV vs -EINVAL when IGT is allocating protected
> buffers or contexts).

fully agree... we can just ignore those

> 
> >
> > >      * {igt@gem_pxp@create-regular-context-1} (NEW):
> > >           + shard-iclb: NOTRUN -> [6]SKIP +12 similar issues
> > >      * {igt@gem_pxp@hw-rejects-pxp-context} (NEW):
> > >           + shard-glk: NOTRUN -> [7]FAIL
> > >           + shard-iclb: NOTRUN -> [8]FAIL
> > >           + shard-snb: NOTRUN -> [9]FAIL
> > >           + shard-kbl: NOTRUN -> [10]FAIL
> > >      * {igt@gem_pxp@protected-encrypted-src-copy-not-readible}
> > > (NEW):
> > >           + shard-tglb: NOTRUN -> [11]FAIL +10 similar issues
> > >      * igt@i915_selftest@perf@request:
> > >           + shard-tglb: [12]PASS -> [13]DMESG-FAIL
> > >      * igt@kms_flip_tiling@flip-changes-tiling-y@hdmi-a-2-pipe-a:
> > >           + shard-glk: [14]PASS -> [15]FAIL +5 similar issues
> > >
> > >     Suppressed
> > >
> > >    The following results come from untrusted machines, tests, or
> > > statuses.
> > >    They do not affect the overall result.
> > >      * {igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-
> > > planes}:
> > >           + shard-glk: [16]PASS -> [17]FAIL
> > >
> > > New tests
> > >
> > >    New tests have been introduced between IGT_6087_full and
> > >    IGTPW_5817_full:
> > >
> > >   New IGT tests (20)
> > >
> > >      * igt@gem_pxp@create-protected-buffer:
> > >           + Statuses : 1 fail(s) 4 skip(s)
> > >           + Exec time: [0.0, 0.01] s
> > >      * igt@gem_pxp@create-regular-buffer:
> > >           + Statuses :
> > >           + Exec time: [None] s
> > >      * igt@gem_pxp@create-regular-context-1:
> > >           + Statuses : 1 fail(s) 4 skip(s)
> > >           + Exec time: [0.0, 0.01] s
> > >      * igt@gem_pxp@create-regular-context-2:
> > >           + Statuses : 1 fail(s) 4 skip(s)
> > >           + Exec time: [0.0, 0.02] s
> > >      * igt@gem_pxp@create-valid-protected-context:
> > >           + Statuses : 1 fail(s) 4 skip(s)
> > >           + Exec time: [0.0, 0.01] s
> > >      * igt@gem_pxp@display-protected-crc-with-hdcp:
> > >           + Statuses : 1 fail(s) 4 skip(s)
> > >           + Exec time: [0.0, 0.01] s
> > >      * igt@gem_pxp@display-protected-crc-without-hdcp:
> > >           + Statuses : 1 fail(s) 2 skip(s)
> > >           + Exec time: [0.0, 0.01] s
> > >      * igt@gem
> > > _pxp@dmabuf-shared-protected-dst-is-context-refcounted:
> > >           + Statuses : 1 fail(s) 4 skip(s)
> > >           + Exec time: [0.0, 0.03] s
> > >      * igt@gem_pxp@fail-invalid-protected-context:
> > >           + Statuses : 1 skip(s)
> > >           + Exec time: [0.0] s
> > >      * igt@gem_pxp@hw-rejects-pxp-buffer:
> > >           + Statuses :
> > >           + Exec time: [None] s
> > >      * igt@gem_pxp@hw-rejects-pxp-context:
> > >           + Statuses : 4 fail(s)
> > >           + Exec time: [0.01, 0.02] s
> > >      * igt@gem_pxp@protected-encrypted-src-copy-not-readible:
> > >           + Statuses : 1 fail(s) 5 skip(s)
> > >           + Exec time: [0.0, 0.01] s
> > >      * igt@gem_pxp@protected-raw-src-copy-not-readible:
> > >           + Statuses : 1 fail(s) 3 skip(s)
> > >           + Exec time: [0.0, 0.01] s
> > >      * igt@gem_pxp@regular-baseline-src-copy-readible:
> > >           + Statuses : 1 pass(s) 2 skip(s)
> > >           + Exec time: [0.0, 0.01] s
> > >      * igt@gem_pxp@reject-modify-context-protection-off-1:
> > >           + Statuses : 1 skip(s)
> > >           + Exec time: [0.0] s
> > >      * igt@gem_pxp@reject-modify-context-protection-off-2:
> > >           + Statuses :
> > >           + Exec time: [None] s
> > >      * igt@gem_pxp@reject-modify-context-protection-off-3:
> > >           + Statuses : 3 skip(s)
> > >           + Exec time: [0.0] s
> > >      * igt@gem_pxp@reject-modify-context-protection-on:
> > >           + Statuses : 1 fail(s) 5 skip(s)
> > >           + Exec time: [0.0, 0.00] s
> > >      * igt@gem
> > > _pxp@verify-pxp-execution-behavior-after-suspend-resume:
> > >           + Statuses :
> > >           + Exec time: [None] s
> > >      * igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
> > >           + Statuses : 1 fail(s) 5 skip(s)
> > >           + Exec time: [0.0, 0.01] s
> > >
> > > Known issues
> > >
> > >    Here are the changes found in IGTPW_5817_full that come from
> > > known
> > >    issues:
> > >
> > >   IGT changes
> > >
> > >     Issues hit
> > >
> > >      * igt@api_intel_bb@blit-noreloc-purge-cache:
> > >           + shard-iclb: NOTRUN -> [18]DMESG-WARN ([i915#3457]) +3
> > > similar
> > >             issues
> > >           + shard-glk: NOTRUN -> [19]DMESG-FAIL ([i915#3457]) +2
> > > similar
> > >             issues
> > >      * igt@api_intel_bb@offset-control:
> > >           + shard-apl: NOTRUN -> [20]DMESG-WARN ([i915#3457]) +1
> > > similar
> > >             issue
> > >           + shard-glk: NOTRUN -> [21]DMESG-WARN ([i915#3457])
> > >      * igt@feature_discovery@chamelium:
> > >           + shard-tglb: NOTRUN -> [22]SKIP ([fdo#111827])
> > >           + shard-iclb: NOTRUN -> [23]SKIP ([fdo#111827])
> > >      * igt@gem_create@create-massive:
> > >           + shard-iclb: NOTRUN -> [24]DMESG-WARN ([i915#3002])
> > >           + shard-kbl: NOTRUN -> [25]DMESG-WARN ([i915#3002])
> > >           + shard-tglb: NOTRUN -> [26]DMESG-WARN ([i915#3002])
> > >           + shard-glk: NOTRUN -> [27]DMESG-WARN ([i915#3002])
> > >      * igt@gem_ctx_isolation@preservation-s3@vcs0:
> > >           + shard-kbl: NOTRUN -> [28]DMESG-WARN ([i915#180] /
> > > [i915#3457])
> > >             +4 similar issues
> > >      * igt@gem_ctx_persistence@legacy-engines-hostile:
> > >           + shard-snb: NOTRUN -> [29]SKIP ([fdo#109271] /
> > > [i915#1099]) +2
> > >             similar issues
> > >      * igt@gem_ctx_persistence@many-contexts:
> > >           + shard-glk: [30]PASS -> [31]DMESG-WARN ([i915#118] /
> > >             [i915#3457] / [i915#95])
> > >      * igt@gem_eio@unwedge-stress:
> > >           + shard-apl: NOTRUN -> [32]FAIL ([i915#3457]) +10 similar
> > > issues
> > >           + shard-snb: NOTRUN -> [33]FAIL ([i915#3354] /
> > > [i915#3457])
> > >      * igt@gem_exec_endless@dispatch@vecs0:
> > >           + shard-apl: NOTRUN -> [34]INCOMPLETE ([i915#2502] /
> > >             [i915#3457])
> > >      * igt@gem_exec_fair@basic-none-rrul@rcs0:
> > >           + shard-iclb: NOTRUN -> [35]FAIL ([i915#2842] /
> > > [i915#3457]) +5
> > >             similar issues
> > >           + shard-glk: NOTRUN -> [36]INCOMPLETE ([i915#3457]) +1
> > > similar
> > >             issue
> > >      * igt@gem_exec_fair@basic-none@vcs0:
> > >           + shard-tglb: NOTRUN -> [37]FAIL ([i915#2842] /
> > > [i915#3457]) +5
> > >             similar issues
> > >      * igt@gem_exec_fair@basic-none@vcs1:
> > >           + shard-kbl: NOTRUN -> [38]FAIL ([i915#2842] /
> > > [i915#3457])
> > >      * igt@gem_exec_fair@basic-pace@rcs0:
> > >           + shard-tglb: [39]PASS -> [40]FAIL ([i915#2842] /
> > > [i915#3457])
> > >      * igt@gem_exec_fair@basic-pace@vcs0:
> > >           + shard-iclb: [41]PASS -> [42]FAIL ([i915#2842] /
> > > [i915#3457])
> > >      * igt@gem_exec_fair@basic-pace@vcs1:
> > >           + shard-kbl: [43]PASS -> [44]FAIL ([i915#2842] /
> > > [i915#3457])
> > >      * igt@gem_exec_schedule@preempt-hang@vcs0:
> > >           + shard-glk: [45]PASS -> [46]FAIL ([i915#3457]) +28
> > > similar
> > >             issues
> > >      * igt@gem_exec_schedule@submit-early-slice@vecs0:
> > >           + shard-glk: NOTRUN -> [47]FAIL ([i915#3457]) +50 similar
> > > issues
> > >      * igt@gem_exec_whisper@basic-contexts-all:
> > >           + shard-glk: NOTRUN -> [48]DMESG-WARN ([i915#118] /
> > > [i915#95])
> > >      * igt@gem_huc_copy@huc-copy:
> > >           + shard-tglb: [49]PASS -> [50]SKIP ([i915#2190])
> > >      * igt@gem_mmap_gtt@cpuset-basic-small-copy:
> > >           + shard-snb: NOTRUN -> [51]INCOMPLETE ([i915#3468]) +1
> > > similar
> > >             issue
> > >           + shard-kbl: [52]PASS -> [53]INCOMPLETE ([i915#3468])
> > >      * igt@gem_mmap_gtt@cpuset-basic-small-copy-xy:
> > >           + shard-tglb: NOTRUN -> [54]INCOMPLETE ([i915#3468]) +2
> > > similar
> > >             issues
> > >           + shard-kbl: NOTRUN -> [55]INCOMPLETE ([i915#3468]) +3
> > > similar
> > >             issues
> > >      * igt@gem_mmap_offset@clear:
> > >           + shard-glk: NOTRUN -> [56]FAIL ([i915#1888] /
> > > [i915#3160])
> > >      * igt@gem_pwrite@basic-exhaustion:
> > >           + shard-apl: NOTRUN -> [57]WARN ([i915#2658])
> > >      * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
> > >           + shard-apl: NOTRUN -> [58]INCOMPLETE ([i915#3468])
> > >      * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled:
> > >           + shard-iclb: NOTRUN -> [59]SKIP ([i915#768]) +4 similar
> > > issues
> > >      * igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled:
> > >           + shard-iclb: NOTRUN -> [60]INCOMPLETE ([i915#3468]) +2
> > > similar
> > >             issues
> > >           + shard-glk: NOTRUN -> [61]INCOMPLETE ([i915#3468]) +2
> > > similar
> > >             issues
> > >           + shard-tglb: NOTRUN -> [62]INCOMPLETE ([i915#3457] /
> > >             [i915#3468])
> > >      * igt@gem_softpin@evict-snoop-interruptible:
> > >           + shard-tglb: NOTRUN -> [63]SKIP ([fdo#109312])
> > >           + shard-iclb: NOTRUN -> [64]SKIP ([fdo#109312])
> > >      * igt@gem_userptr_blits@dmabuf-sync:
> > >           + shard-apl: NOTRUN -> [65]SKIP ([fdo#109271] /
> > > [i915#3323])
> > >      * igt@gem_userptr_blits@dmabuf-unsync:
> > >           + shard-tglb: NOTRUN -> [66]SKIP ([i915#3297]) +2 similar
> > > issues
> > >           + shard-iclb: NOTRUN -> [67]SKIP ([i915#3297]) +3 similar
> > > issues
> > >      * igt@gem_wait@await@bcs0:
> > >           + shard-apl: [68]PASS -> [69]FAIL ([i915#3457]) +1
> > > similar issue
> > >      * igt@gen3_render_linear_blits:
> > >           + shard-tglb: NOTRUN -> [70]SKIP ([fdo#109289]) +4
> > > similar
> > >             issues
> > >           + shard-iclb: NOTRUN -> [71]SKIP ([fdo#109289]) +3
> > > similar
> > >             issues
> > >      * igt@gen7_exec_parse@basic-offset:
> > >           + shard-apl: NOTRUN -> [72]SKIP ([fdo#109271]) +171
> > > similar
> > >             issues
> > >      * igt@gen9_exec_parse@allowed-all:
> > >           + shard-iclb: NOTRUN -> [73]SKIP ([fdo#112306]) +4
> > > similar
> > >             issues
> > >      * igt@gen9_exec_parse@bb-start-out:
> > >           + shard-tglb: NOTRUN -> [74]SKIP ([fdo#112306]) +3
> > > similar
> > >             issues
> > >      * igt@i915_hangman@error-state-capture@bcs0:
> > >           + shard-snb: NOTRUN -> [75]DMESG-WARN ([i915#3457]) +2
> > > similar
> > >             issues
> > >      * igt@i915_module_load@reload:
> > >           + shard-tglb: NOTRUN -> [76]DMESG-WARN ([i915#3457]) +3
> > > similar
> > >             issues
> > >           + shard-kbl: NOTRUN -> [77]DMESG-WARN ([i915#3457]) +5
> > > similar
> > >             issues
> > >      * igt@i915_pm_dc@dc9-dpms:
> > >           + shard-tglb: NOTRUN -> [78]SKIP ([i915#3288])
> > >           + shard-iclb: NOTRUN -> [79]FAIL ([i915#3343])
> > >      * igt@i915_pm_rpm@cursor:
> > >           + shard-tglb: [80]PASS -> [81]DMESG-WARN ([i915#2411] /
> > >             [i915#3457]) +1 similar issue
> > >           + shard-kbl: [82]PASS -> [83]DMESG-WARN ([i915#3457])
> > >           + shard-glk: [84]PASS -> [85]DMESG-WARN ([i915#3457])
> > >      * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
> > >           + shard-iclb: NOTRUN -> [86]SKIP ([fdo#110892]) +1
> > > similar issue
> > >      * igt@i915_pm_rps@reset:
> > >           + shard-apl: NOTRUN -> [87]DMESG-FAIL ([i915#3457]) +2
> > > similar
> > >             issues
> > >      * igt@kms_atomic@plane-immutable-zpos:
> > >           + shard-glk: [88]PASS -> [89]FAIL ([i915#2657] /
> > > [i915#3457])
> > >      * igt@kms_big_fb@linear-16bpp-rotate-90:
> > >           + shard-iclb: NOTRUN -> [90]SKIP ([fdo#110725] /
> > > [fdo#111614])
> > >             +6 similar issues
> > >           + shard-tglb: NOTRUN -> [91]SKIP ([fdo#111614]) +6
> > > similar
> > >             issues
> > >      * igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
> > >           + shard-tglb: NOTRUN -> [92]SKIP ([fdo#111615]) +3
> > > similar
> > >             issues
> > >      * igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
> > >           + shard-iclb: NOTRUN -> [93]SKIP ([fdo#110723])
> > >      * igt@kms_big_joiner@invalid-modeset:
> > >           + shard-iclb: NOTRUN -> [94]SKIP ([i915#2705])
> > >           + shard-kbl: NOTRUN -> [95]SKIP ([fdo#109271] /
> > > [i915#2705])
> > >           + shard-apl: NOTRUN -> [96]SKIP ([fdo#109271] /
> > > [i915#2705])
> > >           + shard-glk: NOTRUN -> [97]SKIP ([fdo#109271] /
> > > [i915#2705])
> > >           + shard-tglb: NOTRUN -> [98]SKIP ([i915#2705])
> > >      * igt@kms_chamelium@dp-hpd-storm-disable:
> > >           + shard-glk: NOTRUN -> [99]SKIP ([fdo#109271] /
> > > [fdo#111827])
> > >             +19 similar issues
> > >      * igt@kms_chamelium@dp-mode-timings:
> > >           + shard-apl: NOTRUN -> [100]SKIP ([fdo#109271] /
> > > [fdo#111827])
> > >             +15 similar issues
> > >      * igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
> > >           + shard-snb: NOTRUN -> [101]SKIP ([fdo#109271] /
> > > [fdo#111827])
> > >             +16 similar issues
> > >      * igt@kms_chamelium@hdmi-hpd-storm:
> > >           + shard-kbl: NOTRUN -> [102]SKIP ([fdo#109271] /
> > > [fdo#111827])
> > >             +30 similar issues
> > >      * igt@kms_color@pipe-b-degamma:
> > >           + shard-tglb: NOTRUN -> [103]FAIL ([i915#1149])
> > >           + shard-glk: NOTRUN -> [104]FAIL ([i915#71])
> > >           + shard-iclb: NOTRUN -> [105]FAIL ([i915#1149])
> > >      * igt@kms_color@pipe-c-degamma:
> > >           + shard-glk: [106]PASS -> [107]FAIL ([i915#71]) +1
> > > similar issue
> > >      * igt@kms_color@pipe-d-ctm-0-25:
> > >           + shard-iclb: NOTRUN -> [108]SKIP ([fdo#109278] /
> > > [i915#1149])
> > >             +2 similar issues
> > >      * igt@kms_color_chamelium@pipe-b-ctm-0-75:
> > >           + shard-tglb: NOTRUN -> [109]SKIP ([fdo#109284] /
> > > [fdo#111827])
> > >             +21 similar issues
> > >      * igt@kms_color_chamelium@pipe-b-ctm-red-to-blue:
> > >           + shard-iclb: NOTRUN -> [110]SKIP ([fdo#109284] /
> > > [fdo#111827])
> > >             +19 similar issues
> > >      * igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
> > >           + shard-iclb: NOTRUN -> [111]SKIP ([fdo#109278] /
> > > [fdo#109284] /
> > >             [fdo#111827]) +1 similar issue
> > >      * igt@kms_content_protection@atomic-dpms:
> > >           + shard-kbl: NOTRUN -> [112]TIMEOUT ([i915#1319])
> > >      * igt@kms_content_protection@dp-mst-lic-type-1:
> > >           + shard-iclb: NOTRUN -> [113]SKIP ([i915#3116])
> > >           + shard-tglb: NOTRUN -> [114]SKIP ([i915#3116])
> > >      * igt@kms_content_protection@uevent:
> > >           + shard-kbl: NOTRUN -> [115]FAIL ([i915#2105])
> > >           + shard-tglb: NOTRUN -> [116]SKIP ([fdo#111828])
> > >           + shard-iclb: NOTRUN -> [117]SKIP ([fdo#109300] /
> > > [fdo#111066])
> > >      * igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen:
> > >           + shard-snb: NOTRUN -> [118]FAIL ([i915#3457]) +4 similar
> > > issues
> > >      * igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding:
> > >           + shard-tglb: NOTRUN -> [119]SKIP ([i915#3319] /
> > > [i915#3457]) +6
> > >             similar issues
> > >      * igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen:
> > >           + shard-kbl: NOTRUN -> [120]FAIL ([i915#3444] /
> > > [i915#3457]) +16
> > >             similar issues
> > >      * igt@kms_cursor_crc@pipe-a-cursor-dpms:
> > >           + shard-apl: [121]PASS -> [122]FAIL ([i915#3444] /
> > > [i915#3457])
> > >      * igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen:
> > >           + shard-iclb: NOTRUN -> [123]SKIP ([fdo#109278] /
> > > [fdo#109279] /
> > >             [i915#3457]) +6 similar issues
> > >      * igt@kms_cursor_crc@pipe-b-cursor-64x21-random:
> > >           + shard-apl: NOTRUN -> [124]FAIL ([i915#3444] /
> > > [i915#3457]) +3
> > >             similar issues
> > >      * igt@kms_cursor_crc@pipe-b-cursor-64x64-random:
> > >           + shard-iclb: NOTRUN -> [125]FAIL ([i915#3457]) +13
> > > similar
> > >             issues
> > >           + shard-glk: NOTRUN -> [126]FAIL ([i915#3444] /
> > > [i915#3457]) +11
> > >             similar issues
> > >      * igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque:
> > >           + shard-glk: [127]PASS -> [128]FAIL ([i915#3444] /
> > > [i915#3457])
> > >             +4 similar issues
> > >           + shard-kbl: [129]PASS -> [130]FAIL ([i915#3444] /
> > > [i915#3457])
> > >      * igt@kms_cursor_crc@pipe-b-cursor-dpms:
> > >           + shard-iclb: [131]PASS -> [132]FAIL ([i915#3457]) +1
> > > similar
> > >             issue
> > >      * igt@kms_cursor_crc@pi
> > >
> > > References
> > >
> > >    1. https://patchwork.freedesktop.org/series/87570/
> > >    2.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/index.html
> > >    3.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb5/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
> > >    4.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-apl7/igt@gem_ppgtt@blt-vs-render-ctx0.html
> > >    5.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@gem_ppgtt@blt-vs-render-ctx0.html
> > >    6.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb3/igt@gem_pxp@create-regular-context-1.html
> > >    7.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk6/igt@gem_pxp@hw-rejects-pxp-context.html
> > >    8.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb5/igt@gem_pxp@hw-rejects-pxp-context.html
> > >    9.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb6/igt@gem_pxp@hw-rejects-pxp-context.html
> > >   10.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl1/igt@gem_pxp@hw-rejects-pxp-context.html
> > >   11.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
> > >   12.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-tglb3/igt@i915_selftest@perf@request.html
> > >   13.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb6/igt@i915_selftest@perf@request.html
> > >   14.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk6/igt@kms_flip_tiling@flip-changes-tiling-y@hdmi-a-2-pipe-a.html
> > >   15.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk3/igt@kms_flip_tiling@flip-changes-tiling-y@hdmi-a-2-pipe-a.html
> > >   16.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
> > >   17.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
> > >   18.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb7/igt@api_intel_bb@blit-noreloc-purge-cache.html
> > >   19.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk3/igt@api_intel_bb@blit-noreloc-purge-cache.html
> > >   20.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@api_intel_bb@offset-control.html
> > >   21.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk1/igt@api_intel_bb@offset-control.html
> > >   22.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb2/igt@feature_discovery@chamelium.html
> > >   23.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@feature_discovery@chamelium.html
> > >   24.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb6/igt@gem_create@create-massive.html
> > >   25.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@gem_create@create-massive.html
> > >   26.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@gem_create@create-massive.html
> > >   27.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@gem_create@create-massive.html
> > >   28.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html
> > >   29.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb7/igt@gem_ctx_persistence@legacy-engines-hostile.html
> > >   30.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk5/igt@gem_ctx_persistence@many-contexts.html
> > >   31.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@gem_ctx_persistence@many-contexts.html
> > >   32.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@gem_eio@unwedge-stress.html
> > >   33.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb5/igt@gem_eio@unwedge-stress.html
> > >   34.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl6/igt@gem_exec_endless@dispatch@vecs0.html
> > >   35.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@gem_exec_fair@basic-none-rrul@rcs0.html
> > >   36.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
> > >   37.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@gem_exec_fair@basic-none@vcs0.html
> > >   38.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl3/igt@gem_exec_fair@basic-none@vcs1.html
> > >   39.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-tglb2/igt@gem_exec_fair@basic-pace@rcs0.html
> > >   40.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb6/igt@gem_exec_fair@basic-pace@rcs0.html
> > >   41.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-iclb8/igt@gem_exec_fair@basic-pace@vcs0.html
> > >   42.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@gem_exec_fair@basic-pace@vcs0.html
> > >   43.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html
> > >   44.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
> > >   45.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk2/igt@gem_exec_schedule@preempt-hang@vcs0.html
> > >   46.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk8/igt@gem_exec_schedule@preempt-hang@vcs0.html
> > >   47.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@gem_exec_schedule@submit-early-slice@vecs0.html
> > >   48.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@gem_exec_whisper@basic-contexts-all.html
> > >   49.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-tglb2/igt@gem_huc_copy@huc-copy.html
> > >   50.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb6/igt@gem_huc_copy@huc-copy.html
> > >   51.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb7/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
> > >   52.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-kbl1/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
> > >   53.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl4/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
> > >   54.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb2/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
> > >   55.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl6/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
> > >   56.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@gem_mmap_offset@clear.html
> > >   57.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl6/igt@gem_pwrite@basic-exhaustion.html
> > >   58.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl6/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html
> > >   59.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
> > >   60.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb1/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled.html
> > >   61.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk5/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled.html
> > >   62.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled.html
> > >   63.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb6/igt@gem_softpin@evict-snoop-interruptible.html
> > >   64.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb6/igt@gem_softpin@evict-snoop-interruptible.html
> > >   65.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@gem_userptr_blits@dmabuf-sync.html
> > >   66.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@gem_userptr_blits@dmabuf-unsync.html
> > >   67.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb4/igt@gem_userptr_blits@dmabuf-unsync.html
> > >   68.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-apl7/igt@gem_wait@await@bcs0.html
> > >   69.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@gem_wait@await@bcs0.html
> > >   70.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb2/igt@gen3_render_linear_blits.html
> > >   71.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb7/igt@gen3_render_linear_blits.html
> > >   72.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@gen7_exec_parse@basic-offset.html
> > >   73.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@gen9_exec_parse@allowed-all.html
> > >   74.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@gen9_exec_parse@bb-start-out.html
> > >   75.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb7/igt@i915_hangman@error-state-capture@bcs0.html
> > >   76.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb2/igt@i915_module_load@reload.html
> > >   77.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@i915_module_load@reload.html
> > >   78.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@i915_pm_dc@dc9-dpms.html
> > >   79.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb1/igt@i915_pm_dc@dc9-dpms.html
> > >   80.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-tglb6/igt@i915_pm_rpm@cursor.html
> > >   81.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb6/igt@i915_pm_rpm@cursor.html
> > >   82.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-kbl2/igt@i915_pm_rpm@cursor.html
> > >   83.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl3/igt@i915_pm_rpm@cursor.html
> > >   84.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk7/igt@i915_pm_rpm@cursor.html
> > >   85.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk2/igt@i915_pm_rpm@cursor.html
> > >   86.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb5/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
> > >   87.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@i915_pm_rps@reset.html
> > >   88.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk3/igt@kms_atomic@plane-immutable-zpos.html
> > >   89.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk8/igt@kms_atomic@plane-immutable-zpos.html
> > >   90.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb5/igt@kms_big_fb@linear-16bpp-rotate-90.html
> > >   91.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@kms_big_fb@linear-16bpp-rotate-90.html
> > >   92.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html
> > >   93.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb1/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
> > >   94.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb3/igt@kms_big_joiner@invalid-modeset.html
> > >   95.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@kms_big_joiner@invalid-modeset.html
> > >   96.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@kms_big_joiner@invalid-modeset.html
> > >   97.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk7/igt@kms_big_joiner@invalid-modeset.html
> > >   98.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@kms_big_joiner@invalid-modeset.html
> > >   99.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk3/igt@kms_chamelium@dp-hpd-storm-disable.html
> > >  100.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl6/igt@kms_chamelium@dp-mode-timings.html
> > >  101.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb6/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
> > >  102.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@kms_chamelium@hdmi-hpd-storm.html
> > >  103.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@kms_color@pipe-b-degamma.html
> > >  104.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk3/igt@kms_color@pipe-b-degamma.html
> > >  105.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb5/igt@kms_color@pipe-b-degamma.html
> > >  106.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk5/igt@kms_color@pipe-c-degamma.html
> > >  107.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk6/igt@kms_color@pipe-c-degamma.html
> > >  108.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb5/igt@kms_color@pipe-d-ctm-0-25.html
> > >  109.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@kms_color_chamelium@pipe-b-ctm-0-75.html
> > >  110.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb8/igt@kms_color_chamelium@pipe-b-ctm-red-to-blue.html
> > >  111.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb7/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
> > >  112.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@kms_content_protection@atomic-dpms.html
> > >  113.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb7/igt@kms_content_protection@dp-mst-lic-type-1.html
> > >  114.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb2/igt@kms_content_protection@dp-mst-lic-type-1.html
> > >  115.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@kms_content_protection@uevent.html
> > >  116.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb1/igt@kms_content_protection@uevent.html
> > >  117.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb1/igt@kms_content_protection@uevent.html
> > >  118.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-snb5/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html
> > >  119.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-tglb5/igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding.html
> > >  120.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html
> > >  121.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-dpms.html
> > >  122.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-dpms.html
> > >  123.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb6/igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen.html
> > >  124.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-apl7/igt@kms_cursor_crc@pipe-b-cursor-64x21-random.html
> > >  125.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb7/igt@kms_cursor_crc@pipe-b-cursor-64x64-random.html
> > >  126.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk1/igt@kms_cursor_crc@pipe-b-cursor-64x64-random.html
> > >  127.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-glk8/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
> > >  128.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-glk3/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
> > >  129.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
> > >  130.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-kbl2/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
> > >  131.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6087/shard-iclb5/igt@kms_cursor_crc@pipe-b-cursor-dpms.html
> > >  132.
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5817/shard-iclb1/igt@kms_cursor_crc@pipe-b-cursor-dpms.html
> > > _______________________________________________
> > > igt-dev mailing list
> > > igt-dev@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t 11/17] Verify PXP teardown occurred through suspend-resume

[Rodrigo Vivi]

On Tue, May 18, 2021 at 03:33:38AM -0700, Alan Previn wrote:
> During a suspend-resume cycle, the hardware and driver shall
> ensure the PXP session and keys are torn down and re-
> established. Verify that key change did occur by repeating
> the 3d rendercopy operation before and after a suspend cycle
> and ensuring that the encrypted output is different.
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  tests/i915/gem_pxp.c | 67 +++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 66 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
> index 2f2d2716..10134604 100644
> --- a/tests/i915/gem_pxp.c
> +++ b/tests/i915/gem_pxp.c
> @@ -9,6 +9,12 @@
>  IGT_TEST_DESCRIPTION("Test PXP that manages protected content through arbitrated HW-PXP-session");
>  /* Note: PXP = "Protected Xe Path" */
>  
> +/* Struct and definitions for power management. */
> +struct powermgt_data {
> +	int debugfsdir;
> +	bool has_runtime_pm;
> +};
> +
>  static bool is_pxp_hw_supported(int i915)
>  {
>  	uint32_t devid = intel_get_drm_devid(i915);
> @@ -465,7 +471,7 @@ static void test_render_baseline(int i915)
>  	buf_ops_destroy(bops);
>  }
>  
> -static void test_render_pxp_src_to_protdest(int i915)
> +static void __test_render_pxp_src_to_protdest(int i915, uint32_t *outpixels, int outsize)
>  {
>  	uint32_t ctx, srcbo, dstbo;
>  	struct intel_buf *srcbuf, *dstbuf;
> @@ -507,6 +513,10 @@ static void test_render_pxp_src_to_protdest(int i915)
>  	assert_bo_content_check(i915, dstbo, COMPARE_COLOR_UNREADIBLE,
>  				TSTSURF_SIZE, TSTSURF_FILLCOLOR2, NULL, 0);
>  
> +	if (outpixels)
> +		assert_bo_content_check(i915, dstbo, COPY_BUFFER,
> +					TSTSURF_SIZE, 0, outpixels, outsize);
> +
>  	intel_bb_destroy(ibb);
>  	intel_buf_destroy(srcbuf);
>  	gem_close(i915, srcbo);
> @@ -516,6 +526,11 @@ static void test_render_pxp_src_to_protdest(int i915)
>  	buf_ops_destroy(bops);
>  }
>  
> +static void test_render_pxp_src_to_protdest(int i915)
> +{
> +	__test_render_pxp_src_to_protdest(i915, NULL, 0);
> +}
> +
>  static void test_render_pxp_protsrc_to_protdest(int i915)
>  {
>  	uint32_t ctx, srcbo, dstbo, dstbo2;
> @@ -595,10 +610,47 @@ static void test_render_pxp_protsrc_to_protdest(int i915)
>  	buf_ops_destroy(bops);
>  }
>  
> +static void init_powermgt_resources(int i915, struct powermgt_data *pm)
> +{
> +	pm->debugfsdir = igt_debugfs_dir(i915);
> +	igt_require(pm->debugfsdir != -1);
> +	pm->has_runtime_pm = igt_setup_runtime_pm(i915);
> +	igt_require(pm->has_runtime_pm);
> +}
> +
> +static void trigger_powermgt_suspend_cycle(int i915,
> +	struct powermgt_data *pm)
> +{
> +	igt_pm_enable_sata_link_power_management();
> +	igt_system_suspend_autoresume(SUSPEND_STATE_MEM, SUSPEND_TEST_DEVICES);
> +	igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_SUSPENDED);
> +}
> +
> +static void test_pxp_pwrcycle_teardown_keychange(int i915, struct powermgt_data *pm)
> +{
> +	uint32_t encrypted_pixels_b4[TSTSURF_SIZE/TSTSURF_BYTESPP];
> +	uint32_t encrypted_pixels_aft[TSTSURF_SIZE/TSTSURF_BYTESPP];
> +	int matched_after_keychange = 0, loop = 0;
> +
> +	__test_render_pxp_src_to_protdest(i915, encrypted_pixels_b4, TSTSURF_SIZE);
> +
> +	trigger_powermgt_suspend_cycle(i915, pm);
> +
> +	__test_render_pxp_src_to_protdest(i915, encrypted_pixels_aft, TSTSURF_SIZE);
> +
> +	while (loop < (TSTSURF_SIZE/TSTSURF_BYTESPP)) {
> +		if (encrypted_pixels_b4[loop] == encrypted_pixels_aft[loop])
> +			++matched_after_keychange;
> +		++loop;
> +	}
> +	igt_assert_eq(matched_after_keychange, 0);
> +}
> +
>  igt_main
>  {
>  	int i915 = -1;
>  	bool pxp_supported = false;
> +	struct powermgt_data pm = {0};
>  	igt_render_copyfunc_t rendercopy = NULL;
>  	uint32_t devid = 0;
>  
> @@ -671,6 +723,19 @@ igt_main
>  		igt_subtest("protected-encrypted-src-copy-not-readible")
>  			test_render_pxp_protsrc_to_protdest(i915);
>  	}
> +	igt_subtest_group {
> +		igt_fixture {
> +			igt_require(pxp_supported);
> +			devid = intel_get_drm_devid(i915);
> +			igt_assert(devid);
> +			rendercopy = igt_get_render_copyfunc(devid);
> +			igt_require(rendercopy);
> +			init_powermgt_resources(i915, &pm);
> +		}
> +		igt_describe("Verify suspend-resume teardown management:");
> +		igt_subtest("verify-pxp-key-change-after-suspend-resume")
> +			test_pxp_pwrcycle_teardown_keychange(i915, &pm);
> +	}
>  
>  	igt_fixture {
>  		close(i915);
> -- 
> 2.25.1
> 
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t 13/17] Verify execbuf fails with stale PXP buffer after teardown

[Rodrigo Vivi]

On Tue, May 18, 2021 at 03:33:40AM -0700, Alan Previn wrote:
> Add a check to verify that reusing a stale protected buffer
> in a gem_execbuff (with a protected context) after a teardown
> (triggered by suspend-resume cycle) shall fail with -ENOEXEC error.
> Reuse the existing subtest function to with separate assets
> to minimize the number of suspend-resume cycles we take.
> 
> NOTE: The end-to-end architecture requirement includes that
> any break in the links of the PXP sessions needs to trigger a
> full teardown and the application needs to be made aware of that
> allowing it to re-establish the end-to-end pipeline of buffers,
> contexts and renders again if it chooses to. This stricter
> behavior targets only contexts created with PXP enabled.
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  tests/i915/gem_pxp.c | 34 ++++++++++++++++++++++++++++------
>  1 file changed, 28 insertions(+), 6 deletions(-)
> 
> diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
> index f1ef0a24..b4f369ae 100644
> --- a/tests/i915/gem_pxp.c
> +++ b/tests/i915/gem_pxp.c
> @@ -760,23 +760,45 @@ static void free_exec_assets(int i915, struct simple_exec_assets *data)
>  static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_data *pm)
>  {
>  	int ret;
> -	struct simple_exec_assets data = {0};
> +	struct simple_exec_assets data[2] = {{0}, {0}};
> +	uint32_t ctx2;
> +	struct intel_bb *ibb2;
>  
>  	/*
> -	 * Use normal buffers for testing for invalidation
> +	 * For data[0]: Use normal buffers for testing for invalidation
>  	 * of protected contexts to ensure kernel is catching
>  	 * the invalidated context (not buffer)
>  	 */
> -	prepare_exec_assets(i915, &data, true, false);
> -	ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf);
> +	prepare_exec_assets(i915, &data[0], true, false);
> +	ret = gem_execbuf_flush_store_dw(i915, data[0].ibb, data[0].ctx, data[0].fencebuf);
> +	igt_assert(ret == 0);
> +
> +	prepare_exec_assets(i915, &data[1], true, true);
> +	ret = gem_execbuf_flush_store_dw(i915, data[1].ibb, data[1].ctx, data[1].fencebuf);
>  	igt_assert(ret == 0);
>  
>  	trigger_powermgt_suspend_cycle(i915, pm);
>  
> -	ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf);
> +	ret = gem_execbuf_flush_store_dw(i915, data[0].ibb, data[0].ctx, data[0].fencebuf);
>  	igt_assert_f((ret == -EACCES), "Executing stale pxp context didn't fail with -EACCES\n");
>  
> -	free_exec_assets(i915, &data);
> +	/*
> +	 * For data[1]: after teardown, alloc new assets for context but
> +	 * reuse the bo to ensure the kernel is catching the
> +	 * invalidated bo (not context)
> +	 */
> +	ret = create_ctx_with_params(i915, true, true, true, false, &ctx2);
> +	igt_assert_eq(ret, 0);
> +	igt_assert_eq(get_ctx_protected_param(i915, ctx2), 1);
> +	ibb2 = intel_bb_create_with_context(i915, ctx2, 4096);
> +	igt_assert(ibb2);
> +	intel_bb_detach_intel_buf(data[1].ibb, data[1].fencebuf);
> +	intel_bb_add_intel_buf(ibb2, data[1].fencebuf, true);
> +	ret = gem_execbuf_flush_store_dw(i915, ibb2, ctx2, data[1].fencebuf);
> +	igt_assert_f((ret == -ENOEXEC), "Executing stale pxp buffer didn't fail with -ENOEXEC\n");
> +
> +	free_exec_assets(i915, &data[0]);
> +	free_exec_assets(i915, &data[1]);
>  }
>  
>  igt_main
> -- 
> 2.25.1
> 
> _______________________________________________
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> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t 15/17] Ensure RESET_STATS reports invalidated protected context

[Rodrigo Vivi]

On Tue, May 18, 2021 at 03:33:42AM -0700, Alan Previn wrote:
> When protected contexts are created but get invalidated
> due to PXP session teardown (such as after a suspend-resume
> cycle), RESET_STATS ioctl for said context will report it
> as I915_CONTEXT_INVALIDATED.
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  tests/i915/gem_pxp.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
> index e3c21c70..69a3143a 100644
> --- a/tests/i915/gem_pxp.c
> +++ b/tests/i915/gem_pxp.c
> @@ -757,6 +757,22 @@ static void free_exec_assets(int i915, struct simple_exec_assets *data)
>  	buf_ops_destroy(data->bops);
>  }
>  
> +static bool is_context_valid(int i915, uint32_t ctx)
> +{
> +	struct drm_i915_reset_stats rs;
> +	int ret;
> +
> +	memset(&rs, 0, sizeof(rs));
> +	rs.ctx_id = ctx;
> +	ret = drmIoctl(i915, DRM_IOCTL_I915_GET_RESET_STATS, &rs);
> +	igt_assert(ret == 0);
> +
> +	if (rs.flags & I915_CONTEXT_INVALIDATED)
> +		return false;
> +
> +	return true;
> +}
> +
>  static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_data *pm)
>  {
>  	int ret;
> @@ -788,6 +804,8 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
>  
>  	trigger_powermgt_suspend_cycle(i915, pm);
>  
> +	igt_assert_f(!is_context_valid(i915, data[0].ctx),
> +				       "RESET_STATS missed INVAL bit on stale pxp context\n");
>  	ret = gem_execbuf_flush_store_dw(i915, data[0].ibb, data[0].ctx, data[0].fencebuf);
>  	igt_assert_f((ret == -EACCES), "Executing stale pxp context didn't fail with -EACCES\n");
>  
> @@ -796,6 +814,8 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
>  	 * reuse the bo to ensure the kernel is catching the
>  	 * invalidated bo (not context)
>  	 */
> +	igt_assert_f(!is_context_valid(i915, data[1].ctx),
> +				       "RESET_STATS missed INVAL bit on stale pxp context\n");
>  	ret = create_ctx_with_params(i915, true, true, true, false, &ctx2);
>  	igt_assert_eq(ret, 0);
>  	igt_assert_eq(get_ctx_protected_param(i915, ctx2), 1);
> @@ -806,6 +826,8 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
>  	ret = gem_execbuf_flush_store_dw(i915, ibb2, ctx2, data[1].fencebuf);
>  	igt_assert_f((ret == -ENOEXEC), "Executing stale pxp buffer didn't fail with -ENOEXEC\n");
>  
> +	igt_assert_f(is_context_valid(i915, data[2].ctx),
> +				       "RESET_STATS false-hit on opt-out context\n");
>  	ret = gem_execbuf_flush_store_dw(i915, data[2].ibb, data[2].ctx, data[2].fencebuf);
>  	igt_assert_f((ret == 0), "Opt-out-execution with stale pxp buffer didn't succeed\n");
>  
> -- 
> 2.25.1
> 
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Re: [igt-dev] [PATCH i-g-t 08/17] Enable protected session cmd in gen12_render_copyfunc

[Rodrigo Vivi]

On Tue, May 18, 2021 at 03:33:35AM -0700, Alan Previn wrote:
> 1. In _gen9_render_op, check if the incoming batchbuffer
>    is marked with pxp enabled. If so, insert MI_SET_APPID
>    along with PIPE_CONTROL instructions at the start and
>    end of the rendering operation in the command buffer.
> 
> 2. The two PIPE_CONTROLs will enable protected memory
>    at the start of the batch and disabling protected
>    memory at the end of it. These PIPE_CONTROLs require a
>    Post-Sync operation with a write to memory for hardware
>    to accept.
> 
> 3. In order to satisfy #2, _gen9_render_op uses unused
>    regions of the ibb buffer for the PIPE_CONTROL PostSync
>    write to memory (no different from how other 3d states
>    are being referenced).
> 
> 4. _gen9_render_op shall check the incoming surface
>    buffers for "is_protected" flag and if its set, it
>    will mark the SURFACE_STATE's MOCS field accordingly.
> 
> NOTE: _gen9_render_op needs to program the HW to enable
> the PXP session as part of the rendering batch buffer
> because the HW requires that enabling/disabling protected
> memory access must be programmed in pairs within the same
> "dispatch of rendering commands" to HW.
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
>  lib/rendercopy_gen9.c | 72 ++++++++++++++++++++++++++++++++++++++-----
>  1 file changed, 65 insertions(+), 7 deletions(-)
> 
> diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
> index eecf73d3..bfcf311b 100644
> --- a/lib/rendercopy_gen9.c
> +++ b/lib/rendercopy_gen9.c
> @@ -19,7 +19,8 @@
>  #include "intel_bufops.h"
>  #include "intel_batchbuffer.h"
>  #include "intel_io.h"
> -#include "rendercopy.h"
> +#include "igt.h"
> +#include "i915/gem.h"
>  #include "gen9_render.h"
>  #include "intel_reg.h"
>  #include "igt_aux.h"
> @@ -152,6 +153,8 @@ gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst) {
>  		ss->ss0.tiled_mode = 3;
>  
>  	ss->ss1.memory_object_control = I915_MOCS_PTE << 1;
> +	if (intel_buf_pxp(buf))
> +		ss->ss1.memory_object_control |= 1;
>  
>  	if (buf->tiling == I915_TILING_Yf)
>  		ss->ss5.trmode = 1;
> @@ -873,6 +876,53 @@ static void gen8_emit_primitive(struct intel_bb *ibb, uint32_t offset)
>  	intel_bb_out(ibb, 0);	/* index buffer offset, ignored */
>  }
>  
> +#define GFX_OP_PIPE_CONTROL    ((3 << 29) | (3 << 27) | (2 << 24))

there's no len defined here...

> +#define PIPE_CONTROL_CS_STALL	            (1 << 20)
> +#define PIPE_CONTROL_RENDER_TARGET_FLUSH    (1 << 12)
> +#define PIPE_CONTROL_FLUSH_ENABLE           (1 << 7)
> +#define PIPE_CONTROL_DATA_CACHE_INVALIDATE  (1 << 5)
> +#define PIPE_CONTROL_PROTECTEDPATH_DISABLE  (1 << 27)
> +#define PIPE_CONTROL_PROTECTEDPATH_ENABLE   (1 << 22)
> +#define PIPE_CONTROL_POST_SYNC_OP           (1 << 14)
> +#define PIPE_CONTROL_POST_SYNC_OP_STORE_DW_IDX (1 << 21)
> +#define PS_OP_TAG_START                     0x1234fed0
> +#define PS_OP_TAG_END                       0x5678cbaf
> +static void gen12_emit_pxp_state(struct intel_bb *ibb, bool enable,
> +		 uint32_t pxp_write_op_offset)
> +{
> +	uint32_t pipe_ctl_flags;
> +	uint32_t set_app_id, ps_op_id;
> +
> +	if (enable) {
> +		pipe_ctl_flags = PIPE_CONTROL_FLUSH_ENABLE;
> +		intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);

... so, I believe this one should be GFX_OP_PIPE_CONTROL | 1

(len - 2) = (3 - 2) = 1

> +		intel_bb_out(ibb, pipe_ctl_flags);
> +
> +		set_app_id =  MI_SET_APPID |
> +			      APPTYPE(intel_bb_pxp_apptype(ibb)) |
> +			      APPID(intel_bb_pxp_appid(ibb));
> +		intel_bb_out(ibb, set_app_id);
> +
> +		pipe_ctl_flags = PIPE_CONTROL_PROTECTEDPATH_ENABLE;
> +		ps_op_id = PS_OP_TAG_START;
> +	} else {
> +		pipe_ctl_flags = PIPE_CONTROL_PROTECTEDPATH_DISABLE;
> +		ps_op_id = PS_OP_TAG_END;
> +	}
> +
> +	pipe_ctl_flags |= (PIPE_CONTROL_CS_STALL |
> +			   PIPE_CONTROL_RENDER_TARGET_FLUSH |
> +			   PIPE_CONTROL_DATA_CACHE_INVALIDATE |
> +			   PIPE_CONTROL_POST_SYNC_OP);
> +	intel_bb_out(ibb, GFX_OP_PIPE_CONTROL | 4);

and this one should be GFX_OP_PIPE_CONTROL | 2

(len - 2) = (4 - 2) = 2

but to be honest, I always get lost and confused with these pipe_control len...
specially looking IGT tests, many of them don't make sense to me.

However I see, at least, some inconsistency here between these 2 pipe_control
emissions. What am I missing?

> +	intel_bb_out(ibb, pipe_ctl_flags);
> +	intel_bb_emit_reloc(ibb, ibb->handle, 0, I915_GEM_DOMAIN_COMMAND,
> +			    (enable ? pxp_write_op_offset : (pxp_write_op_offset+8)),
> +			    ibb->batch_offset);
> +	intel_bb_out(ibb, ps_op_id);
> +	intel_bb_out(ibb, ps_op_id);
> +}
> +
>  /* The general rule is if it's named gen6 it is directly copied from
>   * gen6_render_copyfunc.
>   *
> @@ -922,6 +972,7 @@ void _gen9_render_op(struct intel_bb *ibb,
>  	uint32_t vertex_buffer;
>  	uint32_t aux_pgtable_state;
>  	bool fast_clear = !src;
> +	uint32_t pxp_scratch_offset;
>  
>  	if (!fast_clear)
>  		igt_assert(src->bpp == dst->bpp);
> @@ -950,8 +1001,12 @@ void _gen9_render_op(struct intel_bb *ibb,
>  	aux_pgtable_state = gen12_create_aux_pgtable_state(ibb, aux_pgtable_buf);
>  
>  	/* TODO: there is other state which isn't setup */
> +	pxp_scratch_offset = intel_bb_offset(ibb);
>  	intel_bb_ptr_set(ibb, 0);
>  
> +	if (intel_bb_pxp_enabled(ibb))
> +		gen12_emit_pxp_state(ibb, true, pxp_scratch_offset);
> +
>  	/* Start emitting the commands. The order roughly follows the mesa blorp
>  	 * order */
>  	intel_bb_out(ibb, G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D |
> @@ -963,13 +1018,12 @@ void _gen9_render_op(struct intel_bb *ibb,
>  		for (int i = 0; i < 4; i++) {
>  			intel_bb_out(ibb, MI_STORE_DWORD_IMM);
>  			intel_bb_emit_reloc(ibb, dst->handle,
> -					    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
> -                                            dst->cc.offset + i*sizeof(float),
> -					    dst->addr.offset);
> +					I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
> +					dst->cc.offset + i*sizeof(float),
> +					dst->addr.offset);
>  			intel_bb_out(ibb, *(uint32_t*)&clear_color[i]);
> -               }
> -       }
> -
> +		}
> +	}
>  
>  	gen8_emit_sip(ibb);
>  
> @@ -1023,10 +1077,14 @@ void _gen9_render_op(struct intel_bb *ibb,
>  	gen8_emit_vf_topology(ibb);
>  	gen8_emit_primitive(ibb, vertex_buffer);
>  
> +	if (intel_bb_pxp_enabled(ibb))
> +		gen12_emit_pxp_state(ibb, false, pxp_scratch_offset);
> +
>  	intel_bb_emit_bbe(ibb);
>  	intel_bb_exec(ibb, intel_bb_offset(ibb),
>  		      I915_EXEC_RENDER | I915_EXEC_NO_RELOC, false);
>  	dump_batch(ibb);
> +
>  	intel_bb_reset(ibb, false);
>  }
>  
> -- 
> 2.25.1
> 
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Re: [igt-dev] [PATCH i-g-t 09/17] Add subtest to copy raw source to protected dest

[Rodrigo Vivi]

On Tue, May 18, 2021 at 03:33:36AM -0700, Alan Previn wrote:
> Add subtest to 3d-copy raw source buffer (with
> known readible content) to a destination buffer
> marked as protected with a protected session using
> default session keys. The destination buffer is
> verified to be different from the source (when
> read via CPU) because its encrypted.
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
>  tests/i915/gem_pxp.c | 55 ++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 55 insertions(+)
> 
> diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
> index b1415efc..5a29024a 100644
> --- a/tests/i915/gem_pxp.c
> +++ b/tests/i915/gem_pxp.c
> @@ -376,7 +376,9 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected, uint32_t size
>  #define TSTSURF_STRIDE      (TSTSURF_WIDTH*TSTSURF_BYTESPP)
>  #define TSTSURF_SIZE        (TSTSURF_STRIDE*TSTSURF_HEIGHT)
>  #define TSTSURF_FILLCOLOR1  0xfaceface
> +#define TSTSURF_FILLCOLOR2  0xdeaddead
>  #define TSTSURF_INITCOLOR1  0x12341234
> +#define TSTSURF_INITCOLOR2  0x56785678

I couldn't understand why we can't simply reuse the ones who were there
already, but anyway:


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>



>  
>  static void test_render_baseline(int i915)
>  {
> @@ -422,6 +424,57 @@ static void test_render_baseline(int i915)
>  	buf_ops_destroy(bops);
>  }
>  
> +static void test_render_pxp_src_to_protdest(int i915)
> +{
> +	uint32_t ctx, srcbo, dstbo;
> +	struct intel_buf *srcbuf, *dstbuf;
> +	struct buf_ops *bops;
> +	struct intel_bb *ibb;
> +	uint32_t devid;
> +	int ret;
> +
> +	devid = intel_get_drm_devid(i915);
> +	igt_assert(devid);
> +
> +	bops = buf_ops_create(i915);
> +	igt_assert(bops);
> +
> +	/*
> +	 * Perform a protected render operation but only label
> +	 * the dest as protected. After rendering, the content
> +	 * should be encrypted
> +	 */
> +	ret = create_ctx_with_params(i915, true, true, true, false, &ctx);
> +	igt_assert_eq(ret, 0);
> +	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
> +	ibb = intel_bb_create_with_context(i915, ctx, 4096);
> +	igt_assert(ibb);
> +	intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, I915_PROTECTED_CONTENT_DEFAULT_SESSION);
> +
> +	dstbo = alloc_and_fill_dest_buff(i915, true, TSTSURF_SIZE, TSTSURF_INITCOLOR2);
> +	dstbuf = intel_buf_create_using_handle(bops, dstbo, TSTSURF_WIDTH, TSTSURF_HEIGHT,
> +						TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
> +	intel_buf_set_pxp(dstbuf, true);
> +
> +	srcbo = alloc_and_fill_dest_buff(i915, false, TSTSURF_SIZE, TSTSURF_FILLCOLOR2);
> +	srcbuf = intel_buf_create_using_handle(bops, srcbo, TSTSURF_WIDTH, TSTSURF_HEIGHT,
> +						TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
> +
> +	gen12_render_copyfunc(ibb, srcbuf, 0, 0, TSTSURF_WIDTH, TSTSURF_HEIGHT, dstbuf, 0, 0);
> +	gem_sync(i915, dstbo);
> +
> +	assert_bo_content_check(i915, dstbo, COMPARE_COLOR_UNREADIBLE,
> +				TSTSURF_SIZE, TSTSURF_FILLCOLOR2);
> +
> +	intel_bb_destroy(ibb);
> +	intel_buf_destroy(srcbuf);
> +	gem_close(i915, srcbo);
> +	intel_buf_destroy(dstbuf);
> +	gem_close(i915, dstbo);
> +	gem_context_destroy(i915, ctx);
> +	buf_ops_destroy(bops);
> +}
> +
>  igt_main
>  {
>  	int i915 = -1;
> @@ -493,6 +546,8 @@ igt_main
>  		igt_describe("Verify protected render operations:");
>  		igt_subtest("regular-baseline-src-copy-readible")
>  			test_render_baseline(i915);
> +		igt_subtest("protected-raw-src-copy-not-readible")
> +			test_render_pxp_src_to_protdest(i915);
>  	}
>  
>  	igt_fixture {
> -- 
> 2.25.1
> 
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Re: [igt-dev] [PATCH i-g-t 10/17] Add test where both src and dest are protected

[Rodrigo Vivi]

On Tue, May 18, 2021 at 03:33:37AM -0700, Alan Previn wrote:
> When both the source and destination surfaces are
> protected, the destination pixel result of the 3d
> copy operation would be the same as the source. By
> appending this test case to the end of the prior
> test (raw-src to protected-dest) and reusing the
> previous' test destination as the current source,
> we can prove that new-source was decrypted properly
> as we would see the difference in results: repeating
> the same render operation but with a src buffer
> that is protected in this case yields matching
> (but still encrypted) output rendered pixels.
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
>  tests/i915/gem_pxp.c | 144 +++++++++++++++++++++++++++++++++++++++----
>  1 file changed, 133 insertions(+), 11 deletions(-)
> 
> diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
> index 5a29024a..2f2d2716 100644
> --- a/tests/i915/gem_pxp.c
> +++ b/tests/i915/gem_pxp.c
> @@ -308,29 +308,51 @@ static void fill_bo_content(int i915, uint32_t bo, uint32_t size, uint32_t initc
>  
>  #define COMPARE_COLOR_READIBLE     1
>  #define COMPARE_COLOR_UNREADIBLE   2
> +#define COMPARE_BUFFER_READIBLE    3
> +#define COMPARE_BUFFER_UNREADIBLE  4
> +#define COPY_BUFFER                5
>  #define COMPARE_N_PIXELS_VERBOSELY 0
>  
> -static void assert_bo_content_check(int i915, uint32_t bo, int compare_op,
> -				    uint32_t size, uint32_t color)
> +static void assert_bo_content_check(int i915, uint32_t bo, int compare_op, uint32_t size,
> +				    uint32_t color, uint32_t *auxptr, int auxsize)
>  {
> -	uint32_t *ptr, *ptrtmp;
> +	uint32_t *ptr, *ptrtmp, *auxtmp;
>  	int loop = 0, num_matches = 0;
>  	uint32_t value;
> -	bool op_readible = (compare_op == COMPARE_COLOR_READIBLE);
> +	bool op_readible = ((compare_op == COMPARE_COLOR_READIBLE) ||
> +		 (compare_op == COMPARE_BUFFER_READIBLE));
> +	bool chk_buff = ((compare_op == COMPARE_BUFFER_READIBLE) ||
> +		 (compare_op == COMPARE_BUFFER_UNREADIBLE));

why do we need to differentiate between color and buffer if they
are doing the same thing everywhere?

well, I'm assuming this is a future case, so anyway:


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>



> +	bool copy_buff = (compare_op == COPY_BUFFER);
>  
>  	ptr = gem_mmap__device_coherent(i915, bo, 0, size, PROT_READ);
>  	ptrtmp = ptr;
>  
> +	if (chk_buff || copy_buff) {
> +		if (auxsize < size)
> +			auxptr = NULL;
> +		igt_assert(auxptr);
> +		auxtmp = auxptr;
> +	}
> +
>  	if (COMPARE_N_PIXELS_VERBOSELY) {
>  		igt_info("--------->>>\n");
>  		while (loop < COMPARE_N_PIXELS_VERBOSELY && loop < (size/4)) {
>  			value = *ptrtmp;
> -			igt_info("Color read = 0x%08x ", value);
> -			igt_info("expected %c= 0x%08x)\n", op_readible?'=':'!', color);
> +			if (chk_buff)
> +				color = *auxtmp;
> +			if (copy_buff)
> +				igt_info("Color copy = 0x%08x\n", value);
> +			else {
> +				igt_info("Color read = 0x%08x ", value);
> +				igt_info("expected %c= 0x%08x)\n", op_readible?'=':'!', color);
> +			}
> +			++auxtmp;
>  			++ptrtmp;
>  			++loop;
>  		}
>  		igt_info("<<<---------\n");
> +		auxtmp = auxptr;
>  		ptrtmp = ptr;
>  		loop = 0;
>  	}
> @@ -338,8 +360,25 @@ static void assert_bo_content_check(int i915, uint32_t bo, int compare_op,
>  	/* count all pixels for matches */
>  	while (loop++ < (size/4)) {
>  		value = *ptrtmp;
> -		if (value == color)
> -			++num_matches;
> +		switch (compare_op) {
> +		case COMPARE_COLOR_READIBLE:
> +		case COMPARE_COLOR_UNREADIBLE:
> +			if (value == color)
> +				++num_matches;
> +			break;
> +		case COMPARE_BUFFER_READIBLE:
> +		case COMPARE_BUFFER_UNREADIBLE:
> +			if (value == (*auxtmp))
> +				++num_matches;
> +			++auxtmp;
> +			break;
> +		case COPY_BUFFER:
> +			*auxtmp = value;
> +			++auxtmp;
> +			break;
> +		default:
> +			break;
> +		}
>  		++ptrtmp;
>  	}
>  
> @@ -361,7 +400,8 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected, uint32_t size
>  	igt_assert_eq(ret, 0);
>  	igt_assert(bo);
>  	fill_bo_content(i915, bo, size, init_color);
> -	assert_bo_content_check(i915, bo, COMPARE_COLOR_READIBLE, size, init_color);
> +	assert_bo_content_check(i915, bo, COMPARE_COLOR_READIBLE,
> +				size, init_color, NULL, 0);
>  
>  	return bo;
>  }
> @@ -379,6 +419,7 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected, uint32_t size
>  #define TSTSURF_FILLCOLOR2  0xdeaddead
>  #define TSTSURF_INITCOLOR1  0x12341234
>  #define TSTSURF_INITCOLOR2  0x56785678
> +#define TSTSURF_INITCOLOR3  0xabcdabcd
>  
>  static void test_render_baseline(int i915)
>  {
> @@ -413,7 +454,7 @@ static void test_render_baseline(int i915)
>  	gem_sync(i915, dstbo);
>  
>  	assert_bo_content_check(i915, dstbo, COMPARE_COLOR_READIBLE,
> -				TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
> +				TSTSURF_SIZE, TSTSURF_FILLCOLOR1, NULL, 0);
>  
>  	intel_bb_destroy(ibb);
>  	intel_buf_destroy(srcbuf);
> @@ -464,13 +505,92 @@ static void test_render_pxp_src_to_protdest(int i915)
>  	gem_sync(i915, dstbo);
>  
>  	assert_bo_content_check(i915, dstbo, COMPARE_COLOR_UNREADIBLE,
> -				TSTSURF_SIZE, TSTSURF_FILLCOLOR2);
> +				TSTSURF_SIZE, TSTSURF_FILLCOLOR2, NULL, 0);
> +
> +	intel_bb_destroy(ibb);
> +	intel_buf_destroy(srcbuf);
> +	gem_close(i915, srcbo);
> +	intel_buf_destroy(dstbuf);
> +	gem_close(i915, dstbo);
> +	gem_context_destroy(i915, ctx);
> +	buf_ops_destroy(bops);
> +}
> +
> +static void test_render_pxp_protsrc_to_protdest(int i915)
> +{
> +	uint32_t ctx, srcbo, dstbo, dstbo2;
> +	struct intel_buf *srcbuf, *dstbuf, *dstbuf2;
> +	struct buf_ops *bops;
> +	struct intel_bb *ibb;
> +	uint32_t devid;
> +	int ret;
> +	uint32_t encrypted[TSTSURF_SIZE/TSTSURF_BYTESPP];
> +
> +	devid = intel_get_drm_devid(i915);
> +	igt_assert(devid);
> +
> +	bops = buf_ops_create(i915);
> +	igt_assert(bops);
> +
> +	/*
> +	 * Perform a protected render operation but only label
> +	 * the dest as protected. After rendering, the content
> +	 * should be encrypted
> +	 */
> +	ret = create_ctx_with_params(i915, true, true, true, false, &ctx);
> +	igt_assert_eq(ret, 0);
> +	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
> +	ibb = intel_bb_create_with_context(i915, ctx, 4096);
> +	igt_assert(ibb);
> +	intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, I915_PROTECTED_CONTENT_DEFAULT_SESSION);
> +
> +	dstbo = alloc_and_fill_dest_buff(i915, true, TSTSURF_SIZE, TSTSURF_INITCOLOR2);
> +	dstbuf = intel_buf_create_using_handle(bops, dstbo, TSTSURF_WIDTH, TSTSURF_HEIGHT,
> +						TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
> +	intel_buf_set_pxp(dstbuf, true);
> +
> +	srcbo = alloc_and_fill_dest_buff(i915, false, TSTSURF_SIZE, TSTSURF_FILLCOLOR2);
> +	srcbuf = intel_buf_create_using_handle(bops, srcbo, TSTSURF_WIDTH, TSTSURF_HEIGHT,
> +						TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
> +
> +	gen12_render_copyfunc(ibb, srcbuf, 0, 0, TSTSURF_WIDTH, TSTSURF_HEIGHT, dstbuf, 0, 0);
> +	gem_sync(i915, dstbo);
> +
> +	assert_bo_content_check(i915, dstbo, COMPARE_COLOR_UNREADIBLE,
> +				TSTSURF_SIZE, TSTSURF_FILLCOLOR2, NULL, 0);
> +
> +	/*
> +	 * Reuse prior dst as the new-src and create dst2 as the new-dest.
> +	 * Take a copy of encrypted content from new-src for comparison after render
> +	 * operation. After the rendering, we should find no difference in content
> +	 * since both new-src and new-dest are labelled as encrypted. HW should read
> +	 * and decrypt new-src, perform the render and re-encrypt when going into
> +	 * new-dest
> +	 */
> +	assert_bo_content_check(i915, dstbo, COPY_BUFFER,
> +				TSTSURF_SIZE, 0, encrypted, TSTSURF_SIZE);
> +
> +	dstbo2 = alloc_and_fill_dest_buff(i915, false, TSTSURF_SIZE, TSTSURF_INITCOLOR3);
> +	dstbuf2 = intel_buf_create_using_handle(bops, dstbo2, TSTSURF_WIDTH, TSTSURF_HEIGHT,
> +						TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
> +	intel_buf_set_pxp(dstbuf2, true);
> +	intel_buf_set_pxp(dstbuf, true);/*this time, src is protected*/
> +
> +	intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, I915_PROTECTED_CONTENT_DEFAULT_SESSION);
> +
> +	gen12_render_copyfunc(ibb, dstbuf, 0, 0, TSTSURF_WIDTH, TSTSURF_HEIGHT, dstbuf2, 0, 0);
> +	gem_sync(i915, dstbo2);
> +
> +	assert_bo_content_check(i915, dstbo2, COMPARE_BUFFER_READIBLE,
> +				TSTSURF_SIZE, 0, encrypted, TSTSURF_SIZE);
>  
>  	intel_bb_destroy(ibb);
>  	intel_buf_destroy(srcbuf);
>  	gem_close(i915, srcbo);
>  	intel_buf_destroy(dstbuf);
>  	gem_close(i915, dstbo);
> +	intel_buf_destroy(dstbuf2);
> +	gem_close(i915, dstbo2);
>  	gem_context_destroy(i915, ctx);
>  	buf_ops_destroy(bops);
>  }
> @@ -548,6 +668,8 @@ igt_main
>  			test_render_baseline(i915);
>  		igt_subtest("protected-raw-src-copy-not-readible")
>  			test_render_pxp_src_to_protdest(i915);
> +		igt_subtest("protected-encrypted-src-copy-not-readible")
> +			test_render_pxp_protsrc_to_protdest(i915);
>  	}
>  
>  	igt_fixture {
> -- 
> 2.25.1
> 
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> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t 12/17] Verify execbuf fails with stale PXP context after teardown

[Rodrigo Vivi]

On Tue, May 18, 2021 at 03:33:39AM -0700, Alan Previn wrote:
> Add a subtest to verify that reusing a stale protected context
> in a gem_execbuff after a teardown (triggered by suspend-resume
> cycle) shall fail with -EACCES error.
> 
> NOTE: The end-to-end architecture requirement includes that
> any break in the links of the PXP sessions needs to trigger a
> full teardown and the application needs to be made aware of that
> allowing it to re-establish the end-to-end pipeline of buffers,
> contexts and renders again if it chooses to. This stricter
> behavior targets only contexts created with PXP enabled.
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
>  lib/intel_batchbuffer.c |   2 +-
>  lib/intel_batchbuffer.h |   3 +
>  tests/i915/gem_pxp.c    | 135 ++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 139 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> index 23957109..e16ab056 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -2536,7 +2536,7 @@ static void update_offsets(struct intel_bb *ibb,
>   * Note: In this step execobj for bb is allocated and inserted to the objects
>   * array.
>  */
> -static int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
> +int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
>  			   uint64_t flags, bool sync)
>  {
>  	struct drm_i915_gem_execbuffer2 execbuf;
> diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
> index 389da7b2..b16ae00f 100644
> --- a/lib/intel_batchbuffer.h
> +++ b/lib/intel_batchbuffer.h
> @@ -664,6 +664,9 @@ uint64_t intel_bb_offset_reloc_to_object(struct intel_bb *ibb,
>  					 uint32_t offset,
>  					 uint64_t presumed_offset);
>  
> +int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
> +			uint64_t flags, bool sync);
> +
>  void intel_bb_dump_cache(struct intel_bb *ibb);
>  
>  void intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
> diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
> index 10134604..f1ef0a24 100644
> --- a/tests/i915/gem_pxp.c
> +++ b/tests/i915/gem_pxp.c
> @@ -15,6 +15,14 @@ struct powermgt_data {
>  	bool has_runtime_pm;
>  };
>  
> +struct simple_exec_assets {
> +	uint32_t ctx;
> +	uint32_t fencebo;
> +	struct intel_buf *fencebuf;
> +	struct buf_ops *bops;
> +	struct intel_bb *ibb;
> +};
> +
>  static bool is_pxp_hw_supported(int i915)
>  {
>  	uint32_t devid = intel_get_drm_devid(i915);
> @@ -646,6 +654,131 @@ static void test_pxp_pwrcycle_teardown_keychange(int i915, struct powermgt_data
>  	igt_assert_eq(matched_after_keychange, 0);
>  }
>  
> +#define GFX_OP_PIPE_CONTROL    ((3 << 29) | (3 << 27) | (2 << 24))
> +#define PIPE_CONTROL_CS_STALL	            (1 << 20)
> +#define PIPE_CONTROL_RENDER_TARGET_FLUSH    (1 << 12)
> +#define PIPE_CONTROL_FLUSH_ENABLE           (1 << 7)
> +#define PIPE_CONTROL_DATA_CACHE_INVALIDATE  (1 << 5)
> +#define PIPE_CONTROL_PROTECTEDPATH_DISABLE  (1 << 27)
> +#define PIPE_CONTROL_PROTECTEDPATH_ENABLE   (1 << 22)
> +#define PIPE_CONTROL_POST_SYNC_OP           (1 << 14)
> +#define PIPE_CONTROL_POST_SYNC_OP_STORE_DW_IDX (1 << 21)
> +#define PS_OP_TAG_BEFORE                    0x1234fed0
> +#define PS_OP_TAG_AFTER                     0x5678cbaf
> +
> +static void emit_pipectrl(struct intel_bb *ibb, struct intel_buf *fenceb, bool before)
> +{
> +	uint32_t pipe_ctl_flags = 0;
> +	uint32_t ps_op_id;
> +
> +	intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
> +	intel_bb_out(ibb, pipe_ctl_flags);
> +
> +	if (before)
> +		ps_op_id = PS_OP_TAG_BEFORE;
> +	else
> +		ps_op_id = PS_OP_TAG_AFTER;
> +
> +	pipe_ctl_flags = (PIPE_CONTROL_FLUSH_ENABLE |
> +			  PIPE_CONTROL_CS_STALL |
> +			  PIPE_CONTROL_POST_SYNC_OP);
> +	intel_bb_out(ibb, GFX_OP_PIPE_CONTROL | 4);

(side comment: the pipe control len in this patch looks right!)


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


> +	intel_bb_out(ibb, pipe_ctl_flags);
> +	intel_bb_emit_reloc(ibb, fenceb->handle, 0, I915_GEM_DOMAIN_COMMAND, (before?0:8),
> +			    fenceb->addr.offset);
> +	intel_bb_out(ibb, ps_op_id);
> +	intel_bb_out(ibb, ps_op_id);
> +	intel_bb_out(ibb, MI_NOOP);
> +	intel_bb_out(ibb, MI_NOOP);
> +}
> +
> +static void assert_pipectl_storedw_done(int i915, uint32_t bo)
> +{
> +	uint32_t *ptr;
> +	uint32_t success_mask = 0x0;
> +
> +	ptr = gem_mmap__device_coherent(i915, bo, 0, 4096, PROT_READ);
> +
> +	if (ptr[0] == PS_OP_TAG_BEFORE && ptr[1] == PS_OP_TAG_BEFORE)
> +		success_mask |= 0x1;
> +
> +	igt_assert_eq(success_mask, 0x1);
> +	igt_assert(gem_munmap(ptr, 4096) == 0);
> +}
> +
> +static int gem_execbuf_flush_store_dw(int i915, struct intel_bb *ibb, uint32_t ctx,
> +				      struct intel_buf *fence)
> +{
> +	int ret;
> +
> +	intel_bb_ptr_set(ibb, 0);
> +	intel_bb_add_intel_buf(ibb, fence, true);
> +	emit_pipectrl(ibb, fence, true);
> +	intel_bb_emit_bbe(ibb);
> +	ret = __intel_bb_exec(ibb, intel_bb_offset(ibb),
> +				  I915_EXEC_RENDER | I915_EXEC_NO_RELOC, false);
> +	if (ret == 0) {
> +		gem_sync(ibb->i915, fence->handle);
> +		assert_pipectl_storedw_done(i915, fence->handle);
> +	}
> +	return ret;
> +}
> +
> +static void prepare_exec_assets(int i915, struct simple_exec_assets *data, bool ctx_pxp,
> +				bool buf_pxp)
> +{
> +	int ret;
> +
> +	if (ctx_pxp)
> +		ret = create_ctx_with_params(i915, true, true, true, false, &(data->ctx));
> +	else
> +		ret = create_ctx_with_params(i915, false, false, false, false, &(data->ctx));
> +	igt_assert_eq(ret, 0);
> +	igt_assert_eq(get_ctx_protected_param(i915, data->ctx), ctx_pxp);
> +	data->ibb = intel_bb_create_with_context(i915, data->ctx, 4096);
> +	igt_assert(data->ibb);
> +
> +	data->fencebo = alloc_and_fill_dest_buff(i915, buf_pxp, 4096, 0);
> +
> +	data->bops = buf_ops_create(i915);
> +	igt_assert(data->bops);
> +
> +	data->fencebuf = intel_buf_create_using_handle(data->bops, data->fencebo, 256, 4,
> +						       32, 0, I915_TILING_NONE, 0);
> +	intel_bb_add_intel_buf(data->ibb, data->fencebuf, true);
> +}
> +
> +static void free_exec_assets(int i915, struct simple_exec_assets *data)
> +{
> +	intel_bb_destroy(data->ibb);
> +	gem_close(i915, data->fencebo);
> +	intel_buf_destroy(data->fencebuf);
> +	gem_context_destroy(i915, data->ctx);
> +	buf_ops_destroy(data->bops);
> +}
> +
> +static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_data *pm)
> +{
> +	int ret;
> +	struct simple_exec_assets data = {0};
> +
> +	/*
> +	 * Use normal buffers for testing for invalidation
> +	 * of protected contexts to ensure kernel is catching
> +	 * the invalidated context (not buffer)
> +	 */
> +	prepare_exec_assets(i915, &data, true, false);
> +	ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf);
> +	igt_assert(ret == 0);
> +
> +	trigger_powermgt_suspend_cycle(i915, pm);
> +
> +	ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf);
> +	igt_assert_f((ret == -EACCES), "Executing stale pxp context didn't fail with -EACCES\n");
> +
> +	free_exec_assets(i915, &data);
> +}
> +
>  igt_main
>  {
>  	int i915 = -1;
> @@ -735,6 +868,8 @@ igt_main
>  		igt_describe("Verify suspend-resume teardown management:");
>  		igt_subtest("verify-pxp-key-change-after-suspend-resume")
>  			test_pxp_pwrcycle_teardown_keychange(i915, &pm);
> +		igt_subtest("verify-pxp-execution-behavior-after-suspend-resume")
> +			test_pxp_pwrcycle_staleasset_execution(i915, &pm);
>  	}
>  
>  	igt_fixture {
> -- 
> 2.25.1
> 
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> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev

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Re: [igt-dev] [PATCH i-g-t 14/17] Verify execbuf ok with stale prot-buff and regular context

[Rodrigo Vivi]

On Tue, May 18, 2021 at 03:33:41AM -0700, Alan Previn wrote:
> Add a check to verify that reusing a stale protected
> buffer in a gem_execbuff call, but using a regular (not-
> protcted) context will succeed despite after a teardown
       ^ typo

with this fixed:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> (triggered by suspend-resume cycle).
> 
> This ensures that user space applications that choose
> not to opt-in for strict PXP teardown awareness (by
> using a regular context) won't suffer gem_execbuff
> failures if a protected buffer was among the assets
> used in any of its rendering operations.
> 
> Reuse the existing subtest to minimize the number
> of suspend resume cycles we take.
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
>  tests/i915/gem_pxp.c | 15 ++++++++++++++-
>  1 file changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
> index b4f369ae..e3c21c70 100644
> --- a/tests/i915/gem_pxp.c
> +++ b/tests/i915/gem_pxp.c
> @@ -760,7 +760,7 @@ static void free_exec_assets(int i915, struct simple_exec_assets *data)
>  static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_data *pm)
>  {
>  	int ret;
> -	struct simple_exec_assets data[2] = {{0}, {0}};
> +	struct simple_exec_assets data[3] = {{0}, {0}, {0}};
>  	uint32_t ctx2;
>  	struct intel_bb *ibb2;
>  
> @@ -777,6 +777,15 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
>  	ret = gem_execbuf_flush_store_dw(i915, data[1].ibb, data[1].ctx, data[1].fencebuf);
>  	igt_assert(ret == 0);
>  
> +	/*
> +	 * For data[2]: Use non-pxp contexts but with protected buffers
> +	 * to verify the "pxp-execution-opt-in" expectation where
> +	 * execution will run without error (not buffer)
> +	 */
> +	prepare_exec_assets(i915, &data[2], false, true);
> +	ret = gem_execbuf_flush_store_dw(i915, data[2].ibb, data[2].ctx, data[2].fencebuf);
> +	igt_assert(ret == 0);
> +
>  	trigger_powermgt_suspend_cycle(i915, pm);
>  
>  	ret = gem_execbuf_flush_store_dw(i915, data[0].ibb, data[0].ctx, data[0].fencebuf);
> @@ -797,8 +806,12 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
>  	ret = gem_execbuf_flush_store_dw(i915, ibb2, ctx2, data[1].fencebuf);
>  	igt_assert_f((ret == -ENOEXEC), "Executing stale pxp buffer didn't fail with -ENOEXEC\n");
>  
> +	ret = gem_execbuf_flush_store_dw(i915, data[2].ibb, data[2].ctx, data[2].fencebuf);
> +	igt_assert_f((ret == 0), "Opt-out-execution with stale pxp buffer didn't succeed\n");
> +
>  	free_exec_assets(i915, &data[0]);
>  	free_exec_assets(i915, &data[1]);
> +	free_exec_assets(i915, &data[2]);
>  }
>  
>  igt_main
> -- 
> 2.25.1
> 
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Re: [igt-dev] [PATCH i-g-t 16/17] Verify protected surfaces are dma buffer sharable

[Rodrigo Vivi]

On Tue, May 18, 2021 at 03:33:43AM -0700, Alan Previn wrote:
> Verify we can export a protected surface from
> protected context A into protected context B (with
> different client driver handles) and protected
> rendering is successful even after prior file
> handle is closed (i.e. pxp specific refcounting
> works).
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  tests/i915/gem_pxp.c | 103 +++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 103 insertions(+)
> 
> diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
> index 69a3143a..179fb742 100644
> --- a/tests/i915/gem_pxp.c
> +++ b/tests/i915/gem_pxp.c
> @@ -3,6 +3,7 @@
>   * Copyright © 2021 Intel Corporation
>   */
>  
> +#include <fcntl.h>
>  #include "igt.h"
>  #include "i915/gem.h"
>  
> @@ -618,6 +619,106 @@ static void test_render_pxp_protsrc_to_protdest(int i915)
>  	buf_ops_destroy(bops);
>  }
>  
> +static int export_handle(int fd, uint32_t handle, int *outfd)
> +{
> +	struct drm_prime_handle args;
> +	int ret;
> +
> +	args.handle = handle;
> +	args.flags = DRM_CLOEXEC;
> +	args.fd = -1;
> +
> +	ret = drmIoctl(fd, DRM_IOCTL_PRIME_HANDLE_TO_FD, &args);
> +	if (ret)
> +		ret = errno;
> +	*outfd = args.fd;
> +
> +	return ret;
> +}
> +
> +static void test_pxp_dmabuffshare_refcnt(void)
> +{
> +	uint32_t ctx[2], sbo[2], dbo[2];
> +	struct intel_buf *sbuf[2], *dbuf[2];
> +	struct buf_ops *bops[2];
> +	struct intel_bb *ibb[2];
> +	int fd[2], dmabuf_fd = 0, ret, n, num_matches = 0;
> +	uint32_t encrypted[2][TSTSURF_SIZE/TSTSURF_BYTESPP];
> +
> +	/* First, create the client driver handles and
> +	 * protected dest buffer (is exported via dma-buff
> +	 * from first handle and imported to the second).
> +	 */
> +	for (n = 0; n < 2; ++n) {
> +		fd[n] = drm_open_driver(DRIVER_INTEL);
> +		igt_require(fd[n]);
> +		if (n == 0) {
> +			dbo[0] = alloc_and_fill_dest_buff(fd[0], true, TSTSURF_SIZE,
> +							  TSTSURF_INITCOLOR1);
> +		} else {
> +			ret = export_handle(fd[0], dbo[0], &dmabuf_fd);
> +			igt_assert(ret == 0);
> +			dbo[1] = prime_fd_to_handle(fd[1], dmabuf_fd);
> +			igt_assert(dbo[1]);
> +		}
> +	}
> +	/* Repeat twice: Create a full set of assets to perform
> +	 * a protected 3D session but using the same dest buffer
> +	 * from above.
> +	 */
> +	for (n = 0; n < 2; ++n) {
> +		ret = create_ctx_with_params(fd[n], true, true, true, false, &ctx[n]);
> +		igt_assert_eq(ret, 0);
> +		igt_assert_eq(get_ctx_protected_param(fd[n], ctx[n]), 1);
> +		ibb[n] = intel_bb_create_with_context(fd[n], ctx[n], 4096);
> +		intel_bb_set_pxp(ibb[n], true, DISPLAY_APPTYPE,
> +				 I915_PROTECTED_CONTENT_DEFAULT_SESSION);
> +
> +		bops[n] = buf_ops_create(fd[n]);
> +		if (n == 1)
> +			fill_bo_content(fd[1], dbo[1], TSTSURF_SIZE, TSTSURF_INITCOLOR2);
> +
> +		dbuf[n] = intel_buf_create_using_handle(bops[n], dbo[n], TSTSURF_WIDTH,
> +							TSTSURF_HEIGHT,	TSTSURF_BYTESPP*8, 0,
> +							I915_TILING_NONE, 0);
> +		intel_buf_set_pxp(dbuf[n], true);
> +
> +		sbo[n] = alloc_and_fill_dest_buff(fd[n], false, TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
> +		sbuf[n] = intel_buf_create_using_handle(bops[n], sbo[n], TSTSURF_WIDTH,
> +							TSTSURF_HEIGHT, TSTSURF_BYTESPP*8, 0,
> +							I915_TILING_NONE, 0);
> +
> +		gen12_render_copyfunc(ibb[n], sbuf[n], 0, 0, TSTSURF_WIDTH, TSTSURF_HEIGHT,
> +				      dbuf[n], 0, 0);
> +		gem_sync(fd[n], dbo[n]);
> +
> +		assert_bo_content_check(fd[n], dbo[n], COMPARE_COLOR_UNREADIBLE, TSTSURF_SIZE,
> +					TSTSURF_FILLCOLOR1, NULL, 0);
> +		assert_bo_content_check(fd[n], dbo[n], COPY_BUFFER, TSTSURF_SIZE, 0, encrypted[n],
> +					TSTSURF_SIZE);
> +
> +		/* free up all assets except the dest buffer to
> +		 * verify dma buff refcounting is performed on
> +		 * the protected dest buffer on the 2nd loop with
> +		 * successful reuse in another protected render.
> +		 */
> +		intel_bb_destroy(ibb[n]);
> +		intel_buf_destroy(sbuf[n]);
> +		intel_buf_destroy(dbuf[n]);
> +		gem_close(fd[n], sbo[n]);
> +		gem_close(fd[n], dbo[n]);
> +		gem_context_destroy(fd[n], ctx[n]);
> +		close(fd[n]);
> +	}
> +
> +	/* Verify that encrypted output across loops were equal */
> +	for (n = 0; n < (TSTSURF_SIZE/4); ++n)
> +		if (encrypted[0][n] == encrypted[1][n])
> +			++num_matches;
> +	igt_assert(num_matches == (TSTSURF_SIZE/4));
> +}
> +
> +
>  static void init_powermgt_resources(int i915, struct powermgt_data *pm)
>  {
>  	pm->debugfsdir = igt_debugfs_dir(i915);
> @@ -912,6 +1013,8 @@ igt_main
>  			test_render_pxp_src_to_protdest(i915);
>  		igt_subtest("protected-encrypted-src-copy-not-readible")
>  			test_render_pxp_protsrc_to_protdest(i915);
> +		igt_subtest("dmabuf-shared-protected-dst-is-context-refcounted")
> +			test_pxp_dmabuffshare_refcnt();
>  	}
>  	igt_subtest_group {
>  		igt_fixture {
> -- 
> 2.25.1
> 
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Re: [igt-dev] [PATCH i-g-t 17/17] tests/i915_pxp: CRC validation for display tests.

[Rodrigo Vivi]

On Tue, May 18, 2021 at 03:33:44AM -0700, Alan Previn wrote:
> From: Karthik B S <karthik.b.s@intel.com>
> 
> Added subtests to validate pxp using CRC validation.
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>

> ---
>  tests/i915/gem_pxp.c | 286 ++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 283 insertions(+), 3 deletions(-)
> 
> diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
> index 179fb742..728c925a 100644
> --- a/tests/i915/gem_pxp.c
> +++ b/tests/i915/gem_pxp.c
> @@ -435,6 +435,7 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected, uint32_t size
>  #define TSTSURF_INITCOLOR1  0x12341234
>  #define TSTSURF_INITCOLOR2  0x56785678
>  #define TSTSURF_INITCOLOR3  0xabcdabcd
> +#define TSTSURF_GREENCOLOR  0xFF00FF00
>  
>  static void test_render_baseline(int i915)
>  {
> @@ -906,7 +907,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
>  	trigger_powermgt_suspend_cycle(i915, pm);
>  
>  	igt_assert_f(!is_context_valid(i915, data[0].ctx),
> -				       "RESET_STATS missed INVAL bit on stale pxp context\n");
> +		     "RESET_STATS missed INVAL bit on stale pxp context\n");
>  	ret = gem_execbuf_flush_store_dw(i915, data[0].ibb, data[0].ctx, data[0].fencebuf);
>  	igt_assert_f((ret == -EACCES), "Executing stale pxp context didn't fail with -EACCES\n");
>  
> @@ -916,7 +917,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
>  	 * invalidated bo (not context)
>  	 */
>  	igt_assert_f(!is_context_valid(i915, data[1].ctx),
> -				       "RESET_STATS missed INVAL bit on stale pxp context\n");
> +		     "RESET_STATS missed INVAL bit on stale pxp context\n");
>  	ret = create_ctx_with_params(i915, true, true, true, false, &ctx2);
>  	igt_assert_eq(ret, 0);
>  	igt_assert_eq(get_ctx_protected_param(i915, ctx2), 1);
> @@ -928,7 +929,7 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
>  	igt_assert_f((ret == -ENOEXEC), "Executing stale pxp buffer didn't fail with -ENOEXEC\n");
>  
>  	igt_assert_f(is_context_valid(i915, data[2].ctx),
> -				       "RESET_STATS false-hit on opt-out context\n");
> +		     "RESET_STATS false-hit on opt-out context\n");
>  	ret = gem_execbuf_flush_store_dw(i915, data[2].ibb, data[2].ctx, data[2].fencebuf);
>  	igt_assert_f((ret == 0), "Opt-out-execution with stale pxp buffer didn't succeed\n");
>  
> @@ -937,6 +938,266 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
>  	free_exec_assets(i915, &data[2]);
>  }
>  
> +static void setup_protected_fb(int i915, int width, int height, igt_fb_t *fb, uint32_t ctx)
> +{
> +	int err;
> +	uint32_t srcbo;
> +	struct intel_buf *srcbuf, *dstbuf;
> +	struct buf_ops *bops;
> +	struct intel_bb *ibb;
> +	uint32_t devid;
> +	igt_render_copyfunc_t rendercopy;
> +
> +	devid = intel_get_drm_devid(i915);
> +	igt_assert(devid);
> +
> +	rendercopy = igt_get_render_copyfunc(devid);
> +	igt_assert(rendercopy);
> +
> +	bops = buf_ops_create(i915);
> +	igt_assert(bops);
> +
> +	igt_init_fb(fb, i915, width, height, DRM_FORMAT_XRGB8888, LOCAL_DRM_FORMAT_MOD_NONE,
> +		    IGT_COLOR_YCBCR_BT709, IGT_COLOR_YCBCR_LIMITED_RANGE);
> +
> +	igt_calc_fb_size(i915, width, height, DRM_FORMAT_XRGB8888, LOCAL_DRM_FORMAT_MOD_NONE,
> +			 &fb->size, &fb->strides[0]);
> +
> +	err = create_bo_ext(i915, fb->size, true, &(fb->gem_handle));
> +	igt_assert_eq(err, 0);
> +	igt_assert(fb->gem_handle);
> +
> +	err = __gem_set_tiling(i915, fb->gem_handle, igt_fb_mod_to_tiling(fb->modifier),
> +			       fb->strides[0]);
> +	igt_assert(err == 0 || err == -EOPNOTSUPP);
> +
> +	do_or_die(__kms_addfb(fb->fd, fb->gem_handle, fb->width, fb->height, fb->drm_format,
> +			      fb->modifier, fb->strides, fb->offsets, fb->num_planes,
> +			      LOCAL_DRM_MODE_FB_MODIFIERS, &fb->fb_id));
> +
> +	dstbuf = intel_buf_create_using_handle(bops, fb->gem_handle, fb->width, fb->height,
> +					       fb->plane_bpp[0], 0,
> +					       igt_fb_mod_to_tiling(fb->modifier), 0);
> +	dstbuf->is_protected = true;
> +
> +	srcbo = alloc_and_fill_dest_buff(i915, false, fb->size, TSTSURF_GREENCOLOR);
> +	srcbuf = intel_buf_create_using_handle(bops, srcbo, fb->width, fb->height,
> +					       fb->plane_bpp[0], 0,
> +					       igt_fb_mod_to_tiling(fb->modifier), 0);
> +
> +	ibb = intel_bb_create_with_context(i915, ctx, 4096);
> +	igt_assert(ibb);
> +
> +	ibb->pxp.enabled = true;
> +	ibb->pxp.apptype = DISPLAY_APPTYPE;
> +	ibb->pxp.appid = I915_PROTECTED_CONTENT_DEFAULT_SESSION;
> +
> +	gen12_render_copyfunc(ibb, srcbuf, 0, 0, fb->width, fb->height, dstbuf, 0, 0);
> +
> +	gem_sync(i915, fb->gem_handle);
> +	assert_bo_content_check(i915, fb->gem_handle, COMPARE_COLOR_UNREADIBLE, fb->size,
> +				TSTSURF_GREENCOLOR, NULL, 0);
> +
> +	intel_bb_destroy(ibb);
> +	intel_buf_destroy(srcbuf);
> +	gem_close(i915, srcbo);
> +}
> +
> +static void __debugfs_read(int fd, const char *param, char *buf, int len)
> +{
> +	len = igt_debugfs_simple_read(fd, param, buf, len);
> +	if (len < 0)
> +		igt_assert_eq(len, -ENODEV);
> +}
> +
> +#define debugfs_read(fd, p, arr) __debugfs_read(fd, p, arr, sizeof(arr))
> +#define MAX_SINK_HDCP_CAP_BUF_LEN	5000
> +
> +#define CP_UNDESIRED				0
> +#define CP_DESIRED				1
> +#define CP_ENABLED				2
> +
> +#define KERNEL_AUTH_TIME_ALLOWED_MSEC		(3 *  6 * 1000)
> +#define KERNEL_DISABLE_TIME_ALLOWED_MSEC	(1 * 1000)
> +
> +static bool
> +wait_for_prop_value(igt_output_t *output, uint64_t expected,
> +		    uint32_t timeout_mSec)
> +{
> +	uint64_t val;
> +	int i;
> +
> +	for (i = 0; i < timeout_mSec; i++) {
> +		val = igt_output_get_prop(output, IGT_CONNECTOR_CONTENT_PROTECTION);
> +		if (val == expected)
> +			return true;
> +		usleep(1000);
> +	}
> +
> +	igt_info("prop_value mismatch %" PRId64 " != %" PRId64 "\n", val, expected);
> +
> +	return false;
> +}
> +
> +static bool sink_hdcp_capable(int i915, igt_output_t *output)
> +{
> +	char buf[MAX_SINK_HDCP_CAP_BUF_LEN];
> +	int fd;
> +
> +	fd = igt_debugfs_connector_dir(i915, output->name, O_RDONLY);
> +	if (fd < 0)
> +		return false;
> +
> +	if (is_i915_device(i915))
> +		debugfs_read(fd, "i915_hdcp_sink_capability", buf);
> +	else
> +		debugfs_read(fd, "hdcp_sink_capability", buf);
> +
> +	close(fd);
> +
> +	igt_debug("Sink capability: %s\n", buf);
> +
> +	return strstr(buf, "HDCP1.4");
> +}
> +
> +static bool output_hdcp_capable(int i915, igt_output_t *output, bool content_type)
> +{
> +	if (!output->props[IGT_CONNECTOR_CONTENT_PROTECTION])
> +		return false;
> +	if (!output->props[IGT_CONNECTOR_HDCP_CONTENT_TYPE] && content_type)
> +		return false;
> +	if (!sink_hdcp_capable(i915, output))
> +		return false;
> +
> +	return true;
> +}
> +
> +static void test_display_protected_crc(int i915, igt_display_t *display, bool hdcp)
> +{
> +	igt_output_t *output;
> +	drmModeModeInfo *mode;
> +	igt_fb_t ref_fb, protected_fb;
> +	igt_plane_t *plane;
> +	igt_pipe_t *pipe;
> +	igt_pipe_crc_t *pipe_crc;
> +	igt_crc_t ref_crc, new_crc;
> +	int width = 0, height = 0, i = 0, ret, count, valid_outputs = 0;
> +	uint32_t ctx;
> +	igt_output_t *hdcp_output[IGT_MAX_PIPES];
> +
> +	ret = create_ctx_with_params(i915, true, true, true, false, &ctx);
> +	igt_assert_eq(ret, 0);
> +
> +	for_each_connected_output(display, output) {
> +		mode = igt_output_get_mode(output);
> +
> +		width = max(width, mode->hdisplay);
> +		height = max(height, mode->vdisplay);
> +
> +		if (!output_hdcp_capable(i915, output, 0))
> +			continue;
> +
> +		hdcp_output[valid_outputs++] = output;
> +	}
> +
> +	if (hdcp)
> +		igt_require_f(valid_outputs > 0, "No HDCP capable connector found\n");
> +
> +	igt_create_color_fb(i915, width, height, DRM_FORMAT_XRGB8888, LOCAL_DRM_FORMAT_MOD_NONE,
> +			    0, 1, 0, &ref_fb);
> +
> +	/* Do a modeset on all outputs */
> +	for_each_connected_output(display, output) {
> +		mode = igt_output_get_mode(output);
> +		pipe = &display->pipes[i];
> +		plane = igt_pipe_get_plane_type(pipe, DRM_PLANE_TYPE_PRIMARY);
> +		igt_require(igt_pipe_connector_valid(i, output));
> +		igt_output_set_pipe(output, i);
> +
> +		igt_plane_set_fb(plane, &ref_fb);
> +		igt_fb_set_size(&ref_fb, plane, mode->hdisplay, mode->vdisplay);
> +		igt_plane_set_size(plane, mode->hdisplay, mode->vdisplay);
> +
> +		igt_display_commit2(display, COMMIT_ATOMIC);
> +		i++;
> +	}
> +
> +	if (hdcp) {
> +		/* Enable HDCP on all the valid connectors */
> +		for (count = 0; count < valid_outputs; count++) {
> +			igt_output_set_prop_value(hdcp_output[count],
> +						  IGT_CONNECTOR_CONTENT_PROTECTION, CP_DESIRED);
> +			if (output->props[IGT_CONNECTOR_HDCP_CONTENT_TYPE])
> +				igt_output_set_prop_value(hdcp_output[count],
> +							  IGT_CONNECTOR_HDCP_CONTENT_TYPE, 0);
> +		}
> +
> +		igt_display_commit2(display, COMMIT_ATOMIC);
> +
> +		/*Verify that HDCP is enabled on all valid connectors */
> +		for (count = 0; count < valid_outputs; count++) {
> +			ret = wait_for_prop_value(hdcp_output[count], CP_ENABLED,
> +						  KERNEL_AUTH_TIME_ALLOWED_MSEC);
> +			igt_assert_f(ret, "Content Protection not enabled on %s\n",
> +				     hdcp_output[count]->name);
> +		}
> +	}
> +
> +	setup_protected_fb(i915, width, height, &protected_fb, ctx);
> +
> +	for_each_connected_output(display, output) {
> +		mode = igt_output_get_mode(output);
> +		pipe = &display->pipes[output->pending_pipe];
> +		pipe_crc = igt_pipe_crc_new(i915, pipe->pipe, INTEL_PIPE_CRC_SOURCE_AUTO);
> +		plane = igt_pipe_get_plane_type(pipe, DRM_PLANE_TYPE_PRIMARY);
> +		igt_require(igt_pipe_connector_valid(pipe->pipe, output));
> +		igt_output_set_pipe(output, pipe->pipe);
> +
> +		igt_plane_set_fb(plane, &ref_fb);
> +		igt_fb_set_size(&ref_fb, plane, mode->hdisplay, mode->vdisplay);
> +		igt_plane_set_size(plane, mode->hdisplay, mode->vdisplay);
> +
> +		igt_display_commit2(display, COMMIT_ATOMIC);
> +		igt_pipe_crc_collect_crc(pipe_crc, &ref_crc);
> +
> +		igt_plane_set_fb(plane, &protected_fb);
> +		igt_fb_set_size(&protected_fb, plane, mode->hdisplay, mode->vdisplay);
> +		igt_plane_set_size(plane, mode->hdisplay, mode->vdisplay);
> +
> +		igt_display_commit2(display, COMMIT_ATOMIC);
> +		igt_pipe_crc_collect_crc(pipe_crc, &new_crc);
> +		igt_assert_crc_equal(&ref_crc, &new_crc);
> +
> +		if (hdcp) {
> +			/* Disable HDCP and collect CRC */
> +			igt_output_set_prop_value(hdcp_output[0], IGT_CONNECTOR_CONTENT_PROTECTION,
> +						  CP_UNDESIRED);
> +			igt_display_commit2(display, COMMIT_ATOMIC);
> +			ret = wait_for_prop_value(hdcp_output[0], CP_UNDESIRED,
> +						  KERNEL_DISABLE_TIME_ALLOWED_MSEC);
> +			igt_assert_f(ret, "Content Protection not cleared\n");
> +
> +			igt_plane_set_fb(plane, &protected_fb);
> +			igt_fb_set_size(&protected_fb, plane, mode->hdisplay, mode->vdisplay);
> +			igt_plane_set_size(plane, mode->hdisplay, mode->vdisplay);
> +
> +			igt_display_commit2(display, COMMIT_ATOMIC);
> +			igt_pipe_crc_collect_crc(pipe_crc, &new_crc);
> +			igt_assert_f(!igt_check_crc_equal(&ref_crc, &new_crc),
> +				    "CRC's expected to be different after HDCP is disabled\n");

The CRC is at the pipe level, but I believe it is right to expect that
after disabling the HDCP we will get different CRC.

+Uma to help me to confirm this.

But also, I'm asking myself if this test case here is really bringing
any value to PXP itself. To me, it looks like it is only testing
HDCP disable scenario... nothing to do with the PXP flow.

With the HDCP removed, or with Uma confirming my assumption is right
and that I'm wrong about the value-added, feel free to use:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> +		}
> +		/*
> +		 * Testing with one pipe-output combination is sufficient.
> +		 * So break the loop.
> +		 */
> +		break;
> +	}
> +
> +	gem_context_destroy(i915, ctx);
> +	igt_remove_fb(i915, &ref_fb);
> +	igt_remove_fb(i915, &protected_fb);
> +}
> +
>  igt_main
>  {
>  	int i915 = -1;
> @@ -944,6 +1205,7 @@ igt_main
>  	struct powermgt_data pm = {0};
>  	igt_render_copyfunc_t rendercopy = NULL;
>  	uint32_t devid = 0;
> +	igt_display_t display;
>  
>  	igt_fixture
>  	{
> @@ -1031,6 +1293,24 @@ igt_main
>  		igt_subtest("verify-pxp-execution-behavior-after-suspend-resume")
>  			test_pxp_pwrcycle_staleasset_execution(i915, &pm);
>  	}
> +	igt_subtest_group {
> +		igt_fixture {
> +			igt_require(pxp_supported);
> +			devid = intel_get_drm_devid(i915);
> +			igt_assert(devid);
> +			rendercopy = igt_get_render_copyfunc(devid);
> +			igt_require(rendercopy);
> +
> +			igt_require_pipe_crc(i915);
> +			igt_display_require(&display, i915);
> +		}
> +		igt_describe("Test the display CRC");
> +		igt_subtest("display-protected-crc-without-hdcp")
> +			test_display_protected_crc(i915, &display, 0);
> +		igt_subtest("display-protected-crc-with-hdcp")
> +			test_display_protected_crc(i915, &display, 1);
> +	}
> +
>  
>  	igt_fixture {
>  		close(i915);
> -- 
> 2.25.1
> 
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Re: [igt-dev] [PATCH i-g-t 14/17] Verify execbuf ok with stale prot-buff and regular context

[Teres Alexis, Alan Previn]

Will do - thanks.

-----Original Message-----
From: Vivi, Rodrigo <rodrigo.vivi@intel.com> 
Sent: Friday, June 4, 2021 6:56 AM
To: Teres Alexis, Alan Previn <alan.previn.teres.alexis@intel.com>
Cc: igt-dev@lists.freedesktop.org
Subject: Re: [igt-dev] [PATCH i-g-t 14/17] Verify execbuf ok with stale prot-buff and regular context

On Tue, May 18, 2021 at 03:33:41AM -0700, Alan Previn wrote:
> Add a check to verify that reusing a stale protected buffer in a 
> gem_execbuff call, but using a regular (not-
> protcted) context will succeed despite after a teardown
       ^ typo

with this fixed:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> (triggered by suspend-resume cycle).
> 
> This ensures that user space applications that choose not to opt-in 
> for strict PXP teardown awareness (by using a regular context) won't 
> suffer gem_execbuff failures if a protected buffer was among the 
> assets used in any of its rendering operations.
> 
> Reuse the existing subtest to minimize the number of suspend resume 
> cycles we take.
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
>  tests/i915/gem_pxp.c | 15 ++++++++++++++-
>  1 file changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c index 
> b4f369ae..e3c21c70 100644
> --- a/tests/i915/gem_pxp.c
> +++ b/tests/i915/gem_pxp.c
> @@ -760,7 +760,7 @@ static void free_exec_assets(int i915, struct 
> simple_exec_assets *data)  static void 
> test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_data *pm)  {
>  	int ret;
> -	struct simple_exec_assets data[2] = {{0}, {0}};
> +	struct simple_exec_assets data[3] = {{0}, {0}, {0}};
>  	uint32_t ctx2;
>  	struct intel_bb *ibb2;
>  
> @@ -777,6 +777,15 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
>  	ret = gem_execbuf_flush_store_dw(i915, data[1].ibb, data[1].ctx, data[1].fencebuf);
>  	igt_assert(ret == 0);
>  
> +	/*
> +	 * For data[2]: Use non-pxp contexts but with protected buffers
> +	 * to verify the "pxp-execution-opt-in" expectation where
> +	 * execution will run without error (not buffer)
> +	 */
> +	prepare_exec_assets(i915, &data[2], false, true);
> +	ret = gem_execbuf_flush_store_dw(i915, data[2].ibb, data[2].ctx, data[2].fencebuf);
> +	igt_assert(ret == 0);
> +
>  	trigger_powermgt_suspend_cycle(i915, pm);
>  
>  	ret = gem_execbuf_flush_store_dw(i915, data[0].ibb, data[0].ctx, 
> data[0].fencebuf); @@ -797,8 +806,12 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
>  	ret = gem_execbuf_flush_store_dw(i915, ibb2, ctx2, data[1].fencebuf);
>  	igt_assert_f((ret == -ENOEXEC), "Executing stale pxp buffer didn't 
> fail with -ENOEXEC\n");
>  
> +	ret = gem_execbuf_flush_store_dw(i915, data[2].ibb, data[2].ctx, data[2].fencebuf);
> +	igt_assert_f((ret == 0), "Opt-out-execution with stale pxp buffer 
> +didn't succeed\n");
> +
>  	free_exec_assets(i915, &data[0]);
>  	free_exec_assets(i915, &data[1]);
> +	free_exec_assets(i915, &data[2]);
>  }
>  
>  igt_main
> --
> 2.25.1
> 
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> igt-dev@lists.freedesktop.org
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Re: [igt-dev] [PATCH i-g-t 16/17] Verify protected surfaces are dma buffer sharable

[Teres Alexis, Alan Previn]

Thanks! :)

-----Original Message-----
From: Vivi, Rodrigo <rodrigo.vivi@intel.com> 
Sent: Friday, June 4, 2021 7:18 AM
To: Teres Alexis, Alan Previn <alan.previn.teres.alexis@intel.com>
Cc: igt-dev@lists.freedesktop.org
Subject: Re: [igt-dev] [PATCH i-g-t 16/17] Verify protected surfaces are dma buffer sharable

On Tue, May 18, 2021 at 03:33:43AM -0700, Alan Previn wrote:
> Verify we can export a protected surface from protected context A into 
> protected context B (with different client driver handles) and 
> protected rendering is successful even after prior file handle is 
> closed (i.e. pxp specific refcounting works).
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  tests/i915/gem_pxp.c | 103 
> +++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 103 insertions(+)
> 
> diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c index 
> 69a3143a..179fb742 100644
> --- a/tests/i915/gem_pxp.c
> +++ b/tests/i915/gem_pxp.c
> @@ -3,6 +3,7 @@
>   * Copyright (c) 2021 Intel Corporation
>   */
>  
> +#include <fcntl.h>
>  #include "igt.h"
>  #include "i915/gem.h"
>  
> @@ -618,6 +619,106 @@ static void test_render_pxp_protsrc_to_protdest(int i915)
>  	buf_ops_destroy(bops);
>  }
>  
> +static int export_handle(int fd, uint32_t handle, int *outfd) {
> +	struct drm_prime_handle args;
> +	int ret;
> +
> +	args.handle = handle;
> +	args.flags = DRM_CLOEXEC;
> +	args.fd = -1;
> +
> +	ret = drmIoctl(fd, DRM_IOCTL_PRIME_HANDLE_TO_FD, &args);
> +	if (ret)
> +		ret = errno;
> +	*outfd = args.fd;
> +
> +	return ret;
> +}
> +
> +static void test_pxp_dmabuffshare_refcnt(void)
> +{
> +	uint32_t ctx[2], sbo[2], dbo[2];
> +	struct intel_buf *sbuf[2], *dbuf[2];
> +	struct buf_ops *bops[2];
> +	struct intel_bb *ibb[2];
> +	int fd[2], dmabuf_fd = 0, ret, n, num_matches = 0;
> +	uint32_t encrypted[2][TSTSURF_SIZE/TSTSURF_BYTESPP];
> +
> +	/* First, create the client driver handles and
> +	 * protected dest buffer (is exported via dma-buff
> +	 * from first handle and imported to the second).
> +	 */
> +	for (n = 0; n < 2; ++n) {
> +		fd[n] = drm_open_driver(DRIVER_INTEL);
> +		igt_require(fd[n]);
> +		if (n == 0) {
> +			dbo[0] = alloc_and_fill_dest_buff(fd[0], true, TSTSURF_SIZE,
> +							  TSTSURF_INITCOLOR1);
> +		} else {
> +			ret = export_handle(fd[0], dbo[0], &dmabuf_fd);
> +			igt_assert(ret == 0);
> +			dbo[1] = prime_fd_to_handle(fd[1], dmabuf_fd);
> +			igt_assert(dbo[1]);
> +		}
> +	}
> +	/* Repeat twice: Create a full set of assets to perform
> +	 * a protected 3D session but using the same dest buffer
> +	 * from above.
> +	 */
> +	for (n = 0; n < 2; ++n) {
> +		ret = create_ctx_with_params(fd[n], true, true, true, false, &ctx[n]);
> +		igt_assert_eq(ret, 0);
> +		igt_assert_eq(get_ctx_protected_param(fd[n], ctx[n]), 1);
> +		ibb[n] = intel_bb_create_with_context(fd[n], ctx[n], 4096);
> +		intel_bb_set_pxp(ibb[n], true, DISPLAY_APPTYPE,
> +				 I915_PROTECTED_CONTENT_DEFAULT_SESSION);
> +
> +		bops[n] = buf_ops_create(fd[n]);
> +		if (n == 1)
> +			fill_bo_content(fd[1], dbo[1], TSTSURF_SIZE, TSTSURF_INITCOLOR2);
> +
> +		dbuf[n] = intel_buf_create_using_handle(bops[n], dbo[n], TSTSURF_WIDTH,
> +							TSTSURF_HEIGHT,	TSTSURF_BYTESPP*8, 0,
> +							I915_TILING_NONE, 0);
> +		intel_buf_set_pxp(dbuf[n], true);
> +
> +		sbo[n] = alloc_and_fill_dest_buff(fd[n], false, TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
> +		sbuf[n] = intel_buf_create_using_handle(bops[n], sbo[n], TSTSURF_WIDTH,
> +							TSTSURF_HEIGHT, TSTSURF_BYTESPP*8, 0,
> +							I915_TILING_NONE, 0);
> +
> +		gen12_render_copyfunc(ibb[n], sbuf[n], 0, 0, TSTSURF_WIDTH, TSTSURF_HEIGHT,
> +				      dbuf[n], 0, 0);
> +		gem_sync(fd[n], dbo[n]);
> +
> +		assert_bo_content_check(fd[n], dbo[n], COMPARE_COLOR_UNREADIBLE, TSTSURF_SIZE,
> +					TSTSURF_FILLCOLOR1, NULL, 0);
> +		assert_bo_content_check(fd[n], dbo[n], COPY_BUFFER, TSTSURF_SIZE, 0, encrypted[n],
> +					TSTSURF_SIZE);
> +
> +		/* free up all assets except the dest buffer to
> +		 * verify dma buff refcounting is performed on
> +		 * the protected dest buffer on the 2nd loop with
> +		 * successful reuse in another protected render.
> +		 */
> +		intel_bb_destroy(ibb[n]);
> +		intel_buf_destroy(sbuf[n]);
> +		intel_buf_destroy(dbuf[n]);
> +		gem_close(fd[n], sbo[n]);
> +		gem_close(fd[n], dbo[n]);
> +		gem_context_destroy(fd[n], ctx[n]);
> +		close(fd[n]);
> +	}
> +
> +	/* Verify that encrypted output across loops were equal */
> +	for (n = 0; n < (TSTSURF_SIZE/4); ++n)
> +		if (encrypted[0][n] == encrypted[1][n])
> +			++num_matches;
> +	igt_assert(num_matches == (TSTSURF_SIZE/4)); }
> +
> +
>  static void init_powermgt_resources(int i915, struct powermgt_data 
> *pm)  {
>  	pm->debugfsdir = igt_debugfs_dir(i915); @@ -912,6 +1013,8 @@ 
> igt_main
>  			test_render_pxp_src_to_protdest(i915);
>  		igt_subtest("protected-encrypted-src-copy-not-readible")
>  			test_render_pxp_protsrc_to_protdest(i915);
> +		igt_subtest("dmabuf-shared-protected-dst-is-context-refcounted")
> +			test_pxp_dmabuffshare_refcnt();
>  	}
>  	igt_subtest_group {
>  		igt_fixture {
> --
> 2.25.1
> 
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Re: [igt-dev] [PATCH i-g-t 17/17] tests/i915_pxp: CRC validation for display tests.

[Teres Alexis, Alan Previn]

On Fri, 2021-06-04 at 10:40 -0400, Rodrigo Vivi wrote:
> On Tue, May 18, 2021 at 03:33:44AM -0700, Alan Previn wrote:
> > From: Karthik B S <karthik.b.s@intel.com>
> > 
> > Added subtests to validate pxp using CRC validation.
> > 
> > Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Cc: Uma Shankar <uma.shankar@intel.com>
> 
> > ---
> >  tests/i915/gem_pxp.c | 286
> > ++++++++++++++++++++++++++++++++++++++++++-
> >  1 file changed, 283 insertions(+), 3 deletions(-)
> > 
> > diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
> > index 179fb742..728c925a 100644
> > +		if (hdcp) {
> > +			/* Disable HDCP and collect CRC */
> > +			igt_output_set_prop_value(hdcp_output[0],
> > IGT_CONNECTOR_CONTENT_PROTECTION,
> > +						  CP_UNDESIRED);
> > +			igt_display_commit2(display, COMMIT_ATOMIC);
> > +			ret = wait_for_prop_value(hdcp_output[0],
> > CP_UNDESIRED,
> > +						  KERNEL_DISABLE_TIME_A
> > LLOWED_MSEC);
> > +			igt_assert_f(ret, "Content Protection not
> > cleared\n");
> > +
> > +			igt_plane_set_fb(plane, &protected_fb);
> > +			igt_fb_set_size(&protected_fb, plane, mode-
> > >hdisplay, mode->vdisplay);
> > +			igt_plane_set_size(plane, mode->hdisplay, mode-
> > >vdisplay);
> > +
> > +			igt_display_commit2(display, COMMIT_ATOMIC);
> > +			igt_pipe_crc_collect_crc(pipe_crc, &new_crc);
> > +			igt_assert_f(!igt_check_crc_equal(&ref_crc,
> > &new_crc),
> > +				    "CRC's expected to be different
> > after HDCP is disabled\n");
> 
> The CRC is at the pipe level, but I believe it is right to expect
> that
> after disabling the HDCP we will get different CRC.
> 
> +Uma to help me to confirm this.
> 
> But also, I'm asking myself if this test case here is really bringing
> any value to PXP itself. To me, it looks like it is only testing
> HDCP disable scenario... nothing to do with the PXP flow.
> 
> With the HDCP removed, or with Uma confirming my assumption is right
> and that I'm wrong about the value-added, feel free to use:
> 

If i recall our earlier conversations on test requirements, we wanted
to ensure that the HW had indeed changed the key or completely disabled
plane decryption in response to the teardown (i.e. disabling hdcp).
With that in mind, I thought pipe crc is not a reflection of hdcp
encryption state - i thought that was the transcoder CRC. So Pipe CRC
really does reflect the content (and, as such, plane decryption) unless
the plane is disabled or occluded by another plane (which is never the
case in this controlled IGT environment). But lets hear from Uma - i
maybe crc input-signal.

> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> > 
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Re: [igt-dev] [PATCH i-g-t 09/17] Add subtest to copy raw source to protected dest

[Teres Alexis, Alan Previn]

On Fri, 2021-06-04 at 09:22 -0400, Rodrigo Vivi wrote:
> On Tue, May 18, 2021 at 03:33:36AM -0700, Alan Previn wrote:
> > Add subtest to 3d-copy raw source buffer (with
> > known readible content) to a destination buffer
> > marked as protected with a protected session using
> > default session keys. The destination buffer is
> > verified to be different from the source (when
> > read via CPU) because its encrypted.
> > 
> > Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> > ---
> >  tests/i915/gem_pxp.c | 55
> > ++++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 55 insertions(+)
> > 
> > diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
> > index b1415efc..5a29024a 100644
> > --- a/tests/i915/gem_pxp.c
> > +++ b/tests/i915/gem_pxp.c
> > @@ -376,7 +376,9 @@ static uint32_t alloc_and_fill_dest_buff(int
> > i915, bool protected, uint32_t size
> >  #define TSTSURF_STRIDE      (TSTSURF_WIDTH*TSTSURF_BYTESPP)
> >  #define TSTSURF_SIZE        (TSTSURF_STRIDE*TSTSURF_HEIGHT)
> >  #define TSTSURF_FILLCOLOR1  0xfaceface
> > +#define TSTSURF_FILLCOLOR2  0xdeaddead
> >  #define TSTSURF_INITCOLOR1  0x12341234
> > +#define TSTSURF_INITCOLOR2  0x56785678
> 
> I couldn't understand why we can't simply reuse the ones who were
> there
> already, but anyway:
> 

Since this operation required me to start with a raw-src, then encrypt
it once to a dest-buf and then reuse that dest-buf as another source in
a second render operation, i wanted to ensure that none of the initial
color values of that second operation happenned to be the same as the
first operation. This is to avoid the event of stale data from re-used
memory not cleared properly (a bug we want to catch?) and missing it as
we setup the buffers for the second render.

We could perhaps forgo FILLCOLOR2 but since you gave the rv-b, I'm
assuming i can skip this.

Thanks again btw.

> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> 

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Re: [igt-dev] [PATCH i-g-t 10/17] Add test where both src and dest are protected

[Teres Alexis, Alan Previn]

On Fri, 2021-06-04 at 09:31 -0400, Rodrigo Vivi wrote:
> On Tue, May 18, 2021 at 03:33:37AM -0700, Alan Previn wrote:
> > -static void assert_bo_content_check(int i915, uint32_t bo, int
> > compare_op,
> > -				    uint32_t size, uint32_t color)
> > +static void assert_bo_content_check(int i915, uint32_t bo, int
> > compare_op, uint32_t size,
> > +				    uint32_t color, uint32_t *auxptr,
> > int auxsize)
> >  {
> > -	uint32_t *ptr, *ptrtmp;
> > +	uint32_t *ptr, *ptrtmp, *auxtmp;
> >  	int loop = 0, num_matches = 0;
> >  	uint32_t value;
> > -	bool op_readible = (compare_op == COMPARE_COLOR_READIBLE);
> > +	bool op_readible = ((compare_op == COMPARE_COLOR_READIBLE) ||
> > +		 (compare_op == COMPARE_BUFFER_READIBLE));
> > +	bool chk_buff = ((compare_op == COMPARE_BUFFER_READIBLE) ||
> > +		 (compare_op == COMPARE_BUFFER_UNREADIBLE));
> 
> why do we need to differentiate between color and buffer if they
> are doing the same thing everywhere?
> 
> well, I'm assuming this is a future case, so anyway:
> 
Yes, depending on the subtest, we're comparing rendered buffers against
a constant color value or we're comparing rendered buffers against an
auxiliary buffer to compare against. In some subtests, they need to
match and in other subtests they need to fail. that's why mirrored op
definitions. Thanks.

> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> 
> 
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Re: [igt-dev] [PATCH i-g-t 17/17] tests/i915_pxp: CRC validation for display tests.

[Shankar, Uma]

> -----Original Message-----
> From: Teres Alexis, Alan Previn <alan.previn.teres.alexis@intel.com>
> Sent: Saturday, June 5, 2021 6:38 AM
> To: Shankar, Uma <uma.shankar@intel.com>; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>
> Cc: igt-dev@lists.freedesktop.org
> Subject: Re: [igt-dev] [PATCH i-g-t 17/17] tests/i915_pxp: CRC validation for display
> tests.
> 
> On Fri, 2021-06-04 at 10:40 -0400, Rodrigo Vivi wrote:
> > On Tue, May 18, 2021 at 03:33:44AM -0700, Alan Previn wrote:
> > > From: Karthik B S <karthik.b.s@intel.com>
> > >
> > > Added subtests to validate pxp using CRC validation.
> > >
> > > Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> > Cc: Uma Shankar <uma.shankar@intel.com>
> >
> > > ---
> > >  tests/i915/gem_pxp.c | 286
> > > ++++++++++++++++++++++++++++++++++++++++++-
> > >  1 file changed, 283 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c index
> > > 179fb742..728c925a 100644
> > > +		if (hdcp) {
> > > +			/* Disable HDCP and collect CRC */
> > > +			igt_output_set_prop_value(hdcp_output[0],
> > > IGT_CONNECTOR_CONTENT_PROTECTION,
> > > +						  CP_UNDESIRED);
> > > +			igt_display_commit2(display, COMMIT_ATOMIC);
> > > +			ret = wait_for_prop_value(hdcp_output[0],
> > > CP_UNDESIRED,
> > > +						  KERNEL_DISABLE_TIME_A
> > > LLOWED_MSEC);
> > > +			igt_assert_f(ret, "Content Protection not
> > > cleared\n");
> > > +
> > > +			igt_plane_set_fb(plane, &protected_fb);
> > > +			igt_fb_set_size(&protected_fb, plane, mode-
> > > >hdisplay, mode->vdisplay);
> > > +			igt_plane_set_size(plane, mode->hdisplay, mode-
> > > >vdisplay);
> > > +
> > > +			igt_display_commit2(display, COMMIT_ATOMIC);
> > > +			igt_pipe_crc_collect_crc(pipe_crc, &new_crc);
> > > +			igt_assert_f(!igt_check_crc_equal(&ref_crc,
> > > &new_crc),
> > > +				    "CRC's expected to be different
> > > after HDCP is disabled\n");
> >
> > The CRC is at the pipe level, but I believe it is right to expect that
> > after disabling the HDCP we will get different CRC.
> >
> > +Uma to help me to confirm this.
> >
> > But also, I'm asking myself if this test case here is really bringing
> > any value to PXP itself. To me, it looks like it is only testing HDCP
> > disable scenario... nothing to do with the PXP flow.
> >
> > With the HDCP removed, or with Uma confirming my assumption is right
> > and that I'm wrong about the value-added, feel free to use:
> >
> 
> If i recall our earlier conversations on test requirements, we wanted to ensure that
> the HW had indeed changed the key or completely disabled plane decryption in
> response to the teardown (i.e. disabling hdcp).
> With that in mind, I thought pipe crc is not a reflection of hdcp encryption state - i
> thought that was the transcoder CRC. So Pipe CRC really does reflect the content
> (and, as such, plane decryption) unless the plane is disabled or occluded by another
> plane (which is never the case in this controlled IGT environment). But lets hear from
> Uma - i maybe crc input-signal.

Sorry for a late response, somehow missed this mail.

We have crc's at both pipe and at port level but it appears in the test here we are relying on pipe crc.
So pipe crc will not be dependent on any HDCP state change as that happens at port. But if we expect
that as part of HDCP teardown we will also disable plane decryption then surely we will get a different
crc. But is it really the case here. Are we expecting both Plane decryption which is a PAVP usecase and
HDCP to be operating together.  My understanding is we will have PAVP only for internal LFP's and go with
HDCP when we operate with external sync.

Regards,
Uma Shankar

> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >
> > >

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Re: [igt-dev] [PATCH i-g-t 17/17] tests/i915_pxp: CRC validation for display tests.

[Rodrigo Vivi]

On Thu, Jun 10, 2021 at 01:00:06PM +0000, Shankar, Uma wrote:
> 
> 
> > -----Original Message-----
> > From: Teres Alexis, Alan Previn <alan.previn.teres.alexis@intel.com>
> > Sent: Saturday, June 5, 2021 6:38 AM
> > To: Shankar, Uma <uma.shankar@intel.com>; Vivi, Rodrigo
> > <rodrigo.vivi@intel.com>
> > Cc: igt-dev@lists.freedesktop.org
> > Subject: Re: [igt-dev] [PATCH i-g-t 17/17] tests/i915_pxp: CRC validation for display
> > tests.
> > 
> > On Fri, 2021-06-04 at 10:40 -0400, Rodrigo Vivi wrote:
> > > On Tue, May 18, 2021 at 03:33:44AM -0700, Alan Previn wrote:
> > > > From: Karthik B S <karthik.b.s@intel.com>
> > > >
> > > > Added subtests to validate pxp using CRC validation.
> > > >
> > > > Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> > > Cc: Uma Shankar <uma.shankar@intel.com>
> > >
> > > > ---
> > > >  tests/i915/gem_pxp.c | 286
> > > > ++++++++++++++++++++++++++++++++++++++++++-
> > > >  1 file changed, 283 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c index
> > > > 179fb742..728c925a 100644
> > > > +		if (hdcp) {
> > > > +			/* Disable HDCP and collect CRC */
> > > > +			igt_output_set_prop_value(hdcp_output[0],
> > > > IGT_CONNECTOR_CONTENT_PROTECTION,
> > > > +						  CP_UNDESIRED);
> > > > +			igt_display_commit2(display, COMMIT_ATOMIC);
> > > > +			ret = wait_for_prop_value(hdcp_output[0],
> > > > CP_UNDESIRED,
> > > > +						  KERNEL_DISABLE_TIME_A
> > > > LLOWED_MSEC);
> > > > +			igt_assert_f(ret, "Content Protection not
> > > > cleared\n");
> > > > +
> > > > +			igt_plane_set_fb(plane, &protected_fb);
> > > > +			igt_fb_set_size(&protected_fb, plane, mode-
> > > > >hdisplay, mode->vdisplay);
> > > > +			igt_plane_set_size(plane, mode->hdisplay, mode-
> > > > >vdisplay);
> > > > +
> > > > +			igt_display_commit2(display, COMMIT_ATOMIC);
> > > > +			igt_pipe_crc_collect_crc(pipe_crc, &new_crc);
> > > > +			igt_assert_f(!igt_check_crc_equal(&ref_crc,
> > > > &new_crc),
> > > > +				    "CRC's expected to be different
> > > > after HDCP is disabled\n");
> > >
> > > The CRC is at the pipe level, but I believe it is right to expect that
> > > after disabling the HDCP we will get different CRC.
> > >
> > > +Uma to help me to confirm this.
> > >
> > > But also, I'm asking myself if this test case here is really bringing
> > > any value to PXP itself. To me, it looks like it is only testing HDCP
> > > disable scenario... nothing to do with the PXP flow.
> > >
> > > With the HDCP removed, or with Uma confirming my assumption is right
> > > and that I'm wrong about the value-added, feel free to use:
> > >
> > 
> > If i recall our earlier conversations on test requirements, we wanted to ensure that
> > the HW had indeed changed the key or completely disabled plane decryption in
> > response to the teardown (i.e. disabling hdcp).
> > With that in mind, I thought pipe crc is not a reflection of hdcp encryption state - i
> > thought that was the transcoder CRC. So Pipe CRC really does reflect the content
> > (and, as such, plane decryption) unless the plane is disabled or occluded by another
> > plane (which is never the case in this controlled IGT environment). But lets hear from
> > Uma - i maybe crc input-signal.
> 
> Sorry for a late response, somehow missed this mail.

no problem

> 
> We have crc's at both pipe and at port level but it appears in the test here we are relying on pipe crc.
> So pipe crc will not be dependent on any HDCP state change as that happens at port. But if we expect
> that as part of HDCP teardown we will also disable plane decryption then surely we will get a different
> crc. But is it really the case here. Are we expecting both Plane decryption which is a PAVP usecase and
> HDCP to be operating together.  My understanding is we will have PAVP only for internal LFP's and go with
> HDCP when we operate with external sync.

Thanks.
So, if we want to move faster we probably want to drop this part of the test
or this patch entirely for the next revision and move with a follow up version
after the initial ones are merged.

> 
> Regards,
> Uma Shankar
> 
> > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > >
> > > >
> 
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Re: [igt-dev] [PATCH i-g-t 08/17] Enable protected session cmd in gen12_render_copyfunc

[Teres Alexis, Alan Previn]

On Fri, 2021-06-04 at 09:16 -0400, Rodrigo Vivi wrote:
> On Tue, May 18, 2021 at 03:33:35AM -0700, Alan Previn wrote:
> > 1. In _gen9_render_op, check if the incoming batchbuffer
> >    is marked with pxp enabled. If so, insert MI_SET_APPID
> >    along with PIPE_CONTROL instructions at the start and
> >    end of the rendering operation in the command buffer.
> > 
> > 2. The two PIPE_CONTROLs will enable protected memory
> >    at the start of the batch and disabling protected
> >    memory at the end of it. These PIPE_CONTROLs require a
> >    Post-Sync operation with a write to memory for hardware
> >    to accept.
> > 
> > 3. In order to satisfy #2, _gen9_render_op uses unused
> >    regions of the ibb buffer for the PIPE_CONTROL PostSync
> >    write to memory (no different from how other 3d states
> >    are being referenced).
> > 
> > 4. _gen9_render_op shall check the incoming surface
> >    buffers for "is_protected" flag and if its set, it
> >    will mark the SURFACE_STATE's MOCS field accordingly.
> > 
> > NOTE: _gen9_render_op needs to program the HW to enable
> > the PXP session as part of the rendering batch buffer
> > because the HW requires that enabling/disabling protected
> > memory access must be programmed in pairs within the same
> > "dispatch of rendering commands" to HW.
> > 
> > Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> > ---
> >  lib/rendercopy_gen9.c | 72 ++++++++++++++++++++++++++++++++++++++-
> > ----
> >  1 file changed, 65 insertions(+), 7 deletions(-)
> > 
> > diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
> > index eecf73d3..bfcf311b 100644
> > --- a/lib/rendercopy_gen9.c
> > +++ b/lib/rendercopy_gen9.c
> > @@ -19,7 +19,8 @@
> >  #include "intel_bufops.h"
> >  #include "intel_batchbuffer.h"
> >  #include "intel_io.h"
> > -#include "rendercopy.h"
> > +#include "igt.h"
> > +#include "i915/gem.h"
> >  #include "gen9_render.h"
> >  #include "intel_reg.h"
> >  #include "igt_aux.h"
> > @@ -152,6 +153,8 @@ gen8_bind_buf(struct intel_bb *ibb, const
> > struct intel_buf *buf, int is_dst) {
> >  		ss->ss0.tiled_mode = 3;
> >  
> >  	ss->ss1.memory_object_control = I915_MOCS_PTE << 1;
> > +	if (intel_buf_pxp(buf))
> > +		ss->ss1.memory_object_control |= 1;
> >  
> >  	if (buf->tiling == I915_TILING_Yf)
> >  		ss->ss5.trmode = 1;
> > @@ -873,6 +876,53 @@ static void gen8_emit_primitive(struct
> > intel_bb *ibb, uint32_t offset)
> >  	intel_bb_out(ibb, 0);	/* index buffer offset, ignored */
> >  }
> >  
> +#define GFX_OP_PIPE_CONTROL    ((3 << 29) | (3 << 27) | (2 << 24))
> 
> there's no len defined here...

The calling function (gen12_emit_pxp_state) uses this CMD in 2 ways
where each of them have different lengths. 

Method A : When setting the APP_ID (done before enabling PXP), we call
PIPE_CONTROL with just a FLUSH_ENABLE which has a len == 0 (2 DWORDS). 

Method B : Subsequently, when enabling or disabling PXP, we need to
ensure PIPE_CONTROL op a memory write invalidation + flush which
requires additional post sync up to dest buffer offset.

I didn't want to create two macro's for each usage which is why I didnt
include the length into the macro - which i have seen in other IGT
tests (so i assumed there wasnt a hard rule).

> 
> > +#define PIPE_CONTROL_CS_STALL	            (1 << 20)
> > +#define PIPE_CONTROL_RENDER_TARGET_FLUSH    (1 << 12)
> > +#define PIPE_CONTROL_FLUSH_ENABLE           (1 << 7)
> > +#define PIPE_CONTROL_DATA_CACHE_INVALIDATE  (1 << 5)
> > +#define PIPE_CONTROL_PROTECTEDPATH_DISABLE  (1 << 27)
> > +#define PIPE_CONTROL_PROTECTEDPATH_ENABLE   (1 << 22)
> > +#define PIPE_CONTROL_POST_SYNC_OP           (1 << 14)
> > +#define PIPE_CONTROL_POST_SYNC_OP_STORE_DW_IDX (1 << 21)
> > +#define PS_OP_TAG_START                     0x1234fed0
> > +#define PS_OP_TAG_END                       0x5678cbaf
> > +static void gen12_emit_pxp_state(struct intel_bb *ibb, bool
> > enable,
> > +		 uint32_t pxp_write_op_offset)
> > +{
> > +	uint32_t pipe_ctl_flags;
> > +	uint32_t set_app_id, ps_op_id;
> > +
> > +	if (enable) {
> > +		pipe_ctl_flags = PIPE_CONTROL_FLUSH_ENABLE;
> > +		intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
> 
> ... so, I believe this one should be GFX_OP_PIPE_CONTROL | 1
> 
> (len - 2) = (3 - 2) = 1
No, this is Method A - see intel_bb_out is being called only twice:
	intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
	intel_bb_out(ibb, pipe_ctl_flags);
So "len - 2" = "2 - 2" = 0;

> 
> > +		intel_bb_out(ibb, pipe_ctl_flags);
> > +
> > +		set_app_id =  MI_SET_APPID |
> > +			      APPTYPE(intel_bb_pxp_apptype(ibb)) |
> > +			      APPID(intel_bb_pxp_appid(ibb));
> > +		intel_bb_out(ibb, set_app_id);
> > +
> > +		pipe_ctl_flags = PIPE_CONTROL_PROTECTEDPATH_ENABLE;
> > +		ps_op_id = PS_OP_TAG_START;
> > +	} else {
> > +		pipe_ctl_flags = PIPE_CONTROL_PROTECTEDPATH_DISABLE;
> > +		ps_op_id = PS_OP_TAG_END;
> > +	}
> > +
> > +	pipe_ctl_flags |= (PIPE_CONTROL_CS_STALL |
> > +			   PIPE_CONTROL_RENDER_TARGET_FLUSH |
> > +			   PIPE_CONTROL_DATA_CACHE_INVALIDATE |
> > +			   PIPE_CONTROL_POST_SYNC_OP);
> > +	intel_bb_out(ibb, GFX_OP_PIPE_CONTROL | 4);
> 
> and this one should be GFX_OP_PIPE_CONTROL | 2
> 
> (len - 2) = (4 - 2) = 2
> 
> but to be honest, I always get lost and confused with these
> pipe_control len...
> specially looking IGT tests, many of them don't make sense to me.
> 
> However I see, at least, some inconsistency here between these 2
> pipe_control
> emissions. What am I missing?
> 

This case uses Method B (where we require a PIPE_CONTROL with write
invalidation + flush), I am using a Post-Sync-Op as to a inline gfx
offset but the Post-Sync-Op also needs the inline "Immediate Data" to
be written. Both the gfx-offset and the immediate data are 64-bits
totaling 4 DWORDS.

The first 2-DWs (gfx offset) are populated as part of the
"intel_bb_emit_reloc" call (this function automatically uses 64 bit for
Gen12). The second 2-DWs (immediate data) are populated via the
intel_bb_out(ibb, ps_op_id) calls - i am repeating the same signature
twice (but different signatures for enabling vs disabling - see #define
with suffix '_TAG' above).

Therefore a total of 6 dwords are being populated (2=cmds, 2=gfx-
offsets, 2=immediate-data). So "len - 2" = "6 - 2" = 4;

That said, i dont see anything wrong with this patch - unless you
prefer me to replace the GFX_OP_PIPE_CONTROL macro with 2 distinct
ones:
GFX_OP_PIPE_CONTROL_SIMPLEFLUSH //where len==0
GFX_OP_PIPE_CONTROL_PSO_WRITE2OFFSET //where len==4 

NOTE: I have seen at least one other test define the macro without the
size and populate the size based on usage like like what is currently
done here.

> > +	intel_bb_out(ibb, pipe_ctl_flags);
> > +	intel_bb_emit_reloc(ibb, ibb->handle, 0,
> > I915_GEM_DOMAIN_COMMAND,
> > +			    (enable ? pxp_write_op_offset :
> > (pxp_write_op_offset+8)),
> > +			    ibb->batch_offset);
> > +	intel_bb_out(ibb, ps_op_id);
> > +	intel_bb_out(ibb, ps_op_id);
> > +}
> > +
> >  /* The general rule is if it's named gen6 it is directly copied
> > from
> >   * gen6_render_copyfunc.
> >   *
> > @@ -922,6 +972,7 @@ void _gen9_render_op(struct intel_bb *ibb,
> >  	uint32_t vertex_buffer;
> >  	uint32_t aux_pgtable_state;
> >  	bool fast_clear = !src;
> > +	uint32_t pxp_scratch_offset;
> >  
> >  	if (!fast_clear)
> >  		igt_assert(src->bpp == dst->bpp);
> > @@ -950,8 +1001,12 @@ void _gen9_render_op(struct intel_bb *ibb,
> >  	aux_pgtable_state = gen12_create_aux_pgtable_state(ibb,
> > aux_pgtable_buf);
> >  
> >  	/* TODO: there is other state which isn't setup */
> > +	pxp_scratch_offset = intel_bb_offset(ibb);
> >  	intel_bb_ptr_set(ibb, 0);
> >  
> > +	if (intel_bb_pxp_enabled(ibb))
> > +		gen12_emit_pxp_state(ibb, true, pxp_scratch_offset);
> > +
> >  	/* Start emitting the commands. The order roughly follows the
> > mesa blorp
> >  	 * order */
> >  	intel_bb_out(ibb, G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D |
> > @@ -963,13 +1018,12 @@ void _gen9_render_op(struct intel_bb *ibb,
> >  		for (int i = 0; i < 4; i++) {
> >  			intel_bb_out(ibb, MI_STORE_DWORD_IMM);
> >  			intel_bb_emit_reloc(ibb, dst->handle,
> > -					    I915_GEM_DOMAIN_RENDER,
> > I915_GEM_DOMAIN_RENDER,
> > -                                            dst->cc.offset +
> > i*sizeof(float),
> > -					    dst->addr.offset);
> > +					I915_GEM_DOMAIN_RENDER,
> > I915_GEM_DOMAIN_RENDER,
> > +					dst->cc.offset +
> > i*sizeof(float),
> > +					dst->addr.offset);
> >  			intel_bb_out(ibb, *(uint32_t*)&clear_color[i]);
> > -               }
> > -       }
> > -
> > +		}
> > +	}
> >  
> >  	gen8_emit_sip(ibb);
> >  
> > @@ -1023,10 +1077,14 @@ void _gen9_render_op(struct intel_bb *ibb,
> >  	gen8_emit_vf_topology(ibb);
> >  	gen8_emit_primitive(ibb, vertex_buffer);
> >  
> > +	if (intel_bb_pxp_enabled(ibb))
> > +		gen12_emit_pxp_state(ibb, false, pxp_scratch_offset);
> > +
> >  	intel_bb_emit_bbe(ibb);
> >  	intel_bb_exec(ibb, intel_bb_offset(ibb),
> >  		      I915_EXEC_RENDER | I915_EXEC_NO_RELOC, false);
> >  	dump_batch(ibb);
> > +
> >  	intel_bb_reset(ibb, false);
> >  }
> >  
> > -- 
> > 2.25.1
> > 
> > _______________________________________________
> > igt-dev mailing list
> > igt-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t 08/17] Enable protected session cmd in gen12_render_copyfunc

[Rodrigo Vivi]

On Thu, Jun 10, 2021 at 05:36:57PM +0000, Teres Alexis, Alan Previn wrote:
> On Fri, 2021-06-04 at 09:16 -0400, Rodrigo Vivi wrote:
> > On Tue, May 18, 2021 at 03:33:35AM -0700, Alan Previn wrote:
> > > 1. In _gen9_render_op, check if the incoming batchbuffer
> > >    is marked with pxp enabled. If so, insert MI_SET_APPID
> > >    along with PIPE_CONTROL instructions at the start and
> > >    end of the rendering operation in the command buffer.
> > > 
> > > 2. The two PIPE_CONTROLs will enable protected memory
> > >    at the start of the batch and disabling protected
> > >    memory at the end of it. These PIPE_CONTROLs require a
> > >    Post-Sync operation with a write to memory for hardware
> > >    to accept.
> > > 
> > > 3. In order to satisfy #2, _gen9_render_op uses unused
> > >    regions of the ibb buffer for the PIPE_CONTROL PostSync
> > >    write to memory (no different from how other 3d states
> > >    are being referenced).
> > > 
> > > 4. _gen9_render_op shall check the incoming surface
> > >    buffers for "is_protected" flag and if its set, it
> > >    will mark the SURFACE_STATE's MOCS field accordingly.
> > > 
> > > NOTE: _gen9_render_op needs to program the HW to enable
> > > the PXP session as part of the rendering batch buffer
> > > because the HW requires that enabling/disabling protected
> > > memory access must be programmed in pairs within the same
> > > "dispatch of rendering commands" to HW.
> > > 
> > > Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> > > ---
> > >  lib/rendercopy_gen9.c | 72 ++++++++++++++++++++++++++++++++++++++-
> > > ----
> > >  1 file changed, 65 insertions(+), 7 deletions(-)
> > > 
> > > diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
> > > index eecf73d3..bfcf311b 100644
> > > --- a/lib/rendercopy_gen9.c
> > > +++ b/lib/rendercopy_gen9.c
> > > @@ -19,7 +19,8 @@
> > >  #include "intel_bufops.h"
> > >  #include "intel_batchbuffer.h"
> > >  #include "intel_io.h"
> > > -#include "rendercopy.h"
> > > +#include "igt.h"
> > > +#include "i915/gem.h"
> > >  #include "gen9_render.h"
> > >  #include "intel_reg.h"
> > >  #include "igt_aux.h"
> > > @@ -152,6 +153,8 @@ gen8_bind_buf(struct intel_bb *ibb, const
> > > struct intel_buf *buf, int is_dst) {
> > >  		ss->ss0.tiled_mode = 3;
> > >  
> > >  	ss->ss1.memory_object_control = I915_MOCS_PTE << 1;
> > > +	if (intel_buf_pxp(buf))
> > > +		ss->ss1.memory_object_control |= 1;
> > >  
> > >  	if (buf->tiling == I915_TILING_Yf)
> > >  		ss->ss5.trmode = 1;
> > > @@ -873,6 +876,53 @@ static void gen8_emit_primitive(struct
> > > intel_bb *ibb, uint32_t offset)
> > >  	intel_bb_out(ibb, 0);	/* index buffer offset, ignored */
> > >  }
> > >  
> > +#define GFX_OP_PIPE_CONTROL    ((3 << 29) | (3 << 27) | (2 << 24))
> > 
> > there's no len defined here...
> 
> The calling function (gen12_emit_pxp_state) uses this CMD in 2 ways
> where each of them have different lengths. 
> 
> Method A : When setting the APP_ID (done before enabling PXP), we call
> PIPE_CONTROL with just a FLUSH_ENABLE which has a len == 0 (2 DWORDS). 
> 
> Method B : Subsequently, when enabling or disabling PXP, we need to
> ensure PIPE_CONTROL op a memory write invalidation + flush which
> requires additional post sync up to dest buffer offset.
> 
> I didn't want to create two macro's for each usage which is why I didnt
> include the length into the macro - which i have seen in other IGT
> tests (so i assumed there wasnt a hard rule).

definitely not a requirement... I just wrote to highlight what I was
going to write below.
I actually prefer the way you did...

> 
> > 
> > > +#define PIPE_CONTROL_CS_STALL	            (1 << 20)
> > > +#define PIPE_CONTROL_RENDER_TARGET_FLUSH    (1 << 12)
> > > +#define PIPE_CONTROL_FLUSH_ENABLE           (1 << 7)
> > > +#define PIPE_CONTROL_DATA_CACHE_INVALIDATE  (1 << 5)
> > > +#define PIPE_CONTROL_PROTECTEDPATH_DISABLE  (1 << 27)
> > > +#define PIPE_CONTROL_PROTECTEDPATH_ENABLE   (1 << 22)
> > > +#define PIPE_CONTROL_POST_SYNC_OP           (1 << 14)
> > > +#define PIPE_CONTROL_POST_SYNC_OP_STORE_DW_IDX (1 << 21)
> > > +#define PS_OP_TAG_START                     0x1234fed0
> > > +#define PS_OP_TAG_END                       0x5678cbaf
> > > +static void gen12_emit_pxp_state(struct intel_bb *ibb, bool
> > > enable,
> > > +		 uint32_t pxp_write_op_offset)
> > > +{
> > > +	uint32_t pipe_ctl_flags;
> > > +	uint32_t set_app_id, ps_op_id;
> > > +
> > > +	if (enable) {
> > > +		pipe_ctl_flags = PIPE_CONTROL_FLUSH_ENABLE;
> > > +		intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
> > 
> > ... so, I believe this one should be GFX_OP_PIPE_CONTROL | 1
> > 
> > (len - 2) = (3 - 2) = 1
> No, this is Method A - see intel_bb_out is being called only twice:
> 	intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
> 	intel_bb_out(ibb, pipe_ctl_flags);
> So "len - 2" = "2 - 2" = 0;

Duh! I counted the app_id bb_out (facepalm)
Sorry

> 
> > 
> > > +		intel_bb_out(ibb, pipe_ctl_flags);
> > > +
> > > +		set_app_id =  MI_SET_APPID |
> > > +			      APPTYPE(intel_bb_pxp_apptype(ibb)) |
> > > +			      APPID(intel_bb_pxp_appid(ibb));
> > > +		intel_bb_out(ibb, set_app_id);
> > > +
> > > +		pipe_ctl_flags = PIPE_CONTROL_PROTECTEDPATH_ENABLE;
> > > +		ps_op_id = PS_OP_TAG_START;
> > > +	} else {
> > > +		pipe_ctl_flags = PIPE_CONTROL_PROTECTEDPATH_DISABLE;
> > > +		ps_op_id = PS_OP_TAG_END;
> > > +	}
> > > +
> > > +	pipe_ctl_flags |= (PIPE_CONTROL_CS_STALL |
> > > +			   PIPE_CONTROL_RENDER_TARGET_FLUSH |
> > > +			   PIPE_CONTROL_DATA_CACHE_INVALIDATE |
> > > +			   PIPE_CONTROL_POST_SYNC_OP);
> > > +	intel_bb_out(ibb, GFX_OP_PIPE_CONTROL | 4);
> > 
> > and this one should be GFX_OP_PIPE_CONTROL | 2
> > 
> > (len - 2) = (4 - 2) = 2
> > 
> > but to be honest, I always get lost and confused with these
> > pipe_control len...
> > specially looking IGT tests, many of them don't make sense to me.
> > 
> > However I see, at least, some inconsistency here between these 2
> > pipe_control
> > emissions. What am I missing?

of course I messed the 2 bb_out inside the bb_emit_reloc...
sorry and thanks for the clarifications:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> > 
> 
> This case uses Method B (where we require a PIPE_CONTROL with write
> invalidation + flush), I am using a Post-Sync-Op as to a inline gfx
> offset but the Post-Sync-Op also needs the inline "Immediate Data" to
> be written. Both the gfx-offset and the immediate data are 64-bits
> totaling 4 DWORDS.
> 
> The first 2-DWs (gfx offset) are populated as part of the
> "intel_bb_emit_reloc" call (this function automatically uses 64 bit for
> Gen12). The second 2-DWs (immediate data) are populated via the
> intel_bb_out(ibb, ps_op_id) calls - i am repeating the same signature
> twice (but different signatures for enabling vs disabling - see #define
> with suffix '_TAG' above).
> 
> Therefore a total of 6 dwords are being populated (2=cmds, 2=gfx-
> offsets, 2=immediate-data). So "len - 2" = "6 - 2" = 4;
> 
> That said, i dont see anything wrong with this patch - unless you
> prefer me to replace the GFX_OP_PIPE_CONTROL macro with 2 distinct
> ones:
> GFX_OP_PIPE_CONTROL_SIMPLEFLUSH //where len==0
> GFX_OP_PIPE_CONTROL_PSO_WRITE2OFFSET //where len==4 
> 
> NOTE: I have seen at least one other test define the macro without the
> size and populate the size based on usage like like what is currently
> done here.
> 
> > > +	intel_bb_out(ibb, pipe_ctl_flags);
> > > +	intel_bb_emit_reloc(ibb, ibb->handle, 0,
> > > I915_GEM_DOMAIN_COMMAND,
> > > +			    (enable ? pxp_write_op_offset :
> > > (pxp_write_op_offset+8)),
> > > +			    ibb->batch_offset);
> > > +	intel_bb_out(ibb, ps_op_id);
> > > +	intel_bb_out(ibb, ps_op_id);
> > > +}
> > > +
> > >  /* The general rule is if it's named gen6 it is directly copied
> > > from
> > >   * gen6_render_copyfunc.
> > >   *
> > > @@ -922,6 +972,7 @@ void _gen9_render_op(struct intel_bb *ibb,
> > >  	uint32_t vertex_buffer;
> > >  	uint32_t aux_pgtable_state;
> > >  	bool fast_clear = !src;
> > > +	uint32_t pxp_scratch_offset;
> > >  
> > >  	if (!fast_clear)
> > >  		igt_assert(src->bpp == dst->bpp);
> > > @@ -950,8 +1001,12 @@ void _gen9_render_op(struct intel_bb *ibb,
> > >  	aux_pgtable_state = gen12_create_aux_pgtable_state(ibb,
> > > aux_pgtable_buf);
> > >  
> > >  	/* TODO: there is other state which isn't setup */
> > > +	pxp_scratch_offset = intel_bb_offset(ibb);
> > >  	intel_bb_ptr_set(ibb, 0);
> > >  
> > > +	if (intel_bb_pxp_enabled(ibb))
> > > +		gen12_emit_pxp_state(ibb, true, pxp_scratch_offset);
> > > +
> > >  	/* Start emitting the commands. The order roughly follows the
> > > mesa blorp
> > >  	 * order */
> > >  	intel_bb_out(ibb, G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D |
> > > @@ -963,13 +1018,12 @@ void _gen9_render_op(struct intel_bb *ibb,
> > >  		for (int i = 0; i < 4; i++) {
> > >  			intel_bb_out(ibb, MI_STORE_DWORD_IMM);
> > >  			intel_bb_emit_reloc(ibb, dst->handle,
> > > -					    I915_GEM_DOMAIN_RENDER,
> > > I915_GEM_DOMAIN_RENDER,
> > > -                                            dst->cc.offset +
> > > i*sizeof(float),
> > > -					    dst->addr.offset);
> > > +					I915_GEM_DOMAIN_RENDER,
> > > I915_GEM_DOMAIN_RENDER,
> > > +					dst->cc.offset +
> > > i*sizeof(float),
> > > +					dst->addr.offset);
> > >  			intel_bb_out(ibb, *(uint32_t*)&clear_color[i]);
> > > -               }
> > > -       }
> > > -
> > > +		}
> > > +	}
> > >  
> > >  	gen8_emit_sip(ibb);
> > >  
> > > @@ -1023,10 +1077,14 @@ void _gen9_render_op(struct intel_bb *ibb,
> > >  	gen8_emit_vf_topology(ibb);
> > >  	gen8_emit_primitive(ibb, vertex_buffer);
> > >  
> > > +	if (intel_bb_pxp_enabled(ibb))
> > > +		gen12_emit_pxp_state(ibb, false, pxp_scratch_offset);
> > > +
> > >  	intel_bb_emit_bbe(ibb);
> > >  	intel_bb_exec(ibb, intel_bb_offset(ibb),
> > >  		      I915_EXEC_RENDER | I915_EXEC_NO_RELOC, false);
> > >  	dump_batch(ibb);
> > > +
> > >  	intel_bb_reset(ibb, false);
> > >  }
> > >  
> > > -- 
> > > 2.25.1
> > > 
> > > _______________________________________________
> > > igt-dev mailing list
> > > igt-dev@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/igt-dev
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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[igt-dev] [PATCH i-g-t 00/17] Introduce PXP Test

[Alan Previn]

This series adds gem_pxp tests for the new PXP subsystem currently
being reviewed at https://patchwork.freedesktop.org/series/86798/ .
This series currently includes 4 groups of tests addressing the
features and restrictions described by Daniele's series :
   1. test i915 interfaces for allocation of protected bo's
      and contexts and enforcement of UAPI rule disallowing the
      modification of parameters after it's been created.
   2. verify PXP subsystem protected sessions generate encrypted
      content on protected output buffers and decrypt protected
      inputs buffers.
   3. verify i915 PXP auto-teardown succeeds on suspend-resume
      cycles and gem-exec of stale protected assets fail. Ensure
      protected-contexts adhere to stricter invalidation
      enforcement upon teardown event.
   4. Ensure that display plane decryption works as expected with
      protected buffers with and without HDCP.

NOTE: Although this series is on a third revision, the feature
has not been merged into the kernel yet. One final revision may
be necesssary depending on whether additional UAPI changes are
made on the kernel series. 

Changes from prior rev1 to now:
   v4:
      - Addressed all rev3 review comments. NOTE: that all
        test cases and code logic are the same but a decent
        amount of refactoring has occured due to address
        v3 comments to break out subtests into separate
        functions while combining certain checks into the same
        function to reduce test time by minimizing number of
        suspend-resume power cycles.
   v3:
      - Addressed all rev2 review comments.
      - In line with one of the rev2 comments, a thorough fixup
        of all line-breaks in function calls was made for a more
        consistent styling.
      - Rebased on igt upstream repo and updated to latest kernel
        UAPI that added GEM_CREATE_EXT.
   v2: 
      - Addressed all rev1 review comments except these:
           1.Chris Wilson : "...have the caller do 1-3 once for its protected
             context. Call it something like intel_bb_enable_pxp(),
             intel_bb_set_pxp if it should be reversible.".
             -  This couldn't be implemented because [1] HW needs different
             instruction sequences for enabling/disabling PXP depending
             on the engine class and [2] the pair of "pxp-enable" and "pxp-
             disable" instructions need to be contained within the same batch
             that is dispatched to the hardware. That said, implementing
             internal intel_batchbuffer funtionality for this would conflict
             with how rendercopy_gen9 uses batch buffer memory by repositioing
             the pointer and consuming unused portions of the batch buffer as
             3d state offsets that batchbuffer has no visibility.
         
      - Added these additional subtests:
           1. verify that buffer sharing works across testing pxp context.
           2. verify teardown bans contexts via DRM_IOCTL_I915_GET_RESET_STAT.
           3. verify display plane decryption of protected buffers.

Alan Previn (16):
  Sync i915_drm.h UAPI from kernel
  Add PXP UAPI support in i915_drm.h
  Upadte IOCTL wrapper with DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT
  Add basic PXP testing of buffer and context alloc
  Perform a regular 3d copy as a control checkpoint
  Add PXP attribute support in batchbuffer and buffer_ops libs
  Add MI_SET_APPID instruction definition
  Enable protected session cmd in gen12_render_copyfunc
  Add subtest to copy raw source to protected dest
  Add test where both src and dest are protected
  Verify PXP teardown occured through suspend-resume
  Verify execbuf fails with stale PXP context after teardown
  Verify execbuf fails with stale PXP buffer after teardown
  Verify execbuf ok with stale prot-buff and regular context
  Ensure RESET_STAT reports invalidated protected context
  Verify protected surfaces are dma buffer sharable

Karthik B S (1):
  tests/i915_pxp: CRC validation for display tests.

 include/drm-uapi/i915_drm.h |  448 +++++++++++-
 lib/intel_batchbuffer.c     |   23 +-
 lib/intel_batchbuffer.h     |   31 +
 lib/intel_bufops.h          |   15 +
 lib/intel_reg.h             |    9 +
 lib/ioctl_wrappers.c        |   33 +
 lib/ioctl_wrappers.h        |    2 +
 lib/rendercopy_gen9.c       |   72 +-
 tests/i915/gem_pxp.c        | 1325 +++++++++++++++++++++++++++++++++++
 tests/meson.build           |    1 +
 10 files changed, 1916 insertions(+), 43 deletions(-)
 create mode 100644 tests/i915/gem_pxp.c

-- 
2.25.1

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