From: Catalin Marinas <catalin.marinas@arm.com>
To: psodagud@codeaurora.org
Cc: will@kernel.org, Dave.Martin@arm.com, amit.kachhap@arm.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Mark Brown <broonie@kernel.org>
Subject: Re: sve_user_discard
Date: Fri, 21 May 2021 10:12:54 +0100 [thread overview]
Message-ID: <20210521091254.GA6675@arm.com> (raw)
In-Reply-To: <785d7bc29da6bff0dceeb712c24601fd@codeaurora.org>
On Thu, May 20, 2021 at 04:02:03PM -0700, psodagud@codeaurora.org wrote:
> This is regarding sve_user_disable(CPACR_EL1_ZEN_EL0EN) on every system
> call. If a userspace task is using SVE instructions and making sys calls in
> between, it would impact the performance of the thread. On every SVE
> instructions after SVC/system call, it would trap to EL1.
>
> I think by setting CPACR_EL1_ZEN_EL0EN flag, the processor faults when it
> runs an SVE instruction. This approach may be taken as part of FPSIMD
> registers switching optimizations. Can below portion of the code use
> thread.fpsimd_cpu and fpsimd_last_state variables to avoid clearing
> CPACR_EL1_ZEN_EL0EN for this kind of use cases?
There were attempts over the past couple of years to optimise the
syscall return use-case. I think the latest is this one:
https://lore.kernel.org/r/20201106193553.22946-2-broonie@kernel.org
I'll let Mark comment on his plans for reviving the series. Do you
happen to have some realistic workload that would be improved by this?
We can always write a micro-benchmark but I wonder how much this matters
in the real world.
--
Catalin
WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com>
To: psodagud@codeaurora.org
Cc: will@kernel.org, Dave.Martin@arm.com, amit.kachhap@arm.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Mark Brown <broonie@kernel.org>
Subject: Re: sve_user_discard
Date: Fri, 21 May 2021 10:12:54 +0100 [thread overview]
Message-ID: <20210521091254.GA6675@arm.com> (raw)
In-Reply-To: <785d7bc29da6bff0dceeb712c24601fd@codeaurora.org>
On Thu, May 20, 2021 at 04:02:03PM -0700, psodagud@codeaurora.org wrote:
> This is regarding sve_user_disable(CPACR_EL1_ZEN_EL0EN) on every system
> call. If a userspace task is using SVE instructions and making sys calls in
> between, it would impact the performance of the thread. On every SVE
> instructions after SVC/system call, it would trap to EL1.
>
> I think by setting CPACR_EL1_ZEN_EL0EN flag, the processor faults when it
> runs an SVE instruction. This approach may be taken as part of FPSIMD
> registers switching optimizations. Can below portion of the code use
> thread.fpsimd_cpu and fpsimd_last_state variables to avoid clearing
> CPACR_EL1_ZEN_EL0EN for this kind of use cases?
There were attempts over the past couple of years to optimise the
syscall return use-case. I think the latest is this one:
https://lore.kernel.org/r/20201106193553.22946-2-broonie@kernel.org
I'll let Mark comment on his plans for reviving the series. Do you
happen to have some realistic workload that would be improved by this?
We can always write a micro-benchmark but I wonder how much this matters
in the real world.
--
Catalin
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next prev parent reply other threads:[~2021-05-21 9:13 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-20 23:02 sve_user_discard psodagud
2021-05-21 9:12 ` Catalin Marinas [this message]
2021-05-21 9:12 ` sve_user_discard Catalin Marinas
2021-05-21 11:54 ` sve_user_discard Mark Brown
2021-05-21 11:54 ` sve_user_discard Mark Brown
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