* [PATCH v2 1/4] docs: add a table showing x86-64 ABI compatibility levels
2021-05-26 14:40 [PATCH v2 0/4] target/i386/cpu: introduce new CPU models for x86-64 ABI levels Daniel P. Berrangé
@ 2021-05-26 14:40 ` Daniel P. Berrangé
2021-05-26 14:40 ` [PATCH v2 2/4] target/i386: define CPU models to model x86-64 ABI levels Daniel P. Berrangé
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Daniel P. Berrangé @ 2021-05-26 14:40 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel P. Berrangé,
Eduardo Habkost, Michael S. Tsirkin, Richard Henderson,
Cleber Rosa, Paolo Bonzini
It is useful to know which CPUs satisfy each x86-64 ABI
compatibility level, when dealing with guest OS that require
something newer than the baseline ABI.
These ABI levels are defined in:
https://gitlab.com/x86-psABIs/x86-64-ABI/
and supported by GCC, Clang, glibc and more.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
---
MAINTAINERS | 2 +-
docs/system/cpu-models-x86-abi.csv | 67 ++++++++++++++++++++++++++++++
docs/system/cpu-models-x86.rst.inc | 22 ++++++++++
3 files changed, 90 insertions(+), 1 deletion(-)
create mode 100644 docs/system/cpu-models-x86-abi.csv
diff --git a/MAINTAINERS b/MAINTAINERS
index 75e0f2d750..ed9c361ec1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -329,7 +329,7 @@ F: tests/tcg/i386/
F: tests/tcg/x86_64/
F: hw/i386/
F: disas/i386.c
-F: docs/system/cpu-models-x86.rst.inc
+F: docs/system/cpu-models-x86*
T: git https://gitlab.com/ehabkost/qemu.git x86-next
Xtensa TCG CPUs
diff --git a/docs/system/cpu-models-x86-abi.csv b/docs/system/cpu-models-x86-abi.csv
new file mode 100644
index 0000000000..f3f3b60be1
--- /dev/null
+++ b/docs/system/cpu-models-x86-abi.csv
@@ -0,0 +1,67 @@
+Model,baseline,v2,v3,v4
+486-v1,,,,
+Broadwell-v1,✅,✅,✅,
+Broadwell-v2,✅,✅,✅,
+Broadwell-v3,✅,✅,✅,
+Broadwell-v4,✅,✅,✅,
+Cascadelake-Server-v1,✅,✅,✅,✅
+Cascadelake-Server-v2,✅,✅,✅,✅
+Cascadelake-Server-v3,✅,✅,✅,✅
+Cascadelake-Server-v4,✅,✅,✅,✅
+Conroe-v1,✅,,,
+Cooperlake-v1,✅,✅,✅,✅
+Denverton-v1,✅,✅,,
+Denverton-v2,✅,✅,,
+Dhyana-v1,✅,✅,✅,
+EPYC-Milan-v1,✅,✅,✅,
+EPYC-Rome-v1,✅,✅,✅,
+EPYC-Rome-v2,✅,✅,✅,
+EPYC-v1,✅,✅,✅,
+EPYC-v2,✅,✅,✅,
+EPYC-v3,✅,✅,✅,
+Haswell-v1,✅,✅,✅,
+Haswell-v2,✅,✅,✅,
+Haswell-v3,✅,✅,✅,
+Haswell-v4,✅,✅,✅,
+Icelake-Client-v1,✅,✅,✅,
+Icelake-Client-v2,✅,✅,✅,
+Icelake-Server-v1,✅,✅,✅,✅
+Icelake-Server-v2,✅,✅,✅,✅
+Icelake-Server-v3,✅,✅,✅,✅
+Icelake-Server-v4,✅,✅,✅,✅
+IvyBridge-v1,✅,✅,,
+IvyBridge-v2,✅,✅,,
+KnightsMill-v1,✅,✅,✅,
+Nehalem-v1,✅,✅,,
+Nehalem-v2,✅,✅,,
+Opteron_G1-v1,✅,,,
+Opteron_G2-v1,✅,,,
+Opteron_G3-v1,✅,,,
+Opteron_G4-v1,✅,✅,,
+Opteron_G5-v1,✅,✅,,
+Penryn-v1,✅,,,
+SandyBridge-v1,✅,✅,,
+SandyBridge-v2,✅,✅,,
+Skylake-Client-v1,✅,✅,✅,
+Skylake-Client-v2,✅,✅,✅,
+Skylake-Client-v3,✅,✅,✅,
+Skylake-Server-v1,✅,✅,✅,✅
+Skylake-Server-v2,✅,✅,✅,✅
+Skylake-Server-v3,✅,✅,✅,✅
+Skylake-Server-v4,✅,✅,✅,✅
+Snowridge-v1,✅,✅,,
+Snowridge-v2,✅,✅,,
+Westmere-v1,✅,✅,,
+Westmere-v2,✅,✅,,
+athlon-v1,,,,
+core2duo-v1,✅,,,
+coreduo-v1,,,,
+kvm32-v1,,,,
+kvm64-v1,✅,,,
+n270-v1,,,,
+pentium-v1,,,,
+pentium2-v1,,,,
+pentium3-v1,,,,
+phenom-v1,✅,,,
+qemu32-v1,,,,
+qemu64-v1,✅,,,
diff --git a/docs/system/cpu-models-x86.rst.inc b/docs/system/cpu-models-x86.rst.inc
index 867c8216b5..f40ee03ecc 100644
--- a/docs/system/cpu-models-x86.rst.inc
+++ b/docs/system/cpu-models-x86.rst.inc
@@ -39,6 +39,28 @@ CPU, as they would with "Host passthrough", but gives much of the
benefit of passthrough, while making live migration safe.
+ABI compatibility levels for CPU models
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The x86_64 architecture has a number of `ABI compatibility levels`_
+defined. Traditionally most operating systems and toolchains would
+only target the original baseline ABI. It is expected that in
+future OS and toolchains are likely to target newer ABIs. The
+table that follows illustrates which ABI compatibility levels
+can be satisfied by the QEMU CPU models. Note that the table only
+lists the long term stable CPU model versions (eg Haswell-v4).
+In addition to whats listed, there are also many CPU model
+aliases which resolve to a different CPU model version,
+depending on the machine type is in use.
+
+.. _ABI compatibility levels: https://gitlab.com/x86-psABIs/x86-64-ABI/
+
+.. csv-table:: x86-64 ABI compatibility levels
+ :file: cpu-models-x86-abi.csv
+ :widths: 40,15,15,15,15
+ :header-rows: 2
+
+
Preferred CPU models for Intel x86 hosts
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
--
2.31.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 2/4] target/i386: define CPU models to model x86-64 ABI levels
2021-05-26 14:40 [PATCH v2 0/4] target/i386/cpu: introduce new CPU models for x86-64 ABI levels Daniel P. Berrangé
2021-05-26 14:40 ` [PATCH v2 1/4] docs: add a table showing x86-64 ABI compatibility levels Daniel P. Berrangé
@ 2021-05-26 14:40 ` Daniel P. Berrangé
2021-05-26 14:40 ` [PATCH v2 3/4] scripts: helper to generate x86_64 CPU ABI compat info Daniel P. Berrangé
2021-05-26 14:40 ` [PATCH v2 4/4] NOT FOR MERGE target/i386: use x86-64-abi1 CPU model as default on x86_64 Daniel P. Berrangé
3 siblings, 0 replies; 5+ messages in thread
From: Daniel P. Berrangé @ 2021-05-26 14:40 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel P. Berrangé,
Eduardo Habkost, Michael S. Tsirkin, Richard Henderson,
Cleber Rosa, Paolo Bonzini
To paraphrase:
https://developers.redhat.com/blog/2021/01/05/building-red-hat-enterprise-linux-9-for-the-x86-64-v2-microarchitecture-level/
In 2020, AMD, Intel, Red Hat, and SUSE worked together to define
three microarchitecture levels on top of the historical x86-64
baseline:
* x86-64: original x86_64 baseline instruction set
* x86-64-v2: vector instructions up to Streaming SIMD
Extensions 4.2 (SSE4.2) and Supplemental
Streaming SIMD Extensions 3 (SSSE3), the
POPCNT instruction, and CMPXCHG16B
* x86-64-v3: vector instructions up to AVX2, MOVBE,
and additional bit-manipulation instructions.
* x86-64-v4: vector instructions from some of the
AVX-512 variants.
This list of features is defined in the doc at:
https://gitlab.com/x86-psABIs/x86-64-ABI/
QEMU has historically defaulted to the "qemu64" CPU model on
x86_64 targets, which is approximately the x86-64 baseline
ABI, with 'SVM' added.
It is thought it might be desirable if QEMU could provide CPU models
that closely correspond to the ABI levels, while offering portability
across the maximum number of physical CPUs.
Historically we've found that defining CPU models with an arbitrary
combination of CPU features can be problematic, as some guest OS
will not check all features they use, and instead assume that if
they see feature "XX", then "YY" will always exist. This is reasonable
in bare metal, but subject to breakage in virtualization.
Thus in defining the CPU models for the ABI levels, this patch attempted
to base them off an existing CPU model.
While each x86-64-abiNNN has a designated vendor, they are designed
to be vendor agnostic models. ie they are capable of running on any
physical x86_64 CPU model that satisfies the ABI level. eg although
the x86-64-abi2 model is based on Nehalem, it should be able to run
guests on an Opteron_G4/G5/EPYC host, since those CPUs support the
features required by the x86-64 v2 ABI.
More precisely the models were defined as:
* x86-64-abi1: close match for Opteron_G1, minus
vme
* x86-64-abi2: perfect match for Nehalem
* x86-64-abi3: close match of Haswell-noTSX, minus
aes pcid erms invpcid tsc-deadline
x2apic pclmulqdq
* x86-64-abi4: close match of Skylake-Server-noTSX-IBRS, minus
spec-ctrl
None of the CPU models declare any VMX/SVM capability features.
IOW, even if a "vmx"/"svm" flag is added, it will still be unsafe
to attempt to live migrate the L1 guest if there are any L2
guests running with hardware virtualization.
Given their vendor agnostic design, these CPU models are primarily
thought tobe useful as the default CPU model for machine types.
QEMU upstream is quite conservative in mandating new hardware features,
but a downstream vendor may choose to mandate a newer x86-64 ABI level
for downstream only machine types.
Note that TCG is not capable of supporting the 2 newest ABI levels
currently due to missing features:
* x86-64-abi3:
CPUID.01H:ECX.fma [bit 12]
CPUID.01H:ECX.avx [bit 28]
CPUID.01H:ECX.f16c [bit 29]
CPUID.07H:EBX.avx2 [bit 5]
* x86-64-abi4:
CPUID.01H:ECX.pcid [bit 17]
CPUID.01H:ECX.x2apic [bit 21]
CPUID.01H:ECX.tsc-deadline [bit 24]
CPUID.07H:EBX.invpcid [bit 10]
CPUID.07H:EBX.avx512f [bit 16]
CPUID.07H:EBX.avx512dq [bit 17]
CPUID.07H:EBX.rdseed [bit 18]
CPUID.07H:EBX.avx512cd [bit 28]
CPUID.07H:EBX.avx512bw [bit 30]
CPUID.07H:EBX.avx512vl [bit 31]
CPUID.80000001H:ECX.3dnowprefetch [bit 8]
CPUID.0DH:EAX.xsavec [bit 1]
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
---
docs/system/cpu-models-x86-abi.csv | 8 ++
target/i386/cpu.c | 156 +++++++++++++++++++++++++++++
2 files changed, 164 insertions(+)
diff --git a/docs/system/cpu-models-x86-abi.csv b/docs/system/cpu-models-x86-abi.csv
index f3f3b60be1..3392c39753 100644
--- a/docs/system/cpu-models-x86-abi.csv
+++ b/docs/system/cpu-models-x86-abi.csv
@@ -65,3 +65,11 @@ pentium3-v1,,,,
phenom-v1,✅,,,
qemu32-v1,,,,
qemu64-v1,✅,,,
+x86-64-abi1,✅,,,
+x86-64-abi1-v1,✅,,,
+x86-64-abi2,✅,✅,,
+x86-64-abi2-v1,✅,✅,,
+x86-64-abi3,✅,✅,✅,
+x86-64-abi3-v1,✅,✅,✅,
+x86-64-abi4,✅,✅,✅,✅
+x86-64-abi4-v1,✅,✅,✅,✅
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index c496bfa1c2..e6609e278a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1798,6 +1798,162 @@ static CPUCaches epyc_milan_cache_info = {
*/
static X86CPUDefinition builtin_x86_defs[] = {
+ /*
+ * These first few CPU models are designed to satisfy the
+ * x86_64 ABI levels defined in:
+ *
+ * https://gitlab.com/x86-psABIs/x86-64-ABI/
+ *
+ * They were constructed as follows:
+ *
+ * - Find all the CPU models which can satisfy the ABI
+ * - Calculate the lowest common denominator (LCD) of these
+ * models' features
+ * - Find the named model most closely matching the LCD
+ * - Strip its features back to the LCD
+ *
+ * The above spec uses the "x86-64-vNN" naming convention.
+ * This clashes with the "vNN" suffix QEMU uses for versioning.
+ * Thus we use "abiNNN" as a suffix.
+ */
+ {
+ /*
+ * Derived from Opteron_G1, minus
+ * vme
+ */
+ .name = "x86-64-abi1",
+ .level = 5,
+ .vendor = CPUID_VENDOR_AMD,
+ .family = 15,
+ .model = 6,
+ .stepping = 1,
+ .features[FEAT_1_EDX] =
+ CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+ CPUID_DE | CPUID_FP87,
+ .features[FEAT_1_ECX] =
+ CPUID_EXT_SSE3,
+ .features[FEAT_8000_0001_EDX] =
+ CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
+ .xlevel = 0x80000008,
+ .model_id = "QEMU x86-64 baseline ABI",
+ },
+ {
+ /* Derived from Nehalem */
+ .name = "x86-64-abi2",
+ .level = 11,
+ .vendor = CPUID_VENDOR_INTEL,
+ .family = 6,
+ .model = 26,
+ .stepping = 3,
+ .features[FEAT_1_EDX] =
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+ CPUID_DE | CPUID_FP87,
+ .features[FEAT_1_ECX] =
+ CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
+ CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
+ .features[FEAT_8000_0001_EDX] =
+ CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
+ .features[FEAT_8000_0001_ECX] =
+ CPUID_EXT3_LAHF_LM,
+ .xlevel = 0x80000008,
+ .model_id = "QEMU x86-64-v2 ABI",
+ },
+ {
+ /*
+ * Derived from Haswell-noTSX, minus
+ * aes pcid erms invpcid tsc-deadline x2apic pclmulqdq
+ */
+ .name = "x86-64-abi3",
+ .level = 0xd,
+ .vendor = CPUID_VENDOR_INTEL,
+ .family = 6,
+ .model = 60,
+ .stepping = 1,
+ .features[FEAT_1_EDX] =
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+ CPUID_DE | CPUID_FP87,
+ .features[FEAT_1_ECX] =
+ CPUID_EXT_AVX | CPUID_EXT_XSAVE |
+ CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
+ CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
+ CPUID_EXT_SSE3 |
+ CPUID_EXT_FMA | CPUID_EXT_MOVBE |
+ CPUID_EXT_F16C | CPUID_EXT_RDRAND,
+ .features[FEAT_8000_0001_EDX] =
+ CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
+ CPUID_EXT2_SYSCALL,
+ .features[FEAT_8000_0001_ECX] =
+ CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
+ .features[FEAT_7_0_EBX] =
+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
+ CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
+ CPUID_7_0_EBX_BMI2,
+ .features[FEAT_XSAVE] =
+ CPUID_XSAVE_XSAVEOPT,
+ .features[FEAT_6_EAX] =
+ CPUID_6_EAX_ARAT,
+ .xlevel = 0x80000008,
+ .model_id = "QEMU x86-64-v3 ABI",
+ },
+
+ {
+ /*
+ * Derived from Skylake-Server-noTSX-IBRS, minus:
+ * spec-ctrl
+ */
+ .name = "x86-64-abi4",
+ .level = 0xd,
+ .vendor = CPUID_VENDOR_INTEL,
+ .family = 6,
+ .model = 85,
+ .stepping = 4,
+ .features[FEAT_1_EDX] =
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+ CPUID_DE | CPUID_FP87,
+ .features[FEAT_1_ECX] =
+ CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
+ CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
+ CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
+ CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
+ CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
+ CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
+ .features[FEAT_8000_0001_EDX] =
+ CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
+ CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
+ .features[FEAT_8000_0001_ECX] =
+ CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
+ .features[FEAT_7_0_EBX] =
+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
+ CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
+ CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
+ CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
+ CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
+ CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
+ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
+ CPUID_7_0_EBX_AVX512VL,
+ .features[FEAT_7_0_ECX] =
+ CPUID_7_0_ECX_PKU,
+ .features[FEAT_XSAVE] =
+ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+ CPUID_XSAVE_XGETBV1,
+ .features[FEAT_6_EAX] =
+ CPUID_6_EAX_ARAT,
+ .xlevel = 0x80000008,
+ .model_id = "QEMU x86-64-v4 ABI",
+ },
+
{
.name = "qemu64",
.level = 0xd,
--
2.31.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 3/4] scripts: helper to generate x86_64 CPU ABI compat info
2021-05-26 14:40 [PATCH v2 0/4] target/i386/cpu: introduce new CPU models for x86-64 ABI levels Daniel P. Berrangé
2021-05-26 14:40 ` [PATCH v2 1/4] docs: add a table showing x86-64 ABI compatibility levels Daniel P. Berrangé
2021-05-26 14:40 ` [PATCH v2 2/4] target/i386: define CPU models to model x86-64 ABI levels Daniel P. Berrangé
@ 2021-05-26 14:40 ` Daniel P. Berrangé
2021-05-26 14:40 ` [PATCH v2 4/4] NOT FOR MERGE target/i386: use x86-64-abi1 CPU model as default on x86_64 Daniel P. Berrangé
3 siblings, 0 replies; 5+ messages in thread
From: Daniel P. Berrangé @ 2021-05-26 14:40 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel P. Berrangé,
Eduardo Habkost, Michael S. Tsirkin, Richard Henderson,
Cleber Rosa, Paolo Bonzini
This script is what is used to generate the docs data table in:
docs/system/cpu-models-x86-abi.csv
It can be useful to run if adding new CPU models / versions and
the csv needs updating.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
---
scripts/cpu-x86-uarch-abi.py | 194 +++++++++++++++++++++++++++++++++++
1 file changed, 194 insertions(+)
create mode 100644 scripts/cpu-x86-uarch-abi.py
diff --git a/scripts/cpu-x86-uarch-abi.py b/scripts/cpu-x86-uarch-abi.py
new file mode 100644
index 0000000000..08acc52a81
--- /dev/null
+++ b/scripts/cpu-x86-uarch-abi.py
@@ -0,0 +1,194 @@
+#!/usr/bin/python3
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# A script to generate a CSV file showing the x86_64 ABI
+# compatibility levels for each CPU model.
+#
+
+from qemu import qmp
+import sys
+
+if len(sys.argv) != 1:
+ print("syntax: %s QMP-SOCK\n\n" % __file__ +
+ "Where QMP-SOCK points to a QEMU process such as\n\n" +
+ " # qemu-system-x86_64 -qmp unix:/tmp/qmp,server,nowait " +
+ "-display none -accel kvm", file=sys.stderr)
+ sys.exit(1)
+
+# Mandatory CPUID features for each microarch ABI level
+levels = [
+ [ # x86-64 baseline
+ "cmov",
+ "cx8",
+ "fpu",
+ "fxsr",
+ "mmx",
+ "syscall",
+ "sse",
+ "sse2",
+ ],
+ [ # x86-64-v2
+ "cx16",
+ "lahf-lm",
+ "popcnt",
+ "pni",
+ "sse4.1",
+ "sse4.2",
+ "ssse3",
+ ],
+ [ # x86-64-v3
+ "avx",
+ "avx2",
+ "bmi1",
+ "bmi2",
+ "f16c",
+ "fma",
+ "abm",
+ "movbe",
+ ],
+ [ # x86-64-v4
+ "avx512f",
+ "avx512bw",
+ "avx512cd",
+ "avx512dq",
+ "avx512vl",
+ ],
+]
+
+# Assumes externally launched process such as
+#
+# qemu-system-x86_64 -qmp unix:/tmp/qmp,server,nowait -display none -accel kvm
+#
+# Note different results will be obtained with TCG, as
+# TCG masks out certain features otherwise present in
+# the CPU model definitions, as does KVM.
+
+
+sock = sys.argv[1]
+cmd = sys.argv[2]
+shell = qmp.QEMUMonitorProtocol(sock)
+shell.connect()
+
+models = shell.cmd("query-cpu-definitions")
+
+# These QMP props don't correspond to CPUID fatures
+# so ignore them
+skip = [
+ "family",
+ "min-level",
+ "min-xlevel",
+ "vendor",
+ "model",
+ "model-id",
+ "stepping",
+]
+
+names = []
+
+for model in models["return"]:
+ if "alias-of" in model:
+ continue
+ names.append(model["name"])
+
+models = {}
+
+for name in sorted(names):
+ cpu = shell.cmd("query-cpu-model-expansion",
+ { "type": "static",
+ "model": { "name": name }})
+
+ got = {}
+ for (feature, present) in cpu["return"]["model"]["props"].items():
+ if present and feature not in skip:
+ got[feature] = True
+
+ if name in ["host", "max", "base"]:
+ continue
+
+ models[name] = {
+ # Dict of all present features in this CPU model
+ "features": got,
+
+ # Whether each x86-64 ABI level is satisfied
+ "levels": [False, False, False, False],
+
+ # Number of extra CPUID features compared to the x86-64 ABI level
+ "distance":[-1, -1, -1, -1],
+
+ # CPUID features present in model, but not in ABI level
+ "delta":[[], [], [], []],
+
+ # CPUID features in ABI level but not present in model
+ "missing": [[], [], [], []],
+ }
+
+
+# Calculate whether the CPU models satisfy each ABI level
+for name in models.keys():
+ for level in range(len(levels)):
+ got = set(models[name]["features"])
+ want = set(levels[level])
+ missing = want - got
+ match = True
+ if len(missing) > 0:
+ match = False
+ models[name]["levels"][level] = match
+ models[name]["missing"][level] = missing
+
+# Cache list of CPU models satisfying each ABI level
+abi_models = [
+ [],
+ [],
+ [],
+ [],
+]
+
+for name in models.keys():
+ for level in range(len(levels)):
+ if models[name]["levels"][level]:
+ abi_models[level].append(name)
+
+
+for level in range(len(abi_models)):
+ # Find the union of features in all CPU models satisfying this ABI
+ allfeatures = {}
+ for name in abi_models[level]:
+ for feat in models[name]["features"]:
+ allfeatures[feat] = True
+
+ # Find the intersection of features in all CPU models satisfying this ABI
+ commonfeatures = []
+ for feat in allfeatures:
+ present = True
+ for name in models.keys():
+ if not models[name]["levels"][level]:
+ continue
+ if feat not in models[name]["features"]:
+ present = False
+ if present:
+ commonfeatures.append(feat)
+
+ # Determine how many extra features are present compared to the lowest
+ # common denominator
+ for name in models.keys():
+ if not models[name]["levels"][level]:
+ continue
+
+ delta = set(models[name]["features"].keys()) - set(commonfeatures)
+ models[name]["distance"][level] = len(delta)
+ models[name]["delta"][level] = delta
+
+def print_uarch_abi_csv():
+ print("# Automatically generated from '%s'" % __file__)
+ print("Model,baseline,v2,v3,v4")
+ for name in models.keys():
+ print(name, end="")
+ for level in range(len(levels)):
+ if models[name]["levels"][level]:
+ print(",✅", end="")
+ else:
+ print(",", end="")
+ print()
+
+print_uarch_abi_csv()
--
2.31.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 4/4] NOT FOR MERGE target/i386: use x86-64-abi1 CPU model as default on x86_64
2021-05-26 14:40 [PATCH v2 0/4] target/i386/cpu: introduce new CPU models for x86-64 ABI levels Daniel P. Berrangé
` (2 preceding siblings ...)
2021-05-26 14:40 ` [PATCH v2 3/4] scripts: helper to generate x86_64 CPU ABI compat info Daniel P. Berrangé
@ 2021-05-26 14:40 ` Daniel P. Berrangé
3 siblings, 0 replies; 5+ messages in thread
From: Daniel P. Berrangé @ 2021-05-26 14:40 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel P. Berrangé,
Eduardo Habkost, Michael S. Tsirkin, Richard Henderson,
Cleber Rosa, Paolo Bonzini
The only differences between x86-64-abi1 and qemu64 is that the former
does not have the 'vme' or 'svm' flags.
In practice I don't think we should make this change, because it doesn't
especially add any value as-is. The only possible case is around 'svm'
because KVM already masks that feature, but TCG allows it. Thus using
x86-64-abi1 would mean that KVM and TCG expose a more consistent feature
set.
Also note that while libvirt can cope with default CPUs changing now,
it can't with the default CPU being a model name that it does not
already know about.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
---
hw/i386/pc_piix.c | 3 +++
hw/i386/pc_q35.c | 3 +++
target/i386/cpu.h | 2 +-
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 30b8bd6ea9..8f23bad647 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -444,6 +444,9 @@ static void pc_i440fx_5_2_machine_options(MachineClass *m)
m->is_default = false;
compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len);
compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len);
+#ifdef TARGET_X86_64
+ m->default_cpu_type = X86_CPU_TYPE_NAME("qemu64");
+#endif
}
DEFINE_I440FX_MACHINE(v5_2, "pc-i440fx-5.2", NULL,
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 46a0f196f4..a684c1db3b 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -372,6 +372,9 @@ static void pc_q35_5_2_machine_options(MachineClass *m)
m->alias = NULL;
compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len);
compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len);
+#ifdef TARGET_X86_64
+ m->default_cpu_type = X86_CPU_TYPE_NAME("qemu64");
+#endif
}
DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e6836393f7..e655a17f02 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2001,7 +2001,7 @@ uint64_t cpu_get_tsc(CPUX86State *env);
#define CPU_RESOLVING_TYPE TYPE_X86_CPU
#ifdef TARGET_X86_64
-#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
+#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("x86-64-abi1")
#else
#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
#endif
--
2.31.1
^ permalink raw reply related [flat|nested] 5+ messages in thread