* [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL
@ 2021-06-01 14:52 Stanislav Lisovskiy
2021-06-01 20:20 ` Matt Roper
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Stanislav Lisovskiy @ 2021-06-01 14:52 UTC (permalink / raw)
To: intel-gfx
From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
CDCLK crawl feature allows to change CDCLK frequency
without disabling the actual PLL and doesn't require
a full modeset.
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 72 +++++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 2 +
2 files changed, 65 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 618a9e1e2b0c..b9abed82328c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1548,6 +1548,35 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
dev_priv->cdclk.hw.vco = vco;
}
+static bool has_cdclk_crawl(struct drm_i915_private *i915)
+{
+ return IS_ALDERLAKE_P(i915);
+}
+
+static void gen13_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
+{
+ int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+ u32 val;
+
+ /* Write PLL ratio without disabling */
+ val = CNL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
+ intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
+
+ /* Submit freq change request */
+ val |= BXT_DE_PLL_FREQ_REQ;
+ intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
+
+ /* Timeout 200us */
+ if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
+ BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
+ DRM_ERROR("timeout waiting for FREQ change request ack\n");
+
+ val &= ~BXT_DE_PLL_FREQ_REQ;
+ intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
+
+ dev_priv->cdclk.hw.vco = vco;
+}
+
static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
{
if (DISPLAY_VER(dev_priv) >= 12) {
@@ -1620,14 +1649,16 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
return;
}
- if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
+ if (has_cdclk_crawl(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
+ if (dev_priv->cdclk.hw.vco != vco)
+ gen13_cdclk_pll_crawl(dev_priv, vco);
+ } else if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
if (dev_priv->cdclk.hw.vco != 0 &&
dev_priv->cdclk.hw.vco != vco)
cnl_cdclk_pll_disable(dev_priv);
if (dev_priv->cdclk.hw.vco != vco)
cnl_cdclk_pll_enable(dev_priv, vco);
-
} else {
if (dev_priv->cdclk.hw.vco != 0 &&
dev_priv->cdclk.hw.vco != vco)
@@ -1820,6 +1851,28 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
skl_cdclk_uninit_hw(i915);
}
+static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_config *a,
+ const struct intel_cdclk_config *b)
+{
+ int a_div, b_div;
+
+ if (!has_cdclk_crawl(dev_priv))
+ return false;
+
+ /*
+ * The vco and cd2x divider will change independently
+ * from each, so we disallow cd2x change when crawling.
+ */
+ a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
+ b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
+
+ return a->vco != 0 && b->vco != 0 &&
+ a->vco != b->vco &&
+ a_div == b_div &&
+ a->ref == b->ref;
+}
+
/**
* intel_cdclk_needs_modeset - Determine if changong between the CDCLK
* configurations requires a modeset on all pipes
@@ -2475,7 +2528,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
const struct intel_cdclk_state *old_cdclk_state;
struct intel_cdclk_state *new_cdclk_state;
- enum pipe pipe;
+ enum pipe pipe = INVALID_PIPE;
int ret;
new_cdclk_state = intel_atomic_get_cdclk_state(state);
@@ -2527,15 +2580,18 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
pipe = INVALID_PIPE;
- } else {
- pipe = INVALID_PIPE;
}
- if (pipe != INVALID_PIPE) {
+ if (intel_cdclk_can_crawl(dev_priv,
+ &old_cdclk_state->actual,
+ &new_cdclk_state->actual)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Can change cdclk via crawl\n");
+ } else if (pipe != INVALID_PIPE) {
new_cdclk_state->pipe = pipe;
drm_dbg_kms(&dev_priv->drm,
- "Can change cdclk with pipe %c active\n",
+ "Can change cdclk cd2x divider with pipe %c active\n",
pipe_name(pipe));
} else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
&new_cdclk_state->actual)) {
@@ -2544,8 +2600,6 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
if (ret)
return ret;
- new_cdclk_state->pipe = INVALID_PIPE;
-
drm_dbg_kms(&dev_priv->drm,
"Modeset required for cdclk change\n");
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3b58067a873c..1d1176d1799d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11157,6 +11157,8 @@ enum skl_power_gate {
#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
#define BXT_DE_PLL_LOCK (1 << 30)
+#define BXT_DE_PLL_FREQ_REQ (1 << 23)
+#define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
#define CNL_CDCLK_PLL_RATIO(x) (x)
#define CNL_CDCLK_PLL_RATIO_MASK 0xff
--
2.24.1.485.gad05a3d8e5
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL
2021-06-01 14:52 [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL Stanislav Lisovskiy
@ 2021-06-01 20:20 ` Matt Roper
2021-06-01 22:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-06-02 9:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2 siblings, 0 replies; 7+ messages in thread
From: Matt Roper @ 2021-06-01 20:20 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Tue, Jun 01, 2021 at 05:52:48PM +0300, Stanislav Lisovskiy wrote:
> From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Aren't you (Stan) the original author of this patch? It looks like the
authorship got changed accidentally in one of the preparation rebases.
A couple other quick drive-by comments below.
>
> CDCLK crawl feature allows to change CDCLK frequency
> without disabling the actual PLL and doesn't require
> a full modeset.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 72 +++++++++++++++++++---
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> 2 files changed, 65 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 618a9e1e2b0c..b9abed82328c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1548,6 +1548,35 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
> dev_priv->cdclk.hw.vco = vco;
> }
>
> +static bool has_cdclk_crawl(struct drm_i915_private *i915)
> +{
> + return IS_ALDERLAKE_P(i915);
> +}
Would it make sense to make this a feature flag in the device info
structure?
> +
> +static void gen13_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
Function name prefix should either be "adlp" or "xelpd." Probably
"adlp" in this case since I think this functionality relates more to the
platform itself than the display architecture version.
Matt
> +{
> + int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
> + u32 val;
> +
> + /* Write PLL ratio without disabling */
> + val = CNL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
> + intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
> +
> + /* Submit freq change request */
> + val |= BXT_DE_PLL_FREQ_REQ;
> + intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
> +
> + /* Timeout 200us */
> + if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
> + BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
> + DRM_ERROR("timeout waiting for FREQ change request ack\n");
> +
> + val &= ~BXT_DE_PLL_FREQ_REQ;
> + intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
> +
> + dev_priv->cdclk.hw.vco = vco;
> +}
> +
> static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> {
> if (DISPLAY_VER(dev_priv) >= 12) {
> @@ -1620,14 +1649,16 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> return;
> }
>
> - if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
> + if (has_cdclk_crawl(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
> + if (dev_priv->cdclk.hw.vco != vco)
> + gen13_cdclk_pll_crawl(dev_priv, vco);
> + } else if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
> if (dev_priv->cdclk.hw.vco != 0 &&
> dev_priv->cdclk.hw.vco != vco)
> cnl_cdclk_pll_disable(dev_priv);
>
> if (dev_priv->cdclk.hw.vco != vco)
> cnl_cdclk_pll_enable(dev_priv, vco);
> -
> } else {
> if (dev_priv->cdclk.hw.vco != 0 &&
> dev_priv->cdclk.hw.vco != vco)
> @@ -1820,6 +1851,28 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
> skl_cdclk_uninit_hw(i915);
> }
>
> +static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
> + const struct intel_cdclk_config *a,
> + const struct intel_cdclk_config *b)
> +{
> + int a_div, b_div;
> +
> + if (!has_cdclk_crawl(dev_priv))
> + return false;
> +
> + /*
> + * The vco and cd2x divider will change independently
> + * from each, so we disallow cd2x change when crawling.
> + */
> + a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
> + b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
> +
> + return a->vco != 0 && b->vco != 0 &&
> + a->vco != b->vco &&
> + a_div == b_div &&
> + a->ref == b->ref;
> +}
> +
> /**
> * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
> * configurations requires a modeset on all pipes
> @@ -2475,7 +2528,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> const struct intel_cdclk_state *old_cdclk_state;
> struct intel_cdclk_state *new_cdclk_state;
> - enum pipe pipe;
> + enum pipe pipe = INVALID_PIPE;
> int ret;
>
> new_cdclk_state = intel_atomic_get_cdclk_state(state);
> @@ -2527,15 +2580,18 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
>
> if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
> pipe = INVALID_PIPE;
> - } else {
> - pipe = INVALID_PIPE;
> }
>
> - if (pipe != INVALID_PIPE) {
> + if (intel_cdclk_can_crawl(dev_priv,
> + &old_cdclk_state->actual,
> + &new_cdclk_state->actual)) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Can change cdclk via crawl\n");
> + } else if (pipe != INVALID_PIPE) {
> new_cdclk_state->pipe = pipe;
>
> drm_dbg_kms(&dev_priv->drm,
> - "Can change cdclk with pipe %c active\n",
> + "Can change cdclk cd2x divider with pipe %c active\n",
> pipe_name(pipe));
> } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
> &new_cdclk_state->actual)) {
> @@ -2544,8 +2600,6 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> if (ret)
> return ret;
>
> - new_cdclk_state->pipe = INVALID_PIPE;
> -
> drm_dbg_kms(&dev_priv->drm,
> "Modeset required for cdclk change\n");
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3b58067a873c..1d1176d1799d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11157,6 +11157,8 @@ enum skl_power_gate {
> #define BXT_DE_PLL_ENABLE _MMIO(0x46070)
> #define BXT_DE_PLL_PLL_ENABLE (1 << 31)
> #define BXT_DE_PLL_LOCK (1 << 30)
> +#define BXT_DE_PLL_FREQ_REQ (1 << 23)
> +#define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
> #define CNL_CDCLK_PLL_RATIO(x) (x)
> #define CNL_CDCLK_PLL_RATIO_MASK 0xff
>
> --
> 2.24.1.485.gad05a3d8e5
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adl_p: CDCLK crawl support for ADL
2021-06-01 14:52 [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL Stanislav Lisovskiy
2021-06-01 20:20 ` Matt Roper
@ 2021-06-01 22:38 ` Patchwork
2021-06-02 9:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2021-06-01 22:38 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 5107 bytes --]
== Series Details ==
Series: drm/i915/adl_p: CDCLK crawl support for ADL
URL : https://patchwork.freedesktop.org/series/90842/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10156 -> Patchwork_20260
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/index.html
Known issues
------------
Here are the changes found in Patchwork_20260 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_heartbeat:
- fi-cml-s: [PASS][1] -> [DMESG-FAIL][2] ([i915#2291] / [i915#541])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-cml-s/igt@i915_selftest@live@gt_heartbeat.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/fi-cml-s/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_frontbuffer_tracking@basic:
- fi-tgl-u2: [PASS][3] -> [FAIL][4] ([i915#2416])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-tgl-u2/igt@kms_frontbuffer_tracking@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/fi-tgl-u2/igt@kms_frontbuffer_tracking@basic.html
#### Warnings ####
* igt@i915_selftest@live@execlists:
- fi-tgl-u2: [INCOMPLETE][5] ([i915#3462]) -> [DMESG-FAIL][6] ([i915#3462])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-tgl-u2/igt@i915_selftest@live@execlists.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/fi-tgl-u2/igt@i915_selftest@live@execlists.html
* igt@runner@aborted:
- fi-cfl-8700k: [FAIL][7] ([i915#3363]) -> [FAIL][8] ([i915#2426] / [i915#3363])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-cfl-8700k/igt@runner@aborted.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/fi-cfl-8700k/igt@runner@aborted.html
- fi-glk-dsi: [FAIL][9] ([i915#2426] / [i915#3363] / [k.org#202321]) -> [FAIL][10] ([i915#3363] / [k.org#202321])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-glk-dsi/igt@runner@aborted.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/fi-glk-dsi/igt@runner@aborted.html
- fi-kbl-r: [FAIL][11] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][12] ([i915#1436] / [i915#3363])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-r/igt@runner@aborted.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/fi-kbl-r/igt@runner@aborted.html
- fi-bdw-5557u: [FAIL][13] ([i915#3462]) -> [FAIL][14] ([i915#2426] / [i915#3462])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-bdw-5557u/igt@runner@aborted.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/fi-bdw-5557u/igt@runner@aborted.html
- fi-kbl-soraka: [FAIL][15] ([i915#1436] / [i915#3363]) -> [FAIL][16] ([i915#1436] / [i915#2426] / [i915#3363])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-soraka/igt@runner@aborted.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/fi-kbl-soraka/igt@runner@aborted.html
- fi-kbl-7500u: [FAIL][17] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][18] ([i915#1436] / [i915#3363])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-7500u/igt@runner@aborted.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/fi-kbl-7500u/igt@runner@aborted.html
- fi-bxt-dsi: [FAIL][19] ([i915#3363]) -> [FAIL][20] ([i915#2426] / [i915#3363])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-bxt-dsi/igt@runner@aborted.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/fi-bxt-dsi/igt@runner@aborted.html
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2416]: https://gitlab.freedesktop.org/drm/intel/issues/2416
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (47 -> 42)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_10156 -> Patchwork_20260
CI-20190529: 20190529
CI_DRM_10156: 551125c07e42a44a1b4bf8ad735619f2e315a0e2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6098: 1fbc1e7d602f96a7f4e2b95057eef994656b8e74 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20260: 52b739da49bcfa793a2b3e5f320ab8a0d5f04707 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
52b739da49bc drm/i915/adl_p: CDCLK crawl support for ADL
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/index.html
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_______________________________________________
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* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/adl_p: CDCLK crawl support for ADL
2021-06-01 14:52 [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL Stanislav Lisovskiy
2021-06-01 20:20 ` Matt Roper
2021-06-01 22:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
@ 2021-06-02 9:53 ` Patchwork
2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2021-06-02 9:53 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30266 bytes --]
== Series Details ==
Series: drm/i915/adl_p: CDCLK crawl support for ADL
URL : https://patchwork.freedesktop.org/series/90842/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10156_full -> Patchwork_20260_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_20260_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20260_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20260_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rps@reset:
- shard-skl: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl3/igt@i915_pm_rps@reset.html
Known issues
------------
Here are the changes found in Patchwork_20260_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: [PASS][2] -> [DMESG-WARN][3] ([i915#180]) +5 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-kbl2/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_ctx_persistence@legacy-engines-mixed:
- shard-snb: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +2 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-snb2/igt@gem_ctx_persistence@legacy-engines-mixed.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-tglb: [PASS][5] -> [TIMEOUT][6] ([i915#3063])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-tglb3/igt@gem_eio@in-flight-contexts-immediate.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-tglb1/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][7] -> [TIMEOUT][8] ([i915#2369] / [i915#3063])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-tglb3/igt@gem_eio@unwedge-stress.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-tglb8/igt@gem_eio@unwedge-stress.html
- shard-snb: NOTRUN -> [FAIL][9] ([i915#3354])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-snb5/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-glk9/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-kbl: [PASS][12] -> [FAIL][13] ([i915#2842])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-kbl1/igt@gem_exec_fair@basic-none@vecs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-kbl2/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: NOTRUN -> [FAIL][14] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_reloc@basic-wide-active@bcs0:
- shard-glk: NOTRUN -> [FAIL][15] ([i915#2389]) +3 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-glk5/igt@gem_exec_reloc@basic-wide-active@bcs0.html
* igt@gem_exec_reloc@basic-wide-active@rcs0:
- shard-iclb: NOTRUN -> [FAIL][16] ([i915#2389]) +4 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb1/igt@gem_exec_reloc@basic-wide-active@rcs0.html
- shard-kbl: NOTRUN -> [FAIL][17] ([i915#2389]) +4 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-kbl7/igt@gem_exec_reloc@basic-wide-active@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#2190])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl8/igt@gem_huc_copy@huc-copy.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-odd:
- shard-snb: NOTRUN -> [INCOMPLETE][19] ([i915#2055] / [i915#3468]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-snb6/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
* igt@gem_mmap_gtt@cpuset-big-copy:
- shard-iclb: [PASS][20] -> [FAIL][21] ([i915#2428])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-iclb5/igt@gem_mmap_gtt@cpuset-big-copy.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb2/igt@gem_mmap_gtt@cpuset-big-copy.html
* igt@gem_mmap_gtt@fault-concurrent:
- shard-skl: NOTRUN -> [INCOMPLETE][22] ([i915#3468])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl7/igt@gem_mmap_gtt@fault-concurrent.html
* igt@gem_mmap_gtt@fault-concurrent-y:
- shard-skl: NOTRUN -> [INCOMPLETE][23] ([i915#3468] / [i915#3523])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl9/igt@gem_mmap_gtt@fault-concurrent-y.html
- shard-apl: NOTRUN -> [INCOMPLETE][24] ([i915#3468])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-apl1/igt@gem_mmap_gtt@fault-concurrent-y.html
* igt@gem_mmap_gtt@medium-copy-xy:
- shard-kbl: [PASS][25] -> [INCOMPLETE][26] ([i915#2502] / [i915#3468])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-kbl4/igt@gem_mmap_gtt@medium-copy-xy.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-kbl2/igt@gem_mmap_gtt@medium-copy-xy.html
* igt@gem_pwrite@basic-exhaustion:
- shard-skl: NOTRUN -> [WARN][27] ([i915#2658])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl7/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
- shard-glk: NOTRUN -> [SKIP][28] ([fdo#109271]) +78 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-glk8/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@gem_userptr_blits@sync-overlap:
- shard-glk: [PASS][29] -> [DMESG-WARN][30] ([i915#118] / [i915#95])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-glk4/igt@gem_userptr_blits@sync-overlap.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-glk9/igt@gem_userptr_blits@sync-overlap.html
* igt@gen9_exec_parse@allowed-single:
- shard-iclb: NOTRUN -> [SKIP][31] ([fdo#112306])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb8/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@cmd-crossing-page:
- shard-tglb: NOTRUN -> [SKIP][32] ([fdo#112306])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-tglb1/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- shard-iclb: NOTRUN -> [SKIP][33] ([fdo#110892])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb8/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
* igt@i915_selftest@live@execlists:
- shard-skl: NOTRUN -> [INCOMPLETE][34] ([i915#2782] / [i915#3462])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl8/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_pm:
- shard-skl: NOTRUN -> [DMESG-FAIL][35] ([i915#1886] / [i915#2291])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl8/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: NOTRUN -> [INCOMPLETE][36] ([i915#2782])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-snb2/igt@i915_selftest@live@hangcheck.html
* igt@i915_suspend@forcewake:
- shard-apl: [PASS][37] -> [DMESG-WARN][38] ([i915#180])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-apl7/igt@i915_suspend@forcewake.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-apl1/igt@i915_suspend@forcewake.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: NOTRUN -> [DMESG-WARN][39] ([i915#180])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-apl1/igt@i915_suspend@sysfs-reader.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][40] ([fdo#110725] / [fdo#111614])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb1/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][41] ([fdo#111614]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-tglb1/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
- shard-iclb: NOTRUN -> [SKIP][42] ([fdo#110723])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb8/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html
* igt@kms_big_joiner@invalid-modeset:
- shard-iclb: NOTRUN -> [SKIP][43] ([i915#2705])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb1/igt@kms_big_joiner@invalid-modeset.html
- shard-kbl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#2705])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-kbl7/igt@kms_big_joiner@invalid-modeset.html
- shard-glk: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#2705])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-glk5/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_ccs@pipe-c-bad-pixel-format:
- shard-skl: NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111304])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl8/igt@kms_ccs@pipe-c-bad-pixel-format.html
* igt@kms_chamelium@hdmi-crc-fast:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109284] / [fdo#111827]) +3 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb8/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_chamelium@vga-edid-read:
- shard-apl: NOTRUN -> [SKIP][48] ([fdo#109271] / [fdo#111827]) +17 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-apl1/igt@kms_chamelium@vga-edid-read.html
* igt@kms_chamelium@vga-frame-dump:
- shard-skl: NOTRUN -> [SKIP][49] ([fdo#109271] / [fdo#111827]) +12 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl3/igt@kms_chamelium@vga-frame-dump.html
* igt@kms_color_chamelium@pipe-a-ctm-0-25:
- shard-snb: NOTRUN -> [SKIP][50] ([fdo#109271] / [fdo#111827]) +12 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-snb5/igt@kms_color_chamelium@pipe-a-ctm-0-25.html
* igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
- shard-tglb: NOTRUN -> [SKIP][51] ([fdo#109284] / [fdo#111827]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-tglb1/igt@kms_color_chamelium@pipe-a-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-d-degamma:
- shard-glk: NOTRUN -> [SKIP][52] ([fdo#109271] / [fdo#111827]) +11 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-glk6/igt@kms_color_chamelium@pipe-d-degamma.html
* igt@kms_color_chamelium@pipe-invalid-gamma-lut-sizes:
- shard-kbl: NOTRUN -> [SKIP][53] ([fdo#109271] / [fdo#111827]) +7 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-kbl3/igt@kms_color_chamelium@pipe-invalid-gamma-lut-sizes.html
* igt@kms_content_protection@atomic-dpms:
- shard-kbl: NOTRUN -> [TIMEOUT][54] ([i915#1319])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-kbl2/igt@kms_content_protection@atomic-dpms.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-random:
- shard-tglb: NOTRUN -> [SKIP][55] ([i915#3359]) +3 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-tglb1/igt@kms_cursor_crc@pipe-b-cursor-32x10-random.html
* igt@kms_cursor_crc@pipe-b-cursor-512x170-onscreen:
- shard-iclb: NOTRUN -> [SKIP][56] ([fdo#109278] / [fdo#109279])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb1/igt@kms_cursor_crc@pipe-b-cursor-512x170-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-128x42-offscreen:
- shard-iclb: NOTRUN -> [SKIP][57] ([fdo#109278]) +4 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb1/igt@kms_cursor_crc@pipe-d-cursor-128x42-offscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-kbl: NOTRUN -> [SKIP][58] ([fdo#109271]) +63 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-kbl3/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge:
- shard-snb: NOTRUN -> [SKIP][59] ([fdo#109271]) +216 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-snb6/igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [PASS][60] -> [FAIL][61] ([i915#2346] / [i915#533])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [PASS][62] -> [INCOMPLETE][63] ([i915#155] / [i915#180] / [i915#636])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-kbl2/igt@kms_fbcon_fbt@fbc-suspend.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-tglb: NOTRUN -> [SKIP][64] ([fdo#111825]) +13 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-tglb1/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset:
- shard-iclb: NOTRUN -> [SKIP][65] ([fdo#109274])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb8/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-skl: NOTRUN -> [FAIL][66] ([i915#2122])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#2672])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-apl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-glk: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2642])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-kbl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#2672])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-kbl2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][70] ([fdo#109271]) +87 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl9/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-iclb: NOTRUN -> [SKIP][71] ([fdo#109280]) +6 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#533]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-apl1/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-skl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#533])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl7/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: NOTRUN -> [DMESG-WARN][74] ([i915#180])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-glk: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#533])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-glk8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-glk: NOTRUN -> [FAIL][76] ([fdo#108145] / [i915#265])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-glk9/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][77] ([fdo#108145] / [i915#265]) +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-skl: NOTRUN -> [FAIL][78] ([fdo#108145] / [i915#265]) +2 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-glk: NOTRUN -> [FAIL][79] ([i915#265])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-glk6/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][80] -> [FAIL][81] ([fdo#108145] / [i915#265])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-b-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][82] ([fdo#111615]) +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-tglb1/igt@kms_plane_lowres@pipe-b-tiling-yf.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-skl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#2733])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl7/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
- shard-kbl: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#658]) +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-kbl3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
- shard-tglb: NOTRUN -> [SKIP][85] ([i915#2920])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-tglb1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
- shard-apl: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#658]) +3 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-apl1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
- shard-glk: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#658]) +2 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-glk8/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-skl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#658]) +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][89] -> [SKIP][90] ([fdo#109642] / [fdo#111068] / [i915#658])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb7/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr2_su@page_flip:
- shard-tglb: NOTRUN -> [SKIP][91] ([i915#1911])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-tglb1/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: NOTRUN -> [SKIP][92] ([fdo#109441])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb1/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: [PASS][93] -> [SKIP][94] ([fdo#109441])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb7/igt@kms_psr@psr2_sprite_render.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][95] ([IGT#2])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-apl6/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-d-wait-forked-hang:
- shard-apl: NOTRUN -> [SKIP][96] ([fdo#109271]) +136 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-apl1/igt@kms_vblank@pipe-d-wait-forked-hang.html
* igt@kms_writeback@writeback-check-output:
- shard-skl: NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#2437])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl7/igt@kms_writeback@writeback-check-output.html
* igt@nouveau_crc@pipe-a-source-outp-complete:
- shard-tglb: NOTRUN -> [SKIP][98] ([i915#2530]) +1 similar issue
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-tglb1/igt@nouveau_crc@pipe-a-source-outp-complete.html
* igt@nouveau_crc@pipe-b-source-outp-inactive:
- shard-iclb: NOTRUN -> [SKIP][99] ([i915#2530])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb1/igt@nouveau_crc@pipe-b-source-outp-inactive.html
* igt@prime_nv_api@i915_nv_double_export:
- shard-iclb: NOTRUN -> [SKIP][100] ([fdo#109291])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb1/igt@prime_nv_api@i915_nv_double_export.html
* igt@sysfs_clients@fair-0:
- shard-skl: NOTRUN -> [SKIP][101] ([fdo#109271] / [i915#2994])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl8/igt@sysfs_clients@fair-0.html
* igt@sysfs_clients@fair-1:
- shard-apl: NOTRUN -> [SKIP][102] ([fdo#109271] / [i915#2994]) +1 similar issue
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-apl7/igt@sysfs_clients@fair-1.html
* igt@sysfs_clients@split-10:
- shard-iclb: NOTRUN -> [SKIP][103] ([i915#2994])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb8/igt@sysfs_clients@split-10.html
#### Possible fixes ####
* igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [FAIL][104] ([i915#2410]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-tglb6/igt@gem_ctx_persistence@many-contexts.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-tglb5/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_ctx_ringsize@active@bcs0:
- shard-skl: [INCOMPLETE][106] ([i915#3316]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-skl5/igt@gem_ctx_ringsize@active@bcs0.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl10/igt@gem_ctx_ringsize@active@bcs0.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-tglb: [TIMEOUT][108] ([i915#3063]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-tglb3/igt@gem_eio@in-flight-contexts-10ms.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-tglb1/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [FAIL][110] ([i915#2846]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-kbl4/igt@gem_exec_fair@basic-deadline.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-kbl7/igt@gem_exec_fair@basic-deadline.html
- shard-glk: [FAIL][112] ([i915#2846]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-glk8/igt@gem_exec_fair@basic-deadline.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-glk2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [FAIL][114] ([i915#2842]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-kbl2/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [FAIL][116] ([i915#2842]) -> [PASS][117] +2 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-iclb7/igt@gem_exec_fair@basic-pace@vcs0.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb5/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-tglb: [FAIL][118] ([i915#2842]) -> [PASS][119] +1 similar issue
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-tglb3/igt@gem_exec_fair@basic-pace@vecs0.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-tglb1/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy:
- shard-glk: [INCOMPLETE][120] ([i915#2055] / [i915#3468]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-glk5/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-glk5/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
- shard-iclb: [INCOMPLETE][122] ([i915#3468]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-iclb7/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb1/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
- shard-skl: [INCOMPLETE][124] ([i915#198] / [i915#3468]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-skl8/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-skl3/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
- shard-kbl: [INCOMPLETE][126] ([i915#3468]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-kbl7/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-kbl7/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-odd:
- shard-iclb: [INCOMPLETE][128] ([i915#2910] / [i915#3468]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-iclb6/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb8/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
* igt@gem_mmap_gtt@cpuset-big-copy-xy:
- shard-iclb: [FAIL][130] ([i915#307]) -> [PASS][131] +1 similar issue
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-iclb6/igt@gem_mmap_gtt@cpuset-big-copy-xy.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-iclb8/igt@gem_mmap_gtt@cpuset-big-copy-xy.html
* igt@gem_mmap_gtt@cpuset-medium-copy-odd:
- shard-glk: [FAIL][132] ([i915#307]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-glk9/igt@gem_mmap_gtt@cpuset-medium-copy-odd.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-glk6/igt@gem_mmap_gtt@cpuset-medium-copy-odd.html
* igt@gem_mmap_gtt@cpuset-medium-copy-xy:
- shard-glk: [INCOMPLETE][134] ([i915#3468]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-glk8/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/shard-glk9/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html
* igt@gem_mmap_gtt@medium-copy-xy:
- shard-glk: [INCOMPLETE][136] ([i915#2055] / [i915#2502] / [i915#3468]) -> [PASS][137]
[136]: https://intel-gfx
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/index.html
[-- Attachment #1.2: Type: text/html, Size: 33723 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL
2021-06-03 6:50 [Intel-gfx] [PATCH] " Stanislav Lisovskiy
2021-06-03 7:49 ` Kahola, Mika
@ 2021-06-09 14:36 ` Jani Nikula
1 sibling, 0 replies; 7+ messages in thread
From: Jani Nikula @ 2021-06-09 14:36 UTC (permalink / raw)
To: Stanislav Lisovskiy, intel-gfx
On Thu, 03 Jun 2021, Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> wrote:
> CDCLK crawl feature allows to change CDCLK frequency
> without disabling the actual PLL and doesn't require
> a full modeset.
I've pushed this to din because supposedly this is urgent.
However, there are some issues, comments inline, please fix them
afterwards.
BR,
Jani.
>
> v2: - Added has_cdclk_crawl as a feature flag to
> intel_device_info(Matt Roper)
> - s/gen13_cdclk_pll_crawl/adlp_cdclk_pll_crawl/
> (Matt Roper)
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 72 +++++++++++++++++++---
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> drivers/gpu/drm/i915/intel_device_info.h | 2 +
> 4 files changed, 68 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 4656a6edc3be..f24bd9cf1318 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1547,6 +1547,35 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
> dev_priv->cdclk.hw.vco = vco;
> }
>
> +static bool has_cdclk_crawl(struct drm_i915_private *i915)
> +{
> + return INTEL_INFO(i915)->has_cdclk_crawl;
> +}
For everything else we use HAS_SOMETHING() in i915_drv.h, not local
functions.
[...]
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 1390fad5ec06..b326aff65cd6 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -185,6 +185,8 @@ struct intel_device_info {
>
> u8 abox_mask;
>
> + u8 has_cdclk_crawl; /* does support CDCLK crawling */
> +
Flags are supposed to be added to DEV_INFO_FOR_EACH_FLAG() in
intel_device_info.h. Or, actually, this one's about display, so
DEV_INFO_DISPLAY_FOR_EACH_FLAG().
This makes them 1-bit bitfields instead of 8 bits, and automatically
adds them to debug printouts.
> #define DEFINE_FLAG(name) u8 name:1
> DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
> #undef DEFINE_FLAG
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL
2021-06-03 6:50 [Intel-gfx] [PATCH] " Stanislav Lisovskiy
@ 2021-06-03 7:49 ` Kahola, Mika
2021-06-09 14:36 ` Jani Nikula
1 sibling, 0 replies; 7+ messages in thread
From: Kahola, Mika @ 2021-06-03 7:49 UTC (permalink / raw)
To: Lisovskiy, Stanislav, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Stanislav Lisovskiy
> Sent: Thursday, June 3, 2021 9:51 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL
>
> CDCLK crawl feature allows to change CDCLK frequency without disabling the
> actual PLL and doesn't require a full modeset.
>
> v2: - Added has_cdclk_crawl as a feature flag to
> intel_device_info(Matt Roper)
> - s/gen13_cdclk_pll_crawl/adlp_cdclk_pll_crawl/
> (Matt Roper)
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 72 +++++++++++++++++++---
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> drivers/gpu/drm/i915/intel_device_info.h | 2 +
> 4 files changed, 68 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 4656a6edc3be..f24bd9cf1318 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1547,6 +1547,35 @@ static void cnl_cdclk_pll_enable(struct
> drm_i915_private *dev_priv, int vco)
> dev_priv->cdclk.hw.vco = vco;
> }
>
> +static bool has_cdclk_crawl(struct drm_i915_private *i915) {
> + return INTEL_INFO(i915)->has_cdclk_crawl;
> +}
> +
> +static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int
> +vco) {
> + int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
> + u32 val;
> +
> + /* Write PLL ratio without disabling */
> + val = CNL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
> + intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
> +
> + /* Submit freq change request */
> + val |= BXT_DE_PLL_FREQ_REQ;
> + intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
> +
> + /* Timeout 200us */
> + if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
> + BXT_DE_PLL_LOCK |
> BXT_DE_PLL_FREQ_REQ_ACK, 1))
> + DRM_ERROR("timeout waiting for FREQ change request
> ack\n");
> +
> + val &= ~BXT_DE_PLL_FREQ_REQ;
> + intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
> +
> + dev_priv->cdclk.hw.vco = vco;
> +}
> +
> static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum
> pipe pipe) {
> if (DISPLAY_VER(dev_priv) >= 12) {
> @@ -1619,14 +1648,16 @@ static void bxt_set_cdclk(struct
> drm_i915_private *dev_priv,
> return;
> }
>
> - if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
> + if (has_cdclk_crawl(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco
> > 0) {
> + if (dev_priv->cdclk.hw.vco != vco)
> + adlp_cdclk_pll_crawl(dev_priv, vco);
> + } else if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
> {
> if (dev_priv->cdclk.hw.vco != 0 &&
> dev_priv->cdclk.hw.vco != vco)
> cnl_cdclk_pll_disable(dev_priv);
>
> if (dev_priv->cdclk.hw.vco != vco)
> cnl_cdclk_pll_enable(dev_priv, vco);
> -
> } else {
> if (dev_priv->cdclk.hw.vco != 0 &&
> dev_priv->cdclk.hw.vco != vco)
> @@ -1819,6 +1850,28 @@ void intel_cdclk_uninit_hw(struct
> drm_i915_private *i915)
> skl_cdclk_uninit_hw(i915);
> }
>
> +static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
> + const struct intel_cdclk_config *a,
> + const struct intel_cdclk_config *b) {
> + int a_div, b_div;
> +
> + if (!has_cdclk_crawl(dev_priv))
> + return false;
> +
> + /*
> + * The vco and cd2x divider will change independently
> + * from each, so we disallow cd2x change when crawling.
> + */
> + a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
> + b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
> +
> + return a->vco != 0 && b->vco != 0 &&
> + a->vco != b->vco &&
> + a_div == b_div &&
> + a->ref == b->ref;
> +}
> +
> /**
> * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
> * configurations requires a modeset on all pipes
> @@ -2462,7 +2515,7 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> const struct intel_cdclk_state *old_cdclk_state;
> struct intel_cdclk_state *new_cdclk_state;
> - enum pipe pipe;
> + enum pipe pipe = INVALID_PIPE;
> int ret;
>
> new_cdclk_state = intel_atomic_get_cdclk_state(state);
> @@ -2514,15 +2567,18 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
>
> if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
> pipe = INVALID_PIPE;
> - } else {
> - pipe = INVALID_PIPE;
> }
>
> - if (pipe != INVALID_PIPE) {
> + if (intel_cdclk_can_crawl(dev_priv,
> + &old_cdclk_state->actual,
> + &new_cdclk_state->actual)) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Can change cdclk via crawl\n");
> + } else if (pipe != INVALID_PIPE) {
> new_cdclk_state->pipe = pipe;
>
> drm_dbg_kms(&dev_priv->drm,
> - "Can change cdclk with pipe %c active\n",
> + "Can change cdclk cd2x divider with pipe %c
> active\n",
> pipe_name(pipe));
> } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
> &new_cdclk_state->actual)) {
> @@ -2531,8 +2587,6 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> if (ret)
> return ret;
>
> - new_cdclk_state->pipe = INVALID_PIPE;
> -
> drm_dbg_kms(&dev_priv->drm,
> "Modeset required for cdclk change\n");
> }
> diff --git a/drivers/gpu/drm/i915/i915_pci.c
> b/drivers/gpu/drm/i915/i915_pci.c index 97c98f4fb265..83b500bb170c
> 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -953,6 +953,7 @@ static const struct intel_device_info adl_p_info = {
> GEN12_FEATURES,
> XE_LPD_FEATURES,
> PLATFORM(INTEL_ALDERLAKE_P),
> + .has_cdclk_crawl = 1,
> .require_force_probe = 1,
> .display.has_modular_fia = 1,
> .platform_engine_mask =
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 24307c49085f..c9963b615dd3
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10993,6 +10993,8 @@ enum skl_power_gate {
> #define BXT_DE_PLL_ENABLE _MMIO(0x46070)
> #define BXT_DE_PLL_PLL_ENABLE (1 << 31)
> #define BXT_DE_PLL_LOCK (1 << 30)
> +#define BXT_DE_PLL_FREQ_REQ (1 << 23)
> +#define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
> #define CNL_CDCLK_PLL_RATIO(x) (x)
> #define CNL_CDCLK_PLL_RATIO_MASK 0xff
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 1390fad5ec06..b326aff65cd6 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -185,6 +185,8 @@ struct intel_device_info {
>
> u8 abox_mask;
>
> + u8 has_cdclk_crawl; /* does support CDCLK crawling */
> +
> #define DEFINE_FLAG(name) u8 name:1
> DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
> #undef DEFINE_FLAG
> --
> 2.24.1.485.gad05a3d8e5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL
@ 2021-06-03 6:50 Stanislav Lisovskiy
2021-06-03 7:49 ` Kahola, Mika
2021-06-09 14:36 ` Jani Nikula
0 siblings, 2 replies; 7+ messages in thread
From: Stanislav Lisovskiy @ 2021-06-03 6:50 UTC (permalink / raw)
To: intel-gfx
CDCLK crawl feature allows to change CDCLK frequency
without disabling the actual PLL and doesn't require
a full modeset.
v2: - Added has_cdclk_crawl as a feature flag to
intel_device_info(Matt Roper)
- s/gen13_cdclk_pll_crawl/adlp_cdclk_pll_crawl/
(Matt Roper)
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 72 +++++++++++++++++++---
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_device_info.h | 2 +
4 files changed, 68 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4656a6edc3be..f24bd9cf1318 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1547,6 +1547,35 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
dev_priv->cdclk.hw.vco = vco;
}
+static bool has_cdclk_crawl(struct drm_i915_private *i915)
+{
+ return INTEL_INFO(i915)->has_cdclk_crawl;
+}
+
+static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
+{
+ int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+ u32 val;
+
+ /* Write PLL ratio without disabling */
+ val = CNL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
+ intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
+
+ /* Submit freq change request */
+ val |= BXT_DE_PLL_FREQ_REQ;
+ intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
+
+ /* Timeout 200us */
+ if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
+ BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
+ DRM_ERROR("timeout waiting for FREQ change request ack\n");
+
+ val &= ~BXT_DE_PLL_FREQ_REQ;
+ intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
+
+ dev_priv->cdclk.hw.vco = vco;
+}
+
static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
{
if (DISPLAY_VER(dev_priv) >= 12) {
@@ -1619,14 +1648,16 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
return;
}
- if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
+ if (has_cdclk_crawl(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
+ if (dev_priv->cdclk.hw.vco != vco)
+ adlp_cdclk_pll_crawl(dev_priv, vco);
+ } else if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
if (dev_priv->cdclk.hw.vco != 0 &&
dev_priv->cdclk.hw.vco != vco)
cnl_cdclk_pll_disable(dev_priv);
if (dev_priv->cdclk.hw.vco != vco)
cnl_cdclk_pll_enable(dev_priv, vco);
-
} else {
if (dev_priv->cdclk.hw.vco != 0 &&
dev_priv->cdclk.hw.vco != vco)
@@ -1819,6 +1850,28 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
skl_cdclk_uninit_hw(i915);
}
+static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_config *a,
+ const struct intel_cdclk_config *b)
+{
+ int a_div, b_div;
+
+ if (!has_cdclk_crawl(dev_priv))
+ return false;
+
+ /*
+ * The vco and cd2x divider will change independently
+ * from each, so we disallow cd2x change when crawling.
+ */
+ a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
+ b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
+
+ return a->vco != 0 && b->vco != 0 &&
+ a->vco != b->vco &&
+ a_div == b_div &&
+ a->ref == b->ref;
+}
+
/**
* intel_cdclk_needs_modeset - Determine if changong between the CDCLK
* configurations requires a modeset on all pipes
@@ -2462,7 +2515,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
const struct intel_cdclk_state *old_cdclk_state;
struct intel_cdclk_state *new_cdclk_state;
- enum pipe pipe;
+ enum pipe pipe = INVALID_PIPE;
int ret;
new_cdclk_state = intel_atomic_get_cdclk_state(state);
@@ -2514,15 +2567,18 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
pipe = INVALID_PIPE;
- } else {
- pipe = INVALID_PIPE;
}
- if (pipe != INVALID_PIPE) {
+ if (intel_cdclk_can_crawl(dev_priv,
+ &old_cdclk_state->actual,
+ &new_cdclk_state->actual)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Can change cdclk via crawl\n");
+ } else if (pipe != INVALID_PIPE) {
new_cdclk_state->pipe = pipe;
drm_dbg_kms(&dev_priv->drm,
- "Can change cdclk with pipe %c active\n",
+ "Can change cdclk cd2x divider with pipe %c active\n",
pipe_name(pipe));
} else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
&new_cdclk_state->actual)) {
@@ -2531,8 +2587,6 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
if (ret)
return ret;
- new_cdclk_state->pipe = INVALID_PIPE;
-
drm_dbg_kms(&dev_priv->drm,
"Modeset required for cdclk change\n");
}
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 97c98f4fb265..83b500bb170c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -953,6 +953,7 @@ static const struct intel_device_info adl_p_info = {
GEN12_FEATURES,
XE_LPD_FEATURES,
PLATFORM(INTEL_ALDERLAKE_P),
+ .has_cdclk_crawl = 1,
.require_force_probe = 1,
.display.has_modular_fia = 1,
.platform_engine_mask =
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 24307c49085f..c9963b615dd3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10993,6 +10993,8 @@ enum skl_power_gate {
#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
#define BXT_DE_PLL_LOCK (1 << 30)
+#define BXT_DE_PLL_FREQ_REQ (1 << 23)
+#define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
#define CNL_CDCLK_PLL_RATIO(x) (x)
#define CNL_CDCLK_PLL_RATIO_MASK 0xff
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 1390fad5ec06..b326aff65cd6 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -185,6 +185,8 @@ struct intel_device_info {
u8 abox_mask;
+ u8 has_cdclk_crawl; /* does support CDCLK crawling */
+
#define DEFINE_FLAG(name) u8 name:1
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-06-09 14:36 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-01 14:52 [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL Stanislav Lisovskiy
2021-06-01 20:20 ` Matt Roper
2021-06-01 22:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-06-02 9:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-06-03 6:50 [Intel-gfx] [PATCH] " Stanislav Lisovskiy
2021-06-03 7:49 ` Kahola, Mika
2021-06-09 14:36 ` Jani Nikula
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