* [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL
@ 2021-06-03 6:50 Stanislav Lisovskiy
2021-06-03 7:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adl_p: CDCLK crawl support for ADL (rev2) Patchwork
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Stanislav Lisovskiy @ 2021-06-03 6:50 UTC (permalink / raw)
To: intel-gfx
CDCLK crawl feature allows to change CDCLK frequency
without disabling the actual PLL and doesn't require
a full modeset.
v2: - Added has_cdclk_crawl as a feature flag to
intel_device_info(Matt Roper)
- s/gen13_cdclk_pll_crawl/adlp_cdclk_pll_crawl/
(Matt Roper)
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 72 +++++++++++++++++++---
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_device_info.h | 2 +
4 files changed, 68 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4656a6edc3be..f24bd9cf1318 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1547,6 +1547,35 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
dev_priv->cdclk.hw.vco = vco;
}
+static bool has_cdclk_crawl(struct drm_i915_private *i915)
+{
+ return INTEL_INFO(i915)->has_cdclk_crawl;
+}
+
+static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
+{
+ int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+ u32 val;
+
+ /* Write PLL ratio without disabling */
+ val = CNL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
+ intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
+
+ /* Submit freq change request */
+ val |= BXT_DE_PLL_FREQ_REQ;
+ intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
+
+ /* Timeout 200us */
+ if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
+ BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
+ DRM_ERROR("timeout waiting for FREQ change request ack\n");
+
+ val &= ~BXT_DE_PLL_FREQ_REQ;
+ intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
+
+ dev_priv->cdclk.hw.vco = vco;
+}
+
static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
{
if (DISPLAY_VER(dev_priv) >= 12) {
@@ -1619,14 +1648,16 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
return;
}
- if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
+ if (has_cdclk_crawl(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
+ if (dev_priv->cdclk.hw.vco != vco)
+ adlp_cdclk_pll_crawl(dev_priv, vco);
+ } else if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
if (dev_priv->cdclk.hw.vco != 0 &&
dev_priv->cdclk.hw.vco != vco)
cnl_cdclk_pll_disable(dev_priv);
if (dev_priv->cdclk.hw.vco != vco)
cnl_cdclk_pll_enable(dev_priv, vco);
-
} else {
if (dev_priv->cdclk.hw.vco != 0 &&
dev_priv->cdclk.hw.vco != vco)
@@ -1819,6 +1850,28 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
skl_cdclk_uninit_hw(i915);
}
+static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_config *a,
+ const struct intel_cdclk_config *b)
+{
+ int a_div, b_div;
+
+ if (!has_cdclk_crawl(dev_priv))
+ return false;
+
+ /*
+ * The vco and cd2x divider will change independently
+ * from each, so we disallow cd2x change when crawling.
+ */
+ a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
+ b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
+
+ return a->vco != 0 && b->vco != 0 &&
+ a->vco != b->vco &&
+ a_div == b_div &&
+ a->ref == b->ref;
+}
+
/**
* intel_cdclk_needs_modeset - Determine if changong between the CDCLK
* configurations requires a modeset on all pipes
@@ -2462,7 +2515,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
const struct intel_cdclk_state *old_cdclk_state;
struct intel_cdclk_state *new_cdclk_state;
- enum pipe pipe;
+ enum pipe pipe = INVALID_PIPE;
int ret;
new_cdclk_state = intel_atomic_get_cdclk_state(state);
@@ -2514,15 +2567,18 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
pipe = INVALID_PIPE;
- } else {
- pipe = INVALID_PIPE;
}
- if (pipe != INVALID_PIPE) {
+ if (intel_cdclk_can_crawl(dev_priv,
+ &old_cdclk_state->actual,
+ &new_cdclk_state->actual)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Can change cdclk via crawl\n");
+ } else if (pipe != INVALID_PIPE) {
new_cdclk_state->pipe = pipe;
drm_dbg_kms(&dev_priv->drm,
- "Can change cdclk with pipe %c active\n",
+ "Can change cdclk cd2x divider with pipe %c active\n",
pipe_name(pipe));
} else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
&new_cdclk_state->actual)) {
@@ -2531,8 +2587,6 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
if (ret)
return ret;
- new_cdclk_state->pipe = INVALID_PIPE;
-
drm_dbg_kms(&dev_priv->drm,
"Modeset required for cdclk change\n");
}
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 97c98f4fb265..83b500bb170c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -953,6 +953,7 @@ static const struct intel_device_info adl_p_info = {
GEN12_FEATURES,
XE_LPD_FEATURES,
PLATFORM(INTEL_ALDERLAKE_P),
+ .has_cdclk_crawl = 1,
.require_force_probe = 1,
.display.has_modular_fia = 1,
.platform_engine_mask =
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 24307c49085f..c9963b615dd3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10993,6 +10993,8 @@ enum skl_power_gate {
#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
#define BXT_DE_PLL_LOCK (1 << 30)
+#define BXT_DE_PLL_FREQ_REQ (1 << 23)
+#define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
#define CNL_CDCLK_PLL_RATIO(x) (x)
#define CNL_CDCLK_PLL_RATIO_MASK 0xff
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 1390fad5ec06..b326aff65cd6 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -185,6 +185,8 @@ struct intel_device_info {
u8 abox_mask;
+ u8 has_cdclk_crawl; /* does support CDCLK crawling */
+
#define DEFINE_FLAG(name) u8 name:1
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adl_p: CDCLK crawl support for ADL (rev2)
2021-06-03 6:50 [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL Stanislav Lisovskiy
@ 2021-06-03 7:36 ` Patchwork
2021-06-03 7:49 ` [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL Kahola, Mika
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2021-06-03 7:36 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4715 bytes --]
== Series Details ==
Series: drm/i915/adl_p: CDCLK crawl support for ADL (rev2)
URL : https://patchwork.freedesktop.org/series/90842/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10161 -> Patchwork_20269
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/index.html
Known issues
------------
Here are the changes found in Patchwork_20269 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@core_auth@basic-auth:
- fi-kbl-soraka: [DMESG-WARN][1] ([i915#1982]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/fi-kbl-soraka/igt@core_auth@basic-auth.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/fi-kbl-soraka/igt@core_auth@basic-auth.html
#### Warnings ####
* igt@i915_selftest@live@execlists:
- fi-icl-u2: [DMESG-FAIL][3] ([i915#3462]) -> [INCOMPLETE][4] ([i915#2782] / [i915#3462])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/fi-icl-u2/igt@i915_selftest@live@execlists.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/fi-icl-u2/igt@i915_selftest@live@execlists.html
* igt@runner@aborted:
- fi-cfl-8700k: [FAIL][5] ([i915#3363]) -> [FAIL][6] ([i915#2426] / [i915#3363])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/fi-cfl-8700k/igt@runner@aborted.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/fi-cfl-8700k/igt@runner@aborted.html
- fi-skl-6600u: [FAIL][7] ([i915#1436] / [i915#3363]) -> [FAIL][8] ([i915#1436] / [i915#2426] / [i915#3363])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/fi-skl-6600u/igt@runner@aborted.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/fi-skl-6600u/igt@runner@aborted.html
- fi-icl-u2: [FAIL][9] ([i915#2426] / [i915#2782] / [i915#3363]) -> [FAIL][10] ([i915#2782] / [i915#3363])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/fi-icl-u2/igt@runner@aborted.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/fi-icl-u2/igt@runner@aborted.html
- fi-kbl-soraka: [FAIL][11] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][12] ([i915#1436] / [i915#3363])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/fi-kbl-soraka/igt@runner@aborted.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/fi-kbl-soraka/igt@runner@aborted.html
- fi-cfl-guc: [FAIL][13] ([i915#2426] / [i915#3363]) -> [FAIL][14] ([i915#3363])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/fi-cfl-guc/igt@runner@aborted.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/fi-cfl-guc/igt@runner@aborted.html
- fi-kbl-7567u: [FAIL][15] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][16] ([i915#1436] / [i915#3363])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/fi-kbl-7567u/igt@runner@aborted.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/fi-kbl-7567u/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
[i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[i915#3537]: https://gitlab.freedesktop.org/drm/intel/issues/3537
Participating hosts (46 -> 42)
------------------------------
Additional (1): fi-tgl-1115g4
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_10161 -> Patchwork_20269
CI-20190529: 20190529
CI_DRM_10161: 6ce32fba8fd6caa0cd3ea578b35f76d188ebb155 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6098: 1fbc1e7d602f96a7f4e2b95057eef994656b8e74 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20269: b69711581c105a754587db6114ea6c81dda37d8e @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b69711581c10 drm/i915/adl_p: CDCLK crawl support for ADL
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/index.html
[-- Attachment #1.2: Type: text/html, Size: 6814 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL
2021-06-03 6:50 [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL Stanislav Lisovskiy
2021-06-03 7:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adl_p: CDCLK crawl support for ADL (rev2) Patchwork
@ 2021-06-03 7:49 ` Kahola, Mika
2021-06-03 9:16 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/adl_p: CDCLK crawl support for ADL (rev2) Patchwork
2021-06-09 14:36 ` [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL Jani Nikula
3 siblings, 0 replies; 7+ messages in thread
From: Kahola, Mika @ 2021-06-03 7:49 UTC (permalink / raw)
To: Lisovskiy, Stanislav, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Stanislav Lisovskiy
> Sent: Thursday, June 3, 2021 9:51 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL
>
> CDCLK crawl feature allows to change CDCLK frequency without disabling the
> actual PLL and doesn't require a full modeset.
>
> v2: - Added has_cdclk_crawl as a feature flag to
> intel_device_info(Matt Roper)
> - s/gen13_cdclk_pll_crawl/adlp_cdclk_pll_crawl/
> (Matt Roper)
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 72 +++++++++++++++++++---
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> drivers/gpu/drm/i915/intel_device_info.h | 2 +
> 4 files changed, 68 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 4656a6edc3be..f24bd9cf1318 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1547,6 +1547,35 @@ static void cnl_cdclk_pll_enable(struct
> drm_i915_private *dev_priv, int vco)
> dev_priv->cdclk.hw.vco = vco;
> }
>
> +static bool has_cdclk_crawl(struct drm_i915_private *i915) {
> + return INTEL_INFO(i915)->has_cdclk_crawl;
> +}
> +
> +static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int
> +vco) {
> + int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
> + u32 val;
> +
> + /* Write PLL ratio without disabling */
> + val = CNL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
> + intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
> +
> + /* Submit freq change request */
> + val |= BXT_DE_PLL_FREQ_REQ;
> + intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
> +
> + /* Timeout 200us */
> + if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
> + BXT_DE_PLL_LOCK |
> BXT_DE_PLL_FREQ_REQ_ACK, 1))
> + DRM_ERROR("timeout waiting for FREQ change request
> ack\n");
> +
> + val &= ~BXT_DE_PLL_FREQ_REQ;
> + intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
> +
> + dev_priv->cdclk.hw.vco = vco;
> +}
> +
> static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum
> pipe pipe) {
> if (DISPLAY_VER(dev_priv) >= 12) {
> @@ -1619,14 +1648,16 @@ static void bxt_set_cdclk(struct
> drm_i915_private *dev_priv,
> return;
> }
>
> - if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
> + if (has_cdclk_crawl(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco
> > 0) {
> + if (dev_priv->cdclk.hw.vco != vco)
> + adlp_cdclk_pll_crawl(dev_priv, vco);
> + } else if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
> {
> if (dev_priv->cdclk.hw.vco != 0 &&
> dev_priv->cdclk.hw.vco != vco)
> cnl_cdclk_pll_disable(dev_priv);
>
> if (dev_priv->cdclk.hw.vco != vco)
> cnl_cdclk_pll_enable(dev_priv, vco);
> -
> } else {
> if (dev_priv->cdclk.hw.vco != 0 &&
> dev_priv->cdclk.hw.vco != vco)
> @@ -1819,6 +1850,28 @@ void intel_cdclk_uninit_hw(struct
> drm_i915_private *i915)
> skl_cdclk_uninit_hw(i915);
> }
>
> +static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
> + const struct intel_cdclk_config *a,
> + const struct intel_cdclk_config *b) {
> + int a_div, b_div;
> +
> + if (!has_cdclk_crawl(dev_priv))
> + return false;
> +
> + /*
> + * The vco and cd2x divider will change independently
> + * from each, so we disallow cd2x change when crawling.
> + */
> + a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
> + b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
> +
> + return a->vco != 0 && b->vco != 0 &&
> + a->vco != b->vco &&
> + a_div == b_div &&
> + a->ref == b->ref;
> +}
> +
> /**
> * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
> * configurations requires a modeset on all pipes
> @@ -2462,7 +2515,7 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> const struct intel_cdclk_state *old_cdclk_state;
> struct intel_cdclk_state *new_cdclk_state;
> - enum pipe pipe;
> + enum pipe pipe = INVALID_PIPE;
> int ret;
>
> new_cdclk_state = intel_atomic_get_cdclk_state(state);
> @@ -2514,15 +2567,18 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
>
> if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
> pipe = INVALID_PIPE;
> - } else {
> - pipe = INVALID_PIPE;
> }
>
> - if (pipe != INVALID_PIPE) {
> + if (intel_cdclk_can_crawl(dev_priv,
> + &old_cdclk_state->actual,
> + &new_cdclk_state->actual)) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Can change cdclk via crawl\n");
> + } else if (pipe != INVALID_PIPE) {
> new_cdclk_state->pipe = pipe;
>
> drm_dbg_kms(&dev_priv->drm,
> - "Can change cdclk with pipe %c active\n",
> + "Can change cdclk cd2x divider with pipe %c
> active\n",
> pipe_name(pipe));
> } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
> &new_cdclk_state->actual)) {
> @@ -2531,8 +2587,6 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> if (ret)
> return ret;
>
> - new_cdclk_state->pipe = INVALID_PIPE;
> -
> drm_dbg_kms(&dev_priv->drm,
> "Modeset required for cdclk change\n");
> }
> diff --git a/drivers/gpu/drm/i915/i915_pci.c
> b/drivers/gpu/drm/i915/i915_pci.c index 97c98f4fb265..83b500bb170c
> 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -953,6 +953,7 @@ static const struct intel_device_info adl_p_info = {
> GEN12_FEATURES,
> XE_LPD_FEATURES,
> PLATFORM(INTEL_ALDERLAKE_P),
> + .has_cdclk_crawl = 1,
> .require_force_probe = 1,
> .display.has_modular_fia = 1,
> .platform_engine_mask =
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 24307c49085f..c9963b615dd3
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10993,6 +10993,8 @@ enum skl_power_gate {
> #define BXT_DE_PLL_ENABLE _MMIO(0x46070)
> #define BXT_DE_PLL_PLL_ENABLE (1 << 31)
> #define BXT_DE_PLL_LOCK (1 << 30)
> +#define BXT_DE_PLL_FREQ_REQ (1 << 23)
> +#define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
> #define CNL_CDCLK_PLL_RATIO(x) (x)
> #define CNL_CDCLK_PLL_RATIO_MASK 0xff
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 1390fad5ec06..b326aff65cd6 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -185,6 +185,8 @@ struct intel_device_info {
>
> u8 abox_mask;
>
> + u8 has_cdclk_crawl; /* does support CDCLK crawling */
> +
> #define DEFINE_FLAG(name) u8 name:1
> DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
> #undef DEFINE_FLAG
> --
> 2.24.1.485.gad05a3d8e5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/adl_p: CDCLK crawl support for ADL (rev2)
2021-06-03 6:50 [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL Stanislav Lisovskiy
2021-06-03 7:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adl_p: CDCLK crawl support for ADL (rev2) Patchwork
2021-06-03 7:49 ` [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL Kahola, Mika
@ 2021-06-03 9:16 ` Patchwork
2021-06-09 14:36 ` [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL Jani Nikula
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2021-06-03 9:16 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30273 bytes --]
== Series Details ==
Series: drm/i915/adl_p: CDCLK crawl support for ADL (rev2)
URL : https://patchwork.freedesktop.org/series/90842/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10161_full -> Patchwork_20269_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_20269_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +5 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#198])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-skl10/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl1/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_ctx_persistence@legacy-engines-mixed-process:
- shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-snb2/igt@gem_ctx_persistence@legacy-engines-mixed-process.html
* igt@gem_eio@unwedge-stress:
- shard-snb: NOTRUN -> [FAIL][6] ([i915#3354])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-snb5/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][7] -> [FAIL][8] ([i915#2842]) +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-tglb1/igt@gem_exec_fair@basic-pace@bcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-tglb8/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-glk9/igt@gem_exec_fair@basic-throttle@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-glk6/igt@gem_exec_fair@basic-throttle@rcs0.html
- shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2849])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_reloc@basic-wide-active@bcs0:
- shard-apl: NOTRUN -> [FAIL][15] ([i915#2389]) +3 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl1/igt@gem_exec_reloc@basic-wide-active@bcs0.html
* igt@gem_exec_reloc@basic-wide-active@rcs0:
- shard-snb: NOTRUN -> [FAIL][16] ([i915#2389]) +2 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-snb6/igt@gem_exec_reloc@basic-wide-active@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl3/igt@gem_huc_copy@huc-copy.html
- shard-kbl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#2190])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-kbl3/igt@gem_huc_copy@huc-copy.html
* igt@gem_pwrite@basic-exhaustion:
- shard-apl: NOTRUN -> [WARN][19] ([i915#2658])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl1/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3323])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl6/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][21] ([i915#3318])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl3/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][22] -> [DMESG-WARN][23] ([i915#1436] / [i915#716])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-skl3/igt@gen9_exec_parse@allowed-single.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl4/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][24] -> [FAIL][25] ([i915#454])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#1937])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl6/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_selftest@live@execlists:
- shard-apl: NOTRUN -> [DMESG-FAIL][27] ([i915#3462])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl3/igt@i915_selftest@live@execlists.html
- shard-kbl: NOTRUN -> [INCOMPLETE][28] ([i915#2782] / [i915#3462] / [i915#794])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-kbl3/igt@i915_selftest@live@execlists.html
* igt@kms_big_joiner@invalid-modeset:
- shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#2705])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl1/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180:
- shard-skl: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111304])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl5/igt@kms_ccs@pipe-c-crc-primary-rotation-180.html
* igt@kms_chamelium@hdmi-edid-change-during-suspend:
- shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +33 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl3/igt@kms_chamelium@hdmi-edid-change-during-suspend.html
* igt@kms_color@pipe-a-ctm-0-5:
- shard-skl: [PASS][32] -> [DMESG-WARN][33] ([i915#1982])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-skl4/igt@kms_color@pipe-a-ctm-0-5.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl1/igt@kms_color@pipe-a-ctm-0-5.html
* igt@kms_color_chamelium@pipe-a-ctm-0-25:
- shard-snb: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +12 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-snb5/igt@kms_color_chamelium@pipe-a-ctm-0-25.html
* igt@kms_color_chamelium@pipe-b-gamma:
- shard-kbl: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +8 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-kbl7/igt@kms_color_chamelium@pipe-b-gamma.html
* igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes:
- shard-skl: NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl5/igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> [TIMEOUT][37] ([i915#1319])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl3/igt@kms_content_protection@atomic-dpms.html
- shard-kbl: NOTRUN -> [TIMEOUT][38] ([i915#1319])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-kbl3/igt@kms_content_protection@atomic-dpms.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding:
- shard-skl: [PASS][39] -> [FAIL][40] ([i915#3444])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [PASS][41] -> [FAIL][42] ([i915#2346] / [i915#533])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#2672]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
- shard-apl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#2642])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-kbl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#2672])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-kbl3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-skl: NOTRUN -> [SKIP][46] ([fdo#109271]) +46 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-kbl: NOTRUN -> [SKIP][47] ([fdo#109271]) +60 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-kbl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#533]) +4 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl2/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][49] ([fdo#108145] / [i915#265]) +3 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][50] -> [FAIL][51] ([fdo#108145] / [i915#265]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-kbl: NOTRUN -> [FAIL][52] ([fdo#108145] / [i915#265])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-kbl3/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-skl: NOTRUN -> [FAIL][53] ([fdo#108145] / [i915#265])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][54] ([i915#265])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl7/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-apl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#2733])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl1/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
- shard-apl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#658]) +5 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-kbl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#658]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-kbl7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][58] -> [SKIP][59] ([fdo#109441]) +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-iclb1/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_universal_plane@disable-primary-vs-flip-pipe-d:
- shard-snb: NOTRUN -> [SKIP][60] ([fdo#109271]) +198 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-snb5/igt@kms_universal_plane@disable-primary-vs-flip-pipe-d.html
* igt@kms_vblank@pipe-d-wait-forked-hang:
- shard-apl: NOTRUN -> [SKIP][61] ([fdo#109271]) +339 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl2/igt@kms_vblank@pipe-d-wait-forked-hang.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#2437]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl1/igt@kms_writeback@writeback-check-output.html
* igt@perf@polling-small-buf:
- shard-skl: [PASS][63] -> [FAIL][64] ([i915#1722])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-skl4/igt@perf@polling-small-buf.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl1/igt@perf@polling-small-buf.html
* igt@sysfs_clients@create:
- shard-skl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#2994]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl5/igt@sysfs_clients@create.html
* igt@sysfs_clients@fair-0:
- shard-kbl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#2994])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-kbl3/igt@sysfs_clients@fair-0.html
* igt@sysfs_clients@fair-1:
- shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#2994]) +6 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl3/igt@sysfs_clients@fair-1.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][68] ([i915#658]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-iclb3/igt@feature_discovery@psr2.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_ctx_ringsize@active@bcs0:
- shard-skl: [INCOMPLETE][70] ([i915#3316]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-skl8/igt@gem_ctx_ringsize@active@bcs0.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl10/igt@gem_ctx_ringsize@active@bcs0.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-iclb: [TIMEOUT][72] ([i915#3070]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-iclb1/igt@gem_eio@in-flight-contexts-immediate.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-iclb4/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: ([FAIL][74], [FAIL][75]) ([i915#2842]) -> [PASS][76]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-glk3/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-glk9/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk: [FAIL][77] ([i915#2842]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-glk4/igt@gem_exec_fair@basic-none-vip@rcs0.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-glk5/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [FAIL][79] ([i915#2842]) -> [PASS][80] +2 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_whisper@basic-contexts-priority:
- shard-glk: [DMESG-WARN][81] ([i915#118] / [i915#95]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-glk6/igt@gem_exec_whisper@basic-contexts-priority.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-glk3/igt@gem_exec_whisper@basic-contexts-priority.html
* igt@gem_mmap_gtt@cpuset-big-copy:
- shard-iclb: [FAIL][83] ([i915#2428]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-iclb4/igt@gem_mmap_gtt@cpuset-big-copy.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [DMESG-WARN][85] ([i915#180]) -> [PASS][86] +3 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-kbl1/igt@gem_workarounds@suspend-resume-fd.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-kbl2/igt@gem_workarounds@suspend-resume-fd.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][87] ([i915#2782]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-snb7/igt@i915_selftest@live@hangcheck.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-snb5/igt@i915_selftest@live@hangcheck.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-skl: [FAIL][89] ([i915#2122]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][91] ([fdo#108145] / [i915#265]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [SKIP][93] ([fdo#109441]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-iclb3/igt@kms_psr@psr2_basic.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-iclb2/igt@kms_psr@psr2_basic.html
* igt@perf_pmu@module-unload:
- shard-skl: [DMESG-WARN][95] ([i915#1982] / [i915#262]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-skl5/igt@perf_pmu@module-unload.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl3/igt@perf_pmu@module-unload.html
#### Warnings ####
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: [FAIL][97] ([i915#2852]) -> [FAIL][98] ([i915#2842])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-iclb2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-iclb4/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: ([PASS][99], [FAIL][100]) ([i915#2842]) -> [FAIL][101] ([i915#2842]) +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_mmap_gtt@big-copy:
- shard-glk: ([PASS][102], [FAIL][103]) ([i915#307]) -> [FAIL][104] ([i915#307])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-glk6/igt@gem_mmap_gtt@big-copy.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-glk1/igt@gem_mmap_gtt@big-copy.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-glk9/igt@gem_mmap_gtt@big-copy.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][105] ([i915#1804] / [i915#2684]) -> [WARN][106] ([i915#2684])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-iclb5/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][107] ([i915#2684]) -> [FAIL][108] ([i915#2680])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_selftest@live@execlists:
- shard-iclb: [DMESG-FAIL][109] ([i915#3462]) -> [INCOMPLETE][110] ([i915#2782] / [i915#3462])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-iclb7/igt@i915_selftest@live@execlists.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-iclb1/igt@i915_selftest@live@execlists.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][111] ([fdo#109349]) -> [CRASH][112] ([i915#3494])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-iclb3/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-1:
- shard-iclb: [SKIP][113] ([i915#658]) -> [SKIP][114] ([i915#2920])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-iclb3/igt@kms_psr2_sf@plane-move-sf-dmg-area-1.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-iclb: [SKIP][115] ([i915#2920]) -> [SKIP][116] ([i915#658]) +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-iclb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@runner@aborted:
- shard-apl: ([FAIL][117], [FAIL][118]) ([i915#3002] / [i915#3363]) -> ([FAIL][119], [FAIL][120]) ([fdo#109271] / [i915#3002] / [i915#3363])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-apl7/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-apl6/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl1/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-apl3/igt@runner@aborted.html
- shard-skl: ([FAIL][121], [FAIL][122], [FAIL][123]) ([i915#1436] / [i915#2426] / [i915#3002] / [i915#3363]) -> ([FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128]) ([i915#1436] / [i915#2029] / [i915#3002] / [i915#3363])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-skl6/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-skl3/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10161/shard-skl2/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl4/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl3/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl9/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl1/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/shard-skl3/igt@runner@aborted.html
### Piglit changes ###
#### Issues hit ####
* spec@ext_framebuffer_multisample_blit_scaled@blit-scaled samples=2 with gl_texture_2d_multisample_array:
- pig-skl-6260u: NOTRUN -> [WARN][129] ([i915#3105] / [mesa#1797]) +1 similar issue
[129]: None
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111304]: https://bugs.freedesktop.org/show_bug.cgi?id=111304
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2428]: https://gitlab.freedesktop.org/drm/intel/issues/2428
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#2642]: https://gitlab.freedesktop.org/drm/intel/issues/2642
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2680]: https://gitlab.freedesktop.org/drm/intel/issues/2680
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2733]: https://gitlab.freedesktop.org/drm/intel/issues/2733
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2852]: https://gitlab.freedesktop.org/drm/intel/issues/2852
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#307]: https://gitlab.freedesktop.org/drm/intel/issues/307
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3105]: https://gitlab.freedesktop.org/drm/intel/issues/3105
[i915#3316]: https://gitlab.freedesktop.org/drm/intel/issues/3316
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3354]: https://gitlab.freedesktop.org/drm/intel/issues/3354
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3444]: https://gitlab.freedesktop.org/drm/intel/issues/3444
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[i915#3494]: https://gitlab.freedesktop.org/drm/intel/issues/3494
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[mesa#1797]: https://gitlab.freedesktop.org/mesa/mesa/issues/1797
Participating hosts (9 -> 10)
------------------------------
Additional (1): pig-skl-6260u
Build changes
-------------
* Linux: CI_DRM_10161 -> Patchwork_20269
CI-20190529: 20190529
CI_DRM_10161: 6ce32fba8fd6caa0cd3ea578b35f76d188eb
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20269/index.html
[-- Attachment #1.2: Type: text/html, Size: 38305 bytes --]
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL
2021-06-03 6:50 [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL Stanislav Lisovskiy
` (2 preceding siblings ...)
2021-06-03 9:16 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/adl_p: CDCLK crawl support for ADL (rev2) Patchwork
@ 2021-06-09 14:36 ` Jani Nikula
3 siblings, 0 replies; 7+ messages in thread
From: Jani Nikula @ 2021-06-09 14:36 UTC (permalink / raw)
To: Stanislav Lisovskiy, intel-gfx
On Thu, 03 Jun 2021, Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> wrote:
> CDCLK crawl feature allows to change CDCLK frequency
> without disabling the actual PLL and doesn't require
> a full modeset.
I've pushed this to din because supposedly this is urgent.
However, there are some issues, comments inline, please fix them
afterwards.
BR,
Jani.
>
> v2: - Added has_cdclk_crawl as a feature flag to
> intel_device_info(Matt Roper)
> - s/gen13_cdclk_pll_crawl/adlp_cdclk_pll_crawl/
> (Matt Roper)
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 72 +++++++++++++++++++---
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> drivers/gpu/drm/i915/intel_device_info.h | 2 +
> 4 files changed, 68 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 4656a6edc3be..f24bd9cf1318 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1547,6 +1547,35 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
> dev_priv->cdclk.hw.vco = vco;
> }
>
> +static bool has_cdclk_crawl(struct drm_i915_private *i915)
> +{
> + return INTEL_INFO(i915)->has_cdclk_crawl;
> +}
For everything else we use HAS_SOMETHING() in i915_drv.h, not local
functions.
[...]
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 1390fad5ec06..b326aff65cd6 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -185,6 +185,8 @@ struct intel_device_info {
>
> u8 abox_mask;
>
> + u8 has_cdclk_crawl; /* does support CDCLK crawling */
> +
Flags are supposed to be added to DEV_INFO_FOR_EACH_FLAG() in
intel_device_info.h. Or, actually, this one's about display, so
DEV_INFO_DISPLAY_FOR_EACH_FLAG().
This makes them 1-bit bitfields instead of 8 bits, and automatically
adds them to debug printouts.
> #define DEFINE_FLAG(name) u8 name:1
> DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
> #undef DEFINE_FLAG
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL
2021-06-01 14:52 Stanislav Lisovskiy
@ 2021-06-01 20:20 ` Matt Roper
0 siblings, 0 replies; 7+ messages in thread
From: Matt Roper @ 2021-06-01 20:20 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Tue, Jun 01, 2021 at 05:52:48PM +0300, Stanislav Lisovskiy wrote:
> From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Aren't you (Stan) the original author of this patch? It looks like the
authorship got changed accidentally in one of the preparation rebases.
A couple other quick drive-by comments below.
>
> CDCLK crawl feature allows to change CDCLK frequency
> without disabling the actual PLL and doesn't require
> a full modeset.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 72 +++++++++++++++++++---
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> 2 files changed, 65 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 618a9e1e2b0c..b9abed82328c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1548,6 +1548,35 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
> dev_priv->cdclk.hw.vco = vco;
> }
>
> +static bool has_cdclk_crawl(struct drm_i915_private *i915)
> +{
> + return IS_ALDERLAKE_P(i915);
> +}
Would it make sense to make this a feature flag in the device info
structure?
> +
> +static void gen13_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
Function name prefix should either be "adlp" or "xelpd." Probably
"adlp" in this case since I think this functionality relates more to the
platform itself than the display architecture version.
Matt
> +{
> + int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
> + u32 val;
> +
> + /* Write PLL ratio without disabling */
> + val = CNL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
> + intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
> +
> + /* Submit freq change request */
> + val |= BXT_DE_PLL_FREQ_REQ;
> + intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
> +
> + /* Timeout 200us */
> + if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
> + BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
> + DRM_ERROR("timeout waiting for FREQ change request ack\n");
> +
> + val &= ~BXT_DE_PLL_FREQ_REQ;
> + intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
> +
> + dev_priv->cdclk.hw.vco = vco;
> +}
> +
> static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> {
> if (DISPLAY_VER(dev_priv) >= 12) {
> @@ -1620,14 +1649,16 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> return;
> }
>
> - if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
> + if (has_cdclk_crawl(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
> + if (dev_priv->cdclk.hw.vco != vco)
> + gen13_cdclk_pll_crawl(dev_priv, vco);
> + } else if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
> if (dev_priv->cdclk.hw.vco != 0 &&
> dev_priv->cdclk.hw.vco != vco)
> cnl_cdclk_pll_disable(dev_priv);
>
> if (dev_priv->cdclk.hw.vco != vco)
> cnl_cdclk_pll_enable(dev_priv, vco);
> -
> } else {
> if (dev_priv->cdclk.hw.vco != 0 &&
> dev_priv->cdclk.hw.vco != vco)
> @@ -1820,6 +1851,28 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
> skl_cdclk_uninit_hw(i915);
> }
>
> +static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
> + const struct intel_cdclk_config *a,
> + const struct intel_cdclk_config *b)
> +{
> + int a_div, b_div;
> +
> + if (!has_cdclk_crawl(dev_priv))
> + return false;
> +
> + /*
> + * The vco and cd2x divider will change independently
> + * from each, so we disallow cd2x change when crawling.
> + */
> + a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
> + b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
> +
> + return a->vco != 0 && b->vco != 0 &&
> + a->vco != b->vco &&
> + a_div == b_div &&
> + a->ref == b->ref;
> +}
> +
> /**
> * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
> * configurations requires a modeset on all pipes
> @@ -2475,7 +2528,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> const struct intel_cdclk_state *old_cdclk_state;
> struct intel_cdclk_state *new_cdclk_state;
> - enum pipe pipe;
> + enum pipe pipe = INVALID_PIPE;
> int ret;
>
> new_cdclk_state = intel_atomic_get_cdclk_state(state);
> @@ -2527,15 +2580,18 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
>
> if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
> pipe = INVALID_PIPE;
> - } else {
> - pipe = INVALID_PIPE;
> }
>
> - if (pipe != INVALID_PIPE) {
> + if (intel_cdclk_can_crawl(dev_priv,
> + &old_cdclk_state->actual,
> + &new_cdclk_state->actual)) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Can change cdclk via crawl\n");
> + } else if (pipe != INVALID_PIPE) {
> new_cdclk_state->pipe = pipe;
>
> drm_dbg_kms(&dev_priv->drm,
> - "Can change cdclk with pipe %c active\n",
> + "Can change cdclk cd2x divider with pipe %c active\n",
> pipe_name(pipe));
> } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
> &new_cdclk_state->actual)) {
> @@ -2544,8 +2600,6 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> if (ret)
> return ret;
>
> - new_cdclk_state->pipe = INVALID_PIPE;
> -
> drm_dbg_kms(&dev_priv->drm,
> "Modeset required for cdclk change\n");
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3b58067a873c..1d1176d1799d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11157,6 +11157,8 @@ enum skl_power_gate {
> #define BXT_DE_PLL_ENABLE _MMIO(0x46070)
> #define BXT_DE_PLL_PLL_ENABLE (1 << 31)
> #define BXT_DE_PLL_LOCK (1 << 30)
> +#define BXT_DE_PLL_FREQ_REQ (1 << 23)
> +#define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
> #define CNL_CDCLK_PLL_RATIO(x) (x)
> #define CNL_CDCLK_PLL_RATIO_MASK 0xff
>
> --
> 2.24.1.485.gad05a3d8e5
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL
@ 2021-06-01 14:52 Stanislav Lisovskiy
2021-06-01 20:20 ` Matt Roper
0 siblings, 1 reply; 7+ messages in thread
From: Stanislav Lisovskiy @ 2021-06-01 14:52 UTC (permalink / raw)
To: intel-gfx
From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
CDCLK crawl feature allows to change CDCLK frequency
without disabling the actual PLL and doesn't require
a full modeset.
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 72 +++++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 2 +
2 files changed, 65 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 618a9e1e2b0c..b9abed82328c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1548,6 +1548,35 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
dev_priv->cdclk.hw.vco = vco;
}
+static bool has_cdclk_crawl(struct drm_i915_private *i915)
+{
+ return IS_ALDERLAKE_P(i915);
+}
+
+static void gen13_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
+{
+ int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+ u32 val;
+
+ /* Write PLL ratio without disabling */
+ val = CNL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
+ intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
+
+ /* Submit freq change request */
+ val |= BXT_DE_PLL_FREQ_REQ;
+ intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
+
+ /* Timeout 200us */
+ if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
+ BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
+ DRM_ERROR("timeout waiting for FREQ change request ack\n");
+
+ val &= ~BXT_DE_PLL_FREQ_REQ;
+ intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
+
+ dev_priv->cdclk.hw.vco = vco;
+}
+
static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
{
if (DISPLAY_VER(dev_priv) >= 12) {
@@ -1620,14 +1649,16 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
return;
}
- if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
+ if (has_cdclk_crawl(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
+ if (dev_priv->cdclk.hw.vco != vco)
+ gen13_cdclk_pll_crawl(dev_priv, vco);
+ } else if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
if (dev_priv->cdclk.hw.vco != 0 &&
dev_priv->cdclk.hw.vco != vco)
cnl_cdclk_pll_disable(dev_priv);
if (dev_priv->cdclk.hw.vco != vco)
cnl_cdclk_pll_enable(dev_priv, vco);
-
} else {
if (dev_priv->cdclk.hw.vco != 0 &&
dev_priv->cdclk.hw.vco != vco)
@@ -1820,6 +1851,28 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
skl_cdclk_uninit_hw(i915);
}
+static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_config *a,
+ const struct intel_cdclk_config *b)
+{
+ int a_div, b_div;
+
+ if (!has_cdclk_crawl(dev_priv))
+ return false;
+
+ /*
+ * The vco and cd2x divider will change independently
+ * from each, so we disallow cd2x change when crawling.
+ */
+ a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
+ b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
+
+ return a->vco != 0 && b->vco != 0 &&
+ a->vco != b->vco &&
+ a_div == b_div &&
+ a->ref == b->ref;
+}
+
/**
* intel_cdclk_needs_modeset - Determine if changong between the CDCLK
* configurations requires a modeset on all pipes
@@ -2475,7 +2528,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
const struct intel_cdclk_state *old_cdclk_state;
struct intel_cdclk_state *new_cdclk_state;
- enum pipe pipe;
+ enum pipe pipe = INVALID_PIPE;
int ret;
new_cdclk_state = intel_atomic_get_cdclk_state(state);
@@ -2527,15 +2580,18 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
pipe = INVALID_PIPE;
- } else {
- pipe = INVALID_PIPE;
}
- if (pipe != INVALID_PIPE) {
+ if (intel_cdclk_can_crawl(dev_priv,
+ &old_cdclk_state->actual,
+ &new_cdclk_state->actual)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Can change cdclk via crawl\n");
+ } else if (pipe != INVALID_PIPE) {
new_cdclk_state->pipe = pipe;
drm_dbg_kms(&dev_priv->drm,
- "Can change cdclk with pipe %c active\n",
+ "Can change cdclk cd2x divider with pipe %c active\n",
pipe_name(pipe));
} else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
&new_cdclk_state->actual)) {
@@ -2544,8 +2600,6 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
if (ret)
return ret;
- new_cdclk_state->pipe = INVALID_PIPE;
-
drm_dbg_kms(&dev_priv->drm,
"Modeset required for cdclk change\n");
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3b58067a873c..1d1176d1799d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11157,6 +11157,8 @@ enum skl_power_gate {
#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
#define BXT_DE_PLL_LOCK (1 << 30)
+#define BXT_DE_PLL_FREQ_REQ (1 << 23)
+#define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
#define CNL_CDCLK_PLL_RATIO(x) (x)
#define CNL_CDCLK_PLL_RATIO_MASK 0xff
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-06-09 14:36 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-03 6:50 [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL Stanislav Lisovskiy
2021-06-03 7:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adl_p: CDCLK crawl support for ADL (rev2) Patchwork
2021-06-03 7:49 ` [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL Kahola, Mika
2021-06-03 9:16 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/adl_p: CDCLK crawl support for ADL (rev2) Patchwork
2021-06-09 14:36 ` [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL Jani Nikula
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2021-06-01 14:52 Stanislav Lisovskiy
2021-06-01 20:20 ` Matt Roper
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