From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: daniel.vetter@intel.com Subject: [PATCH 17/20] drm/i915/guc: Don't receive all G2H messages in irq handler Date: Wed, 2 Jun 2021 22:16:27 -0700 [thread overview] Message-ID: <20210603051630.2635-18-matthew.brost@intel.com> (raw) In-Reply-To: <20210603051630.2635-1-matthew.brost@intel.com> From: Michal Wajdeczko <michal.wajdeczko@intel.com> In irq handler try to receive just single G2H message, let other messages to be received from tasklet. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 67 ++++++++++++++++------- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 3 + 2 files changed, 50 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c index 372735c7f5e7..4fac9e4bced4 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c @@ -81,6 +81,7 @@ enum { CTB_SEND = 0, CTB_RECV = 1 }; enum { CTB_OWNER_HOST = 0 }; +static void ct_receive_tasklet_func(struct tasklet_struct *t); static void ct_incoming_request_worker_func(struct work_struct *w); /** @@ -95,6 +96,7 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct) INIT_LIST_HEAD(&ct->requests.pending); INIT_LIST_HEAD(&ct->requests.incoming); INIT_WORK(&ct->requests.worker, ct_incoming_request_worker_func); + tasklet_setup(&ct->receive_tasklet, ct_receive_tasklet_func); } static inline const char *guc_ct_buffer_type_to_str(u32 type) @@ -244,6 +246,7 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) { GEM_BUG_ON(ct->enabled); + tasklet_kill(&ct->receive_tasklet); i915_vma_unpin_and_release(&ct->vma, I915_VMA_RELEASE_MAP); memset(ct, 0, sizeof(*ct)); } @@ -654,7 +657,7 @@ static int ct_read(struct intel_guc_ct *ct, u32 *data) CT_DEBUG(ct, "received %*ph\n", 4 * len, data); desc->head = head * 4; - return 0; + return available - len; corrupted: CT_ERROR(ct, "Corrupted descriptor addr=%#x head=%u tail=%u size=%u\n", @@ -690,10 +693,10 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg) u32 status; u32 datalen; struct ct_request *req; + unsigned long flags; bool found = false; GEM_BUG_ON(!ct_header_is_response(header)); - GEM_BUG_ON(!in_irq()); /* Response payload shall at least include fence and status */ if (unlikely(len < 2)) { @@ -713,7 +716,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg) CT_DEBUG(ct, "response fence %u status %#x\n", fence, status); - spin_lock(&ct->requests.lock); + spin_lock_irqsave(&ct->requests.lock, flags); list_for_each_entry(req, &ct->requests.pending, link) { if (unlikely(fence != req->fence)) { CT_DEBUG(ct, "request %u awaits response\n", @@ -732,7 +735,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg) found = true; break; } - spin_unlock(&ct->requests.lock); + spin_unlock_irqrestore(&ct->requests.lock, flags); if (!found) CT_ERROR(ct, "Unsolicited response %*ph\n", msgsize, msg); @@ -846,31 +849,55 @@ static int ct_handle_request(struct intel_guc_ct *ct, const u32 *msg) return 0; } +static int ct_receive(struct intel_guc_ct *ct) +{ + u32 msg[GUC_CT_MSG_LEN_MASK + 1]; /* one extra dw for the header */ + unsigned long flags; + int ret; + + spin_lock_irqsave(&ct->ctbs.recv.lock, flags); + ret = ct_read(ct, msg); + spin_unlock_irqrestore(&ct->ctbs.recv.lock, flags); + if (ret < 0) + return ret; + + if (ct_header_is_response(msg[0])) + ct_handle_response(ct, msg); + else + ct_handle_request(ct, msg); + + return ret; +} + +static void ct_try_receive_message(struct intel_guc_ct *ct) +{ + int ret; + + if (GEM_WARN_ON(!ct->enabled)) + return; + + ret = ct_receive(ct); + if (ret > 0) + tasklet_hi_schedule(&ct->receive_tasklet); +} + +static void ct_receive_tasklet_func(struct tasklet_struct *t) +{ + struct intel_guc_ct *ct = from_tasklet(ct, t, receive_tasklet); + + ct_try_receive_message(ct); +} + /* * When we're communicating with the GuC over CT, GuC uses events * to notify us about new messages being posted on the RECV buffer. */ void intel_guc_ct_event_handler(struct intel_guc_ct *ct) { - u32 msg[GUC_CT_MSG_LEN_MASK + 1]; /* one extra dw for the header */ - unsigned long flags; - int err = 0; - if (unlikely(!ct->enabled)) { WARN(1, "Unexpected GuC event received while CT disabled!\n"); return; } - do { - spin_lock_irqsave(&ct->ctbs.recv.lock, flags); - err = ct_read(ct, msg); - spin_unlock_irqrestore(&ct->ctbs.recv.lock, flags); - if (err) - break; - - if (ct_header_is_response(msg[0])) - err = ct_handle_response(ct, msg); - else - err = ct_handle_request(ct, msg); - } while (!err); + ct_try_receive_message(ct); } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h index bc52dc479a14..cb222f202301 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h @@ -6,6 +6,7 @@ #ifndef _INTEL_GUC_CT_H_ #define _INTEL_GUC_CT_H_ +#include <linux/interrupt.h> #include <linux/spinlock.h> #include <linux/workqueue.h> @@ -55,6 +56,8 @@ struct intel_guc_ct { struct intel_guc_ct_buffer recv; } ctbs; + struct tasklet_struct receive_tasklet; + struct { u32 last_fence; /* last fence used to send request */ -- 2.28.0
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: daniel.vetter@intel.com Subject: [Intel-gfx] [PATCH 17/20] drm/i915/guc: Don't receive all G2H messages in irq handler Date: Wed, 2 Jun 2021 22:16:27 -0700 [thread overview] Message-ID: <20210603051630.2635-18-matthew.brost@intel.com> (raw) In-Reply-To: <20210603051630.2635-1-matthew.brost@intel.com> From: Michal Wajdeczko <michal.wajdeczko@intel.com> In irq handler try to receive just single G2H message, let other messages to be received from tasklet. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 67 ++++++++++++++++------- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 3 + 2 files changed, 50 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c index 372735c7f5e7..4fac9e4bced4 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c @@ -81,6 +81,7 @@ enum { CTB_SEND = 0, CTB_RECV = 1 }; enum { CTB_OWNER_HOST = 0 }; +static void ct_receive_tasklet_func(struct tasklet_struct *t); static void ct_incoming_request_worker_func(struct work_struct *w); /** @@ -95,6 +96,7 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct) INIT_LIST_HEAD(&ct->requests.pending); INIT_LIST_HEAD(&ct->requests.incoming); INIT_WORK(&ct->requests.worker, ct_incoming_request_worker_func); + tasklet_setup(&ct->receive_tasklet, ct_receive_tasklet_func); } static inline const char *guc_ct_buffer_type_to_str(u32 type) @@ -244,6 +246,7 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) { GEM_BUG_ON(ct->enabled); + tasklet_kill(&ct->receive_tasklet); i915_vma_unpin_and_release(&ct->vma, I915_VMA_RELEASE_MAP); memset(ct, 0, sizeof(*ct)); } @@ -654,7 +657,7 @@ static int ct_read(struct intel_guc_ct *ct, u32 *data) CT_DEBUG(ct, "received %*ph\n", 4 * len, data); desc->head = head * 4; - return 0; + return available - len; corrupted: CT_ERROR(ct, "Corrupted descriptor addr=%#x head=%u tail=%u size=%u\n", @@ -690,10 +693,10 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg) u32 status; u32 datalen; struct ct_request *req; + unsigned long flags; bool found = false; GEM_BUG_ON(!ct_header_is_response(header)); - GEM_BUG_ON(!in_irq()); /* Response payload shall at least include fence and status */ if (unlikely(len < 2)) { @@ -713,7 +716,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg) CT_DEBUG(ct, "response fence %u status %#x\n", fence, status); - spin_lock(&ct->requests.lock); + spin_lock_irqsave(&ct->requests.lock, flags); list_for_each_entry(req, &ct->requests.pending, link) { if (unlikely(fence != req->fence)) { CT_DEBUG(ct, "request %u awaits response\n", @@ -732,7 +735,7 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg) found = true; break; } - spin_unlock(&ct->requests.lock); + spin_unlock_irqrestore(&ct->requests.lock, flags); if (!found) CT_ERROR(ct, "Unsolicited response %*ph\n", msgsize, msg); @@ -846,31 +849,55 @@ static int ct_handle_request(struct intel_guc_ct *ct, const u32 *msg) return 0; } +static int ct_receive(struct intel_guc_ct *ct) +{ + u32 msg[GUC_CT_MSG_LEN_MASK + 1]; /* one extra dw for the header */ + unsigned long flags; + int ret; + + spin_lock_irqsave(&ct->ctbs.recv.lock, flags); + ret = ct_read(ct, msg); + spin_unlock_irqrestore(&ct->ctbs.recv.lock, flags); + if (ret < 0) + return ret; + + if (ct_header_is_response(msg[0])) + ct_handle_response(ct, msg); + else + ct_handle_request(ct, msg); + + return ret; +} + +static void ct_try_receive_message(struct intel_guc_ct *ct) +{ + int ret; + + if (GEM_WARN_ON(!ct->enabled)) + return; + + ret = ct_receive(ct); + if (ret > 0) + tasklet_hi_schedule(&ct->receive_tasklet); +} + +static void ct_receive_tasklet_func(struct tasklet_struct *t) +{ + struct intel_guc_ct *ct = from_tasklet(ct, t, receive_tasklet); + + ct_try_receive_message(ct); +} + /* * When we're communicating with the GuC over CT, GuC uses events * to notify us about new messages being posted on the RECV buffer. */ void intel_guc_ct_event_handler(struct intel_guc_ct *ct) { - u32 msg[GUC_CT_MSG_LEN_MASK + 1]; /* one extra dw for the header */ - unsigned long flags; - int err = 0; - if (unlikely(!ct->enabled)) { WARN(1, "Unexpected GuC event received while CT disabled!\n"); return; } - do { - spin_lock_irqsave(&ct->ctbs.recv.lock, flags); - err = ct_read(ct, msg); - spin_unlock_irqrestore(&ct->ctbs.recv.lock, flags); - if (err) - break; - - if (ct_header_is_response(msg[0])) - err = ct_handle_response(ct, msg); - else - err = ct_handle_request(ct, msg); - } while (!err); + ct_try_receive_message(ct); } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h index bc52dc479a14..cb222f202301 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h @@ -6,6 +6,7 @@ #ifndef _INTEL_GUC_CT_H_ #define _INTEL_GUC_CT_H_ +#include <linux/interrupt.h> #include <linux/spinlock.h> #include <linux/workqueue.h> @@ -55,6 +56,8 @@ struct intel_guc_ct { struct intel_guc_ct_buffer recv; } ctbs; + struct tasklet_struct receive_tasklet; + struct { u32 last_fence; /* last fence used to send request */ -- 2.28.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-06-03 4:59 UTC|newest] Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-03 5:16 [PATCH 00/20] GuC CTBs changes + a few misc patches Matthew Brost 2021-06-03 5:16 ` [Intel-gfx] " Matthew Brost 2021-06-03 5:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork 2021-06-03 5:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-06-03 5:16 ` [PATCH 01/20] drm/i915/guc: skip disabling CTBs before sanitizing the GuC Matthew Brost 2021-06-03 5:16 ` [Intel-gfx] " Matthew Brost 2021-06-03 5:16 ` [PATCH 02/20] drm/i915/guc: use probe_error log for CT enablement failure Matthew Brost 2021-06-03 5:16 ` [Intel-gfx] " Matthew Brost 2021-06-03 5:16 ` [PATCH 03/20] drm/i915/guc: enable only the user interrupt when using GuC submission Matthew Brost 2021-06-03 5:16 ` [Intel-gfx] " Matthew Brost 2021-06-03 5:16 ` [PATCH 04/20] drm/i915/guc: Remove sample_forcewake h2g action Matthew Brost 2021-06-03 5:16 ` [Intel-gfx] " Matthew Brost 2021-06-03 5:16 ` [PATCH 05/20] drm/i915/guc: Keep strict GuC ABI definitions Matthew Brost 2021-06-03 5:16 ` [Intel-gfx] " Matthew Brost 2021-06-03 5:16 ` [PATCH 06/20] drm/i915/guc: Drop guc->interrupts.enabled Matthew Brost 2021-06-03 5:16 ` [Intel-gfx] " Matthew Brost 2021-06-03 5:16 ` [PATCH 07/20] drm/i915/guc: Stop using fence/status from CTB descriptor Matthew Brost 2021-06-03 5:16 ` [Intel-gfx] " Matthew Brost 2021-06-03 5:16 ` [PATCH 08/20] drm/i915: Promote ptrdiff() to i915_utils.h Matthew Brost 2021-06-03 5:16 ` [Intel-gfx] " Matthew Brost 2021-06-03 21:35 ` Daniel Vetter 2021-06-03 21:35 ` [Intel-gfx] " Daniel Vetter 2021-06-04 2:02 ` Matthew Brost 2021-06-04 2:02 ` [Intel-gfx] " Matthew Brost 2021-06-04 8:11 ` Daniel Vetter 2021-06-04 8:11 ` [Intel-gfx] " Daniel Vetter 2021-06-03 5:16 ` [PATCH 09/20] drm/i915/guc: Only rely on own CTB size Matthew Brost 2021-06-03 5:16 ` [Intel-gfx] " Matthew Brost 2021-06-03 5:16 ` [PATCH 10/20] drm/i915/guc: Don't repeat CTB layout calculations Matthew Brost 2021-06-03 5:16 ` [Intel-gfx] " Matthew Brost 2021-06-03 5:16 ` [PATCH 11/20] drm/i915/guc: Replace CTB array with explicit members Matthew Brost 2021-06-03 5:16 ` [Intel-gfx] " Matthew Brost 2021-06-03 7:25 ` kernel test robot 2021-06-03 7:25 ` kernel test robot 2021-06-03 7:25 ` [Intel-gfx] " kernel test robot 2021-06-03 21:37 ` Daniel Vetter 2021-06-03 21:37 ` Daniel Vetter 2021-06-03 21:37 ` Daniel Vetter 2021-06-03 22:44 ` [PATCH 1/2] " Matthew Brost 2021-06-03 22:44 ` [Intel-gfx] " Matthew Brost 2021-06-03 22:44 ` [PATCH 2/2] drm/i915/guc: Update sizes of CTB buffers Matthew Brost 2021-06-03 22:44 ` [Intel-gfx] " Matthew Brost 2021-06-03 23:04 ` [v3 PATCH 1/2] drm/i915/guc: Replace CTB array with explicit members Matthew Brost 2021-06-03 23:04 ` [Intel-gfx] " Matthew Brost 2021-06-03 23:04 ` [v3 PATCH 2/2] drm/i915/guc: Update sizes of CTB buffers Matthew Brost 2021-06-03 23:04 ` [Intel-gfx] " Matthew Brost 2021-06-04 8:20 ` Daniel Vetter 2021-06-04 8:20 ` [Intel-gfx] " Daniel Vetter 2021-06-04 8:49 ` Michal Wajdeczko 2021-06-04 8:49 ` [Intel-gfx] " Michal Wajdeczko 2021-06-03 5:16 ` [PATCH 12/20] " Matthew Brost 2021-06-03 5:16 ` [Intel-gfx] " Matthew Brost 2021-06-03 5:16 ` [PATCH 13/20] drm/i915/guc: Relax CTB response timeout Matthew Brost 2021-06-03 5:16 ` [Intel-gfx] " Matthew Brost 2021-06-04 8:33 ` Daniel Vetter 2021-06-04 8:33 ` Daniel Vetter 2021-06-04 18:35 ` Matthew Brost 2021-06-04 18:35 ` Matthew Brost 2021-06-09 13:24 ` Daniel Vetter 2021-06-09 13:24 ` Daniel Vetter 2021-06-03 5:16 ` [PATCH 14/20] drm/i915/guc: Start protecting access to CTB descriptors Matthew Brost 2021-06-03 5:16 ` [Intel-gfx] " Matthew Brost 2021-06-04 8:35 ` Daniel Vetter 2021-06-04 8:35 ` [Intel-gfx] " Daniel Vetter 2021-06-03 5:16 ` [PATCH 15/20] drm/i915/guc: Ensure H2G buffer updates visible before tail update Matthew Brost 2021-06-03 5:16 ` [Intel-gfx] " Matthew Brost 2021-06-03 9:44 ` Michal Wajdeczko 2021-06-03 9:44 ` Michal Wajdeczko 2021-06-03 16:10 ` Matthew Brost 2021-06-03 16:10 ` Matthew Brost 2021-06-04 8:39 ` Daniel Vetter 2021-06-04 8:39 ` Daniel Vetter 2021-06-03 5:16 ` [PATCH 16/20] drm/i915/guc: Stop using mutex while sending CTB messages Matthew Brost 2021-06-03 5:16 ` [Intel-gfx] " Matthew Brost 2021-06-03 5:16 ` Matthew Brost [this message] 2021-06-03 5:16 ` [Intel-gfx] [PATCH 17/20] drm/i915/guc: Don't receive all G2H messages in irq handler Matthew Brost 2021-06-03 5:16 ` [PATCH 18/20] drm/i915/guc: Always copy CT message to new allocation Matthew Brost 2021-06-03 5:16 ` [Intel-gfx] " Matthew Brost 2021-06-03 5:16 ` [PATCH 19/20] drm/i915/guc: Early initialization of GuC send registers Matthew Brost 2021-06-03 5:16 ` [Intel-gfx] " Matthew Brost 2021-06-03 5:16 ` [PATCH 20/20] drm/i915/guc: Use guc_class instead of engine_class in fw interface Matthew Brost 2021-06-03 5:16 ` [Intel-gfx] " Matthew Brost 2021-06-04 8:44 ` Daniel Vetter 2021-06-04 8:44 ` [Intel-gfx] " Daniel Vetter 2021-06-04 18:12 ` Matthew Brost 2021-06-04 18:12 ` [Intel-gfx] " Matthew Brost 2021-06-03 5:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success for GuC CTBs changes + a few misc patches Patchwork 2021-06-03 6:50 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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