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From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>
Cc: daniel.vetter@intel.com
Subject: [PATCH 19/20] drm/i915/guc: Early initialization of GuC send registers
Date: Wed,  2 Jun 2021 22:16:29 -0700	[thread overview]
Message-ID: <20210603051630.2635-20-matthew.brost@intel.com> (raw)
In-Reply-To: <20210603051630.2635-1-matthew.brost@intel.com>

From: Michal Wajdeczko <michal.wajdeczko@intel.com>

Base offset and count of the GuC scratch registers, used for
sending MMIO messages to GuC, can be initialized earlier with
other GuC members that also depends on platform.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 18da9ed15728..fcfa4fd93841 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -60,15 +60,8 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
 	enum forcewake_domains fw_domains = 0;
 	unsigned int i;
 
-	if (INTEL_GEN(gt->i915) >= 11) {
-		guc->send_regs.base =
-				i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
-		guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
-	} else {
-		guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
-		guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
-		BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
-	}
+	GEM_BUG_ON(!guc->send_regs.base);
+	GEM_BUG_ON(!guc->send_regs.count);
 
 	for (i = 0; i < guc->send_regs.count; i++) {
 		fw_domains |= intel_uncore_forcewake_for_reg(gt->uncore,
@@ -172,11 +165,18 @@ void intel_guc_init_early(struct intel_guc *guc)
 		guc->interrupts.reset = gen11_reset_guc_interrupts;
 		guc->interrupts.enable = gen11_enable_guc_interrupts;
 		guc->interrupts.disable = gen11_disable_guc_interrupts;
+		guc->send_regs.base =
+			i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
+		guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
+
 	} else {
 		guc->notify_reg = GUC_SEND_INTERRUPT;
 		guc->interrupts.reset = gen9_reset_guc_interrupts;
 		guc->interrupts.enable = gen9_enable_guc_interrupts;
 		guc->interrupts.disable = gen9_disable_guc_interrupts;
+		guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
+		guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
+		BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
 	}
 }
 
-- 
2.28.0


WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>
Cc: daniel.vetter@intel.com
Subject: [Intel-gfx] [PATCH 19/20] drm/i915/guc: Early initialization of GuC send registers
Date: Wed,  2 Jun 2021 22:16:29 -0700	[thread overview]
Message-ID: <20210603051630.2635-20-matthew.brost@intel.com> (raw)
In-Reply-To: <20210603051630.2635-1-matthew.brost@intel.com>

From: Michal Wajdeczko <michal.wajdeczko@intel.com>

Base offset and count of the GuC scratch registers, used for
sending MMIO messages to GuC, can be initialized earlier with
other GuC members that also depends on platform.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 18da9ed15728..fcfa4fd93841 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -60,15 +60,8 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
 	enum forcewake_domains fw_domains = 0;
 	unsigned int i;
 
-	if (INTEL_GEN(gt->i915) >= 11) {
-		guc->send_regs.base =
-				i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
-		guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
-	} else {
-		guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
-		guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
-		BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
-	}
+	GEM_BUG_ON(!guc->send_regs.base);
+	GEM_BUG_ON(!guc->send_regs.count);
 
 	for (i = 0; i < guc->send_regs.count; i++) {
 		fw_domains |= intel_uncore_forcewake_for_reg(gt->uncore,
@@ -172,11 +165,18 @@ void intel_guc_init_early(struct intel_guc *guc)
 		guc->interrupts.reset = gen11_reset_guc_interrupts;
 		guc->interrupts.enable = gen11_enable_guc_interrupts;
 		guc->interrupts.disable = gen11_disable_guc_interrupts;
+		guc->send_regs.base =
+			i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
+		guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
+
 	} else {
 		guc->notify_reg = GUC_SEND_INTERRUPT;
 		guc->interrupts.reset = gen9_reset_guc_interrupts;
 		guc->interrupts.enable = gen9_enable_guc_interrupts;
 		guc->interrupts.disable = gen9_disable_guc_interrupts;
+		guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
+		guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
+		BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
 	}
 }
 
-- 
2.28.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2021-06-03  4:59 UTC|newest]

Thread overview: 88+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-03  5:16 [PATCH 00/20] GuC CTBs changes + a few misc patches Matthew Brost
2021-06-03  5:16 ` [Intel-gfx] " Matthew Brost
2021-06-03  5:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2021-06-03  5:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-06-03  5:16 ` [PATCH 01/20] drm/i915/guc: skip disabling CTBs before sanitizing the GuC Matthew Brost
2021-06-03  5:16   ` [Intel-gfx] " Matthew Brost
2021-06-03  5:16 ` [PATCH 02/20] drm/i915/guc: use probe_error log for CT enablement failure Matthew Brost
2021-06-03  5:16   ` [Intel-gfx] " Matthew Brost
2021-06-03  5:16 ` [PATCH 03/20] drm/i915/guc: enable only the user interrupt when using GuC submission Matthew Brost
2021-06-03  5:16   ` [Intel-gfx] " Matthew Brost
2021-06-03  5:16 ` [PATCH 04/20] drm/i915/guc: Remove sample_forcewake h2g action Matthew Brost
2021-06-03  5:16   ` [Intel-gfx] " Matthew Brost
2021-06-03  5:16 ` [PATCH 05/20] drm/i915/guc: Keep strict GuC ABI definitions Matthew Brost
2021-06-03  5:16   ` [Intel-gfx] " Matthew Brost
2021-06-03  5:16 ` [PATCH 06/20] drm/i915/guc: Drop guc->interrupts.enabled Matthew Brost
2021-06-03  5:16   ` [Intel-gfx] " Matthew Brost
2021-06-03  5:16 ` [PATCH 07/20] drm/i915/guc: Stop using fence/status from CTB descriptor Matthew Brost
2021-06-03  5:16   ` [Intel-gfx] " Matthew Brost
2021-06-03  5:16 ` [PATCH 08/20] drm/i915: Promote ptrdiff() to i915_utils.h Matthew Brost
2021-06-03  5:16   ` [Intel-gfx] " Matthew Brost
2021-06-03 21:35   ` Daniel Vetter
2021-06-03 21:35     ` [Intel-gfx] " Daniel Vetter
2021-06-04  2:02     ` Matthew Brost
2021-06-04  2:02       ` [Intel-gfx] " Matthew Brost
2021-06-04  8:11       ` Daniel Vetter
2021-06-04  8:11         ` [Intel-gfx] " Daniel Vetter
2021-06-03  5:16 ` [PATCH 09/20] drm/i915/guc: Only rely on own CTB size Matthew Brost
2021-06-03  5:16   ` [Intel-gfx] " Matthew Brost
2021-06-03  5:16 ` [PATCH 10/20] drm/i915/guc: Don't repeat CTB layout calculations Matthew Brost
2021-06-03  5:16   ` [Intel-gfx] " Matthew Brost
2021-06-03  5:16 ` [PATCH 11/20] drm/i915/guc: Replace CTB array with explicit members Matthew Brost
2021-06-03  5:16   ` [Intel-gfx] " Matthew Brost
2021-06-03  7:25   ` kernel test robot
2021-06-03  7:25     ` kernel test robot
2021-06-03  7:25     ` [Intel-gfx] " kernel test robot
2021-06-03 21:37     ` Daniel Vetter
2021-06-03 21:37       ` Daniel Vetter
2021-06-03 21:37       ` Daniel Vetter
2021-06-03 22:44       ` [PATCH 1/2] " Matthew Brost
2021-06-03 22:44         ` [Intel-gfx] " Matthew Brost
2021-06-03 22:44         ` [PATCH 2/2] drm/i915/guc: Update sizes of CTB buffers Matthew Brost
2021-06-03 22:44           ` [Intel-gfx] " Matthew Brost
2021-06-03 23:04       ` [v3 PATCH 1/2] drm/i915/guc: Replace CTB array with explicit members Matthew Brost
2021-06-03 23:04         ` [Intel-gfx] " Matthew Brost
2021-06-03 23:04         ` [v3 PATCH 2/2] drm/i915/guc: Update sizes of CTB buffers Matthew Brost
2021-06-03 23:04           ` [Intel-gfx] " Matthew Brost
2021-06-04  8:20           ` Daniel Vetter
2021-06-04  8:20             ` [Intel-gfx] " Daniel Vetter
2021-06-04  8:49             ` Michal Wajdeczko
2021-06-04  8:49               ` [Intel-gfx] " Michal Wajdeczko
2021-06-03  5:16 ` [PATCH 12/20] " Matthew Brost
2021-06-03  5:16   ` [Intel-gfx] " Matthew Brost
2021-06-03  5:16 ` [PATCH 13/20] drm/i915/guc: Relax CTB response timeout Matthew Brost
2021-06-03  5:16   ` [Intel-gfx] " Matthew Brost
2021-06-04  8:33   ` Daniel Vetter
2021-06-04  8:33     ` Daniel Vetter
2021-06-04 18:35     ` Matthew Brost
2021-06-04 18:35       ` Matthew Brost
2021-06-09 13:24       ` Daniel Vetter
2021-06-09 13:24         ` Daniel Vetter
2021-06-03  5:16 ` [PATCH 14/20] drm/i915/guc: Start protecting access to CTB descriptors Matthew Brost
2021-06-03  5:16   ` [Intel-gfx] " Matthew Brost
2021-06-04  8:35   ` Daniel Vetter
2021-06-04  8:35     ` [Intel-gfx] " Daniel Vetter
2021-06-03  5:16 ` [PATCH 15/20] drm/i915/guc: Ensure H2G buffer updates visible before tail update Matthew Brost
2021-06-03  5:16   ` [Intel-gfx] " Matthew Brost
2021-06-03  9:44   ` Michal Wajdeczko
2021-06-03  9:44     ` Michal Wajdeczko
2021-06-03 16:10     ` Matthew Brost
2021-06-03 16:10       ` Matthew Brost
2021-06-04  8:39       ` Daniel Vetter
2021-06-04  8:39         ` Daniel Vetter
2021-06-03  5:16 ` [PATCH 16/20] drm/i915/guc: Stop using mutex while sending CTB messages Matthew Brost
2021-06-03  5:16   ` [Intel-gfx] " Matthew Brost
2021-06-03  5:16 ` [PATCH 17/20] drm/i915/guc: Don't receive all G2H messages in irq handler Matthew Brost
2021-06-03  5:16   ` [Intel-gfx] " Matthew Brost
2021-06-03  5:16 ` [PATCH 18/20] drm/i915/guc: Always copy CT message to new allocation Matthew Brost
2021-06-03  5:16   ` [Intel-gfx] " Matthew Brost
2021-06-03  5:16 ` Matthew Brost [this message]
2021-06-03  5:16   ` [Intel-gfx] [PATCH 19/20] drm/i915/guc: Early initialization of GuC send registers Matthew Brost
2021-06-03  5:16 ` [PATCH 20/20] drm/i915/guc: Use guc_class instead of engine_class in fw interface Matthew Brost
2021-06-03  5:16   ` [Intel-gfx] " Matthew Brost
2021-06-04  8:44   ` Daniel Vetter
2021-06-04  8:44     ` [Intel-gfx] " Daniel Vetter
2021-06-04 18:12     ` Matthew Brost
2021-06-04 18:12       ` [Intel-gfx] " Matthew Brost
2021-06-03  5:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success for GuC CTBs changes + a few misc patches Patchwork
2021-06-03  6:50 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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