From: Christoph Hellwig <hch@lst.de> To: guoren@kernel.org Cc: anup.patel@wdc.com, palmerdabbelt@google.com, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, drew@beagleboard.org, liush@allwinnertech.com, lazyparser@gmail.com, wefu@redhat.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-sunxi@lists.linux.dev, Guo Ren <guoren@linux.alibaba.com>, Christoph Hellwig <hch@lst.de> Subject: Re: [PATCH V5 2/3] riscv: Add ASID-based tlbflushing methods Date: Sun, 6 Jun 2021 16:38:48 +0200 [thread overview] Message-ID: <20210606143848.GA5983@lst.de> (raw) In-Reply-To: <1622970249-50770-4-git-send-email-guoren@kernel.org> On Sun, Jun 06, 2021 at 09:03:58AM +0000, guoren@kernel.org wrote: > +static inline void local_flush_tlb_all_asid(unsigned long asid) > +{ > + __asm__ __volatile__ ("sfence.vma x0, %0" > + : > + : "r" (asid) > + : "memory"); > +} > + > +static inline void local_flush_tlb_range_asid(unsigned long start, > + unsigned long size, unsigned long asid) > +{ > + unsigned long tmp, end = ALIGN(start + size, PAGE_SIZE); > + > + for (tmp = start & PAGE_MASK; tmp < end; tmp += PAGE_SIZE) { > + __asm__ __volatile__ ("sfence.vma %0, %1" > + : > + : "r" (tmp), "r" (asid) > + : "memory"); > + } No need to expose these in a header. > +static void __sbi_tlb_flush_range_asid(struct cpumask *cmask, > + unsigned long start, > + unsigned long size, > + unsigned long asid) > +{ > + struct cpumask hmask; > + unsigned int cpuid; > + > + if (cpumask_empty(cmask)) > + return; > + > + cpuid = get_cpu(); > + > + if (cpumask_any_but(cmask, cpuid) >= nr_cpu_ids) { > + if (size == -1) > + local_flush_tlb_all_asid(asid); > + else > + local_flush_tlb_range_asid(start, size, asid); > + } else { > + riscv_cpuid_to_hartid_mask(cmask, &hmask); > + sbi_remote_sfence_vma_asid(cpumask_bits(&hmask), > + start, size, asid); > + } > + > + put_cpu(); > +} Still no need to duplicate most of this logic. Also please document why this uses a different tradeoff for the flush all logic compared to the non-ASID path. > + > void flush_tlb_mm(struct mm_struct *mm) > { > - __sbi_tlb_flush_range(mm_cpumask(mm), 0, -1); > + if (static_branch_unlikely(&use_asid_allocator)) > + __sbi_tlb_flush_range_asid(mm_cpumask(mm), 0, -1, > + atomic_long_read(&mm->context.id)); > + else > + __sbi_tlb_flush_range(mm_cpumask(mm), 0, -1); > } > > void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) > { > - __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE); > + if (static_branch_unlikely(&use_asid_allocator)) > + __sbi_tlb_flush_range_asid(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE, > + atomic_long_read(&vma->vm_mm->context.id)); > + else > + __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE); > } > > void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, > unsigned long end) > { > - __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), start, end - start); > + if (static_branch_unlikely(&use_asid_allocator)) > + __sbi_tlb_flush_range_asid(mm_cpumask(vma->vm_mm), start, end - start, > + atomic_long_read(&vma->vm_mm->context.id)); > + else > + __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), start, end - start); Various overly long lines (which are trivially avoided when doing the right thing from the beginning).
WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de> To: guoren@kernel.org Cc: anup.patel@wdc.com, palmerdabbelt@google.com, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, drew@beagleboard.org, liush@allwinnertech.com, lazyparser@gmail.com, wefu@redhat.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-sunxi@lists.linux.dev, Guo Ren <guoren@linux.alibaba.com>, Christoph Hellwig <hch@lst.de> Subject: Re: [PATCH V5 2/3] riscv: Add ASID-based tlbflushing methods Date: Sun, 6 Jun 2021 16:38:48 +0200 [thread overview] Message-ID: <20210606143848.GA5983@lst.de> (raw) In-Reply-To: <1622970249-50770-4-git-send-email-guoren@kernel.org> On Sun, Jun 06, 2021 at 09:03:58AM +0000, guoren@kernel.org wrote: > +static inline void local_flush_tlb_all_asid(unsigned long asid) > +{ > + __asm__ __volatile__ ("sfence.vma x0, %0" > + : > + : "r" (asid) > + : "memory"); > +} > + > +static inline void local_flush_tlb_range_asid(unsigned long start, > + unsigned long size, unsigned long asid) > +{ > + unsigned long tmp, end = ALIGN(start + size, PAGE_SIZE); > + > + for (tmp = start & PAGE_MASK; tmp < end; tmp += PAGE_SIZE) { > + __asm__ __volatile__ ("sfence.vma %0, %1" > + : > + : "r" (tmp), "r" (asid) > + : "memory"); > + } No need to expose these in a header. > +static void __sbi_tlb_flush_range_asid(struct cpumask *cmask, > + unsigned long start, > + unsigned long size, > + unsigned long asid) > +{ > + struct cpumask hmask; > + unsigned int cpuid; > + > + if (cpumask_empty(cmask)) > + return; > + > + cpuid = get_cpu(); > + > + if (cpumask_any_but(cmask, cpuid) >= nr_cpu_ids) { > + if (size == -1) > + local_flush_tlb_all_asid(asid); > + else > + local_flush_tlb_range_asid(start, size, asid); > + } else { > + riscv_cpuid_to_hartid_mask(cmask, &hmask); > + sbi_remote_sfence_vma_asid(cpumask_bits(&hmask), > + start, size, asid); > + } > + > + put_cpu(); > +} Still no need to duplicate most of this logic. Also please document why this uses a different tradeoff for the flush all logic compared to the non-ASID path. > + > void flush_tlb_mm(struct mm_struct *mm) > { > - __sbi_tlb_flush_range(mm_cpumask(mm), 0, -1); > + if (static_branch_unlikely(&use_asid_allocator)) > + __sbi_tlb_flush_range_asid(mm_cpumask(mm), 0, -1, > + atomic_long_read(&mm->context.id)); > + else > + __sbi_tlb_flush_range(mm_cpumask(mm), 0, -1); > } > > void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) > { > - __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE); > + if (static_branch_unlikely(&use_asid_allocator)) > + __sbi_tlb_flush_range_asid(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE, > + atomic_long_read(&vma->vm_mm->context.id)); > + else > + __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE); > } > > void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, > unsigned long end) > { > - __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), start, end - start); > + if (static_branch_unlikely(&use_asid_allocator)) > + __sbi_tlb_flush_range_asid(mm_cpumask(vma->vm_mm), start, end - start, > + atomic_long_read(&vma->vm_mm->context.id)); > + else > + __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), start, end - start); Various overly long lines (which are trivially avoided when doing the right thing from the beginning). _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-06-06 14:38 UTC|newest] Thread overview: 113+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-06 9:03 [RFC PATCH v2 00/11] riscv: Add DMA_COHERENT support for Allwinner D1 guoren 2021-06-06 9:03 ` guoren 2021-06-06 9:03 ` [RFC PATCH v2 01/11] riscv: asid: Use global mappings for kernel pages guoren 2021-06-06 9:03 ` guoren 2021-06-06 9:03 ` [PATCH V5 1/3] riscv: " guoren 2021-06-06 9:03 ` guoren 2021-06-06 9:03 ` [PATCH V5 2/3] riscv: Add ASID-based tlbflushing methods guoren 2021-06-06 9:03 ` guoren 2021-06-06 14:38 ` Christoph Hellwig [this message] 2021-06-06 14:38 ` Christoph Hellwig 2021-06-06 9:03 ` [RFC PATCH v2 02/11] riscv: asid: " guoren 2021-06-06 9:03 ` guoren 2021-06-06 9:04 ` [RFC PATCH v2 03/11] riscv: asid: Optimize tlbflush coding convention guoren 2021-06-06 9:04 ` guoren 2021-06-06 9:04 ` [PATCH V5 3/3] riscv: tlbflush: Optimize " guoren 2021-06-06 9:04 ` guoren 2021-06-06 9:04 ` [RFC PATCH v2 04/11] riscv: pgtable: Fixup _PAGE_CHG_MASK usage guoren 2021-06-06 9:04 ` guoren 2021-06-06 9:04 ` [RFC PATCH v2 05/11] riscv: pgtable: Add custom protection_map init guoren 2021-06-06 9:04 ` guoren 2021-06-06 9:04 ` [RFC PATCH v2 06/11] riscv: pgtable: Add DMA_COHERENT with custom PTE attributes guoren 2021-06-06 9:04 ` guoren 2021-06-06 14:39 ` Christoph Hellwig 2021-06-06 14:39 ` Christoph Hellwig 2021-06-06 15:08 ` Guo Ren 2021-06-06 15:08 ` Guo Ren 2021-06-06 17:22 ` Nick Kossifidis 2021-06-06 17:22 ` Nick Kossifidis 2021-06-07 6:19 ` Christoph Hellwig 2021-06-07 6:19 ` Christoph Hellwig 2021-06-06 9:04 ` [RFC PATCH v2 07/11] riscv: cmo: Add dma-noncoherency support guoren 2021-06-06 9:04 ` guoren 2021-10-17 9:28 ` twd2 2021-10-17 9:28 ` twd2 2021-10-20 8:11 ` Guo Ren 2021-10-20 8:11 ` Guo Ren 2021-06-06 9:04 ` [RFC PATCH v2 08/11] riscv: cmo: Add vendor custom icache sync guoren 2021-06-06 9:04 ` guoren 2021-06-06 9:04 ` [RFC PATCH v2 09/11] riscv: soc: Initial DTS for Allwinner D1 NeZha board guoren 2021-06-06 9:04 ` guoren 2021-06-06 16:26 ` Jernej Škrabec 2021-06-06 16:26 ` Jernej Škrabec 2021-06-06 17:05 ` Guo Ren 2021-06-06 17:05 ` Guo Ren 2021-06-07 3:44 ` Guo Ren 2021-06-07 3:44 ` Guo Ren 2021-06-07 7:27 ` Maxime Ripard 2021-06-07 7:27 ` Maxime Ripard 2021-06-07 7:53 ` Guo Ren 2021-06-07 7:53 ` Guo Ren 2021-06-07 7:24 ` Maxime Ripard 2021-06-07 7:24 ` Maxime Ripard 2021-06-07 8:07 ` Guo Ren 2021-06-07 8:07 ` Guo Ren 2021-06-14 15:33 ` Maxime Ripard 2021-06-14 15:33 ` Maxime Ripard 2021-06-14 16:28 ` Guo Ren 2021-06-14 16:28 ` Guo Ren 2021-06-14 16:31 ` Jernej Škrabec 2021-06-14 16:31 ` Jernej Škrabec 2021-06-06 9:04 ` [RFC PATCH v2 10/11] riscv: soc: Add Allwinner SoC kconfig option guoren 2021-06-06 9:04 ` guoren 2021-06-07 7:19 ` Maxime Ripard 2021-06-07 7:19 ` Maxime Ripard 2021-06-07 7:27 ` Arnd Bergmann 2021-06-07 7:27 ` Arnd Bergmann 2021-06-07 7:27 ` Arnd Bergmann 2021-06-07 7:45 ` Guo Ren 2021-06-07 7:45 ` Guo Ren 2021-06-07 7:43 ` Guo Ren 2021-06-07 7:43 ` Guo Ren 2021-06-07 12:12 ` Maxime Ripard 2021-06-07 12:12 ` Maxime Ripard 2021-06-07 12:39 ` Guo Ren 2021-06-07 12:39 ` Guo Ren 2021-06-06 9:04 ` [RFC PATCH v2 11/11] riscv: soc: Allwinner D1 GMAC driver only for temp use guoren 2021-06-06 9:04 ` guoren 2021-06-06 10:50 ` Andre Przywara 2021-06-06 10:50 ` Andre Przywara 2021-06-06 15:32 ` Guo Ren 2021-06-06 15:32 ` Guo Ren 2021-06-06 15:39 ` Jernej Škrabec 2021-06-06 15:39 ` Jernej Škrabec 2021-06-06 15:41 ` Guo Ren 2021-06-06 15:41 ` Guo Ren 2021-06-06 16:16 ` Arnd Bergmann 2021-06-06 16:16 ` Arnd Bergmann 2021-06-06 16:16 ` Arnd Bergmann 2021-06-06 16:32 ` Jernej Škrabec 2021-06-06 16:32 ` Jernej Škrabec 2021-06-06 16:53 ` Guo Ren 2021-06-06 16:53 ` Guo Ren 2021-06-06 16:53 ` Guo Ren 2021-06-06 16:53 ` Guo Ren 2021-06-06 16:29 ` [RFC PATCH v2 00/11] riscv: Add DMA_COHERENT support for Allwinner D1 Jernej Škrabec 2021-06-06 16:29 ` Jernej Škrabec 2021-06-06 16:54 ` Guo Ren 2021-06-06 16:54 ` Guo Ren 2021-06-06 17:14 ` Jernej Škrabec 2021-06-06 17:14 ` Jernej Škrabec 2021-06-06 23:42 ` Guo Ren 2021-06-06 23:42 ` Guo Ren 2021-06-07 3:44 ` Anup Patel 2021-06-07 3:44 ` Anup Patel 2021-06-07 4:36 ` Guo Ren 2021-06-07 4:36 ` Guo Ren 2021-06-07 4:36 ` Guo Ren -- strict thread matches above, loose matches on Subject: below -- 2021-05-30 16:49 [PATCH V5 0/3] riscv: Fixup asid_allocator remaining issues guoren 2021-05-30 16:49 ` [PATCH V5 2/3] riscv: Add ASID-based tlbflushing methods guoren 2021-05-30 16:49 ` guoren 2021-05-31 6:17 ` Christoph Hellwig 2021-05-31 6:17 ` Christoph Hellwig 2021-05-31 12:20 ` Guo Ren 2021-05-31 12:20 ` Guo Ren
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