From: "Thomas Hellström" <thomas.hellstrom@linux.intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: matthew.auld@intel.com, Chris Wilson <chris@chris-wilson.co.uk> Subject: [PATCH 5/9] drm/i915/gt: Add a routine to iterate over the pagetables of a GTT Date: Tue, 8 Jun 2021 11:28:42 +0200 [thread overview] Message-ID: <20210608092846.64198-6-thomas.hellstrom@linux.intel.com> (raw) In-Reply-To: <20210608092846.64198-1-thomas.hellstrom@linux.intel.com> From: Chris Wilson <chris@chris-wilson.co.uk> In the next patch, we will want to look at the dma addresses of individual page tables, so add a routine to iterate over them. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 49 ++++++++++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gtt.h | 7 ++++ 2 files changed, 56 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c index 1b676d7700bf..3d02c726c746 100644 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c @@ -361,6 +361,54 @@ static void gen8_ppgtt_alloc(struct i915_address_space *vm, &start, start + length, vm->top); } +static void __gen8_ppgtt_foreach(struct i915_address_space *vm, + struct i915_page_directory *pd, + u64 *start, u64 end, int lvl, + void (*fn)(struct i915_address_space *vm, + struct i915_page_table *pt, + void *data), + void *data) +{ + unsigned int idx, len; + + len = gen8_pd_range(*start, end, lvl--, &idx); + + spin_lock(&pd->lock); + do { + struct i915_page_table *pt = pd->entry[idx]; + + atomic_inc(&pt->used); + spin_unlock(&pd->lock); + + if (lvl) { + __gen8_ppgtt_foreach(vm, as_pd(pt), start, end, lvl, + fn, data); + } else { + fn(vm, pt, data); + *start += gen8_pt_count(*start, end); + } + + spin_lock(&pd->lock); + atomic_dec(&pt->used); + } while (idx++, --len); + spin_unlock(&pd->lock); +} + +static void gen8_ppgtt_foreach(struct i915_address_space *vm, + u64 start, u64 length, + void (*fn)(struct i915_address_space *vm, + struct i915_page_table *pt, + void *data), + void *data) +{ + start >>= GEN8_PTE_SHIFT; + length >>= GEN8_PTE_SHIFT; + + __gen8_ppgtt_foreach(vm, i915_vm_to_ppgtt(vm)->pd, + &start, start + length, vm->top, + fn, data); +} + static __always_inline u64 gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt, struct i915_page_directory *pdp, @@ -755,6 +803,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt) ppgtt->vm.insert_page = gen8_ppgtt_insert_entry; ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc; ppgtt->vm.clear_range = gen8_ppgtt_clear; + ppgtt->vm.foreach = gen8_ppgtt_foreach; ppgtt->vm.pte_encode = gen8_pte_encode; diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index edea95b97c36..9bd89f2a01ff 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -296,6 +296,13 @@ struct i915_address_space { u32 flags); void (*cleanup)(struct i915_address_space *vm); + void (*foreach)(struct i915_address_space *vm, + u64 start, u64 length, + void (*fn)(struct i915_address_space *vm, + struct i915_page_table *pt, + void *data), + void *data); + struct i915_vma_ops vma_ops; I915_SELFTEST_DECLARE(struct fault_attr fault_attr); -- 2.31.1
WARNING: multiple messages have this Message-ID (diff)
From: "Thomas Hellström" <thomas.hellstrom@linux.intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: matthew.auld@intel.com, Chris Wilson <chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 5/9] drm/i915/gt: Add a routine to iterate over the pagetables of a GTT Date: Tue, 8 Jun 2021 11:28:42 +0200 [thread overview] Message-ID: <20210608092846.64198-6-thomas.hellstrom@linux.intel.com> (raw) In-Reply-To: <20210608092846.64198-1-thomas.hellstrom@linux.intel.com> From: Chris Wilson <chris@chris-wilson.co.uk> In the next patch, we will want to look at the dma addresses of individual page tables, so add a routine to iterate over them. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 49 ++++++++++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gtt.h | 7 ++++ 2 files changed, 56 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c index 1b676d7700bf..3d02c726c746 100644 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c @@ -361,6 +361,54 @@ static void gen8_ppgtt_alloc(struct i915_address_space *vm, &start, start + length, vm->top); } +static void __gen8_ppgtt_foreach(struct i915_address_space *vm, + struct i915_page_directory *pd, + u64 *start, u64 end, int lvl, + void (*fn)(struct i915_address_space *vm, + struct i915_page_table *pt, + void *data), + void *data) +{ + unsigned int idx, len; + + len = gen8_pd_range(*start, end, lvl--, &idx); + + spin_lock(&pd->lock); + do { + struct i915_page_table *pt = pd->entry[idx]; + + atomic_inc(&pt->used); + spin_unlock(&pd->lock); + + if (lvl) { + __gen8_ppgtt_foreach(vm, as_pd(pt), start, end, lvl, + fn, data); + } else { + fn(vm, pt, data); + *start += gen8_pt_count(*start, end); + } + + spin_lock(&pd->lock); + atomic_dec(&pt->used); + } while (idx++, --len); + spin_unlock(&pd->lock); +} + +static void gen8_ppgtt_foreach(struct i915_address_space *vm, + u64 start, u64 length, + void (*fn)(struct i915_address_space *vm, + struct i915_page_table *pt, + void *data), + void *data) +{ + start >>= GEN8_PTE_SHIFT; + length >>= GEN8_PTE_SHIFT; + + __gen8_ppgtt_foreach(vm, i915_vm_to_ppgtt(vm)->pd, + &start, start + length, vm->top, + fn, data); +} + static __always_inline u64 gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt, struct i915_page_directory *pdp, @@ -755,6 +803,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt) ppgtt->vm.insert_page = gen8_ppgtt_insert_entry; ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc; ppgtt->vm.clear_range = gen8_ppgtt_clear; + ppgtt->vm.foreach = gen8_ppgtt_foreach; ppgtt->vm.pte_encode = gen8_pte_encode; diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index edea95b97c36..9bd89f2a01ff 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -296,6 +296,13 @@ struct i915_address_space { u32 flags); void (*cleanup)(struct i915_address_space *vm); + void (*foreach)(struct i915_address_space *vm, + u64 start, u64 length, + void (*fn)(struct i915_address_space *vm, + struct i915_page_table *pt, + void *data), + void *data); + struct i915_vma_ops vma_ops; I915_SELFTEST_DECLARE(struct fault_attr fault_attr); -- 2.31.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-06-08 9:29 UTC|newest] Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-08 9:28 [PATCH 0/9] Prereqs for TTM accelerated migration Thomas Hellström 2021-06-08 9:28 ` [Intel-gfx] " Thomas Hellström 2021-06-08 9:28 ` [PATCH 1/9] drm/i915: Reference objects on the ww object list Thomas Hellström 2021-06-08 9:28 ` [Intel-gfx] " Thomas Hellström 2021-06-08 17:05 ` Matthew Auld 2021-06-08 17:05 ` [Intel-gfx] " Matthew Auld 2021-06-08 9:28 ` [PATCH 2/9] drm/i915: Break out dma_resv ww locking utilities to separate files Thomas Hellström 2021-06-08 9:28 ` [Intel-gfx] " Thomas Hellström 2021-06-08 17:10 ` Matthew Auld 2021-06-08 17:10 ` [Intel-gfx] " Matthew Auld 2021-06-08 9:28 ` [PATCH 3/9] drm/i915: Introduce a ww transaction helper Thomas Hellström 2021-06-08 9:28 ` [Intel-gfx] " Thomas Hellström 2021-06-08 17:17 ` Matthew Auld 2021-06-08 17:17 ` Matthew Auld 2021-06-08 19:00 ` Thomas Hellström 2021-06-08 19:00 ` Thomas Hellström 2021-06-08 9:28 ` [PATCH 4/9] drm/i915/gt: Add an insert_entry for gen8_ppgtt Thomas Hellström 2021-06-08 9:28 ` [Intel-gfx] " Thomas Hellström 2021-06-08 9:28 ` Thomas Hellström [this message] 2021-06-08 9:28 ` [Intel-gfx] [PATCH 5/9] drm/i915/gt: Add a routine to iterate over the pagetables of a GTT Thomas Hellström 2021-06-08 9:28 ` [PATCH 6/9] drm/i915/gt: Export the pinned context constructor Thomas Hellström 2021-06-08 9:28 ` [Intel-gfx] " Thomas Hellström 2021-06-08 9:28 ` [PATCH 7/9] drm/i915/gt: Pipelined page migration Thomas Hellström 2021-06-08 9:28 ` [Intel-gfx] " Thomas Hellström 2021-06-08 16:18 ` Matthew Auld 2021-06-08 16:18 ` Matthew Auld 2021-06-08 19:05 ` Thomas Hellström 2021-06-08 19:05 ` Thomas Hellström 2021-06-08 19:09 ` Thomas Hellström 2021-06-08 19:09 ` [Intel-gfx] " Thomas Hellström 2021-06-08 9:28 ` [PATCH 8/9] drm/i915/gt: Pipelined clear Thomas Hellström 2021-06-08 9:28 ` [Intel-gfx] " Thomas Hellström 2021-06-08 9:28 ` [PATCH 9/9] drm/i915/gt: Setup a default migration context on the GT Thomas Hellström 2021-06-08 9:28 ` [Intel-gfx] " Thomas Hellström 2021-06-08 12:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Prereqs for TTM accelerated migration Patchwork 2021-06-08 12:32 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 2021-06-08 12:32 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork
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