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From: Tinghan Shen <tinghan.shen@mediatek.com>
To: <robh+dt@kernel.org>, <matthias.bgg@gmail.com>
Cc: <devicetree@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <srv_heupstream@mediatek.com>,
	<seiya.wang@mediatek.com>, <wenst@google.com>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	Jason-JH Lin <jason-jh.lin@mediatek.com>
Subject: [PATCH 16/27] arm64: dts: mt8195: add display node
Date: Wed, 16 Jun 2021 01:32:22 +0800	[thread overview]
Message-ID: <20210615173233.26682-16-tinghan.shen@mediatek.com> (raw)
In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com>

From: Jason-JH Lin <jason-jh.lin@mediatek.com>

add display node.

Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 76 ++++++++++++++++++++++++
 1 file changed, 76 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 856b0e938009..f362288ad828 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1911,6 +1911,82 @@
 			#clock-cells = <1>;
 		};
 
+		vdosys_config@1c01a000 {
+			compatible = "mediatek,mt8195-vdosys";
+			reg = <0 0x1c01a000 0 0x1000>;
+			reg-names = "vdosys0_config";
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		mutex: disp_mutex0@1c016000 {
+			compatible = "mediatek,mt8195-disp-mutex";
+			reg = <0 0x1c016000 0 0x1000>;
+			reg-names = "vdo0_mutex";
+			clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clock-names = "vdo0_mutex";
+			interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
+		};
+
+		ovl0: disp_ovl@1c000000 {
+			compatible = "mediatek,mt8195-disp-ovl";
+			reg = <0 0x1c000000 0 0x1000>;
+			interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+		};
+
+		rdma0: disp_rdma@1c002000 {
+			compatible = "mediatek,mt8195-disp-rdma";
+			reg = <0 0x1c002000 0 0x1000>;
+			interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+		};
+
+		color0: disp_color@1c003000 {
+			compatible = "mediatek,mt8195-disp-color";
+			reg = <0 0x1c003000 0 0x1000>;
+			interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		ccorr0: disp_ccorr@1c004000 {
+			compatible = "mediatek,mt8195-disp-ccorr";
+			reg = <0 0x1c004000 0 0x1000>;
+			interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		aal0: disp_aal@1c005000 {
+			compatible = "mediatek,mt8195-disp-aal";
+			reg = <0 0x1c005000 0 0x1000>;
+			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		gamma0: disp_gamma@1c006000 {
+			compatible = "mediatek,mt8195-disp-gamma";
+			reg = <0 0x1c006000 0 0x1000>;
+			interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		dither0: disp_dither@1c007000 {
+			compatible = "mediatek,mt8195-disp-dither";
+			reg = <0 0x1c007000 0 0x1000>;
+			interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
 		smi_common0: smi@1c01b000 {
 			compatible = "mediatek,mt8195-smi-common";
 			mediatek,common-id = <0>;
-- 
2.18.0


WARNING: multiple messages have this Message-ID (diff)
From: Tinghan Shen <tinghan.shen@mediatek.com>
To: <robh+dt@kernel.org>, <matthias.bgg@gmail.com>
Cc: <devicetree@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <srv_heupstream@mediatek.com>,
	<seiya.wang@mediatek.com>, <wenst@google.com>,
	 <Project_Global_Chrome_Upstream_Group@mediatek.com>,
	Jason-JH Lin <jason-jh.lin@mediatek.com>
Subject: [PATCH 16/27] arm64: dts: mt8195: add display node
Date: Wed, 16 Jun 2021 01:32:22 +0800	[thread overview]
Message-ID: <20210615173233.26682-16-tinghan.shen@mediatek.com> (raw)
In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com>

From: Jason-JH Lin <jason-jh.lin@mediatek.com>

add display node.

Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 76 ++++++++++++++++++++++++
 1 file changed, 76 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 856b0e938009..f362288ad828 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1911,6 +1911,82 @@
 			#clock-cells = <1>;
 		};
 
+		vdosys_config@1c01a000 {
+			compatible = "mediatek,mt8195-vdosys";
+			reg = <0 0x1c01a000 0 0x1000>;
+			reg-names = "vdosys0_config";
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		mutex: disp_mutex0@1c016000 {
+			compatible = "mediatek,mt8195-disp-mutex";
+			reg = <0 0x1c016000 0 0x1000>;
+			reg-names = "vdo0_mutex";
+			clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clock-names = "vdo0_mutex";
+			interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
+		};
+
+		ovl0: disp_ovl@1c000000 {
+			compatible = "mediatek,mt8195-disp-ovl";
+			reg = <0 0x1c000000 0 0x1000>;
+			interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+		};
+
+		rdma0: disp_rdma@1c002000 {
+			compatible = "mediatek,mt8195-disp-rdma";
+			reg = <0 0x1c002000 0 0x1000>;
+			interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+		};
+
+		color0: disp_color@1c003000 {
+			compatible = "mediatek,mt8195-disp-color";
+			reg = <0 0x1c003000 0 0x1000>;
+			interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		ccorr0: disp_ccorr@1c004000 {
+			compatible = "mediatek,mt8195-disp-ccorr";
+			reg = <0 0x1c004000 0 0x1000>;
+			interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		aal0: disp_aal@1c005000 {
+			compatible = "mediatek,mt8195-disp-aal";
+			reg = <0 0x1c005000 0 0x1000>;
+			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		gamma0: disp_gamma@1c006000 {
+			compatible = "mediatek,mt8195-disp-gamma";
+			reg = <0 0x1c006000 0 0x1000>;
+			interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		dither0: disp_dither@1c007000 {
+			compatible = "mediatek,mt8195-disp-dither";
+			reg = <0 0x1c007000 0 0x1000>;
+			interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
 		smi_common0: smi@1c01b000 {
 			compatible = "mediatek,mt8195-smi-common";
 			mediatek,common-id = <0>;
-- 
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

WARNING: multiple messages have this Message-ID (diff)
From: Tinghan Shen <tinghan.shen@mediatek.com>
To: <robh+dt@kernel.org>, <matthias.bgg@gmail.com>
Cc: <devicetree@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <srv_heupstream@mediatek.com>,
	<seiya.wang@mediatek.com>, <wenst@google.com>,
	 <Project_Global_Chrome_Upstream_Group@mediatek.com>,
	Jason-JH Lin <jason-jh.lin@mediatek.com>
Subject: [PATCH 16/27] arm64: dts: mt8195: add display node
Date: Wed, 16 Jun 2021 01:32:22 +0800	[thread overview]
Message-ID: <20210615173233.26682-16-tinghan.shen@mediatek.com> (raw)
In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com>

From: Jason-JH Lin <jason-jh.lin@mediatek.com>

add display node.

Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 76 ++++++++++++++++++++++++
 1 file changed, 76 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 856b0e938009..f362288ad828 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1911,6 +1911,82 @@
 			#clock-cells = <1>;
 		};
 
+		vdosys_config@1c01a000 {
+			compatible = "mediatek,mt8195-vdosys";
+			reg = <0 0x1c01a000 0 0x1000>;
+			reg-names = "vdosys0_config";
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		mutex: disp_mutex0@1c016000 {
+			compatible = "mediatek,mt8195-disp-mutex";
+			reg = <0 0x1c016000 0 0x1000>;
+			reg-names = "vdo0_mutex";
+			clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clock-names = "vdo0_mutex";
+			interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
+		};
+
+		ovl0: disp_ovl@1c000000 {
+			compatible = "mediatek,mt8195-disp-ovl";
+			reg = <0 0x1c000000 0 0x1000>;
+			interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+		};
+
+		rdma0: disp_rdma@1c002000 {
+			compatible = "mediatek,mt8195-disp-rdma";
+			reg = <0 0x1c002000 0 0x1000>;
+			interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+		};
+
+		color0: disp_color@1c003000 {
+			compatible = "mediatek,mt8195-disp-color";
+			reg = <0 0x1c003000 0 0x1000>;
+			interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		ccorr0: disp_ccorr@1c004000 {
+			compatible = "mediatek,mt8195-disp-ccorr";
+			reg = <0 0x1c004000 0 0x1000>;
+			interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		aal0: disp_aal@1c005000 {
+			compatible = "mediatek,mt8195-disp-aal";
+			reg = <0 0x1c005000 0 0x1000>;
+			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		gamma0: disp_gamma@1c006000 {
+			compatible = "mediatek,mt8195-disp-gamma";
+			reg = <0 0x1c006000 0 0x1000>;
+			interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		dither0: disp_dither@1c007000 {
+			compatible = "mediatek,mt8195-disp-dither";
+			reg = <0 0x1c007000 0 0x1000>;
+			interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
 		smi_common0: smi@1c01b000 {
 			compatible = "mediatek,mt8195-smi-common";
 			mediatek,common-id = <0>;
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-06-15 17:33 UTC|newest]

Thread overview: 102+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-15 17:32 arm64: dts: mt8195: Add Mediatek SoC MT8195 device nodes Tinghan Shen
2021-06-15 17:32 ` Tinghan Shen
2021-06-15 17:32 ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 01/27] arm64: dts: mt8195: add infracfg_rst node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-16  8:01   ` Chen-Yu Tsai
2021-06-16  8:01     ` Chen-Yu Tsai
2021-06-16  8:01     ` Chen-Yu Tsai
2021-06-15 17:32 ` [PATCH 02/27] arm64: dts: mt8195: add pinctrl node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 03/27] arm64: dts: mt8195: add pwrap node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 05/27] arm64: dts: mt8195: add spmi node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 06/27] arm64: dts: mt8195: add clock controllers Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 07/27] arm64: dts: mt8195: add power domains controller Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 08/27] arm64: dts: mt8195: add i2c dts Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 09/27] arm64: dts: mt8195: add spi controller Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 10/27] arm64: dts: mt8195: add PCIe phy device node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 11/27] arm64: dts: mt8195: add PCIe " Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 12/27] arm64: dts: mt8195: fix mmc driver Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-16  1:30   ` Wenbin Mei
2021-06-16  1:30     ` Wenbin Mei
2021-06-16  1:30     ` Wenbin Mei
2021-06-15 17:32 ` [PATCH 13/27] arm64: dts: mt8195: add hdmi nodes Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 14/27] arm64: dts: mt8195: add usb support Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 15/27] arm64: dts: mt8195: add IOMMU and smi nodes Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` Tinghan Shen [this message]
2021-06-15 17:32   ` [PATCH 16/27] arm64: dts: mt8195: add display node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 23:14   ` Chun-Kuang Hu
2021-06-15 23:14     ` Chun-Kuang Hu
2021-06-15 23:14     ` Chun-Kuang Hu
2021-06-15 17:32 ` [PATCH 17/27] arm64: dts: mt8195: add merge node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 18/27] arm64: dts: mt8195: add dsc node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 19/27] arm64: dts: mt8195: add dp_intf node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 20/27] arm64: dts: mt8195: fix nor_flash node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 21/27] arm64: dts: mt8195: add audio related nodes Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 22/27] arm64: dts: mt8195: add edp nodes Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 23:30   ` Chun-Kuang Hu
2021-06-15 23:30     ` Chun-Kuang Hu
2021-06-15 23:30     ` Chun-Kuang Hu
2021-06-15 17:32 ` [PATCH 23/27] arm64: dts: mt8195: add gce node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-18 14:07   ` Chun-Kuang Hu
2021-06-18 14:07     ` Chun-Kuang Hu
2021-06-18 14:07     ` Chun-Kuang Hu
2021-06-15 17:32 ` [PATCH 24/27] arm64: dts: mt8195: add gce setting for disply node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 25/27] arm64: dts: mt8195: add vdosys1 support for MT8195 Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 23:23   ` Chun-Kuang Hu
2021-06-15 23:23     ` Chun-Kuang Hu
2021-06-15 23:23     ` Chun-Kuang Hu
2021-06-15 17:32 ` [PATCH 26/27] arm64: dts: mt8195: add scp device node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 27/27] arm64: dts: mt8195: add cpufreq device nodes Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-18 14:21 ` arm64: dts: mt8195: Add Mediatek SoC MT8195 " Matthias Brugger
2021-06-18 14:21   ` Matthias Brugger
2021-06-18 14:21   ` Matthias Brugger

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