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From: Tinghan Shen <tinghan.shen@mediatek.com>
To: <robh+dt@kernel.org>, <matthias.bgg@gmail.com>
Cc: <devicetree@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <srv_heupstream@mediatek.com>,
	<seiya.wang@mediatek.com>, <wenst@google.com>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	Leilk Liu <leilk.liu@mediatek.com>
Subject: [PATCH 09/27] arm64: dts: mt8195: add spi controller
Date: Wed, 16 Jun 2021 01:32:15 +0800	[thread overview]
Message-ID: <20210615173233.26682-9-tinghan.shen@mediatek.com> (raw)
In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com>

From: Leilk Liu <leilk.liu@mediatek.com>

add spi controller node into mt8195 SoC

Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 106 +++++++++++++++++++++++
 1 file changed, 106 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 9b002bb6d344..80a272703879 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -818,6 +818,112 @@
 			#clock-cells = <1>;
 		};
 
+		spi0: spi@1100a000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x1100a000 0 0x100>;
+			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI0>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spi1: spi@11010000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x11010000 0 0x100>;
+			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI1>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spi2: spi@11012000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x11012000 0 0x100>;
+			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI2>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spi3: spi@11013000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x11013000 0 0x100>;
+			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI3>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spi4: spi@11018000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x11018000 0 0x100>;
+			interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI4>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spi5: spi@11019000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x11019000 0 0x100>;
+			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI5>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spis0: spi@1101d000 {
+			compatible = "mediatek,mt8195-spi-slave";
+			reg = <0 0x1101d000 0 0x100>;
+			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
+			clock-names = "spi";
+			assigned-clocks = <&topckgen CLK_TOP_SPIS_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
+			status = "disabled";
+		};
+
+		spis1: spi@1101e000 {
+			compatible = "mediatek,mt8195-spi-slave";
+			reg = <0 0x1101e000 0 0x100>;
+			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
+			clock-names = "spi";
+			assigned-clocks = <&topckgen CLK_TOP_SPIS_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
+			status = "disabled";
+		};
+
 		mmc0: mmc@11230000 {
 			compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc";
 			reg = <0 0x11230000 0 0x10000>,
-- 
2.18.0


WARNING: multiple messages have this Message-ID (diff)
From: Tinghan Shen <tinghan.shen@mediatek.com>
To: <robh+dt@kernel.org>, <matthias.bgg@gmail.com>
Cc: <devicetree@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <srv_heupstream@mediatek.com>,
	<seiya.wang@mediatek.com>, <wenst@google.com>,
	 <Project_Global_Chrome_Upstream_Group@mediatek.com>,
	Leilk Liu <leilk.liu@mediatek.com>
Subject: [PATCH 09/27] arm64: dts: mt8195: add spi controller
Date: Wed, 16 Jun 2021 01:32:15 +0800	[thread overview]
Message-ID: <20210615173233.26682-9-tinghan.shen@mediatek.com> (raw)
In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com>

From: Leilk Liu <leilk.liu@mediatek.com>

add spi controller node into mt8195 SoC

Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 106 +++++++++++++++++++++++
 1 file changed, 106 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 9b002bb6d344..80a272703879 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -818,6 +818,112 @@
 			#clock-cells = <1>;
 		};
 
+		spi0: spi@1100a000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x1100a000 0 0x100>;
+			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI0>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spi1: spi@11010000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x11010000 0 0x100>;
+			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI1>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spi2: spi@11012000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x11012000 0 0x100>;
+			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI2>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spi3: spi@11013000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x11013000 0 0x100>;
+			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI3>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spi4: spi@11018000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x11018000 0 0x100>;
+			interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI4>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spi5: spi@11019000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x11019000 0 0x100>;
+			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI5>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spis0: spi@1101d000 {
+			compatible = "mediatek,mt8195-spi-slave";
+			reg = <0 0x1101d000 0 0x100>;
+			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
+			clock-names = "spi";
+			assigned-clocks = <&topckgen CLK_TOP_SPIS_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
+			status = "disabled";
+		};
+
+		spis1: spi@1101e000 {
+			compatible = "mediatek,mt8195-spi-slave";
+			reg = <0 0x1101e000 0 0x100>;
+			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
+			clock-names = "spi";
+			assigned-clocks = <&topckgen CLK_TOP_SPIS_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
+			status = "disabled";
+		};
+
 		mmc0: mmc@11230000 {
 			compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc";
 			reg = <0 0x11230000 0 0x10000>,
-- 
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

WARNING: multiple messages have this Message-ID (diff)
From: Tinghan Shen <tinghan.shen@mediatek.com>
To: <robh+dt@kernel.org>, <matthias.bgg@gmail.com>
Cc: <devicetree@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <srv_heupstream@mediatek.com>,
	<seiya.wang@mediatek.com>, <wenst@google.com>,
	 <Project_Global_Chrome_Upstream_Group@mediatek.com>,
	Leilk Liu <leilk.liu@mediatek.com>
Subject: [PATCH 09/27] arm64: dts: mt8195: add spi controller
Date: Wed, 16 Jun 2021 01:32:15 +0800	[thread overview]
Message-ID: <20210615173233.26682-9-tinghan.shen@mediatek.com> (raw)
In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com>

From: Leilk Liu <leilk.liu@mediatek.com>

add spi controller node into mt8195 SoC

Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 106 +++++++++++++++++++++++
 1 file changed, 106 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 9b002bb6d344..80a272703879 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -818,6 +818,112 @@
 			#clock-cells = <1>;
 		};
 
+		spi0: spi@1100a000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x1100a000 0 0x100>;
+			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI0>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spi1: spi@11010000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x11010000 0 0x100>;
+			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI1>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spi2: spi@11012000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x11012000 0 0x100>;
+			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI2>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spi3: spi@11013000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x11013000 0 0x100>;
+			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI3>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spi4: spi@11018000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x11018000 0 0x100>;
+			interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI4>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spi5: spi@11019000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x11019000 0 0x100>;
+			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI5>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spis0: spi@1101d000 {
+			compatible = "mediatek,mt8195-spi-slave";
+			reg = <0 0x1101d000 0 0x100>;
+			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
+			clock-names = "spi";
+			assigned-clocks = <&topckgen CLK_TOP_SPIS_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
+			status = "disabled";
+		};
+
+		spis1: spi@1101e000 {
+			compatible = "mediatek,mt8195-spi-slave";
+			reg = <0 0x1101e000 0 0x100>;
+			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
+			clock-names = "spi";
+			assigned-clocks = <&topckgen CLK_TOP_SPIS_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
+			status = "disabled";
+		};
+
 		mmc0: mmc@11230000 {
 			compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc";
 			reg = <0 0x11230000 0 0x10000>,
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-06-15 17:32 UTC|newest]

Thread overview: 102+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-15 17:32 arm64: dts: mt8195: Add Mediatek SoC MT8195 device nodes Tinghan Shen
2021-06-15 17:32 ` Tinghan Shen
2021-06-15 17:32 ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 01/27] arm64: dts: mt8195: add infracfg_rst node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-16  8:01   ` Chen-Yu Tsai
2021-06-16  8:01     ` Chen-Yu Tsai
2021-06-16  8:01     ` Chen-Yu Tsai
2021-06-15 17:32 ` [PATCH 02/27] arm64: dts: mt8195: add pinctrl node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 03/27] arm64: dts: mt8195: add pwrap node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 05/27] arm64: dts: mt8195: add spmi node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 06/27] arm64: dts: mt8195: add clock controllers Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 07/27] arm64: dts: mt8195: add power domains controller Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 08/27] arm64: dts: mt8195: add i2c dts Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` Tinghan Shen [this message]
2021-06-15 17:32   ` [PATCH 09/27] arm64: dts: mt8195: add spi controller Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 10/27] arm64: dts: mt8195: add PCIe phy device node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 11/27] arm64: dts: mt8195: add PCIe " Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 12/27] arm64: dts: mt8195: fix mmc driver Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-16  1:30   ` Wenbin Mei
2021-06-16  1:30     ` Wenbin Mei
2021-06-16  1:30     ` Wenbin Mei
2021-06-15 17:32 ` [PATCH 13/27] arm64: dts: mt8195: add hdmi nodes Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 14/27] arm64: dts: mt8195: add usb support Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 15/27] arm64: dts: mt8195: add IOMMU and smi nodes Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 16/27] arm64: dts: mt8195: add display node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 23:14   ` Chun-Kuang Hu
2021-06-15 23:14     ` Chun-Kuang Hu
2021-06-15 23:14     ` Chun-Kuang Hu
2021-06-15 17:32 ` [PATCH 17/27] arm64: dts: mt8195: add merge node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 18/27] arm64: dts: mt8195: add dsc node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 19/27] arm64: dts: mt8195: add dp_intf node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 20/27] arm64: dts: mt8195: fix nor_flash node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 21/27] arm64: dts: mt8195: add audio related nodes Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 22/27] arm64: dts: mt8195: add edp nodes Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 23:30   ` Chun-Kuang Hu
2021-06-15 23:30     ` Chun-Kuang Hu
2021-06-15 23:30     ` Chun-Kuang Hu
2021-06-15 17:32 ` [PATCH 23/27] arm64: dts: mt8195: add gce node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-18 14:07   ` Chun-Kuang Hu
2021-06-18 14:07     ` Chun-Kuang Hu
2021-06-18 14:07     ` Chun-Kuang Hu
2021-06-15 17:32 ` [PATCH 24/27] arm64: dts: mt8195: add gce setting for disply node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 25/27] arm64: dts: mt8195: add vdosys1 support for MT8195 Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 23:23   ` Chun-Kuang Hu
2021-06-15 23:23     ` Chun-Kuang Hu
2021-06-15 23:23     ` Chun-Kuang Hu
2021-06-15 17:32 ` [PATCH 26/27] arm64: dts: mt8195: add scp device node Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32 ` [PATCH 27/27] arm64: dts: mt8195: add cpufreq device nodes Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-15 17:32   ` Tinghan Shen
2021-06-18 14:21 ` arm64: dts: mt8195: Add Mediatek SoC MT8195 " Matthias Brugger
2021-06-18 14:21   ` Matthias Brugger
2021-06-18 14:21   ` Matthias Brugger

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