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From: Robert Foss <robert.foss@linaro.org>
To: agross@kernel.org, bjorn.andersson@linaro.org,
	mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
	jonathan@marek.ca, tdas@codeaurora.org,
	linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	Vinod Koul <vinod.koul@linaro.org>
Cc: Robert Foss <robert.foss@linaro.org>
Subject: [RFC v1 01/11] clk: qcom: common: Add runtime init/suspend/resume
Date: Wed, 16 Jun 2021 16:10:57 +0200	[thread overview]
Message-ID: <20210616141107.291430-2-robert.foss@linaro.org> (raw)
In-Reply-To: <20210616141107.291430-1-robert.foss@linaro.org>

Ported over from the downstream driver. Is used by SM8350 DISPCC & VIDEOCC.

This patch includes support for initializing interconnect bandwidth voting.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
 drivers/clk/qcom/common.c | 92 +++++++++++++++++++++++++++++++++++++++
 drivers/clk/qcom/common.h |  6 +++
 2 files changed, 98 insertions(+)

diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index 60d2a78d1395..1375c5de1bd1 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -3,13 +3,17 @@
  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
  */
 
+#include <linux/clk.h>
 #include <linux/export.h>
+#include <linux/interconnect.h>
 #include <linux/module.h>
 #include <linux/regmap.h>
 #include <linux/platform_device.h>
 #include <linux/clk-provider.h>
 #include <linux/reset-controller.h>
 #include <linux/of.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_runtime.h>
 
 #include "common.h"
 #include "clk-rcg.h"
@@ -329,4 +333,92 @@ int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
 }
 EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index);
 
+int qcom_cc_runtime_init(struct platform_device *pdev,
+			 struct qcom_cc_desc *desc)
+{
+	struct device *dev = &pdev->dev;
+	struct clk *clk;
+	int ret;
+
+	clk = clk_get_optional(dev, "iface");
+	if (IS_ERR(clk)) {
+		if (PTR_ERR(clk) != -EPROBE_DEFER)
+			dev_err(dev, "unable to get iface clock\n");
+		return PTR_ERR(clk);
+	}
+	clk_put(clk);
+
+	desc->path = of_icc_get(dev, NULL);
+	if (IS_ERR(desc->path)) {
+		if (PTR_ERR(desc->path) != -EPROBE_DEFER)
+			dev_err(dev, "error getting path\n");
+		return PTR_ERR(desc->path);
+	}
+
+	platform_set_drvdata(pdev, desc);
+	pm_runtime_enable(dev);
+
+	ret = pm_clk_create(dev);
+	if (ret)
+		goto disable_pm_runtime;
+
+	ret = pm_clk_add(dev, "iface");
+	if (ret < 0) {
+		dev_err(dev, "failed to acquire iface clock\n");
+		goto destroy_pm_clk;
+	}
+
+	return 0;
+
+destroy_pm_clk:
+	pm_clk_destroy(dev);
+
+disable_pm_runtime:
+	pm_runtime_disable(dev);
+	icc_put(desc->path);
+
+	return ret;
+}
+EXPORT_SYMBOL(qcom_cc_runtime_init);
+
+int qcom_cc_runtime_resume(struct device *dev)
+{
+	struct qcom_cc_desc *desc = dev_get_drvdata(dev);
+	int ret;
+
+	if (desc->path) {
+		ret = icc_set_bw(desc->path, 0, 1);
+		if (ret) {
+			dev_warn(dev, "%s: failed to vote bw\n", __func__);
+			return ret;
+		}
+	}
+
+	ret = pm_clk_resume(dev);
+	if (ret)
+		dev_warn(dev, "%s: failed to enable clocks\n", __func__);
+
+	return ret;
+}
+EXPORT_SYMBOL(qcom_cc_runtime_resume);
+
+int qcom_cc_runtime_suspend(struct device *dev)
+{
+	struct qcom_cc_desc *desc = dev_get_drvdata(dev);
+	int ret;
+
+	ret = pm_clk_suspend(dev);
+	if (ret)
+		dev_warn(dev, "%s: failed to disable clocks\n", __func__);
+
+	if (desc->path) {
+		ret = icc_set_bw(desc->path, 0, 0);
+		if (ret)
+			dev_warn(dev, "%s: failed to unvote bw\n", __func__);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(qcom_cc_runtime_suspend);
+
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index bb39a7e106d8..e2a9dbd1529d 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -29,6 +29,7 @@ struct qcom_cc_desc {
 	size_t num_gdscs;
 	struct clk_hw **clk_hws;
 	size_t num_clk_hws;
+	struct icc_path *path;
 };
 
 /**
@@ -64,4 +65,9 @@ extern int qcom_cc_probe(struct platform_device *pdev,
 extern int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
 				  const struct qcom_cc_desc *desc);
 
+int qcom_cc_runtime_init(struct platform_device *pdev,
+			 struct qcom_cc_desc *desc);
+int qcom_cc_runtime_suspend(struct device *dev);
+int qcom_cc_runtime_resume(struct device *dev);
+
 #endif
-- 
2.30.2


  reply	other threads:[~2021-06-16 14:11 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-16 14:10 [RFC v1 00/11] Qcom SM8350 DispCC & VideoCC Robert Foss
2021-06-16 14:10 ` Robert Foss [this message]
2021-06-16 14:10 ` [RFC v1 02/11] clk: qcom: rcg2: Add support for flags Robert Foss
2021-06-16 15:33   ` Konrad Dybcio
2021-06-17  7:58     ` Robert Foss
2021-06-16 16:07   ` Dmitry Baryshkov
2021-06-17 13:37     ` Robert Foss
2021-06-16 14:10 ` [RFC v1 03/11] clk: qcom: clk-alpha-pll: Fix typo in comment Robert Foss
2021-06-16 14:11 ` [RFC v1 04/11] clk: qcom: clk-alpha-pll: Add configuration support for LUCID 5LPE Robert Foss
2021-06-16 14:11 ` [RFC v1 05/11] dt-bindings: clock: Add QCOM SM8350 display clock bindings Robert Foss
2021-06-24 21:18   ` Rob Herring
2021-06-25 13:51     ` Robert Foss
2021-06-16 14:11 ` [RFC v1 06/11] clk: qcom: Add display clock controller driver for SM8350 Robert Foss
2021-06-16 15:42   ` Konrad Dybcio
2021-06-17  9:02     ` Robert Foss
2021-06-17 19:37       ` Konrad Dybcio
2021-06-16 14:11 ` [RFC v1 07/11] dt-bindings: clock: Add SM8350 QCOM video clock bindings Robert Foss
2021-06-16 14:11 ` [RFC v1 08/11] clk: qcom: Add video clock controller driver for SM8350 Robert Foss
2021-06-16 14:11 ` [RFC v1 09/11] arm64: dts: qcom: sm8350: Power up dispcc & videocc on sm8350 by MMCX regulator Robert Foss
2021-06-16 14:11 ` [RFC v1 10/11] arm64: dts: qcom: sm8350: Add videocc DT node Robert Foss
2021-06-16 14:11 ` [RFC v1 11/11] arm64: dts: qcom: sm8350: Add dispcc " Robert Foss

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