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From: Robert Foss <robert.foss@linaro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Jonathan Marek <jonathan@marek.ca>,
	Taniya Das <tdas@codeaurora.org>,
	MSM <linux-arm-msm@vger.kernel.org>,
	"open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
	<devicetree@vger.kernel.org>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	Vinod Koul <vinod.koul@linaro.org>
Subject: Re: [RFC v1 02/11] clk: qcom: rcg2: Add support for flags
Date: Thu, 17 Jun 2021 15:37:37 +0200	[thread overview]
Message-ID: <CAG3jFyubcKP71_w83WWxTX9y3aTz+osTKxbq6Mo+hDTfxbf=WQ@mail.gmail.com> (raw)
In-Reply-To: <b48198ff-a954-4941-32d6-65c992b345e7@linaro.org>

On Wed, 16 Jun 2021 at 18:07, Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
> > diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
> > index 99efcc7f8d88..a1f05281d950 100644
> > --- a/drivers/clk/qcom/clk-rcg.h
> > +++ b/drivers/clk/qcom/clk-rcg.h
> > @@ -149,6 +149,10 @@ struct clk_rcg2 {
> >       const struct freq_tbl   *freq_tbl;
> >       struct clk_regmap       clkr;
> >       u8                      cfg_off;
> > +     u8                      flags;
> > +#define FORCE_ENABLE_RCG     BIT(0)
> > +#define HW_CLK_CTRL_MODE     BIT(1)
>
> Downstream also has these flags for 8250, but the upstream driver ended
> up not using them for the dispcc clocks. Could you please check that you
> realy need HW_CLK_CTRL for dispcc clocks?

HW_CLK_CTRL being flagged in dispcc causes the CFG_HW_CLK_CTRL flag to
be set in the RCG_CFG registers of dispcc.

This flag simply marks the clock as having hardware control enabled or disabled.

As for the question if it is really needed, I can't answer that since
no documentation or downstream comments explain the exact behaviour.
As far as I know the only way to figure out if it is required is
disabling the flag and checking for bugs. I did find this[1] patch,
which enabled HW_CLK_CTRL_MODE.

Should I err on the side of the downstream implementation, or try to
create a minimum functional driver based on the downstream driver?

[1] https://patchwork.kernel.org/project/linux-arm-msm/patch/1514877987-8082-2-git-send-email-anischal@codeaurora.org/

  reply	other threads:[~2021-06-17 13:37 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-16 14:10 [RFC v1 00/11] Qcom SM8350 DispCC & VideoCC Robert Foss
2021-06-16 14:10 ` [RFC v1 01/11] clk: qcom: common: Add runtime init/suspend/resume Robert Foss
2021-06-16 14:10 ` [RFC v1 02/11] clk: qcom: rcg2: Add support for flags Robert Foss
2021-06-16 15:33   ` Konrad Dybcio
2021-06-17  7:58     ` Robert Foss
2021-06-16 16:07   ` Dmitry Baryshkov
2021-06-17 13:37     ` Robert Foss [this message]
2021-06-16 14:10 ` [RFC v1 03/11] clk: qcom: clk-alpha-pll: Fix typo in comment Robert Foss
2021-06-16 14:11 ` [RFC v1 04/11] clk: qcom: clk-alpha-pll: Add configuration support for LUCID 5LPE Robert Foss
2021-06-16 14:11 ` [RFC v1 05/11] dt-bindings: clock: Add QCOM SM8350 display clock bindings Robert Foss
2021-06-24 21:18   ` Rob Herring
2021-06-25 13:51     ` Robert Foss
2021-06-16 14:11 ` [RFC v1 06/11] clk: qcom: Add display clock controller driver for SM8350 Robert Foss
2021-06-16 15:42   ` Konrad Dybcio
2021-06-17  9:02     ` Robert Foss
2021-06-17 19:37       ` Konrad Dybcio
2021-06-16 14:11 ` [RFC v1 07/11] dt-bindings: clock: Add SM8350 QCOM video clock bindings Robert Foss
2021-06-16 14:11 ` [RFC v1 08/11] clk: qcom: Add video clock controller driver for SM8350 Robert Foss
2021-06-16 14:11 ` [RFC v1 09/11] arm64: dts: qcom: sm8350: Power up dispcc & videocc on sm8350 by MMCX regulator Robert Foss
2021-06-16 14:11 ` [RFC v1 10/11] arm64: dts: qcom: sm8350: Add videocc DT node Robert Foss
2021-06-16 14:11 ` [RFC v1 11/11] arm64: dts: qcom: sm8350: Add dispcc " Robert Foss

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