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From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Robert Foss <robert.foss@linaro.org>,
	agross@kernel.org, bjorn.andersson@linaro.org,
	mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
	jonathan@marek.ca, tdas@codeaurora.org,
	linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	Vinod Koul <vinod.koul@linaro.org>
Subject: Re: [RFC v1 02/11] clk: qcom: rcg2: Add support for flags
Date: Wed, 16 Jun 2021 19:07:52 +0300	[thread overview]
Message-ID: <b48198ff-a954-4941-32d6-65c992b345e7@linaro.org> (raw)
In-Reply-To: <20210616141107.291430-3-robert.foss@linaro.org>

On 16/06/2021 17:10, Robert Foss wrote:
> These changes are ported from the downstream driver, and are used on SM8350
> for CAMCC, DISPCC, GCC, GPUCC & VIDEOCC.
> 
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
>   drivers/clk/qcom/clk-rcg.h  | 4 ++++
>   drivers/clk/qcom/clk-rcg2.c | 3 +++
>   2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
> index 99efcc7f8d88..a1f05281d950 100644
> --- a/drivers/clk/qcom/clk-rcg.h
> +++ b/drivers/clk/qcom/clk-rcg.h
> @@ -149,6 +149,10 @@ struct clk_rcg2 {
>   	const struct freq_tbl	*freq_tbl;
>   	struct clk_regmap	clkr;
>   	u8			cfg_off;
> +	u8			flags;
> +#define FORCE_ENABLE_RCG	BIT(0)
> +#define HW_CLK_CTRL_MODE	BIT(1)

Downstream also has these flags for 8250, but the upstream driver ended 
up not using them for the dispcc clocks. Could you please check that you 
realy need HW_CLK_CTRL for dispcc clocks?

> +#define DFS_SUPPORT		BIT(2)
>   };
>   
>   #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
> diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
> index 42f13a2d1cc1..ed2c9b6659cc 100644
> --- a/drivers/clk/qcom/clk-rcg2.c
> +++ b/drivers/clk/qcom/clk-rcg2.c
> @@ -295,6 +295,9 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
>   	cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
>   	if (rcg->mnd_width && f->n && (f->m != f->n))
>   		cfg |= CFG_MODE_DUAL_EDGE;
> +	if (rcg->flags & HW_CLK_CTRL_MODE)
> +		cfg |= CFG_HW_CLK_CTRL_MASK;
> +
>   	return regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),
>   					mask, cfg);
>   }
> 


-- 
With best wishes
Dmitry

  parent reply	other threads:[~2021-06-16 16:07 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-16 14:10 [RFC v1 00/11] Qcom SM8350 DispCC & VideoCC Robert Foss
2021-06-16 14:10 ` [RFC v1 01/11] clk: qcom: common: Add runtime init/suspend/resume Robert Foss
2021-06-16 14:10 ` [RFC v1 02/11] clk: qcom: rcg2: Add support for flags Robert Foss
2021-06-16 15:33   ` Konrad Dybcio
2021-06-17  7:58     ` Robert Foss
2021-06-16 16:07   ` Dmitry Baryshkov [this message]
2021-06-17 13:37     ` Robert Foss
2021-06-16 14:10 ` [RFC v1 03/11] clk: qcom: clk-alpha-pll: Fix typo in comment Robert Foss
2021-06-16 14:11 ` [RFC v1 04/11] clk: qcom: clk-alpha-pll: Add configuration support for LUCID 5LPE Robert Foss
2021-06-16 14:11 ` [RFC v1 05/11] dt-bindings: clock: Add QCOM SM8350 display clock bindings Robert Foss
2021-06-24 21:18   ` Rob Herring
2021-06-25 13:51     ` Robert Foss
2021-06-16 14:11 ` [RFC v1 06/11] clk: qcom: Add display clock controller driver for SM8350 Robert Foss
2021-06-16 15:42   ` Konrad Dybcio
2021-06-17  9:02     ` Robert Foss
2021-06-17 19:37       ` Konrad Dybcio
2021-06-16 14:11 ` [RFC v1 07/11] dt-bindings: clock: Add SM8350 QCOM video clock bindings Robert Foss
2021-06-16 14:11 ` [RFC v1 08/11] clk: qcom: Add video clock controller driver for SM8350 Robert Foss
2021-06-16 14:11 ` [RFC v1 09/11] arm64: dts: qcom: sm8350: Power up dispcc & videocc on sm8350 by MMCX regulator Robert Foss
2021-06-16 14:11 ` [RFC v1 10/11] arm64: dts: qcom: sm8350: Add videocc DT node Robert Foss
2021-06-16 14:11 ` [RFC v1 11/11] arm64: dts: qcom: sm8350: Add dispcc " Robert Foss

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