* [PULL 1/7] target/riscv: Use target_ulong for the DisasContext misa
2021-06-24 12:02 [PULL 0/7] riscv-to-apply queue Alistair Francis
@ 2021-06-24 12:02 ` Alistair Francis
2021-06-24 12:02 ` [PULL 2/7] target/riscv: gdbstub: Fix dynamic CSR XML generation Alistair Francis
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Alistair Francis @ 2021-06-24 12:02 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: Bin Meng, Alistair Francis
The is_32bit() check in translate.c expects a 64-bit guest to have a
64-bit misa value otherwise the macro check won't work. This patches
fixes that and fixes a Coverity issue at the same time.
Fixes: CID 1453107
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: c00176c7518c2a7b4de3eec320b6a683ab56f705.1622435221.git.alistair.francis@wdc.com
---
target/riscv/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c6e8739614..62a7d7e4c7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -47,7 +47,7 @@ typedef struct DisasContext {
bool virt_enabled;
uint32_t opcode;
uint32_t mstatus_fs;
- uint32_t misa;
+ target_ulong misa;
uint32_t mem_idx;
/* Remember the rounding mode encoded in the previous fp instruction,
which we have already installed into env->fp_status. Or -1 for
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 2/7] target/riscv: gdbstub: Fix dynamic CSR XML generation
2021-06-24 12:02 [PULL 0/7] riscv-to-apply queue Alistair Francis
2021-06-24 12:02 ` [PULL 1/7] target/riscv: Use target_ulong for the DisasContext misa Alistair Francis
@ 2021-06-24 12:02 ` Alistair Francis
2021-06-24 12:02 ` [PULL 3/7] hw/char: Consistent function names for sifive_uart Alistair Francis
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Alistair Francis @ 2021-06-24 12:02 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: Xuzhou Cheng, Bin Meng, Alistair Francis
From: Bin Meng <bin.meng@windriver.com>
Since commit 605def6eeee5 ("target/riscv: Use the RISCVException enum for CSR operations")
the CSR predicate() function was changed to return RISCV_EXCP_NONE
instead of 0 for a valid CSR, but it forgot to update the dynamic
CSR XML generation codes in gdbstub.
Fixes: 605def6eeee5 ("target/riscv: Use the RISCVException enum for CSR operations")
Reported-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210615085133.389887-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/gdbstub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index ca78682cf4..a7a9c0b1fe 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -170,7 +170,7 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
for (i = 0; i < CSR_TABLE_SIZE; i++) {
predicate = csr_ops[i].predicate;
- if (predicate && !predicate(env, i)) {
+ if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) {
if (csr_ops[i].name) {
g_string_append_printf(s, "<reg name=\"%s\"", csr_ops[i].name);
} else {
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 3/7] hw/char: Consistent function names for sifive_uart
2021-06-24 12:02 [PULL 0/7] riscv-to-apply queue Alistair Francis
2021-06-24 12:02 ` [PULL 1/7] target/riscv: Use target_ulong for the DisasContext misa Alistair Francis
2021-06-24 12:02 ` [PULL 2/7] target/riscv: gdbstub: Fix dynamic CSR XML generation Alistair Francis
@ 2021-06-24 12:02 ` Alistair Francis
2021-06-24 12:02 ` [PULL 4/7] hw/char: QOMify sifive_uart Alistair Francis
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Alistair Francis @ 2021-06-24 12:02 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: Bin Meng, Alistair Francis, Lukas Jünger
From: Lukas Jünger <lukas.juenger@greensocs.com>
This cleans up function names in the SiFive UART model.
Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210616092326.59639-2-lukas.juenger@greensocs.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/char/sifive_uart.c | 46 ++++++++++++++++++++++---------------------
1 file changed, 24 insertions(+), 22 deletions(-)
diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
index fe12666789..5df8212961 100644
--- a/hw/char/sifive_uart.c
+++ b/hw/char/sifive_uart.c
@@ -31,7 +31,7 @@
*/
/* Returns the state of the IP (interrupt pending) register */
-static uint64_t uart_ip(SiFiveUARTState *s)
+static uint64_t sifive_uart_ip(SiFiveUARTState *s)
{
uint64_t ret = 0;
@@ -48,7 +48,7 @@ static uint64_t uart_ip(SiFiveUARTState *s)
return ret;
}
-static void update_irq(SiFiveUARTState *s)
+static void sifive_uart_update_irq(SiFiveUARTState *s)
{
int cond = 0;
if ((s->ie & SIFIVE_UART_IE_TXWM) ||
@@ -63,7 +63,7 @@ static void update_irq(SiFiveUARTState *s)
}
static uint64_t
-uart_read(void *opaque, hwaddr addr, unsigned int size)
+sifive_uart_read(void *opaque, hwaddr addr, unsigned int size)
{
SiFiveUARTState *s = opaque;
unsigned char r;
@@ -74,7 +74,7 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
memmove(s->rx_fifo, s->rx_fifo + 1, s->rx_fifo_len - 1);
s->rx_fifo_len--;
qemu_chr_fe_accept_input(&s->chr);
- update_irq(s);
+ sifive_uart_update_irq(s);
return r;
}
return 0x80000000;
@@ -84,7 +84,7 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
case SIFIVE_UART_IE:
return s->ie;
case SIFIVE_UART_IP:
- return uart_ip(s);
+ return sifive_uart_ip(s);
case SIFIVE_UART_TXCTRL:
return s->txctrl;
case SIFIVE_UART_RXCTRL:
@@ -99,8 +99,8 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
}
static void
-uart_write(void *opaque, hwaddr addr,
- uint64_t val64, unsigned int size)
+sifive_uart_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
{
SiFiveUARTState *s = opaque;
uint32_t value = val64;
@@ -109,11 +109,11 @@ uart_write(void *opaque, hwaddr addr,
switch (addr) {
case SIFIVE_UART_TXFIFO:
qemu_chr_fe_write(&s->chr, &ch, 1);
- update_irq(s);
+ sifive_uart_update_irq(s);
return;
case SIFIVE_UART_IE:
s->ie = val64;
- update_irq(s);
+ sifive_uart_update_irq(s);
return;
case SIFIVE_UART_TXCTRL:
s->txctrl = val64;
@@ -129,9 +129,9 @@ uart_write(void *opaque, hwaddr addr,
__func__, (int)addr, (int)value);
}
-static const MemoryRegionOps uart_ops = {
- .read = uart_read,
- .write = uart_write,
+static const MemoryRegionOps sifive_uart_ops = {
+ .read = sifive_uart_read,
+ .write = sifive_uart_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
@@ -139,7 +139,7 @@ static const MemoryRegionOps uart_ops = {
}
};
-static void uart_rx(void *opaque, const uint8_t *buf, int size)
+static void sifive_uart_rx(void *opaque, const uint8_t *buf, int size)
{
SiFiveUARTState *s = opaque;
@@ -150,26 +150,27 @@ static void uart_rx(void *opaque, const uint8_t *buf, int size)
}
s->rx_fifo[s->rx_fifo_len++] = *buf;
- update_irq(s);
+ sifive_uart_update_irq(s);
}
-static int uart_can_rx(void *opaque)
+static int sifive_uart_can_rx(void *opaque)
{
SiFiveUARTState *s = opaque;
return s->rx_fifo_len < sizeof(s->rx_fifo);
}
-static void uart_event(void *opaque, QEMUChrEvent event)
+static void sifive_uart_event(void *opaque, QEMUChrEvent event)
{
}
-static int uart_be_change(void *opaque)
+static int sifive_uart_be_change(void *opaque)
{
SiFiveUARTState *s = opaque;
- qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
- uart_be_change, s, NULL, true);
+ qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
+ sifive_uart_event, sifive_uart_be_change, s,
+ NULL, true);
return 0;
}
@@ -183,9 +184,10 @@ SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState));
s->irq = irq;
qemu_chr_fe_init(&s->chr, chr, &error_abort);
- qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
- uart_be_change, s, NULL, true);
- memory_region_init_io(&s->mmio, NULL, &uart_ops, s,
+ qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
+ sifive_uart_event, sifive_uart_be_change, s,
+ NULL, true);
+ memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,
TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
memory_region_add_subregion(address_space, base, &s->mmio);
return s;
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 4/7] hw/char: QOMify sifive_uart
2021-06-24 12:02 [PULL 0/7] riscv-to-apply queue Alistair Francis
` (2 preceding siblings ...)
2021-06-24 12:02 ` [PULL 3/7] hw/char: Consistent function names for sifive_uart Alistair Francis
@ 2021-06-24 12:02 ` Alistair Francis
2021-06-24 12:02 ` [PULL 5/7] hw/char/ibex_uart: Make the register layout private Alistair Francis
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Alistair Francis @ 2021-06-24 12:02 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: Bin Meng, Alistair Francis, Lukas Jünger
From: Lukas Jünger <lukas.juenger@greensocs.com>
This QOMifies the SiFive UART model. Migration and reset have been
implemented.
Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210616092326.59639-3-lukas.juenger@greensocs.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/char/sifive_uart.h | 11 ++--
hw/char/sifive_uart.c | 114 +++++++++++++++++++++++++++++++---
2 files changed, 109 insertions(+), 16 deletions(-)
diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h
index 3e962be659..7f6c79f8bd 100644
--- a/include/hw/char/sifive_uart.h
+++ b/include/hw/char/sifive_uart.h
@@ -21,6 +21,7 @@
#define HW_SIFIVE_UART_H
#include "chardev/char-fe.h"
+#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "qom/object.h"
@@ -49,12 +50,10 @@ enum {
#define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7)
#define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7)
+#define SIFIVE_UART_RX_FIFO_SIZE 8
#define TYPE_SIFIVE_UART "riscv.sifive.uart"
-
-typedef struct SiFiveUARTState SiFiveUARTState;
-DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART,
- TYPE_SIFIVE_UART)
+OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART)
struct SiFiveUARTState {
/*< private >*/
@@ -64,8 +63,8 @@ struct SiFiveUARTState {
qemu_irq irq;
MemoryRegion mmio;
CharBackend chr;
- uint8_t rx_fifo[8];
- unsigned int rx_fifo_len;
+ uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE];
+ uint8_t rx_fifo_len;
uint32_t ie;
uint32_t ip;
uint32_t txctrl;
diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
index 5df8212961..278e21c434 100644
--- a/hw/char/sifive_uart.c
+++ b/hw/char/sifive_uart.c
@@ -19,10 +19,12 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/log.h"
+#include "migration/vmstate.h"
#include "chardev/char.h"
#include "chardev/char-fe.h"
#include "hw/irq.h"
#include "hw/char/sifive_uart.h"
+#include "hw/qdev-properties-system.h"
/*
* Not yet implemented:
@@ -175,20 +177,112 @@ static int sifive_uart_be_change(void *opaque)
return 0;
}
+static Property sifive_uart_properties[] = {
+ DEFINE_PROP_CHR("chardev", SiFiveUARTState, chr),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void sifive_uart_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ SiFiveUARTState *s = SIFIVE_UART(obj);
+
+ memory_region_init_io(&s->mmio, OBJECT(s), &sifive_uart_ops, s,
+ TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
+ sysbus_init_mmio(sbd, &s->mmio);
+ sysbus_init_irq(sbd, &s->irq);
+}
+
+static void sifive_uart_realize(DeviceState *dev, Error **errp)
+{
+ SiFiveUARTState *s = SIFIVE_UART(dev);
+
+ qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
+ sifive_uart_event, sifive_uart_be_change, s,
+ NULL, true);
+
+}
+
+static void sifive_uart_reset_enter(Object *obj, ResetType type)
+{
+ SiFiveUARTState *s = SIFIVE_UART(obj);
+ s->ie = 0;
+ s->ip = 0;
+ s->txctrl = 0;
+ s->rxctrl = 0;
+ s->div = 0;
+ s->rx_fifo_len = 0;
+}
+
+static void sifive_uart_reset_hold(Object *obj)
+{
+ SiFiveUARTState *s = SIFIVE_UART(obj);
+ qemu_irq_lower(s->irq);
+}
+
+static const VMStateDescription vmstate_sifive_uart = {
+ .name = TYPE_SIFIVE_UART,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8_ARRAY(rx_fifo, SiFiveUARTState,
+ SIFIVE_UART_RX_FIFO_SIZE),
+ VMSTATE_UINT8(rx_fifo_len, SiFiveUARTState),
+ VMSTATE_UINT32(ie, SiFiveUARTState),
+ VMSTATE_UINT32(ip, SiFiveUARTState),
+ VMSTATE_UINT32(txctrl, SiFiveUARTState),
+ VMSTATE_UINT32(rxctrl, SiFiveUARTState),
+ VMSTATE_UINT32(div, SiFiveUARTState),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+
+static void sifive_uart_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ ResettableClass *rc = RESETTABLE_CLASS(oc);
+
+ dc->realize = sifive_uart_realize;
+ dc->vmsd = &vmstate_sifive_uart;
+ rc->phases.enter = sifive_uart_reset_enter;
+ rc->phases.hold = sifive_uart_reset_hold;
+ device_class_set_props(dc, sifive_uart_properties);
+}
+
+static const TypeInfo sifive_uart_info = {
+ .name = TYPE_SIFIVE_UART,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(SiFiveUARTState),
+ .instance_init = sifive_uart_init,
+ .class_init = sifive_uart_class_init,
+};
+
+static void sifive_uart_register_types(void)
+{
+ type_register_static(&sifive_uart_info);
+}
+
+type_init(sifive_uart_register_types)
+
/*
* Create UART device.
*/
SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
Chardev *chr, qemu_irq irq)
{
- SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState));
- s->irq = irq;
- qemu_chr_fe_init(&s->chr, chr, &error_abort);
- qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
- sifive_uart_event, sifive_uart_be_change, s,
- NULL, true);
- memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,
- TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
- memory_region_add_subregion(address_space, base, &s->mmio);
- return s;
+ DeviceState *dev;
+ SysBusDevice *s;
+ SiFiveUARTState *r;
+
+ dev = qdev_new("riscv.sifive.uart");
+ s = SYS_BUS_DEVICE(dev);
+ qdev_prop_set_chr(dev, "chardev", chr);
+ sysbus_realize_and_unref(s, &error_fatal);
+ memory_region_add_subregion(address_space, base,
+ sysbus_mmio_get_region(s, 0));
+ sysbus_connect_irq(s, 0, irq);
+
+ r = SIFIVE_UART(dev);
+ return r;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 5/7] hw/char/ibex_uart: Make the register layout private
2021-06-24 12:02 [PULL 0/7] riscv-to-apply queue Alistair Francis
` (3 preceding siblings ...)
2021-06-24 12:02 ` [PULL 4/7] hw/char: QOMify sifive_uart Alistair Francis
@ 2021-06-24 12:02 ` Alistair Francis
2021-06-24 12:02 ` [PULL 6/7] hw/timer: Initial commit of Ibex Timer Alistair Francis
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Alistair Francis @ 2021-06-24 12:02 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: Bin Meng, Alistair Francis
We don't need to expose the register layout in the public header, so
don't.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: c437f570b2b30ab4170387a3ba2fad7d116a4986.1624001156.git.alistair.francis@wdc.com
---
include/hw/char/ibex_uart.h | 37 -------------------------------------
hw/char/ibex_uart.c | 37 +++++++++++++++++++++++++++++++++++++
2 files changed, 37 insertions(+), 37 deletions(-)
diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h
index 546f958eb8..a39985516a 100644
--- a/include/hw/char/ibex_uart.h
+++ b/include/hw/char/ibex_uart.h
@@ -31,43 +31,6 @@
#include "qemu/timer.h"
#include "qom/object.h"
-REG32(INTR_STATE, 0x00)
- FIELD(INTR_STATE, TX_WATERMARK, 0, 1)
- FIELD(INTR_STATE, RX_WATERMARK, 1, 1)
- FIELD(INTR_STATE, TX_EMPTY, 2, 1)
- FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)
-REG32(INTR_ENABLE, 0x04)
-REG32(INTR_TEST, 0x08)
-REG32(CTRL, 0x0C)
- FIELD(CTRL, TX_ENABLE, 0, 1)
- FIELD(CTRL, RX_ENABLE, 1, 1)
- FIELD(CTRL, NF, 2, 1)
- FIELD(CTRL, SLPBK, 4, 1)
- FIELD(CTRL, LLPBK, 5, 1)
- FIELD(CTRL, PARITY_EN, 6, 1)
- FIELD(CTRL, PARITY_ODD, 7, 1)
- FIELD(CTRL, RXBLVL, 8, 2)
- FIELD(CTRL, NCO, 16, 16)
-REG32(STATUS, 0x10)
- FIELD(STATUS, TXFULL, 0, 1)
- FIELD(STATUS, RXFULL, 1, 1)
- FIELD(STATUS, TXEMPTY, 2, 1)
- FIELD(STATUS, RXIDLE, 4, 1)
- FIELD(STATUS, RXEMPTY, 5, 1)
-REG32(RDATA, 0x14)
-REG32(WDATA, 0x18)
-REG32(FIFO_CTRL, 0x1c)
- FIELD(FIFO_CTRL, RXRST, 0, 1)
- FIELD(FIFO_CTRL, TXRST, 1, 1)
- FIELD(FIFO_CTRL, RXILVL, 2, 3)
- FIELD(FIFO_CTRL, TXILVL, 5, 2)
-REG32(FIFO_STATUS, 0x20)
- FIELD(FIFO_STATUS, TXLVL, 0, 5)
- FIELD(FIFO_STATUS, RXLVL, 16, 5)
-REG32(OVRD, 0x24)
-REG32(VAL, 0x28)
-REG32(TIMEOUT_CTRL, 0x2c)
-
#define IBEX_UART_TX_FIFO_SIZE 16
#define IBEX_UART_CLOCK 50000000 /* 50MHz clock */
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index 73b8f2e45b..fe4b6c3c9e 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -35,6 +35,43 @@
#include "qemu/log.h"
#include "qemu/module.h"
+REG32(INTR_STATE, 0x00)
+ FIELD(INTR_STATE, TX_WATERMARK, 0, 1)
+ FIELD(INTR_STATE, RX_WATERMARK, 1, 1)
+ FIELD(INTR_STATE, TX_EMPTY, 2, 1)
+ FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)
+REG32(INTR_ENABLE, 0x04)
+REG32(INTR_TEST, 0x08)
+REG32(CTRL, 0x0C)
+ FIELD(CTRL, TX_ENABLE, 0, 1)
+ FIELD(CTRL, RX_ENABLE, 1, 1)
+ FIELD(CTRL, NF, 2, 1)
+ FIELD(CTRL, SLPBK, 4, 1)
+ FIELD(CTRL, LLPBK, 5, 1)
+ FIELD(CTRL, PARITY_EN, 6, 1)
+ FIELD(CTRL, PARITY_ODD, 7, 1)
+ FIELD(CTRL, RXBLVL, 8, 2)
+ FIELD(CTRL, NCO, 16, 16)
+REG32(STATUS, 0x10)
+ FIELD(STATUS, TXFULL, 0, 1)
+ FIELD(STATUS, RXFULL, 1, 1)
+ FIELD(STATUS, TXEMPTY, 2, 1)
+ FIELD(STATUS, RXIDLE, 4, 1)
+ FIELD(STATUS, RXEMPTY, 5, 1)
+REG32(RDATA, 0x14)
+REG32(WDATA, 0x18)
+REG32(FIFO_CTRL, 0x1c)
+ FIELD(FIFO_CTRL, RXRST, 0, 1)
+ FIELD(FIFO_CTRL, TXRST, 1, 1)
+ FIELD(FIFO_CTRL, RXILVL, 2, 3)
+ FIELD(FIFO_CTRL, TXILVL, 5, 2)
+REG32(FIFO_STATUS, 0x20)
+ FIELD(FIFO_STATUS, TXLVL, 0, 5)
+ FIELD(FIFO_STATUS, RXLVL, 16, 5)
+REG32(OVRD, 0x24)
+REG32(VAL, 0x28)
+REG32(TIMEOUT_CTRL, 0x2c)
+
static void ibex_uart_update_irqs(IbexUartState *s)
{
if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_WATERMARK_MASK) {
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 6/7] hw/timer: Initial commit of Ibex Timer
2021-06-24 12:02 [PULL 0/7] riscv-to-apply queue Alistair Francis
` (4 preceding siblings ...)
2021-06-24 12:02 ` [PULL 5/7] hw/char/ibex_uart: Make the register layout private Alistair Francis
@ 2021-06-24 12:02 ` Alistair Francis
2021-06-24 12:02 ` [PULL 7/7] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer Alistair Francis
2021-06-25 17:55 ` [PULL 0/7] riscv-to-apply queue Peter Maydell
7 siblings, 0 replies; 9+ messages in thread
From: Alistair Francis @ 2021-06-24 12:02 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: Bin Meng, Alistair Francis
Add support for the Ibex timer. This is used with the RISC-V
mtime/mtimecmp similar to the SiFive CLINT.
We currently don't support changing the prescale or the timervalue.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 716fdea2244515ce86a2c46fe69467d013c03147.1624001156.git.alistair.francis@wdc.com
---
include/hw/timer/ibex_timer.h | 52 ++++++
hw/timer/ibex_timer.c | 305 ++++++++++++++++++++++++++++++++++
MAINTAINERS | 6 +-
hw/timer/meson.build | 1 +
4 files changed, 360 insertions(+), 4 deletions(-)
create mode 100644 include/hw/timer/ibex_timer.h
create mode 100644 hw/timer/ibex_timer.c
diff --git a/include/hw/timer/ibex_timer.h b/include/hw/timer/ibex_timer.h
new file mode 100644
index 0000000000..6a43537003
--- /dev/null
+++ b/include/hw/timer/ibex_timer.h
@@ -0,0 +1,52 @@
+/*
+ * QEMU lowRISC Ibex Timer device
+ *
+ * Copyright (c) 2021 Western Digital
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_IBEX_TIMER_H
+#define HW_IBEX_TIMER_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_IBEX_TIMER "ibex-timer"
+OBJECT_DECLARE_SIMPLE_TYPE(IbexTimerState, IBEX_TIMER)
+
+struct IbexTimerState {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ /* <public> */
+ MemoryRegion mmio;
+
+ uint32_t timer_ctrl;
+ uint32_t timer_cfg0;
+ uint32_t timer_compare_lower0;
+ uint32_t timer_compare_upper0;
+ uint32_t timer_intr_enable;
+ uint32_t timer_intr_state;
+ uint32_t timer_intr_test;
+
+ uint32_t timebase_freq;
+
+ qemu_irq irq;
+};
+#endif /* HW_IBEX_TIMER_H */
diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
new file mode 100644
index 0000000000..5befb53506
--- /dev/null
+++ b/hw/timer/ibex_timer.c
@@ -0,0 +1,305 @@
+/*
+ * QEMU lowRISC Ibex Timer device
+ *
+ * Copyright (c) 2021 Western Digital
+ *
+ * For details check the documentation here:
+ * https://docs.opentitan.org/hw/ip/rv_timer/doc/
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/timer.h"
+#include "hw/timer/ibex_timer.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "target/riscv/cpu.h"
+#include "migration/vmstate.h"
+
+REG32(CTRL, 0x00)
+ FIELD(CTRL, ACTIVE, 0, 1)
+REG32(CFG0, 0x100)
+ FIELD(CFG0, PRESCALE, 0, 12)
+ FIELD(CFG0, STEP, 16, 8)
+REG32(LOWER0, 0x104)
+REG32(UPPER0, 0x108)
+REG32(COMPARE_LOWER0, 0x10C)
+REG32(COMPARE_UPPER0, 0x110)
+REG32(INTR_ENABLE, 0x114)
+ FIELD(INTR_ENABLE, IE_0, 0, 1)
+REG32(INTR_STATE, 0x118)
+ FIELD(INTR_STATE, IS_0, 0, 1)
+REG32(INTR_TEST, 0x11C)
+ FIELD(INTR_TEST, T_0, 0, 1)
+
+static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
+{
+ return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
+ timebase_freq, NANOSECONDS_PER_SECOND);
+}
+
+static void ibex_timer_update_irqs(IbexTimerState *s)
+{
+ CPUState *cs = qemu_get_cpu(0);
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ uint64_t value = s->timer_compare_lower0 |
+ ((uint64_t)s->timer_compare_upper0 << 32);
+ uint64_t next, diff;
+ uint64_t now = cpu_riscv_read_rtc(s->timebase_freq);
+
+ if (!(s->timer_ctrl & R_CTRL_ACTIVE_MASK)) {
+ /* Timer isn't active */
+ return;
+ }
+
+ /* Update the CPUs mtimecmp */
+ cpu->env.timecmp = value;
+
+ if (cpu->env.timecmp <= now) {
+ /*
+ * If the mtimecmp was in the past raise the interrupt now.
+ */
+ riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
+ if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) {
+ s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
+ qemu_set_irq(s->irq, true);
+ }
+ return;
+ }
+
+ /* Setup a timer to trigger the interrupt in the future */
+ riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0));
+ qemu_set_irq(s->irq, false);
+
+ diff = cpu->env.timecmp - now;
+ next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
+ muldiv64(diff,
+ NANOSECONDS_PER_SECOND,
+ s->timebase_freq);
+
+ if (next < qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
+ /* We overflowed the timer, just set it as large as we can */
+ timer_mod(cpu->env.timer, 0x7FFFFFFFFFFFFFFF);
+ } else {
+ timer_mod(cpu->env.timer, next);
+ }
+}
+
+static void ibex_timer_cb(void *opaque)
+{
+ IbexTimerState *s = opaque;
+ CPUState *cs = qemu_get_cpu(0);
+ RISCVCPU *cpu = RISCV_CPU(cs);
+
+ riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
+ if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) {
+ s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
+ qemu_set_irq(s->irq, true);
+ }
+}
+
+static void ibex_timer_reset(DeviceState *dev)
+{
+ IbexTimerState *s = IBEX_TIMER(dev);
+
+ CPUState *cpu = qemu_get_cpu(0);
+ CPURISCVState *env = cpu->env_ptr;
+ env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+ &ibex_timer_cb, s);
+ env->timecmp = 0;
+
+ s->timer_ctrl = 0x00000000;
+ s->timer_cfg0 = 0x00010000;
+ s->timer_compare_lower0 = 0xFFFFFFFF;
+ s->timer_compare_upper0 = 0xFFFFFFFF;
+ s->timer_intr_enable = 0x00000000;
+ s->timer_intr_state = 0x00000000;
+ s->timer_intr_test = 0x00000000;
+
+ ibex_timer_update_irqs(s);
+}
+
+static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ IbexTimerState *s = opaque;
+ uint64_t now = cpu_riscv_read_rtc(s->timebase_freq);
+ uint64_t retvalue = 0;
+
+ switch (addr >> 2) {
+ case R_CTRL:
+ retvalue = s->timer_ctrl;
+ break;
+ case R_CFG0:
+ retvalue = s->timer_cfg0;
+ break;
+ case R_LOWER0:
+ retvalue = now;
+ break;
+ case R_UPPER0:
+ retvalue = now >> 32;
+ break;
+ case R_COMPARE_LOWER0:
+ retvalue = s->timer_compare_lower0;
+ break;
+ case R_COMPARE_UPPER0:
+ retvalue = s->timer_compare_upper0;
+ break;
+ case R_INTR_ENABLE:
+ retvalue = s->timer_intr_enable;
+ break;
+ case R_INTR_STATE:
+ retvalue = s->timer_intr_state;
+ break;
+ case R_INTR_TEST:
+ retvalue = s->timer_intr_test;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+ return 0;
+ }
+
+ return retvalue;
+}
+
+static void ibex_timer_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ IbexTimerState *s = opaque;
+ uint32_t val = val64;
+
+ switch (addr >> 2) {
+ case R_CTRL:
+ s->timer_ctrl = val;
+ break;
+ case R_CFG0:
+ qemu_log_mask(LOG_UNIMP, "Changing prescale or step not supported");
+ s->timer_cfg0 = val;
+ break;
+ case R_LOWER0:
+ qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported");
+ break;
+ case R_UPPER0:
+ qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported");
+ break;
+ case R_COMPARE_LOWER0:
+ s->timer_compare_lower0 = val;
+ ibex_timer_update_irqs(s);
+ break;
+ case R_COMPARE_UPPER0:
+ s->timer_compare_upper0 = val;
+ ibex_timer_update_irqs(s);
+ break;
+ case R_INTR_ENABLE:
+ s->timer_intr_enable = val;
+ break;
+ case R_INTR_STATE:
+ /* Write 1 to clear */
+ s->timer_intr_state &= ~val;
+ break;
+ case R_INTR_TEST:
+ s->timer_intr_test = val;
+ if (s->timer_intr_enable &
+ s->timer_intr_test &
+ R_INTR_ENABLE_IE_0_MASK) {
+ s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
+ qemu_set_irq(s->irq, true);
+ }
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+ }
+}
+
+static const MemoryRegionOps ibex_timer_ops = {
+ .read = ibex_timer_read,
+ .write = ibex_timer_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl.min_access_size = 4,
+ .impl.max_access_size = 4,
+};
+
+static int ibex_timer_post_load(void *opaque, int version_id)
+{
+ IbexTimerState *s = opaque;
+
+ ibex_timer_update_irqs(s);
+ return 0;
+}
+
+static const VMStateDescription vmstate_ibex_timer = {
+ .name = TYPE_IBEX_TIMER,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .post_load = ibex_timer_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(timer_ctrl, IbexTimerState),
+ VMSTATE_UINT32(timer_cfg0, IbexTimerState),
+ VMSTATE_UINT32(timer_compare_lower0, IbexTimerState),
+ VMSTATE_UINT32(timer_compare_upper0, IbexTimerState),
+ VMSTATE_UINT32(timer_intr_enable, IbexTimerState),
+ VMSTATE_UINT32(timer_intr_state, IbexTimerState),
+ VMSTATE_UINT32(timer_intr_test, IbexTimerState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property ibex_timer_properties[] = {
+ DEFINE_PROP_UINT32("timebase-freq", IbexTimerState, timebase_freq, 10000),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ibex_timer_init(Object *obj)
+{
+ IbexTimerState *s = IBEX_TIMER(obj);
+
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+
+ memory_region_init_io(&s->mmio, obj, &ibex_timer_ops, s,
+ TYPE_IBEX_TIMER, 0x400);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+}
+
+static void ibex_timer_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = ibex_timer_reset;
+ dc->vmsd = &vmstate_ibex_timer;
+ device_class_set_props(dc, ibex_timer_properties);
+}
+
+static const TypeInfo ibex_timer_info = {
+ .name = TYPE_IBEX_TIMER,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(IbexTimerState),
+ .instance_init = ibex_timer_init,
+ .class_init = ibex_timer_class_init,
+};
+
+static void ibex_timer_register_types(void)
+{
+ type_register_static(&ibex_timer_info);
+}
+
+type_init(ibex_timer_register_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1a041eaf86..77e4570ea0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1364,11 +1364,9 @@ M: Alistair Francis <Alistair.Francis@wdc.com>
L: qemu-riscv@nongnu.org
S: Supported
F: hw/riscv/opentitan.c
-F: hw/char/ibex_uart.c
-F: hw/intc/ibex_plic.c
+F: hw/*/ibex_*.c
F: include/hw/riscv/opentitan.h
-F: include/hw/char/ibex_uart.h
-F: include/hw/intc/ibex_plic.h
+F: include/hw/*/ibex_*.h
Microchip PolarFire SoC Icicle Kit
M: Bin Meng <bin.meng@windriver.com>
diff --git a/hw/timer/meson.build b/hw/timer/meson.build
index 157f540ecd..1aa3cd2284 100644
--- a/hw/timer/meson.build
+++ b/hw/timer/meson.build
@@ -33,5 +33,6 @@ softmmu_ss.add(when: 'CONFIG_SSE_COUNTER', if_true: files('sse-counter.c'))
softmmu_ss.add(when: 'CONFIG_SSE_TIMER', if_true: files('sse-timer.c'))
softmmu_ss.add(when: 'CONFIG_STM32F2XX_TIMER', if_true: files('stm32f2xx_timer.c'))
softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_timer.c'))
+specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_timer.c'))
specific_ss.add(when: 'CONFIG_AVR_TIMER16', if_true: files('avr_timer16.c'))
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 7/7] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
2021-06-24 12:02 [PULL 0/7] riscv-to-apply queue Alistair Francis
` (5 preceding siblings ...)
2021-06-24 12:02 ` [PULL 6/7] hw/timer: Initial commit of Ibex Timer Alistair Francis
@ 2021-06-24 12:02 ` Alistair Francis
2021-06-25 17:55 ` [PULL 0/7] riscv-to-apply queue Peter Maydell
7 siblings, 0 replies; 9+ messages in thread
From: Alistair Francis @ 2021-06-24 12:02 UTC (permalink / raw)
To: peter.maydell, qemu-devel; +Cc: Bin Meng, Alistair Francis
Connect the Ibex timer to the OpenTitan machine. The timer can trigger
the RISC-V MIE interrupt as well as a custom device interrupt.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 5e7f4e9b4537f863bcb8db1264b840b56ef2a929.1624001156.git.alistair.francis@wdc.com
---
include/hw/riscv/opentitan.h | 5 ++++-
hw/riscv/opentitan.c | 14 +++++++++++---
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index aab9bc9245..86cceef698 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -22,6 +22,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/intc/ibex_plic.h"
#include "hw/char/ibex_uart.h"
+#include "hw/timer/ibex_timer.h"
#include "qom/object.h"
#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
@@ -35,6 +36,7 @@ struct LowRISCIbexSoCState {
RISCVHartArrayState cpus;
IbexPlicState plic;
IbexUartState uart;
+ IbexTimerState timer;
MemoryRegion flash_mem;
MemoryRegion rom;
@@ -57,7 +59,7 @@ enum {
IBEX_DEV_SPI,
IBEX_DEV_I2C,
IBEX_DEV_PATTGEN,
- IBEX_DEV_RV_TIMER,
+ IBEX_DEV_TIMER,
IBEX_DEV_SENSOR_CTRL,
IBEX_DEV_OTP_CTRL,
IBEX_DEV_PWRMGR,
@@ -82,6 +84,7 @@ enum {
};
enum {
+ IBEX_TIMER_TIMEREXPIRED0_0 = 125,
IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
IBEX_UART0_RX_TIMEOUT_IRQ = 7,
IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 7545dcda9c..c5a7e3bacb 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -36,7 +36,7 @@ static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_SPI] = { 0x40050000, 0x1000 },
[IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
[IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },
- [IBEX_DEV_RV_TIMER] = { 0x40100000, 0x1000 },
+ [IBEX_DEV_TIMER] = { 0x40100000, 0x1000 },
[IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 },
[IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 },
[IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 },
@@ -106,6 +106,8 @@ static void lowrisc_ibex_soc_init(Object *obj)
object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
+
+ object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER);
}
static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -159,6 +161,14 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
3, qdev_get_gpio_in(DEVICE(&s->plic),
IBEX_UART0_RX_OVERFLOW_IRQ));
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer),
+ 0, qdev_get_gpio_in(DEVICE(&s->plic),
+ IBEX_TIMER_TIMEREXPIRED0_0));
+
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
create_unimplemented_device("riscv.lowrisc.ibex.spi",
@@ -167,8 +177,6 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);
- create_unimplemented_device("riscv.lowrisc.ibex.rv_timer",
- memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size);
create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl",
memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PULL 0/7] riscv-to-apply queue
2021-06-24 12:02 [PULL 0/7] riscv-to-apply queue Alistair Francis
` (6 preceding siblings ...)
2021-06-24 12:02 ` [PULL 7/7] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer Alistair Francis
@ 2021-06-25 17:55 ` Peter Maydell
7 siblings, 0 replies; 9+ messages in thread
From: Peter Maydell @ 2021-06-25 17:55 UTC (permalink / raw)
To: Alistair Francis; +Cc: QEMU Developers
On Thu, 24 Jun 2021 at 13:02, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit d0ac9a61474cf594d19082bc8976247e984ea9a3:
>
> Merge remote-tracking branch 'remotes/thuth-gitlab/tags/pull-request-2021-06-21' into staging (2021-06-24 09:31:26 +0100)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210624-2
>
> for you to fetch changes up to 3ef6434409c575e11faf537ce50ca05426c78940:
>
> hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer (2021-06-24 05:00:13 -0700)
>
> ----------------------------------------------------------------
> Third RISC-V PR for 6.1 release
>
> - Fix MISA in the DisasContext
> - Fix GDB CSR XML generation
> - QOMify the SiFive UART
> - Add support for the OpenTitan timer
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 9+ messages in thread