From: Daniel Vetter <daniel.vetter@ffwll.ch>
To: DRI Development <dri-devel@lists.freedesktop.org>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
Daniel Vetter <daniel.vetter@ffwll.ch>,
Daniel Vetter <daniel.vetter@intel.com>,
Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org
Subject: [PATCH 1/7] drm/msm: Don't break exclusive fence ordering
Date: Tue, 6 Jul 2021 12:12:03 +0200 [thread overview]
Message-ID: <20210706101209.3034092-2-daniel.vetter@ffwll.ch> (raw)
In-Reply-To: <20210706101209.3034092-1-daniel.vetter@ffwll.ch>
There's only one exclusive slot, and we must not break the ordering.
A better fix would be to us a dma_fence_chain or _array like e.g.
amdgpu now uses, but
- msm has a synchronous dma_fence_wait for anything from another
context, so doesn't seem to care much,
- and it probably makes sense to lift this into dma-resv.c code as a
proper concept, so that drivers don't have to hack up their own
solution each on their own.
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Sean Paul <sean@poorly.run>
Cc: linux-arm-msm@vger.kernel.org
Cc: freedreno@lists.freedesktop.org
---
drivers/gpu/drm/msm/msm_gem_submit.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c
index b71da71a3dd8..edd0051d849f 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -306,7 +306,8 @@ static int submit_fence_sync(struct msm_gem_submit *submit, bool no_implicit)
return ret;
}
- if (no_implicit)
+ /* exclusive fences must be ordered */
+ if (no_implicit && !write)
continue;
ret = msm_gem_sync_object(&msm_obj->base, submit->ring->fctx,
--
2.32.0
WARNING: multiple messages have this Message-ID (diff)
From: Daniel Vetter <daniel.vetter@ffwll.ch>
To: DRI Development <dri-devel@lists.freedesktop.org>
Cc: freedreno@lists.freedesktop.org,
Daniel Vetter <daniel.vetter@ffwll.ch>,
Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
linux-arm-msm@vger.kernel.org,
Daniel Vetter <daniel.vetter@intel.com>,
Sean Paul <sean@poorly.run>
Subject: [PATCH 1/7] drm/msm: Don't break exclusive fence ordering
Date: Tue, 6 Jul 2021 12:12:03 +0200 [thread overview]
Message-ID: <20210706101209.3034092-2-daniel.vetter@ffwll.ch> (raw)
In-Reply-To: <20210706101209.3034092-1-daniel.vetter@ffwll.ch>
There's only one exclusive slot, and we must not break the ordering.
A better fix would be to us a dma_fence_chain or _array like e.g.
amdgpu now uses, but
- msm has a synchronous dma_fence_wait for anything from another
context, so doesn't seem to care much,
- and it probably makes sense to lift this into dma-resv.c code as a
proper concept, so that drivers don't have to hack up their own
solution each on their own.
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Sean Paul <sean@poorly.run>
Cc: linux-arm-msm@vger.kernel.org
Cc: freedreno@lists.freedesktop.org
---
drivers/gpu/drm/msm/msm_gem_submit.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c
index b71da71a3dd8..edd0051d849f 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -306,7 +306,8 @@ static int submit_fence_sync(struct msm_gem_submit *submit, bool no_implicit)
return ret;
}
- if (no_implicit)
+ /* exclusive fences must be ordered */
+ if (no_implicit && !write)
continue;
ret = msm_gem_sync_object(&msm_obj->base, submit->ring->fctx,
--
2.32.0
WARNING: multiple messages have this Message-ID (diff)
From: Daniel Vetter <daniel.vetter@ffwll.ch>
To: DRI Development <dri-devel@lists.freedesktop.org>
Cc: freedreno@lists.freedesktop.org,
Daniel Vetter <daniel.vetter@ffwll.ch>,
Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
linux-arm-msm@vger.kernel.org,
Daniel Vetter <daniel.vetter@intel.com>
Subject: [Intel-gfx] [PATCH 1/7] drm/msm: Don't break exclusive fence ordering
Date: Tue, 6 Jul 2021 12:12:03 +0200 [thread overview]
Message-ID: <20210706101209.3034092-2-daniel.vetter@ffwll.ch> (raw)
In-Reply-To: <20210706101209.3034092-1-daniel.vetter@ffwll.ch>
There's only one exclusive slot, and we must not break the ordering.
A better fix would be to us a dma_fence_chain or _array like e.g.
amdgpu now uses, but
- msm has a synchronous dma_fence_wait for anything from another
context, so doesn't seem to care much,
- and it probably makes sense to lift this into dma-resv.c code as a
proper concept, so that drivers don't have to hack up their own
solution each on their own.
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Sean Paul <sean@poorly.run>
Cc: linux-arm-msm@vger.kernel.org
Cc: freedreno@lists.freedesktop.org
---
drivers/gpu/drm/msm/msm_gem_submit.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c
index b71da71a3dd8..edd0051d849f 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -306,7 +306,8 @@ static int submit_fence_sync(struct msm_gem_submit *submit, bool no_implicit)
return ret;
}
- if (no_implicit)
+ /* exclusive fences must be ordered */
+ if (no_implicit && !write)
continue;
ret = msm_gem_sync_object(&msm_obj->base, submit->ring->fctx,
--
2.32.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-06 10:12 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-06 10:12 [PATCH 0/7] dma-resv fence DAG fixes Daniel Vetter
2021-07-06 10:12 ` [Intel-gfx] " Daniel Vetter
2021-07-06 10:12 ` Daniel Vetter [this message]
2021-07-06 10:12 ` [Intel-gfx] [PATCH 1/7] drm/msm: Don't break exclusive fence ordering Daniel Vetter
2021-07-06 10:12 ` Daniel Vetter
2021-07-06 10:12 ` [PATCH 2/7] drm/msm: always wait for the exclusive fence Daniel Vetter
2021-07-06 10:12 ` [Intel-gfx] " Daniel Vetter
2021-07-06 10:12 ` Daniel Vetter
2021-07-06 10:12 ` [PATCH 3/7] drm/etnaviv: Don't break exclusive fence ordering Daniel Vetter
2021-07-06 10:12 ` [Intel-gfx] " Daniel Vetter
2021-07-07 8:54 ` Lucas Stach
2021-07-07 8:54 ` [Intel-gfx] " Lucas Stach
2021-07-07 11:37 ` Daniel Vetter
2021-07-07 11:37 ` [Intel-gfx] " Daniel Vetter
2021-07-07 12:31 ` Lucas Stach
2021-07-07 12:31 ` [Intel-gfx] " Lucas Stach
2021-07-07 12:59 ` Daniel Vetter
2021-07-07 12:59 ` [Intel-gfx] " Daniel Vetter
2021-07-06 10:12 ` [PATCH 4/7] drm/i915: delete exclude argument from i915_sw_fence_await_reservation Daniel Vetter
2021-07-06 10:12 ` [Intel-gfx] " Daniel Vetter
2021-07-06 10:12 ` [PATCH 5/7] drm/i915: Always wait for the exclusive fence Daniel Vetter
2021-07-06 10:12 ` [Intel-gfx] " Daniel Vetter
2021-07-06 12:47 ` Matthew Auld
2021-07-06 12:47 ` Matthew Auld
2021-07-06 12:58 ` Daniel Vetter
2021-07-06 12:58 ` Daniel Vetter
2021-07-06 10:12 ` [PATCH 6/7] drm/i915: Don't break exclusive fence ordering Daniel Vetter
2021-07-06 10:12 ` [Intel-gfx] " Daniel Vetter
2021-07-06 10:12 ` [PATCH 7/7] dma-resv: Give the docs a do-over Daniel Vetter
2021-07-06 10:12 ` [Intel-gfx] " Daniel Vetter
2021-07-06 10:12 ` Daniel Vetter
2021-07-06 12:34 ` [Intel-gfx] " Matthew Auld
2021-07-06 12:34 ` Matthew Auld
2021-07-06 12:34 ` Matthew Auld
2021-07-06 23:47 ` Jason Ekstrand
2021-07-06 23:47 ` [Intel-gfx] " Jason Ekstrand
2021-07-06 23:47 ` Jason Ekstrand
2021-07-07 8:06 ` [Linaro-mm-sig] " Christian König
2021-07-07 8:06 ` [Intel-gfx] " Christian König
2021-07-07 8:06 ` Christian König
2021-07-07 9:13 ` Daniel Vetter
2021-07-07 9:13 ` [Intel-gfx] " Daniel Vetter
2021-07-07 9:13 ` Daniel Vetter
2021-07-06 10:35 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for dma-resv fence DAG fixes Patchwork
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