From: Lucas De Marchi <lucas.demarchi@intel.com>
To: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 08/53] drm/i915/xehp: Extra media engines - Part 2 (interrupts)
Date: Tue, 6 Jul 2021 14:15:03 -0700 [thread overview]
Message-ID: <20210706211503.la6t4lvvjuoycizd@ldmartin-desk2> (raw)
In-Reply-To: <96b1625f-1b72-d28c-6d92-02bd5d255277@linux.intel.com>
On Fri, Jul 02, 2021 at 01:42:59PM +0100, Tvrtko Ursulin wrote:
>
>On 01/07/2021 21:23, Matt Roper wrote:
>>From: John Harrison <John.C.Harrison@Intel.com>
>>
>>Xe_HP can have a lot of extra media engines. This patch adds the
>>interrupt handler support for them.
>>
>>Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>---
>> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13 ++++++++++++-
>> drivers/gpu/drm/i915/i915_reg.h | 3 +++
>> 2 files changed, 15 insertions(+), 1 deletion(-)
>>
>>diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>>index c13462274fe8..b2de83be4d97 100644
>>--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>>+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>>@@ -184,7 +184,13 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
>> intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~0);
>> intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~0);
>> intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~0);
>>+ if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
>>+ intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~0);
>>+ if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
>>+ intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~0);
>> intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~0);
>>+ if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
>>+ intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~0);
>> intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
>> intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
>>@@ -218,8 +224,13 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
>> intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~smask);
>> intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~dmask);
>> intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~dmask);
>>+ if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
>>+ intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~dmask);
>>+ if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
>>+ intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~dmask);
>> intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask);
>
>Poor 0-1 sandwiched between 4-7 and 2-3. ;) With hopefully order restored:
not sure I understand this, order looks correct to me. It handles all
(possible) VCS engines, and later VECS
Lucas De Marchi
WARNING: multiple messages have this Message-ID (diff)
From: Lucas De Marchi <lucas.demarchi@intel.com>
To: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 08/53] drm/i915/xehp: Extra media engines - Part 2 (interrupts)
Date: Tue, 6 Jul 2021 14:15:03 -0700 [thread overview]
Message-ID: <20210706211503.la6t4lvvjuoycizd@ldmartin-desk2> (raw)
In-Reply-To: <96b1625f-1b72-d28c-6d92-02bd5d255277@linux.intel.com>
On Fri, Jul 02, 2021 at 01:42:59PM +0100, Tvrtko Ursulin wrote:
>
>On 01/07/2021 21:23, Matt Roper wrote:
>>From: John Harrison <John.C.Harrison@Intel.com>
>>
>>Xe_HP can have a lot of extra media engines. This patch adds the
>>interrupt handler support for them.
>>
>>Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>---
>> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13 ++++++++++++-
>> drivers/gpu/drm/i915/i915_reg.h | 3 +++
>> 2 files changed, 15 insertions(+), 1 deletion(-)
>>
>>diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>>index c13462274fe8..b2de83be4d97 100644
>>--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>>+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>>@@ -184,7 +184,13 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
>> intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~0);
>> intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~0);
>> intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~0);
>>+ if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
>>+ intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~0);
>>+ if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
>>+ intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~0);
>> intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~0);
>>+ if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
>>+ intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~0);
>> intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
>> intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
>>@@ -218,8 +224,13 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
>> intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~smask);
>> intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~dmask);
>> intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~dmask);
>>+ if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
>>+ intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~dmask);
>>+ if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
>>+ intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~dmask);
>> intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask);
>
>Poor 0-1 sandwiched between 4-7 and 2-3. ;) With hopefully order restored:
not sure I understand this, order looks correct to me. It handles all
(possible) VCS engines, and later VECS
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-06 21:15 UTC|newest]
Thread overview: 173+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-01 20:23 [PATCH 00/53] Begin enabling Xe_HP SDV and DG2 platforms Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 20:23 ` [PATCH 01/53] drm/i915: Add "release id" version Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-02 12:33 ` Tvrtko Ursulin
2021-07-02 12:33 ` Tvrtko Ursulin
2021-07-05 11:52 ` Jani Nikula
2021-07-05 11:52 ` Jani Nikula
2021-07-06 21:09 ` Lucas De Marchi
2021-07-06 21:09 ` Lucas De Marchi
2021-07-07 8:34 ` Jani Nikula
2021-07-07 8:34 ` Jani Nikula
2021-07-07 15:40 ` Lucas De Marchi
2021-07-07 15:40 ` Lucas De Marchi
2021-07-06 20:57 ` Lucas De Marchi
2021-07-06 20:57 ` Lucas De Marchi
2021-07-01 20:23 ` [PATCH 02/53] drm/i915: Add XE_HP initial definitions Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 20:23 ` [PATCH 03/53] drm/i915: Fork DG1 interrupt handler Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-02 9:21 ` Daniel Vetter
2021-07-02 9:21 ` [Intel-gfx] " Daniel Vetter
2021-07-06 22:48 ` Lucas De Marchi
2021-07-06 22:48 ` Lucas De Marchi
2021-07-07 7:39 ` Daniel Vetter
2021-07-07 7:39 ` Daniel Vetter
2021-07-07 15:53 ` Lucas De Marchi
2021-07-07 15:53 ` Lucas De Marchi
2021-07-01 20:23 ` [PATCH 04/53] drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 22:06 ` Lucas De Marchi
2021-07-01 22:06 ` [Intel-gfx] " Lucas De Marchi
2021-07-01 20:23 ` [PATCH 05/53] drm/i915/gen12: Use fuse info to enable SFC Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 22:19 ` Lucas De Marchi
2021-07-01 22:19 ` Lucas De Marchi
2021-07-02 12:08 ` Tvrtko Ursulin
2021-07-02 12:08 ` Tvrtko Ursulin
2021-07-01 20:23 ` [PATCH 06/53] drm/i915/selftests: Allow for larger engine counts Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 22:33 ` Lucas De Marchi
2021-07-01 22:33 ` [Intel-gfx] " Lucas De Marchi
2021-07-01 20:23 ` [PATCH 07/53] drm/i915/xehp: Extra media engines - Part 1 (engine definitions) Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-02 12:22 ` Tvrtko Ursulin
2021-07-02 12:22 ` Tvrtko Ursulin
2021-07-07 22:17 ` [Intel-gfx] [PATCH v2] " Matt Roper
2021-07-01 20:23 ` [PATCH 08/53] drm/i915/xehp: Extra media engines - Part 2 (interrupts) Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-02 12:42 ` Tvrtko Ursulin
2021-07-02 12:42 ` Tvrtko Ursulin
2021-07-06 21:15 ` Lucas De Marchi [this message]
2021-07-06 21:15 ` Lucas De Marchi
2021-07-07 7:46 ` Tvrtko Ursulin
2021-07-07 7:46 ` Tvrtko Ursulin
2021-07-01 20:23 ` [PATCH 09/53] drm/i915/xehp: Extra media engines - Part 3 (reset) Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 20:23 ` [PATCH 10/53] drm/i915/xehp: Xe_HP forcewake support Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 20:23 ` [PATCH 11/53] drm/i915/xehp: Define multicast register ranges Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 20:23 ` [PATCH 12/53] drm/i915/xehp: Handle new device context ID format Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 20:23 ` [PATCH 13/53] drm/i915/xehp: New engine context offsets Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 20:23 ` [PATCH 14/53] drm/i915/xehp: handle new steering options Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 20:23 ` [PATCH 15/53] drm/i915/xehp: Loop over all gslices for INSTDONE processing Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 20:23 ` [PATCH 16/53] drm/i915/xehpsdv: add initial XeHP SDV definitions Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 21:41 ` Rodrigo Vivi
2021-07-01 21:41 ` [Intel-gfx] " Rodrigo Vivi
2021-07-02 7:57 ` Jani Nikula
2021-07-02 7:57 ` [Intel-gfx] " Jani Nikula
2021-07-07 22:20 ` [Intel-gfx] [PATCH v2] " Matt Roper
2021-07-01 20:23 ` [PATCH 17/53] drm/i915/xehp: Changes to ss/eu definitions Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 20:23 ` [PATCH 18/53] drm/i915/xehpsdv: Add maximum sseu limits Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 20:23 ` [PATCH 19/53] drm/i915/xehpsdv: Add compute DSS type Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 20:23 ` [PATCH 20/53] drm/i915/xehpsdv: Define steering tables Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 20:23 ` [PATCH 21/53] drm/i915/xehpsdv: Define MOCS table for XeHP SDV Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 20:23 ` [PATCH 22/53] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 20:23 ` [PATCH 23/53] drm/i915/xehpsdv: Read correct RP_STATE_CAP register Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 21:41 ` Rodrigo Vivi
2021-07-01 21:41 ` [Intel-gfx] " Rodrigo Vivi
2021-07-01 20:23 ` [PATCH 24/53] drm/i915/dg2: add DG2 platform info Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 20:23 ` [PATCH 25/53] drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV Matt Roper
2021-07-01 20:23 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 26/53] drm/i915/dg2: Add forcewake table Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 27/53] drm/i915/dg2: Update LNCF steering ranges Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 28/53] drm/i915/dg2: Add SQIDI steering Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 29/53] drm/i915/dg2: Add new LRI reg offsets Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 30/53] drm/i915/dg2: Maintain backward-compatible nested batch behavior Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 31/53] drm/i915/dg2: Report INSTDONE_GEOM values in error state Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-02 8:57 ` Lionel Landwerlin
2021-07-02 8:57 ` [Intel-gfx] " Lionel Landwerlin
2021-07-01 20:24 ` [PATCH 32/53] drm/i915/dg2: Define MOCS table for DG2 Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 33/53] drm/i915/dg2: Add fake PCH Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-06 21:47 ` Lucas De Marchi
2021-07-06 21:47 ` [Intel-gfx] " Lucas De Marchi
2021-07-01 20:24 ` [PATCH 34/53] drm/i915/dg2: Add cdclk table and reference clock Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 35/53] drm/i915/dg2: Skip shared DPLL handling Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 36/53] drm/i915/dg2: Don't wait for AUX power well enable ACKs Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 37/53] drm/i915/dg2: Setup display outputs Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 38/53] drm/i915/dg2: Add dbuf programming Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 39/53] drm/i915/dg2: Don't program BW_BUDDY registers Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 40/53] drm/i915/dg2: Don't read DRAM info Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 41/53] drm/i915/dg2: DG2 has fixed memory bandwidth Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 42/53] drm/i915/dg2: Add MPLLB programming for SNPS PHY Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 43/53] drm/i915/dg2: Add MPLLB programming for HDMI Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 44/53] drm/i915/dg2: Add vswing programming for SNPS phys Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-02 8:14 ` Jani Nikula
2021-07-02 8:14 ` [Intel-gfx] " Jani Nikula
2021-07-01 20:24 ` [PATCH 45/53] drm/i915/dg2: Update modeset sequences Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-02 8:16 ` Jani Nikula
2021-07-02 8:16 ` Jani Nikula
2021-07-07 22:22 ` [Intel-gfx] [PATCH v2] " Matt Roper
2021-07-09 18:25 ` Lucas De Marchi
2021-07-01 20:24 ` [PATCH 46/53] drm/i915/dg2: Classify DG2 PHY types Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 47/53] drm/i915/dg2: Wait for SNPS PHY calibration during display init Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 48/53] drm/i915/dg2: Update lane disable power state during PSR Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 49/53] drm/i915/dg2: Add DG2 to the PSR2 defeature list Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 50/53] drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP enable Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-02 8:19 ` Jani Nikula
2021-07-02 8:19 ` [Intel-gfx] " Jani Nikula
2021-08-23 5:42 ` Kulkarni, Vandita
2021-08-23 5:42 ` [Intel-gfx] " Kulkarni, Vandita
2021-07-01 20:24 ` [PATCH 51/53] drm/i915/display/dsc: Set BPP in the kernel Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-01 20:24 ` [PATCH 52/53] drm/i915/dg2: Update to bigjoiner path Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-09 0:11 ` Navare, Manasi
2021-07-09 0:11 ` [Intel-gfx] " Navare, Manasi
2021-07-01 20:24 ` [PATCH 53/53] drm/i915/dg2: Configure PCON in DP pre-enable path Matt Roper
2021-07-01 20:24 ` [Intel-gfx] " Matt Roper
2021-07-02 1:55 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms Patchwork
2021-07-02 1:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-02 2:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-02 8:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-07-07 22:48 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Begin enabling Xe_HP SDV and DG2 platforms (rev4) Patchwork
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