From: Rodrigo Vivi <rodrigo.vivi@intel.com> To: Matt Roper <matthew.d.roper@intel.com> Cc: intel-gfx@lists.freedesktop.org, "Lucas De Marchi" <lucas.demarchi@intel.com>, "José Roberto de Souza" <jose.souza@intel.com>, "Stuart Summers" <stuart.summers@intel.com>, "Daniele Ceraolo Spurio" <daniele.ceraolospurio@intel.com>, dri-devel@lists.freedesktop.org, "Tomas Winkler" <tomas.winkler@intel.com> Subject: Re: [PATCH 16/53] drm/i915/xehpsdv: add initial XeHP SDV definitions Date: Thu, 1 Jul 2021 17:41:58 -0400 [thread overview] Message-ID: <YN42pr7P2iVLHIql@intel.com> (raw) In-Reply-To: <20210701202427.1547543-17-matthew.d.roper@intel.com> On Thu, Jul 01, 2021 at 01:23:50PM -0700, Matt Roper wrote: > From: Lucas De Marchi <lucas.demarchi@intel.com> > > XeHP SDV is a Intel® dGPU without display. This is just the definition > of some basic platform macros, by large a copy of current state of > Tigerlake which does not reflect the end state of this platform. > > Bspec: 44467, 48077 > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > Signed-off-by: Stuart Summers <stuart.summers@intel.com> > Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 10 ++++++++++ > drivers/gpu/drm/i915/i915_pci.c | 20 ++++++++++++++++++++ > drivers/gpu/drm/i915/intel_device_info.c | 1 + > drivers/gpu/drm/i915/intel_device_info.h | 1 + > 4 files changed, 32 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index c02600850246..63bed18a2be7 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1406,6 +1406,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1) > #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S) > #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P) > +#define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV) > #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ > (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) > #define IS_BDW_ULT(dev_priv) \ > @@ -1564,6 +1565,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > (IS_ALDERLAKE_P(__i915) && \ > IS_GT_STEP(__i915, since, until)) > > +#define XEHPSDV_REVID_A0 0x0 > +#define XEHPSDV_REVID_A1 0x1 > +#define XEHPSDV_REVID_A_LAST XEHPSDV_REVID_A1 > +#define XEHPSDV_REVID_B0 0x4 > +#define XEHPSDV_REVID_C0 0x8 > + > +#define IS_XEHPSDV_REVID(p, since, until) \ > + (IS_XEHPSDV(p) && IS_REVID(p, since, until)) > + > #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) > #define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv)) > #define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv)) > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index 88b279452b87..046309e95f43 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -1020,6 +1020,26 @@ static const struct intel_device_info adl_p_info = { > .ppgtt_size = 48, \ > .ppgtt_type = INTEL_PPGTT_FULL > > +#define XE_HPM_FEATURES \ > + .media_ver = 12, \ > + .media_ver_release = 50 > + > +__maybe_unused > +static const struct intel_device_info xehpsdv_info = { > + XE_HP_FEATURES, > + XE_HPM_FEATURES, > + DGFX_FEATURES, > + PLATFORM(INTEL_XEHPSDV), > + .display = { }, > + .pipe_mask = 0, > + .platform_engine_mask = > + BIT(RCS0) | BIT(BCS0) | > + BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) | > + BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) | > + BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7), > + .require_force_probe = 1, > +}; > + > #undef PLATFORM > > /* > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index e8ad14f002c1..7b37b68f4548 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -68,6 +68,7 @@ static const char * const platform_names[] = { > PLATFORM_NAME(DG1), > PLATFORM_NAME(ALDERLAKE_S), > PLATFORM_NAME(ALDERLAKE_P), > + PLATFORM_NAME(XEHPSDV), > }; > #undef PLATFORM_NAME > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index f824de632cfe..e8684199b0c9 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -88,6 +88,7 @@ enum intel_platform { > INTEL_DG1, > INTEL_ALDERLAKE_S, > INTEL_ALDERLAKE_P, > + INTEL_XEHPSDV, > INTEL_MAX_PLATFORMS > }; > > -- > 2.25.4 >
WARNING: multiple messages have this Message-ID (diff)
From: Rodrigo Vivi <rodrigo.vivi@intel.com> To: Matt Roper <matthew.d.roper@intel.com> Cc: intel-gfx@lists.freedesktop.org, Lucas De Marchi <lucas.demarchi@intel.com>, dri-devel@lists.freedesktop.org, Tomas Winkler <tomas.winkler@intel.com> Subject: Re: [Intel-gfx] [PATCH 16/53] drm/i915/xehpsdv: add initial XeHP SDV definitions Date: Thu, 1 Jul 2021 17:41:58 -0400 [thread overview] Message-ID: <YN42pr7P2iVLHIql@intel.com> (raw) In-Reply-To: <20210701202427.1547543-17-matthew.d.roper@intel.com> On Thu, Jul 01, 2021 at 01:23:50PM -0700, Matt Roper wrote: > From: Lucas De Marchi <lucas.demarchi@intel.com> > > XeHP SDV is a Intel® dGPU without display. This is just the definition > of some basic platform macros, by large a copy of current state of > Tigerlake which does not reflect the end state of this platform. > > Bspec: 44467, 48077 > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > Signed-off-by: Stuart Summers <stuart.summers@intel.com> > Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 10 ++++++++++ > drivers/gpu/drm/i915/i915_pci.c | 20 ++++++++++++++++++++ > drivers/gpu/drm/i915/intel_device_info.c | 1 + > drivers/gpu/drm/i915/intel_device_info.h | 1 + > 4 files changed, 32 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index c02600850246..63bed18a2be7 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1406,6 +1406,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1) > #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S) > #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P) > +#define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV) > #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ > (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) > #define IS_BDW_ULT(dev_priv) \ > @@ -1564,6 +1565,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > (IS_ALDERLAKE_P(__i915) && \ > IS_GT_STEP(__i915, since, until)) > > +#define XEHPSDV_REVID_A0 0x0 > +#define XEHPSDV_REVID_A1 0x1 > +#define XEHPSDV_REVID_A_LAST XEHPSDV_REVID_A1 > +#define XEHPSDV_REVID_B0 0x4 > +#define XEHPSDV_REVID_C0 0x8 > + > +#define IS_XEHPSDV_REVID(p, since, until) \ > + (IS_XEHPSDV(p) && IS_REVID(p, since, until)) > + > #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) > #define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv)) > #define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv)) > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index 88b279452b87..046309e95f43 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -1020,6 +1020,26 @@ static const struct intel_device_info adl_p_info = { > .ppgtt_size = 48, \ > .ppgtt_type = INTEL_PPGTT_FULL > > +#define XE_HPM_FEATURES \ > + .media_ver = 12, \ > + .media_ver_release = 50 > + > +__maybe_unused > +static const struct intel_device_info xehpsdv_info = { > + XE_HP_FEATURES, > + XE_HPM_FEATURES, > + DGFX_FEATURES, > + PLATFORM(INTEL_XEHPSDV), > + .display = { }, > + .pipe_mask = 0, > + .platform_engine_mask = > + BIT(RCS0) | BIT(BCS0) | > + BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) | > + BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) | > + BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7), > + .require_force_probe = 1, > +}; > + > #undef PLATFORM > > /* > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index e8ad14f002c1..7b37b68f4548 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -68,6 +68,7 @@ static const char * const platform_names[] = { > PLATFORM_NAME(DG1), > PLATFORM_NAME(ALDERLAKE_S), > PLATFORM_NAME(ALDERLAKE_P), > + PLATFORM_NAME(XEHPSDV), > }; > #undef PLATFORM_NAME > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index f824de632cfe..e8684199b0c9 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -88,6 +88,7 @@ enum intel_platform { > INTEL_DG1, > INTEL_ALDERLAKE_S, > INTEL_ALDERLAKE_P, > + INTEL_XEHPSDV, > INTEL_MAX_PLATFORMS > }; > > -- > 2.25.4 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-01 21:42 UTC|newest] Thread overview: 173+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-01 20:23 [PATCH 00/53] Begin enabling Xe_HP SDV and DG2 platforms Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 01/53] drm/i915: Add "release id" version Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-02 12:33 ` Tvrtko Ursulin 2021-07-02 12:33 ` Tvrtko Ursulin 2021-07-05 11:52 ` Jani Nikula 2021-07-05 11:52 ` Jani Nikula 2021-07-06 21:09 ` Lucas De Marchi 2021-07-06 21:09 ` Lucas De Marchi 2021-07-07 8:34 ` Jani Nikula 2021-07-07 8:34 ` Jani Nikula 2021-07-07 15:40 ` Lucas De Marchi 2021-07-07 15:40 ` Lucas De Marchi 2021-07-06 20:57 ` Lucas De Marchi 2021-07-06 20:57 ` Lucas De Marchi 2021-07-01 20:23 ` [PATCH 02/53] drm/i915: Add XE_HP initial definitions Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 03/53] drm/i915: Fork DG1 interrupt handler Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-02 9:21 ` Daniel Vetter 2021-07-02 9:21 ` [Intel-gfx] " Daniel Vetter 2021-07-06 22:48 ` Lucas De Marchi 2021-07-06 22:48 ` Lucas De Marchi 2021-07-07 7:39 ` Daniel Vetter 2021-07-07 7:39 ` Daniel Vetter 2021-07-07 15:53 ` Lucas De Marchi 2021-07-07 15:53 ` Lucas De Marchi 2021-07-01 20:23 ` [PATCH 04/53] drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 22:06 ` Lucas De Marchi 2021-07-01 22:06 ` [Intel-gfx] " Lucas De Marchi 2021-07-01 20:23 ` [PATCH 05/53] drm/i915/gen12: Use fuse info to enable SFC Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 22:19 ` Lucas De Marchi 2021-07-01 22:19 ` Lucas De Marchi 2021-07-02 12:08 ` Tvrtko Ursulin 2021-07-02 12:08 ` Tvrtko Ursulin 2021-07-01 20:23 ` [PATCH 06/53] drm/i915/selftests: Allow for larger engine counts Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 22:33 ` Lucas De Marchi 2021-07-01 22:33 ` [Intel-gfx] " Lucas De Marchi 2021-07-01 20:23 ` [PATCH 07/53] drm/i915/xehp: Extra media engines - Part 1 (engine definitions) Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-02 12:22 ` Tvrtko Ursulin 2021-07-02 12:22 ` Tvrtko Ursulin 2021-07-07 22:17 ` [Intel-gfx] [PATCH v2] " Matt Roper 2021-07-01 20:23 ` [PATCH 08/53] drm/i915/xehp: Extra media engines - Part 2 (interrupts) Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-02 12:42 ` Tvrtko Ursulin 2021-07-02 12:42 ` Tvrtko Ursulin 2021-07-06 21:15 ` Lucas De Marchi 2021-07-06 21:15 ` Lucas De Marchi 2021-07-07 7:46 ` Tvrtko Ursulin 2021-07-07 7:46 ` Tvrtko Ursulin 2021-07-01 20:23 ` [PATCH 09/53] drm/i915/xehp: Extra media engines - Part 3 (reset) Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 10/53] drm/i915/xehp: Xe_HP forcewake support Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 11/53] drm/i915/xehp: Define multicast register ranges Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 12/53] drm/i915/xehp: Handle new device context ID format Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 13/53] drm/i915/xehp: New engine context offsets Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 14/53] drm/i915/xehp: handle new steering options Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 15/53] drm/i915/xehp: Loop over all gslices for INSTDONE processing Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 16/53] drm/i915/xehpsdv: add initial XeHP SDV definitions Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 21:41 ` Rodrigo Vivi [this message] 2021-07-01 21:41 ` Rodrigo Vivi 2021-07-02 7:57 ` Jani Nikula 2021-07-02 7:57 ` [Intel-gfx] " Jani Nikula 2021-07-07 22:20 ` [Intel-gfx] [PATCH v2] " Matt Roper 2021-07-01 20:23 ` [PATCH 17/53] drm/i915/xehp: Changes to ss/eu definitions Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 18/53] drm/i915/xehpsdv: Add maximum sseu limits Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 19/53] drm/i915/xehpsdv: Add compute DSS type Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 20/53] drm/i915/xehpsdv: Define steering tables Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 21/53] drm/i915/xehpsdv: Define MOCS table for XeHP SDV Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 22/53] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 23/53] drm/i915/xehpsdv: Read correct RP_STATE_CAP register Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 21:41 ` Rodrigo Vivi 2021-07-01 21:41 ` [Intel-gfx] " Rodrigo Vivi 2021-07-01 20:23 ` [PATCH 24/53] drm/i915/dg2: add DG2 platform info Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 25/53] drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 26/53] drm/i915/dg2: Add forcewake table Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 27/53] drm/i915/dg2: Update LNCF steering ranges Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 28/53] drm/i915/dg2: Add SQIDI steering Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 29/53] drm/i915/dg2: Add new LRI reg offsets Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 30/53] drm/i915/dg2: Maintain backward-compatible nested batch behavior Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 31/53] drm/i915/dg2: Report INSTDONE_GEOM values in error state Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-02 8:57 ` Lionel Landwerlin 2021-07-02 8:57 ` [Intel-gfx] " Lionel Landwerlin 2021-07-01 20:24 ` [PATCH 32/53] drm/i915/dg2: Define MOCS table for DG2 Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 33/53] drm/i915/dg2: Add fake PCH Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-06 21:47 ` Lucas De Marchi 2021-07-06 21:47 ` [Intel-gfx] " Lucas De Marchi 2021-07-01 20:24 ` [PATCH 34/53] drm/i915/dg2: Add cdclk table and reference clock Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 35/53] drm/i915/dg2: Skip shared DPLL handling Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 36/53] drm/i915/dg2: Don't wait for AUX power well enable ACKs Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 37/53] drm/i915/dg2: Setup display outputs Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 38/53] drm/i915/dg2: Add dbuf programming Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 39/53] drm/i915/dg2: Don't program BW_BUDDY registers Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 40/53] drm/i915/dg2: Don't read DRAM info Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 41/53] drm/i915/dg2: DG2 has fixed memory bandwidth Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 42/53] drm/i915/dg2: Add MPLLB programming for SNPS PHY Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 43/53] drm/i915/dg2: Add MPLLB programming for HDMI Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 44/53] drm/i915/dg2: Add vswing programming for SNPS phys Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-02 8:14 ` Jani Nikula 2021-07-02 8:14 ` [Intel-gfx] " Jani Nikula 2021-07-01 20:24 ` [PATCH 45/53] drm/i915/dg2: Update modeset sequences Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-02 8:16 ` Jani Nikula 2021-07-02 8:16 ` Jani Nikula 2021-07-07 22:22 ` [Intel-gfx] [PATCH v2] " Matt Roper 2021-07-09 18:25 ` Lucas De Marchi 2021-07-01 20:24 ` [PATCH 46/53] drm/i915/dg2: Classify DG2 PHY types Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 47/53] drm/i915/dg2: Wait for SNPS PHY calibration during display init Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 48/53] drm/i915/dg2: Update lane disable power state during PSR Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 49/53] drm/i915/dg2: Add DG2 to the PSR2 defeature list Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 50/53] drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP enable Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-02 8:19 ` Jani Nikula 2021-07-02 8:19 ` [Intel-gfx] " Jani Nikula 2021-08-23 5:42 ` Kulkarni, Vandita 2021-08-23 5:42 ` [Intel-gfx] " Kulkarni, Vandita 2021-07-01 20:24 ` [PATCH 51/53] drm/i915/display/dsc: Set BPP in the kernel Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 52/53] drm/i915/dg2: Update to bigjoiner path Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-09 0:11 ` Navare, Manasi 2021-07-09 0:11 ` [Intel-gfx] " Navare, Manasi 2021-07-01 20:24 ` [PATCH 53/53] drm/i915/dg2: Configure PCON in DP pre-enable path Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-02 1:55 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms Patchwork 2021-07-02 1:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-07-02 2:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-07-02 8:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-07-07 22:48 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Begin enabling Xe_HP SDV and DG2 platforms (rev4) Patchwork
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