From: Kefeng Wang <wangkefeng.wang@huawei.com>
To: <palmerdabbelt@google.com>, <paul.walmsley@sifive.com>,
<palmer@dabbelt.com>, <linux-riscv@lists.infradead.org>
Cc: Kefeng Wang <wangkefeng.wang@huawei.com>
Subject: [PATCH 3/3] riscv: Enable GENERIC_IRQ_SHOW_LEVEL
Date: Thu, 8 Jul 2021 09:59:49 +0800 [thread overview]
Message-ID: <20210708015949.20076-4-wangkefeng.wang@huawei.com> (raw)
In-Reply-To: <20210708015949.20076-1-wangkefeng.wang@huawei.com>
The interrupt controllers on riscv support both edge and level triggered
interrupts, it's useful to provide that information in /proc/interrupts.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index c3a6d63841de..1bd3760d6bce 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -52,6 +52,7 @@ config RISCV
select GENERIC_IOREMAP
select GENERIC_IRQ_MULTI_HANDLER
select GENERIC_IRQ_SHOW
+ select GENERIC_IRQ_SHOW_LEVEL
select GENERIC_LIB_DEVMEM_IS_ALLOWED
select GENERIC_PCI_IOMAP
select GENERIC_PTDUMP if MMU
--
2.26.2
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prev parent reply other threads:[~2021-07-08 1:53 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-08 1:59 [PATCH 0/3] riscv: Enable some feature for RISCV Kefeng Wang
2021-07-08 1:59 ` [PATCH 1/3] riscv: Allow forced irq threading Kefeng Wang
2021-07-08 5:28 ` Christoph Hellwig
2021-07-08 6:42 ` Kefeng Wang
2021-08-04 20:33 ` Palmer Dabbelt
2021-07-08 1:59 ` [PATCH 2/3] riscv: Enable idle generic idle loop Kefeng Wang
2021-07-08 1:59 ` Kefeng Wang [this message]
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