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From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH 1/7] drm/i915: Settle on "adl-x" in WA comments
Date: Thu,  8 Jul 2021 14:18:21 -0700	[thread overview]
Message-ID: <20210708211827.288601-1-jose.souza@intel.com> (raw)

From: Lucas De Marchi <lucas.demarchi@intel.com>

Most of the places are using this format so lets consolidate it.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c         |  2 +-
 drivers/gpu/drm/i915/display/intel_cursor.c        |  2 +-
 drivers/gpu/drm/i915/display/intel_display.c       |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c           | 10 +++++-----
 drivers/gpu/drm/i915/display/skl_universal_plane.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c        |  2 +-
 drivers/gpu/drm/i915/intel_pm.c                    |  4 ++--
 7 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index df2d8ce4a12f6..71067a62264de 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2878,7 +2878,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
 		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
 		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
-		/* Wa_22011320316:adlp[a0] */
+		/* Wa_22011320316:adl-p[a0] */
 		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
 			dev_priv->cdclk.table = adlp_a_step_cdclk_table;
 		else
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index bb61e736de911..f61a25fb87e90 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -383,7 +383,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
 	if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
 		cntl |= MCURSOR_ROTATE_180;
 
-	/* Wa_22012358565:adlp */
+	/* Wa_22012358565:adl-p */
 	if (DISPLAY_VER(dev_priv) == 13)
 		cntl |= MCURSOR_ARB_SLOTS(1);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 026c28c612f07..65ddb6ca16e67 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -975,7 +975,7 @@ void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
 		/* FIXME: assert CPU port conditions for SNB+ */
 	}
 
-	/* Wa_22012358565:adlp */
+	/* Wa_22012358565:adl-p */
 	if (DISPLAY_VER(dev_priv) == 13)
 		intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
 			     0, PIPE_ARB_USE_PROG_SLOTS);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 9643624fe160d..4dfe1dceb8635 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -545,7 +545,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1);
 	val |= intel_psr2_get_tp_time(intel_dp);
 
-	/* Wa_22012278275:adlp */
+	/* Wa_22012278275:adl-p */
 	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D1)) {
 		static const u8 map[] = {
 			2, /* 5 lines */
@@ -733,7 +733,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
 	if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
 		return;
 
-	/* Wa_16011303918:adlp */
+	/* Wa_16011303918:adl-p */
 	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
 		return;
 
@@ -965,7 +965,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	/* Wa_16011303918:adlp */
+	/* Wa_16011303918:adl-p */
 	if (crtc_state->vrr.enable &&
 	    IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) {
 		drm_dbg_kms(&dev_priv->drm,
@@ -1160,7 +1160,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
 			     intel_dp->psr.psr2_sel_fetch_enabled ?
 			     IGNORE_PSR2_HW_TRACKING : 0);
 
-	/* Wa_16011168373:adlp */
+	/* Wa_16011168373:adl-p */
 	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) &&
 	    intel_dp->psr.psr2_enabled)
 		intel_de_rmw(dev_priv,
@@ -1346,7 +1346,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
 			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
 
-	/* Wa_16011168373:adlp */
+	/* Wa_16011168373:adl-p */
 	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) &&
 	    intel_dp->psr.psr2_enabled)
 		intel_de_rmw(dev_priv,
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index c7263f4ff11d7..628b678d9a71c 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -926,7 +926,7 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 	else if (key->flags & I915_SET_COLORKEY_SOURCE)
 		plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
 
-	/* Wa_22012358565:adlp */
+	/* Wa_22012358565:adl-p */
 	if (DISPLAY_VER(dev_priv) == 13)
 		plane_ctl |= adlp_plane_ctl_arb_slots(plane_state);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index d9a5a445ceecd..e5e3f820074a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1078,7 +1078,7 @@ gen12_gt_workarounds_init(struct drm_i915_private *i915,
 {
 	icl_wa_init_mcr(i915, wal);
 
-	/* Wa_14011060649:tgl,rkl,dg1,adls,adl-p */
+	/* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */
 	wa_14011060649(i915, wal);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5fdb96e7d2668..0cbb79452fcf9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7356,7 +7356,7 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
 
 static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-	/* Wa_1409120013:tgl,rkl,adl_s,dg1 */
+	/* Wa_1409120013:tgl,rkl,adl-s,dg1 */
 	if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
 	    IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv))
 		intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
@@ -7367,7 +7367,7 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
 		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
 			   TGL_VRH_GATING_DIS);
 
-	/* Wa_14011059788:tgl,rkl,adl_s,dg1,adl-p */
+	/* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */
 	intel_uncore_rmw(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
 			 0, DFR_DISABLE);
 
-- 
2.32.0

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             reply	other threads:[~2021-07-08 21:14 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-08 21:18 José Roberto de Souza [this message]
2021-07-08 21:18 ` [Intel-gfx] [PATCH 2/7] drm/i915: Implement Wa_1508744258 José Roberto de Souza
2021-07-10  5:06   ` Matt Roper
2021-08-12  3:27   ` Timo Aaltonen
2021-08-12  6:29     ` Timo Aaltonen
2021-08-12 15:56       ` Souza, Jose
2021-07-08 21:18 ` [Intel-gfx] [PATCH 3/7] drm/i915/adl_s: Extend Wa_1406941453 José Roberto de Souza
2021-07-10  5:07   ` Matt Roper
2021-07-08 21:18 ` [Intel-gfx] [PATCH 4/7] drm/i915: Limit maximum number of memory channels José Roberto de Souza
2021-07-08 21:18 ` [Intel-gfx] [PATCH 5/7] drm/i915: Limit Wa_22010178259 to affected platforms José Roberto de Souza
2021-07-10  5:29   ` Matt Roper
2021-07-08 21:18 ` [Intel-gfx] [PATCH 6/7] drm/i915/display/adl_p: Correctly program MBUS DBOX A credits José Roberto de Souza
2021-07-10  5:41   ` Matt Roper
2021-08-03 20:19     ` Souza, Jose
2021-08-03 22:39       ` Matt Roper
2021-07-08 21:18 ` [Intel-gfx] [PATCH 7/7] drm/i915/display/xelpd: Exetend Wa_14011508470 José Roberto de Souza
2021-07-10  5:42   ` Matt Roper
2021-07-08 23:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/7] drm/i915: Settle on "adl-x" in WA comments Patchwork
2021-07-08 23:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-09 14:30 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-07-10  4:55 ` [Intel-gfx] [PATCH 1/7] " Matt Roper

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