From: Vinay Belgaumkar <vinay.belgaumkar@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Subject: [PATCH 12/16] drm/i915/guc/slpc: Cache platform frequency limits for slpc Date: Fri, 9 Jul 2021 18:20:22 -0700 [thread overview] Message-ID: <20210710012026.19705-13-vinay.belgaumkar@intel.com> (raw) In-Reply-To: <20210710012026.19705-1-vinay.belgaumkar@intel.com> Cache rp0, rp1 and rpn platform limits into slpc structure for range checking while setting min/max frequencies. Also add "soft" limits which keep track of frequency changes made from userland. These are initially set to platform min and max. Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 41 +++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c index d32274cd1db7..6e978f27b7a6 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c @@ -86,6 +86,9 @@ static int slpc_shared_data_init(struct intel_guc_slpc *slpc) return err; } + slpc->max_freq_softlimit = 0; + slpc->min_freq_softlimit = 0; + return err; } @@ -384,6 +387,29 @@ void intel_guc_pm_intrmsk_enable(struct intel_gt *gt) GEN6_PMINTRMSK, pm_intrmsk_mbz, 0); } +static int intel_guc_slpc_set_softlimits(struct intel_guc_slpc *slpc) +{ + int ret = 0; + + /* Softlimits are initially equivalent to platform limits + * unless they have deviated from defaults, in which case, + * we retain the values and set min/max accordingly. + */ + if (!slpc->max_freq_softlimit) + slpc->max_freq_softlimit = slpc->rp0_freq; + else if (slpc->max_freq_softlimit != slpc->rp0_freq) + ret = intel_guc_slpc_set_max_freq(slpc, + slpc->max_freq_softlimit); + + if (!slpc->min_freq_softlimit) + slpc->min_freq_softlimit = slpc->min_freq; + else if (slpc->min_freq_softlimit != slpc->min_freq) + ret = intel_guc_slpc_set_min_freq(slpc, + slpc->min_freq_softlimit); + + return ret; +} + /* * intel_guc_slpc_enable() - Start SLPC * @slpc: pointer to intel_guc_slpc. @@ -402,6 +428,7 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc) struct drm_i915_private *i915 = slpc_to_i915(slpc); struct slpc_shared_data *data; int ret; + u32 rp_state_cap; GEM_BUG_ON(!slpc->vma); @@ -445,6 +472,20 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc) DIV_ROUND_CLOSEST(data->task_state_data.max_unslice_freq * GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER)); + rp_state_cap = intel_uncore_read(i915->gt.uncore, GEN6_RP_STATE_CAP); + + slpc->rp0_freq = ((rp_state_cap >> 0) & 0xff) * GT_FREQUENCY_MULTIPLIER; + slpc->min_freq = ((rp_state_cap >> 16) & 0xff) * GT_FREQUENCY_MULTIPLIER; + slpc->rp1_freq = ((rp_state_cap >> 8) & 0xff) * GT_FREQUENCY_MULTIPLIER; + + if (intel_guc_slpc_set_softlimits(slpc)) + drm_err(&i915->drm, "Unable to set softlimits"); + + drm_info(&i915->drm, + "Platform fused frequency values - min: %u Mhz, max: %u Mhz", + slpc->min_freq, + slpc->rp0_freq); + return 0; } -- 2.25.0
WARNING: multiple messages have this Message-ID (diff)
From: Vinay Belgaumkar <vinay.belgaumkar@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 12/16] drm/i915/guc/slpc: Cache platform frequency limits for slpc Date: Fri, 9 Jul 2021 18:20:22 -0700 [thread overview] Message-ID: <20210710012026.19705-13-vinay.belgaumkar@intel.com> (raw) In-Reply-To: <20210710012026.19705-1-vinay.belgaumkar@intel.com> Cache rp0, rp1 and rpn platform limits into slpc structure for range checking while setting min/max frequencies. Also add "soft" limits which keep track of frequency changes made from userland. These are initially set to platform min and max. Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 41 +++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c index d32274cd1db7..6e978f27b7a6 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c @@ -86,6 +86,9 @@ static int slpc_shared_data_init(struct intel_guc_slpc *slpc) return err; } + slpc->max_freq_softlimit = 0; + slpc->min_freq_softlimit = 0; + return err; } @@ -384,6 +387,29 @@ void intel_guc_pm_intrmsk_enable(struct intel_gt *gt) GEN6_PMINTRMSK, pm_intrmsk_mbz, 0); } +static int intel_guc_slpc_set_softlimits(struct intel_guc_slpc *slpc) +{ + int ret = 0; + + /* Softlimits are initially equivalent to platform limits + * unless they have deviated from defaults, in which case, + * we retain the values and set min/max accordingly. + */ + if (!slpc->max_freq_softlimit) + slpc->max_freq_softlimit = slpc->rp0_freq; + else if (slpc->max_freq_softlimit != slpc->rp0_freq) + ret = intel_guc_slpc_set_max_freq(slpc, + slpc->max_freq_softlimit); + + if (!slpc->min_freq_softlimit) + slpc->min_freq_softlimit = slpc->min_freq; + else if (slpc->min_freq_softlimit != slpc->min_freq) + ret = intel_guc_slpc_set_min_freq(slpc, + slpc->min_freq_softlimit); + + return ret; +} + /* * intel_guc_slpc_enable() - Start SLPC * @slpc: pointer to intel_guc_slpc. @@ -402,6 +428,7 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc) struct drm_i915_private *i915 = slpc_to_i915(slpc); struct slpc_shared_data *data; int ret; + u32 rp_state_cap; GEM_BUG_ON(!slpc->vma); @@ -445,6 +472,20 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc) DIV_ROUND_CLOSEST(data->task_state_data.max_unslice_freq * GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER)); + rp_state_cap = intel_uncore_read(i915->gt.uncore, GEN6_RP_STATE_CAP); + + slpc->rp0_freq = ((rp_state_cap >> 0) & 0xff) * GT_FREQUENCY_MULTIPLIER; + slpc->min_freq = ((rp_state_cap >> 16) & 0xff) * GT_FREQUENCY_MULTIPLIER; + slpc->rp1_freq = ((rp_state_cap >> 8) & 0xff) * GT_FREQUENCY_MULTIPLIER; + + if (intel_guc_slpc_set_softlimits(slpc)) + drm_err(&i915->drm, "Unable to set softlimits"); + + drm_info(&i915->drm, + "Platform fused frequency values - min: %u Mhz, max: %u Mhz", + slpc->min_freq, + slpc->rp0_freq); + return 0; } -- 2.25.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-10 1:23 UTC|newest] Thread overview: 108+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-10 1:20 [PATCH 00/16] Enable GuC based power management features Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] [PATCH 01/16] drm/i915/guc: Squashed patch - DO NOT REVIEW Vinay Belgaumkar 2021-07-10 1:20 ` [PATCH 02/16] drm/i915/guc/slpc: Initial definitions for slpc Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 14:27 ` Michal Wajdeczko 2021-07-10 14:27 ` [Intel-gfx] " Michal Wajdeczko 2021-07-12 18:40 ` Belgaumkar, Vinay 2021-07-12 18:40 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-12 23:43 ` Belgaumkar, Vinay 2021-07-12 23:43 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 03/16] drm/i915/guc/slpc: Gate Host RPS when slpc is enabled Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 1:20 ` [PATCH 04/16] drm/i915/guc/slpc: Lay out slpc init/enable/disable/fini Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 14:35 ` Michal Wajdeczko 2021-07-10 14:35 ` Michal Wajdeczko 2021-07-13 0:37 ` Belgaumkar, Vinay 2021-07-13 0:37 ` Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 05/16] drm/i915/guc/slpc: Adding slpc communication interfaces Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 15:52 ` Michal Wajdeczko 2021-07-10 15:52 ` [Intel-gfx] " Michal Wajdeczko 2021-07-13 23:22 ` Belgaumkar, Vinay 2021-07-13 23:22 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 06/16] drm/i915/guc/slpc: Allocate, initialize and release slpc Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 16:05 ` Michal Wajdeczko 2021-07-10 16:05 ` [Intel-gfx] " Michal Wajdeczko 2021-07-14 1:40 ` Belgaumkar, Vinay 2021-07-14 1:40 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 07/16] drm/i915/guc/slpc: Enable slpc and add related H2G events Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 17:37 ` Michal Wajdeczko 2021-07-10 17:37 ` Michal Wajdeczko 2021-07-15 1:58 ` Belgaumkar, Vinay 2021-07-15 1:58 ` Belgaumkar, Vinay 2021-07-21 17:36 ` Michal Wajdeczko 2021-07-21 17:36 ` Michal Wajdeczko 2021-07-10 1:20 ` [PATCH 08/16] drm/i915/guc/slpc: Add methods to set min/max frequency Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 3:07 ` kernel test robot 2021-07-10 3:07 ` kernel test robot 2021-07-10 3:07 ` [Intel-gfx] " kernel test robot 2021-07-10 5:17 ` kernel test robot 2021-07-10 5:17 ` kernel test robot 2021-07-10 5:17 ` [Intel-gfx] " kernel test robot 2021-07-10 17:47 ` Michal Wajdeczko 2021-07-10 17:47 ` [Intel-gfx] " Michal Wajdeczko 2021-07-16 18:00 ` Belgaumkar, Vinay 2021-07-16 18:00 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 09/16] drm/i915/guc/slpc: Add get max/min freq hooks Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 17:52 ` Michal Wajdeczko 2021-07-10 17:52 ` [Intel-gfx] " Michal Wajdeczko 2021-07-20 22:08 ` Belgaumkar, Vinay 2021-07-20 22:08 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 10/16] drm/i915/guc/slpc: Add debugfs for slpc info Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 18:08 ` Michal Wajdeczko 2021-07-10 18:08 ` [Intel-gfx] " Michal Wajdeczko 2021-07-20 23:00 ` Belgaumkar, Vinay 2021-07-20 23:00 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 11/16] drm/i915/guc/slpc: Enable ARAT timer interrupt Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 1:20 ` Vinay Belgaumkar [this message] 2021-07-10 1:20 ` [Intel-gfx] [PATCH 12/16] drm/i915/guc/slpc: Cache platform frequency limits for slpc Vinay Belgaumkar 2021-07-10 18:15 ` Michal Wajdeczko 2021-07-10 18:15 ` Michal Wajdeczko 2021-07-17 19:30 ` Belgaumkar, Vinay 2021-07-17 19:30 ` Belgaumkar, Vinay 2021-07-20 23:05 ` Belgaumkar, Vinay 2021-07-20 23:05 ` Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 13/16] drm/i915/guc/slpc: Update slpc to use platform min/max Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 1:20 ` [PATCH 14/16] drm/i915/guc/slpc: Sysfs hooks for slpc Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 6:18 ` kernel test robot 2021-07-10 6:18 ` kernel test robot 2021-07-10 6:18 ` [Intel-gfx] " kernel test robot 2021-07-10 7:30 ` kernel test robot 2021-07-10 7:30 ` kernel test robot 2021-07-10 7:30 ` [Intel-gfx] " kernel test robot 2021-07-10 7:30 ` [RFC PATCH] drm/i915/guc/slpc: intel_rps_read_punit_req() can be static kernel test robot 2021-07-10 7:30 ` kernel test robot 2021-07-10 7:30 ` [Intel-gfx] " kernel test robot 2021-07-10 13:54 ` [PATCH 14/16] drm/i915/guc/slpc: Sysfs hooks for slpc kernel test robot 2021-07-10 13:54 ` kernel test robot 2021-07-10 13:54 ` [Intel-gfx] " kernel test robot 2021-07-10 18:20 ` Michal Wajdeczko 2021-07-10 18:20 ` [Intel-gfx] " Michal Wajdeczko 2021-07-20 23:38 ` Belgaumkar, Vinay 2021-07-20 23:38 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 15/16] drm/i915/guc/slpc: slpc selftest Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 18:29 ` Michal Wajdeczko 2021-07-10 18:29 ` [Intel-gfx] " Michal Wajdeczko 2021-07-21 1:06 ` Belgaumkar, Vinay 2021-07-21 1:06 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 16/16] drm/i915/guc/rc: Setup and enable GUCRC feature Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 18:41 ` Michal Wajdeczko 2021-07-10 18:41 ` Michal Wajdeczko 2021-07-21 1:11 ` Belgaumkar, Vinay 2021-07-21 1:11 ` Belgaumkar, Vinay 2021-07-10 1:40 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable GuC based power management features Patchwork 2021-07-10 1:41 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-07-10 2:09 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20210710012026.19705-13-vinay.belgaumkar@intel.com \ --to=vinay.belgaumkar@intel.com \ --cc=dri-devel@lists.freedesktop.org \ --cc=intel-gfx@lists.freedesktop.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.