From: Vinay Belgaumkar <vinay.belgaumkar@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>, Sundaresan Sujaritha <sujaritha.sundaresan@intel.com> Subject: [PATCH 08/16] drm/i915/guc/slpc: Add methods to set min/max frequency Date: Fri, 9 Jul 2021 18:20:18 -0700 [thread overview] Message-ID: <20210710012026.19705-9-vinay.belgaumkar@intel.com> (raw) In-Reply-To: <20210710012026.19705-1-vinay.belgaumkar@intel.com> Add param set h2g helpers to set the min and max frequencies for use by SLPC. Signed-off-by: Sundaresan Sujaritha <sujaritha.sundaresan@intel.com> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 94 +++++++++++++++++++++ drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 + 2 files changed, 96 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c index e579408d1c19..19cb26479942 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c @@ -106,6 +106,19 @@ static int slpc_send(struct intel_guc_slpc *slpc, return intel_guc_send(guc, action, in_len); } +static int host2guc_slpc_set_param(struct intel_guc_slpc *slpc, + u32 id, u32 value) +{ + struct slpc_event_input data = {0}; + + data.header.value = SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2); + data.args[0] = id; + data.args[1] = value; + + return slpc_send(slpc, &data, 4); +} + + static bool slpc_running(struct intel_guc_slpc *slpc) { struct slpc_shared_data *data; @@ -134,6 +147,19 @@ static int host2guc_slpc_query_task_state(struct intel_guc_slpc *slpc) return slpc_send(slpc, &data, 4); } +static int slpc_set_param(struct intel_guc_slpc *slpc, u32 id, u32 value) +{ + struct drm_i915_private *i915 = slpc_to_i915(slpc); + GEM_BUG_ON(id >= SLPC_MAX_PARAM); + + if (host2guc_slpc_set_param(slpc, id, value)) { + drm_err(&i915->drm, "Unable to set param %x", id); + return -EIO; + } + + return 0; +} + static int slpc_read_task_state(struct intel_guc_slpc *slpc) { return host2guc_slpc_query_task_state(slpc); @@ -218,6 +244,74 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc) return slpc_shared_data_init(slpc); } +/** + * intel_guc_slpc_max_freq_set() - Set max frequency limit for SLPC. + * @slpc: pointer to intel_guc_slpc. + * @val: encoded frequency + * + * This function will invoke GuC SLPC action to update the max frequency + * limit for slice and unslice. + * + * Return: 0 on success, non-zero error code on failure. + */ +int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val) +{ + int ret; + struct drm_i915_private *i915 = slpc_to_i915(slpc); + intel_wakeref_t wakeref; + + wakeref = intel_runtime_pm_get(&i915->runtime_pm); + + ret = slpc_set_param(slpc, + SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ, + val); + + if (ret) { + drm_err(&i915->drm, + "Set max frequency unslice returned %d", ret); + ret = -EIO; + goto done; + } + +done: + intel_runtime_pm_put(&i915->runtime_pm, wakeref); + return ret; +} + +/** + * intel_guc_slpc_min_freq_set() - Set min frequency limit for SLPC. + * @slpc: pointer to intel_guc_slpc. + * @val: encoded frequency + * + * This function will invoke GuC SLPC action to update the min frequency + * limit. + * + * Return: 0 on success, non-zero error code on failure. + */ +int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val) +{ + int ret; + struct intel_guc *guc = slpc_to_guc(slpc); + struct drm_i915_private *i915 = guc_to_gt(guc)->i915; + intel_wakeref_t wakeref; + + wakeref = intel_runtime_pm_get(&i915->runtime_pm); + + ret = slpc_set_param(slpc, + SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ, + val); + if (ret) { + drm_err(&i915->drm, + "Set min frequency for unslice returned %d", ret); + ret = -EIO; + goto done; + } + +done: + intel_runtime_pm_put(&i915->runtime_pm, wakeref); + return ret; +} + /* * intel_guc_slpc_enable() - Start SLPC * @slpc: pointer to intel_guc_slpc. diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h index a2643b904165..a473e1ea7c10 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h @@ -34,5 +34,7 @@ struct intel_guc_slpc { int intel_guc_slpc_init(struct intel_guc_slpc *slpc); int intel_guc_slpc_enable(struct intel_guc_slpc *slpc); void intel_guc_slpc_fini(struct intel_guc_slpc *slpc); +int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val); +int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val); #endif -- 2.25.0
WARNING: multiple messages have this Message-ID (diff)
From: Vinay Belgaumkar <vinay.belgaumkar@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 08/16] drm/i915/guc/slpc: Add methods to set min/max frequency Date: Fri, 9 Jul 2021 18:20:18 -0700 [thread overview] Message-ID: <20210710012026.19705-9-vinay.belgaumkar@intel.com> (raw) In-Reply-To: <20210710012026.19705-1-vinay.belgaumkar@intel.com> Add param set h2g helpers to set the min and max frequencies for use by SLPC. Signed-off-by: Sundaresan Sujaritha <sujaritha.sundaresan@intel.com> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 94 +++++++++++++++++++++ drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 + 2 files changed, 96 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c index e579408d1c19..19cb26479942 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c @@ -106,6 +106,19 @@ static int slpc_send(struct intel_guc_slpc *slpc, return intel_guc_send(guc, action, in_len); } +static int host2guc_slpc_set_param(struct intel_guc_slpc *slpc, + u32 id, u32 value) +{ + struct slpc_event_input data = {0}; + + data.header.value = SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2); + data.args[0] = id; + data.args[1] = value; + + return slpc_send(slpc, &data, 4); +} + + static bool slpc_running(struct intel_guc_slpc *slpc) { struct slpc_shared_data *data; @@ -134,6 +147,19 @@ static int host2guc_slpc_query_task_state(struct intel_guc_slpc *slpc) return slpc_send(slpc, &data, 4); } +static int slpc_set_param(struct intel_guc_slpc *slpc, u32 id, u32 value) +{ + struct drm_i915_private *i915 = slpc_to_i915(slpc); + GEM_BUG_ON(id >= SLPC_MAX_PARAM); + + if (host2guc_slpc_set_param(slpc, id, value)) { + drm_err(&i915->drm, "Unable to set param %x", id); + return -EIO; + } + + return 0; +} + static int slpc_read_task_state(struct intel_guc_slpc *slpc) { return host2guc_slpc_query_task_state(slpc); @@ -218,6 +244,74 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc) return slpc_shared_data_init(slpc); } +/** + * intel_guc_slpc_max_freq_set() - Set max frequency limit for SLPC. + * @slpc: pointer to intel_guc_slpc. + * @val: encoded frequency + * + * This function will invoke GuC SLPC action to update the max frequency + * limit for slice and unslice. + * + * Return: 0 on success, non-zero error code on failure. + */ +int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val) +{ + int ret; + struct drm_i915_private *i915 = slpc_to_i915(slpc); + intel_wakeref_t wakeref; + + wakeref = intel_runtime_pm_get(&i915->runtime_pm); + + ret = slpc_set_param(slpc, + SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ, + val); + + if (ret) { + drm_err(&i915->drm, + "Set max frequency unslice returned %d", ret); + ret = -EIO; + goto done; + } + +done: + intel_runtime_pm_put(&i915->runtime_pm, wakeref); + return ret; +} + +/** + * intel_guc_slpc_min_freq_set() - Set min frequency limit for SLPC. + * @slpc: pointer to intel_guc_slpc. + * @val: encoded frequency + * + * This function will invoke GuC SLPC action to update the min frequency + * limit. + * + * Return: 0 on success, non-zero error code on failure. + */ +int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val) +{ + int ret; + struct intel_guc *guc = slpc_to_guc(slpc); + struct drm_i915_private *i915 = guc_to_gt(guc)->i915; + intel_wakeref_t wakeref; + + wakeref = intel_runtime_pm_get(&i915->runtime_pm); + + ret = slpc_set_param(slpc, + SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ, + val); + if (ret) { + drm_err(&i915->drm, + "Set min frequency for unslice returned %d", ret); + ret = -EIO; + goto done; + } + +done: + intel_runtime_pm_put(&i915->runtime_pm, wakeref); + return ret; +} + /* * intel_guc_slpc_enable() - Start SLPC * @slpc: pointer to intel_guc_slpc. diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h index a2643b904165..a473e1ea7c10 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h @@ -34,5 +34,7 @@ struct intel_guc_slpc { int intel_guc_slpc_init(struct intel_guc_slpc *slpc); int intel_guc_slpc_enable(struct intel_guc_slpc *slpc); void intel_guc_slpc_fini(struct intel_guc_slpc *slpc); +int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val); +int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val); #endif -- 2.25.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-10 1:23 UTC|newest] Thread overview: 108+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-10 1:20 [PATCH 00/16] Enable GuC based power management features Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] [PATCH 01/16] drm/i915/guc: Squashed patch - DO NOT REVIEW Vinay Belgaumkar 2021-07-10 1:20 ` [PATCH 02/16] drm/i915/guc/slpc: Initial definitions for slpc Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 14:27 ` Michal Wajdeczko 2021-07-10 14:27 ` [Intel-gfx] " Michal Wajdeczko 2021-07-12 18:40 ` Belgaumkar, Vinay 2021-07-12 18:40 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-12 23:43 ` Belgaumkar, Vinay 2021-07-12 23:43 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 03/16] drm/i915/guc/slpc: Gate Host RPS when slpc is enabled Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 1:20 ` [PATCH 04/16] drm/i915/guc/slpc: Lay out slpc init/enable/disable/fini Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 14:35 ` Michal Wajdeczko 2021-07-10 14:35 ` Michal Wajdeczko 2021-07-13 0:37 ` Belgaumkar, Vinay 2021-07-13 0:37 ` Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 05/16] drm/i915/guc/slpc: Adding slpc communication interfaces Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 15:52 ` Michal Wajdeczko 2021-07-10 15:52 ` [Intel-gfx] " Michal Wajdeczko 2021-07-13 23:22 ` Belgaumkar, Vinay 2021-07-13 23:22 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 06/16] drm/i915/guc/slpc: Allocate, initialize and release slpc Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 16:05 ` Michal Wajdeczko 2021-07-10 16:05 ` [Intel-gfx] " Michal Wajdeczko 2021-07-14 1:40 ` Belgaumkar, Vinay 2021-07-14 1:40 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 07/16] drm/i915/guc/slpc: Enable slpc and add related H2G events Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 17:37 ` Michal Wajdeczko 2021-07-10 17:37 ` Michal Wajdeczko 2021-07-15 1:58 ` Belgaumkar, Vinay 2021-07-15 1:58 ` Belgaumkar, Vinay 2021-07-21 17:36 ` Michal Wajdeczko 2021-07-21 17:36 ` Michal Wajdeczko 2021-07-10 1:20 ` Vinay Belgaumkar [this message] 2021-07-10 1:20 ` [Intel-gfx] [PATCH 08/16] drm/i915/guc/slpc: Add methods to set min/max frequency Vinay Belgaumkar 2021-07-10 3:07 ` kernel test robot 2021-07-10 3:07 ` kernel test robot 2021-07-10 3:07 ` [Intel-gfx] " kernel test robot 2021-07-10 5:17 ` kernel test robot 2021-07-10 5:17 ` kernel test robot 2021-07-10 5:17 ` [Intel-gfx] " kernel test robot 2021-07-10 17:47 ` Michal Wajdeczko 2021-07-10 17:47 ` [Intel-gfx] " Michal Wajdeczko 2021-07-16 18:00 ` Belgaumkar, Vinay 2021-07-16 18:00 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 09/16] drm/i915/guc/slpc: Add get max/min freq hooks Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 17:52 ` Michal Wajdeczko 2021-07-10 17:52 ` [Intel-gfx] " Michal Wajdeczko 2021-07-20 22:08 ` Belgaumkar, Vinay 2021-07-20 22:08 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 10/16] drm/i915/guc/slpc: Add debugfs for slpc info Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 18:08 ` Michal Wajdeczko 2021-07-10 18:08 ` [Intel-gfx] " Michal Wajdeczko 2021-07-20 23:00 ` Belgaumkar, Vinay 2021-07-20 23:00 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 11/16] drm/i915/guc/slpc: Enable ARAT timer interrupt Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 1:20 ` [PATCH 12/16] drm/i915/guc/slpc: Cache platform frequency limits for slpc Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 18:15 ` Michal Wajdeczko 2021-07-10 18:15 ` Michal Wajdeczko 2021-07-17 19:30 ` Belgaumkar, Vinay 2021-07-17 19:30 ` Belgaumkar, Vinay 2021-07-20 23:05 ` Belgaumkar, Vinay 2021-07-20 23:05 ` Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 13/16] drm/i915/guc/slpc: Update slpc to use platform min/max Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 1:20 ` [PATCH 14/16] drm/i915/guc/slpc: Sysfs hooks for slpc Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 6:18 ` kernel test robot 2021-07-10 6:18 ` kernel test robot 2021-07-10 6:18 ` [Intel-gfx] " kernel test robot 2021-07-10 7:30 ` kernel test robot 2021-07-10 7:30 ` kernel test robot 2021-07-10 7:30 ` [Intel-gfx] " kernel test robot 2021-07-10 7:30 ` [RFC PATCH] drm/i915/guc/slpc: intel_rps_read_punit_req() can be static kernel test robot 2021-07-10 7:30 ` kernel test robot 2021-07-10 7:30 ` [Intel-gfx] " kernel test robot 2021-07-10 13:54 ` [PATCH 14/16] drm/i915/guc/slpc: Sysfs hooks for slpc kernel test robot 2021-07-10 13:54 ` kernel test robot 2021-07-10 13:54 ` [Intel-gfx] " kernel test robot 2021-07-10 18:20 ` Michal Wajdeczko 2021-07-10 18:20 ` [Intel-gfx] " Michal Wajdeczko 2021-07-20 23:38 ` Belgaumkar, Vinay 2021-07-20 23:38 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 15/16] drm/i915/guc/slpc: slpc selftest Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 18:29 ` Michal Wajdeczko 2021-07-10 18:29 ` [Intel-gfx] " Michal Wajdeczko 2021-07-21 1:06 ` Belgaumkar, Vinay 2021-07-21 1:06 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 16/16] drm/i915/guc/rc: Setup and enable GUCRC feature Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 18:41 ` Michal Wajdeczko 2021-07-10 18:41 ` Michal Wajdeczko 2021-07-21 1:11 ` Belgaumkar, Vinay 2021-07-21 1:11 ` Belgaumkar, Vinay 2021-07-10 1:40 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable GuC based power management features Patchwork 2021-07-10 1:41 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-07-10 2:09 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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