* [PATCH 1/3] clk: socfpga: agilex: fix the parents of the psi_ref_clk @ 2021-07-13 14:46 Dinh Nguyen 2021-07-13 14:46 ` [PATCH 2/3] clk: socfpga: agilex: fix up s2f_user0_clk representation Dinh Nguyen ` (2 more replies) 0 siblings, 3 replies; 6+ messages in thread From: Dinh Nguyen @ 2021-07-13 14:46 UTC (permalink / raw) To: linux-clk; +Cc: dinguyen, sboyd, mturquette, stable, Kris Chaplin The psi_ref_clk comes from the C2 node of the main_pll and periph_pll, not the C3. Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Kris Chaplin <kris.chaplin@intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- drivers/clk/socfpga/clk-agilex.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c index 1cb21ea79c64..9dffe9ba0e74 100644 --- a/drivers/clk/socfpga/clk-agilex.c +++ b/drivers/clk/socfpga/clk-agilex.c @@ -107,10 +107,10 @@ static const struct clk_parent_data gpio_db_free_mux[] = { }; static const struct clk_parent_data psi_ref_free_mux[] = { - { .fw_name = "main_pll_c3", - .name = "main_pll_c3", }, - { .fw_name = "peri_pll_c3", - .name = "peri_pll_c3", }, + { .fw_name = "main_pll_c2", + .name = "main_pll_c2", }, + { .fw_name = "peri_pll_c2", + .name = "peri_pll_c2", }, { .fw_name = "osc1", .name = "osc1", }, { .fw_name = "cb-intosc-hs-div2-clk", -- 2.25.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/3] clk: socfpga: agilex: fix up s2f_user0_clk representation 2021-07-13 14:46 [PATCH 1/3] clk: socfpga: agilex: fix the parents of the psi_ref_clk Dinh Nguyen @ 2021-07-13 14:46 ` Dinh Nguyen 2021-07-27 0:56 ` Stephen Boyd 2021-07-13 14:46 ` [PATCH 3/3] clk: socfpga: agilex: add the bypass register for s2f_usr0 clock Dinh Nguyen 2021-07-27 0:56 ` [PATCH 1/3] clk: socfpga: agilex: fix the parents of the psi_ref_clk Stephen Boyd 2 siblings, 1 reply; 6+ messages in thread From: Dinh Nguyen @ 2021-07-13 14:46 UTC (permalink / raw) To: linux-clk; +Cc: dinguyen, sboyd, mturquette, stable, Kris Chaplin Correct the s2f_user0_mux clock representation. Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Kris Chaplin <kris.chaplin@intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- drivers/clk/socfpga/clk-agilex.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c index 9dffe9ba0e74..7baaa16dea7b 100644 --- a/drivers/clk/socfpga/clk-agilex.c +++ b/drivers/clk/socfpga/clk-agilex.c @@ -195,6 +195,13 @@ static const struct clk_parent_data sdmmc_mux[] = { .name = "boot_clk", }, }; +static const struct clk_parent_data s2f_user0_mux[] = { + { .fw_name = "s2f_user0_free_clk", + .name = "s2f_user0_free_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + static const struct clk_parent_data s2f_user1_mux[] = { { .fw_name = "s2f_user1_free_clk", .name = "s2f_user1_free_clk", }, @@ -319,6 +326,8 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = { 4, 0x98, 0, 16, 0x88, 3, 0}, { AGILEX_SDMMC_CLK, "sdmmc_clk", NULL, sdmmc_mux, ARRAY_SIZE(sdmmc_mux), 0, 0x7C, 5, 0, 0, 0, 0x88, 4, 4}, + { AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_user0_mux, ARRAY_SIZE(s2f_user0_mux), 0, 0x24, + 6, 0, 0, 0, 0x30, 2, 0}, { AGILEX_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, ARRAY_SIZE(s2f_user1_mux), 0, 0x7C, 6, 0, 0, 0, 0x88, 5, 0}, { AGILEX_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, ARRAY_SIZE(psi_mux), 0, 0x7C, -- 2.25.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/3] clk: socfpga: agilex: fix up s2f_user0_clk representation 2021-07-13 14:46 ` [PATCH 2/3] clk: socfpga: agilex: fix up s2f_user0_clk representation Dinh Nguyen @ 2021-07-27 0:56 ` Stephen Boyd 0 siblings, 0 replies; 6+ messages in thread From: Stephen Boyd @ 2021-07-27 0:56 UTC (permalink / raw) To: Dinh Nguyen, linux-clk; +Cc: dinguyen, mturquette, stable, Kris Chaplin Quoting Dinh Nguyen (2021-07-13 07:46:20) > Correct the s2f_user0_mux clock representation. > > Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") > Cc: stable@vger.kernel.org > Signed-off-by: Kris Chaplin <kris.chaplin@intel.com> > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> > --- Applied to clk-next ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/3] clk: socfpga: agilex: add the bypass register for s2f_usr0 clock 2021-07-13 14:46 [PATCH 1/3] clk: socfpga: agilex: fix the parents of the psi_ref_clk Dinh Nguyen 2021-07-13 14:46 ` [PATCH 2/3] clk: socfpga: agilex: fix up s2f_user0_clk representation Dinh Nguyen @ 2021-07-13 14:46 ` Dinh Nguyen 2021-07-27 0:56 ` Stephen Boyd 2021-07-27 0:56 ` [PATCH 1/3] clk: socfpga: agilex: fix the parents of the psi_ref_clk Stephen Boyd 2 siblings, 1 reply; 6+ messages in thread From: Dinh Nguyen @ 2021-07-13 14:46 UTC (permalink / raw) To: linux-clk; +Cc: dinguyen, sboyd, mturquette, stable, Kris Chaplin Add the bypass register for the s2f_user0_clk. Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Kris Chaplin <kris.chaplin@intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- drivers/clk/socfpga/clk-agilex.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c index 7baaa16dea7b..242e94c0cf8a 100644 --- a/drivers/clk/socfpga/clk-agilex.c +++ b/drivers/clk/socfpga/clk-agilex.c @@ -280,7 +280,7 @@ static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = { { AGILEX_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux, ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0, 0}, { AGILEX_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, s2f_usr0_free_mux, - ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0, 0}, + ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0x30, 2}, { AGILEX_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux, ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88, 5}, { AGILEX_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux, -- 2.25.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] clk: socfpga: agilex: add the bypass register for s2f_usr0 clock 2021-07-13 14:46 ` [PATCH 3/3] clk: socfpga: agilex: add the bypass register for s2f_usr0 clock Dinh Nguyen @ 2021-07-27 0:56 ` Stephen Boyd 0 siblings, 0 replies; 6+ messages in thread From: Stephen Boyd @ 2021-07-27 0:56 UTC (permalink / raw) To: Dinh Nguyen, linux-clk; +Cc: dinguyen, mturquette, stable, Kris Chaplin Quoting Dinh Nguyen (2021-07-13 07:46:21) > Add the bypass register for the s2f_user0_clk. > > Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") > Cc: stable@vger.kernel.org > Signed-off-by: Kris Chaplin <kris.chaplin@intel.com> > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> > --- Applied to clk-next ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] clk: socfpga: agilex: fix the parents of the psi_ref_clk 2021-07-13 14:46 [PATCH 1/3] clk: socfpga: agilex: fix the parents of the psi_ref_clk Dinh Nguyen 2021-07-13 14:46 ` [PATCH 2/3] clk: socfpga: agilex: fix up s2f_user0_clk representation Dinh Nguyen 2021-07-13 14:46 ` [PATCH 3/3] clk: socfpga: agilex: add the bypass register for s2f_usr0 clock Dinh Nguyen @ 2021-07-27 0:56 ` Stephen Boyd 2 siblings, 0 replies; 6+ messages in thread From: Stephen Boyd @ 2021-07-27 0:56 UTC (permalink / raw) To: Dinh Nguyen, linux-clk; +Cc: dinguyen, mturquette, stable, Kris Chaplin Quoting Dinh Nguyen (2021-07-13 07:46:19) > The psi_ref_clk comes from the C2 node of the main_pll and periph_pll, > not the C3. > > Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") > Cc: stable@vger.kernel.org > Signed-off-by: Kris Chaplin <kris.chaplin@intel.com> > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> > --- Applied to clk-next ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-07-27 0:56 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-07-13 14:46 [PATCH 1/3] clk: socfpga: agilex: fix the parents of the psi_ref_clk Dinh Nguyen 2021-07-13 14:46 ` [PATCH 2/3] clk: socfpga: agilex: fix up s2f_user0_clk representation Dinh Nguyen 2021-07-27 0:56 ` Stephen Boyd 2021-07-13 14:46 ` [PATCH 3/3] clk: socfpga: agilex: add the bypass register for s2f_usr0 clock Dinh Nguyen 2021-07-27 0:56 ` Stephen Boyd 2021-07-27 0:56 ` [PATCH 1/3] clk: socfpga: agilex: fix the parents of the psi_ref_clk Stephen Boyd
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